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RT9259C
12V Synchronous Buck PWM DC-DC and Linear Power Controller
General Description
The RT9259C is a dual-channel DC/DC controller specifically designed to deliver high quality power where 12V power source is available. This part consists of a synchronous buck controller and an LDO controller. The synchronous buck controller integrates MOSFET drivers that support 12V+12V bootstrapped voltage for high efficiency power conversion. The bootstrap diode is builtin to simplify the circuit design and minimize external part count. The LDO controller drives an external N-MOSFET for lower power requirement. Other features include adjustable operation frequency, internal soft start, under voltage protection, over current protection and shut down function. With the above functions, this part provides customers a compact, high efficiency, well-protected and cost-effective solution. This part comes to VQFN-16L 4x4, SOP14 and SSOP-16 packages.
Features
Single 12V Bias Supply Support Dual Channel Power Conversion One Synchronous Rectified Buck PWM Controller One Linear Controller Both Controllers Drive Low Cost N-MOSFETs Adjustable Frequency from 150kHz to 1MHz and Free-Run Frequency at 230kHz Small External Component Count 1% High Accuracy Output Voltage Regulation for Both PWM and LDO Controller Two Internal VREF Power Support Lower to 0.8V Adjustable External Compensation Linear Controller Drives N-MOSFET Pass Transistor Fully-Adjustable Outputs Under Voltage Protection for Both Outputs Over Current Fault Monitor on MOSFET; No Current Sense Resistor is Required. RoHS Compliant and 100% Lead (Pb)-Free
Ordering Information
RT9259C Package Type S : SOP-14 A : SSOP-16 QV : VQFN-16 4x4 (V-Type)
Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
Note : Richtek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating.
Applications
Graphic Card GPU, Memory Core Power Graphic Card Interface Power Motherboard, Desktop and Servers Chipset and Memory Core Power IA Equipments Telecomm Equipments High Power DC-DC Regulators
Marking Information
For marking information, contact our sales representative directly or through a Richtek distributor located in your area, otherwise visit our website for detail.
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RT9259C
Pin Configurations
(TOP VIEW)
RT_DIS BOOT UGATE PHASE
12 11 17 5 6 7 8 10 9
BOOT RT_DIS COMP FB DRV FBL GND
2 3 4 5 6 7
14 13 12 11 10 9 8
UGATE PHASE PGND LGATE NC NC VCC12
GND
NC
SOP-14
SSOP-16
VQFN-16L 4x4
Typical Application Circuit
VCC +12V VIN1 +3.3V/+5V/+12V
RT9259C
VIN2 +5V to +12V
CIN Q1 LOUT
1
BOOT Q3 VCC12 DRV FBL RT_DIS GND
UGATE PHASE LGATE PGND FB
VOUT1 COUT
VOUT2 COUT2
Q2
NC NC
COMP
Functional Pin Description
Pin No. RT9259C S RT9259C A RT9259CPQV 1 1 15 Pin Name Pin Function
2 3 4 5
2 3 4 5
16 1 2 3
Bootstrap supply for the upper gate driver. Connect the bootstrap capacitor between BOOT pin and the PHASE pin. BOOT The bootstrap capacitor provides the charge to turn on the upper MOSFET. Connect a resistor from RT_DIS to GND to set frequency. In RT_DIS addition, if this pin is pulled down towards GND, it will disable both regulator outputs until released. Buck converter external compensation. This pin is used to COMP compensate the control loop of the buck converter. Buck converter feedback voltage. This pin is the inverting FB input of the PWM error amplifier. FB senses the switcher output through an external resistor divider network. Connect this pin to the gate of an external MOSFET. This pin DRV provides the drive for the linear regulator's pass MOSFET.
To be continued
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VCC12 NC
BOOT RT_DIS COMP FB DRV FBL GND GND
2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
UGATE PHASE PGND LGATE NC NC VCC12 VCC12
16 15 14 13
COMP FB DRV FBL
1 2 3 4
PGND LGATE NC NC
RT9259C
Pin No. RT9259C S RT9259C A 6 7 8 9, 10 6 7, 8 9, 10 11, 12 RT9259CPQV 4 5 7 Pin Name Pin Function Linear regulator feedback voltage. This pin is the inverting input of the LDO error amplifier and protection monitor. Connect this pin to an external resistor divider network of the linear regulator. Ground. Connect this pin to a well-decoupled 12V bias supply. It is also the positive supply for the lower gate driver, LGATE. No Internal Connection.
FBL GND VCC12
6, 8, 9, 10, NC Exposed Pad (17) 11 12 13
11 12 13
13 14 15
Lower gate driver output. Connect to the gate of the low-side power N-MOSFET. This pin is monitored by the LGATE adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. PGND Power ground return for the lower gate driver. Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin is monitored by PHASE the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. Connect this pin to a well-decoupled 12V bias supply. It is UGATE also the positive supply for the lower gate driver, LGATE.
14
16
14
Function Block Diagram
VCC12
Voltage Reference VREF2 FBL VCC12 DRV Inhibit + + 0.4V + +
Bias
Power On Reset
5V Regulator
5VDD
POR OC Soft-Start & Fault Logic + ROCSET 20k PH_M + 0.4V 40uA
SSE
1.5V BOOT UGATE
Shutdown SSE VREF1 + + EA + PWM Driver Logic
PHASE
RT_DIS GND
Oscillator
LGATE PGND
FB
COMP
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RT9259C
Absolute Maximum Ratings
(Note 1) Supply Voltage, VCC -------------------------------------------------------------------------------------- 15V PHASE to GND DC ------------------------------------------------------------------------------------------------------------- -5V to 15V < 200ns ------------------------------------------------------------------------------------------------------ -10V to 30V BOOT to PHASE ------------------------------------------------------------------------------------------ 15V BOOT to GND DC ------------------------------------------------------------------------------------------------------------- -0.3V to VCC+15V < 200ns ------------------------------------------------------------------------------------------------------ -0.3V to 42V UGATE ------------------------------------------------------------------------------------------------------- VPHASE - 0.3V to VBOOT + 0.3V LGATE ------------------------------------------------------------------------------------------------------- GND - 0.3V to VCC + 0.3V DRV ---------------------------------------------------------------------------------------------------------- GND - 0.3V to VCC + 0.3V Input, Output or I/O Voltage ----------------------------------------------------------------------------- GND - 0.3V to 7V Power Dissipation, PD @ TA = 25C SOP-14 ------------------------------------------------------------------------------------------------------ 1.000W SSOP-16 ---------------------------------------------------------------------------------------------------- 0.909W VQFN-16L 4x4 --------------------------------------------------------------------------------------------- 1.852W Package Thermal Resistance (Note 4) SOP-14, JA ------------------------------------------------------------------------------------------------- 100C/W SSOP-16, JA ----------------------------------------------------------------------------------------------- 110C/W VQFN-16L 4x4, JA ---------------------------------------------------------------------------------------- 54C/W Junction Temperature ------------------------------------------------------------------------------------- 150C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260C Storage Temperature Range ---------------------------------------------------------------------------- -40C to 150C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
Supply Voltage, VCC -------------------------------------------------------------------------------------- 12V 10% Junction Temperature Range ---------------------------------------------------------------------------- -40C to 125C Ambient Temperature Range ---------------------------------------------------------------------------- -40C to 85C
Electrical Characteristics
(VCC = 12V, TA = 25C unless otherwise specified)
Parameter Supply Input Power Supply Voltage Power On Reset Power On Reset Hysteresis Power Supply Current
Symbol
Test Conditions
Min
Typ
Max
Units
VCC VVCCRTH VVCCHYS IVCC UGATE, LGATE Open VCC Rising
-8.8 0.4 --
12 9.6 0.78 3
15 10.4 1.2 --
V V V mA
To be continued
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RT9259C
Parameter Oscillator Free Running Frequency Ramp Amplitude Reference Voltage PWM Error Amplifier Reference Linear Driver Reference Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate Gate Driver Upper Drive Source Upper Drive Sink Lower Drive Source Lower Drive Sink Protection Under Voltage Protection Soft-Start Time Interval Over Current Threshold RT_DIS Shutdown Threshold Linear Regulator Output High Voltage Output Low Voltage Source Current Sink Current VDRV VDRV IDRVSR IDRVSC 9.5 -2 0.5 10.3 0.1 ---1 --V V mA mA VUVP TSS VOC 0.36 2 -0.35 0.4 3 -400 0.4 0.45 4 --V ms mV V RUGATE RUGATE RLGATE RLGATE VBO OT - VPHASE = 12V, VBO OT - VUGATE = 1V VUGATE = 1V VCC - VLG ATE = 1V VLGA TE = 1V ----4 4 4 2 8 8 6 4 GBW SR CLOA D = 5pF 70 6 3 88 15 6 ---dB MHz V/us V REF1 V REF2 0.792 0.792 0.8 0.8 0.808 0.808 V V fOSC RRT = 110k 250 -300 1.6 350 -kHz V Symbol Test Conditions Min Typ Max Units
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. JA is measured in the natural convection at TA = 25C on a high effective 4-layers 2S2P thermal conductivity test board of JEDEC 51-7 thermal measurement standard.
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RT9259C
Typical Operating Characteristics
Dead Time
No Load, Falling UGATE UGATE VIN1 PHASE VIN1 No Load, Rising
Dead Time
PHASE
(5V/Div)
LGATE
(5V/Div)
LGATE
Time (25ns/Div)
Time (25ns/Div)
OCP
Power Off
No Load UGATE
VOUT1
(2V/Div)
(10V/Div)
V REF IL
(10V/Div)
LGATE
(0.5A/Div) (10A/Div) (200mV/Div)
IL
Time (2.5ms/Div)
Time (5s/Div)
Shut Down
Full Load UGATE No Load VIN1
Start Up
(20V/Div) (5V/Div)
LGATE RT_Dis
(10V/Div)
VOUT1
(500mV/Div)
PHASE RT_Dis
(500mV/Div) (10V/Div) (1V/Div) (500mV/Div)
V OUT1
Time (5s/Div)
Time (1ms/Div)
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RT9259C
Start Up
No Load ILOAD ILOAD = 20A
Start Up
(2.5A/Div)
RT_Dis
(500mV/Div)
V OUT1
(500mV/Div)
(500mV/Div) Time (1ms/Div)
V OUT1
Time (1ms/Div)
Transient Response
Transient Response
UGATE V OUT
(20V/Div) (100mV/Div)
VOUT1
(100mV/Div)
(20V/Div)
UGATE
IL
(10A/Div)
VIN1 = 12V, VOUT1 = 2V ILOAD = 1A to 20A
(10A/Div)
VIN1 = 12V, VOUT1 = 2V ILOAD = 20A to 1A
IL
Time (2.5s/Div)
Time (10s/Div)
Transient Response
LDO VIN2 = 12V, VOUT2 = 2.5V ILOAD = 1A to 100mA LDO LGATE
Under Voltage Protection
VIN2 = 0V
(2mV/Div)
VOUT2
(10V/Div)
UGATE
(20V/Div)
IL
COMP
(500mV/Div) (0.5A/Div) (1V/Div) Time (100s/Div)
V OUT2
Time (10ms/Div)
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RT9259C
Application Information
Introduction The RT9259C is a dual-channel DC/DC controller specifically designed to deliver high quality power where 12V power source is available. This part consists of a synchronous buck controller and an LDO controller. The synchronous buck controller integrates internal MOSFET drivers that support 12V+12V bootstrapped voltage for high efficiency power conversion. The bootstrap diode is builtin to simplify the circuit design and minimize external part count. The LDO controller drives an external N-MOSFET for lower power requirement. Internal 5VDD Regulator It is highly recommended to power the RT9259C with welldecoupled 12V to VCC12 pin. VCC12 powers the RT9259C control circuit, low side gate driver and bootstrap circuit for high side gate driver. A bootstrap diode is embedded to facilitates PCB design and reduce the total BOM cost. No external Schottky diode is required. The RT9259C integrates MOSFET gate drives that are powered from the VCC12 pin and support 12V + 12V driving capability. Converters that consist of RT9259C feature high efficiency without special consideration on the selection of MOSFETs. An internal linear regulator regulates VCC12 input to a 5VDD voltage for internal control logic circuit. No external bypass capacitor is required for filtering the 5VDD voltage. This further facilitates PCB design and reduces the total BOM cost. Power On Reset The RT9259C automatically initializes upon applying input power (at the VCC12) pin. The power on reset function (POR) continually monitors the input bias supply voltage at the VCC12 pin. The VCC12V POR level is typically 9.6V at VCC12V rising. Frequency Setting and Shut Down Connecting a resistor RRT from the RT_DIS pin to GND sets the operation frequency. The relation can be roughly expressed in the equation.
fOSC 230kHz + 7700 (kHz) RRT
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When let open, the free running frequency is 230kHz typically. Figure 1 shows the operation frequency vs. RRT for quick reference.
1400 1200 1000
f SW (kHz)
800 600 400 200 0 10 100 1000
RRT (k) (kohm)
Figure 1. RT vs. fsw at Low Frequency Shorting the RT_DIS pin to GND with an external signallevel MOSFET shuts down the device. This allows flexible power sequence control for specified application. The RT_DIS pin threshold voltage is 0.4V typically. VIN1 Detection The RT9259C continuously generates a 10kHz pulse train with 1s pulse width to turn on the upper MOSFET for detecting the existence of VIN1 after VCC12V POR and RT_DIS enabled as shown in Figure 2. PHASE pin voltage is monitored during the detection duration. If the PHASE voltage crosses 1.5V four times, VIN1 existence is recognized and the RT9259C initiates its soft start cycle as described in next section.
VIN1 POR_H PHASE_M
+ 1.5V
PHASE UGATE 1st 2nd 3rd 4th PHASE waveform Internal Counter will count (VPHASE > 1.5V) four times (rising & falling) to recognize VIN1 is ready.
Figure 2
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RT9259C
Soft Start for Synchronous Buck Converter A built-in soft-start is used to prevent surge current from power supply input during power on (referring to the Functional Block Diagram). The error amplifier EA is a threeinput device. SSE or VREF1 whichever is smaller dominates the behavior non-inverting input. The internal soft start voltage SSE linearly ramps up to about 4V after VIN1 existence is recognized with about 2ms delay. According, the output voltage ramps up smoothly to its target level. The rise time of output voltage is about 2ms as shown in Figure 3. VREF1 takes over the behavior EA when SSE > VREF1. SSE is also used for LDO soft start. LDO input voltage VIN2 MUST be ready before SSE starts to ramp up. Otherwise UVP function of LDO may be triggered and shut down the RT9259C.
LGATE (10V/Div) UGATE (20V/Div) RT_DIS (500mV/Div) UGATE (20V/Div) VOUT1 (500mV/Div) LGATE (10V/Div) COMP (500mV/Div) VOUT1 (1V/Div) Time (10ms/Div) Time (1ms/Div) UGATE (20V/Div)
VIN1 = 12V to 0V
FB (500mV/Div)
VOUT (20V/Div) Time (10ms/Div)
Figure 4. UVP triggered by FB
VIN2 = 0V
Figure 5. UVP Hiccups Triggered by FBL Over Current Protection The RT9259C senses the current flowing through lower MOSFET for over current protection (OCP) by sensing the PHASE pin voltage as shown in the Functional Block Diagram. A 40uA current source flows through internal 20k ROCSET to PHASE pin causes 0.8V voltage drop across the resistor. OCP is triggered if the voltage at PHASE pin (drop of lower MOSFET VDS) is lower than -0.4V when low side MOSFET conducting. Accordingly inductor current threshold for OCP is a function of conducting resistance of lower MOSFET RDS(ON) as :
IOCSET = 40 A x R OCSET (20k ) - 0.4V = 0.4V RDS(ON) RDS(ON)
Figure 3 : Start Up by RT_DIS Under Voltage Protection The voltages at FB and FBL pin are monitored for under voltage protection (UVP) after the soft start is completed. UVP is triggered if one of the feedback voltages is under (50% x VREFX) with a 30us delay. As shown in Figure 4, the RT9259C PWM controller is shut down when VFB drops lower than the UVP threshold. In Figure 5, the RT9259C shuts down after 4 time UVP hiccups triggered by FBL.
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RT9259C
If MOSFET with RDS(ON) = 16m is used, the OCP threshold current is about 25A. Once OCP is triggered, the RT9259C enters hiccup mode and re-soft starts again. The RT9259C shuts down after 4 time OCP hiccups. A well-designed compensator regulates the output voltage to the reference voltage VREF with fast transient response and good stability. In order to achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. The goal of the compensation network is to provide adequate phase margin (greater than 45 degrees) and the highest 0dB crossing frequency. It is also recommended to manipulate loop frequency response that its gain crosses over 0dB at a slope of -20dB/dec.
VIN OSC Driver L Driver PHASE COUT ESR ZFB COMP EA + REF ZIN
Inductor Current (20A/Div)
VOSC
PWM Comparator +
VOUT
Time (2.5ms/Div)
Figure 6. Shorted then Start Up
IL (20A/Div)
C2 C1
ZFB R2 C3
ZIN R3 R1
VOUT
LGATE (5V/Div) UGATE (5V/Div)
COMP EA + REF
FB
Time (5s/Div)
Figure 7. Shorted then Start Up (Extended Figure 3) Feedback Compensation The RT9259C is a voltage mode controller. The control loop is a single voltage feedback path including a compensator and modulator as shown Figure 8. The modulator consists of the PWM comparator and power stage. The PWM comparator compares error amplifier EA output (COMP) with oscillator (OSC) sawtooth wave to provide a pulse-width modulated (PWM) with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter LOUT and COUT. The output voltage (VOUT) is sensed and fed to the inverting input of the error amplifier.
Figure 8. Closed Loop 1) Modulator Frequency Equations The modulator transfer function is the small-signal transfer function of VOUT/VCOMP (output voltage over the error amplifier output. This transfer function is dominated by a DC gain, a double pole, and a zero as shown in Figure 10. The DC gain of the modulator is the input voltage (VIN) divided by the peak to peak oscillator voltage VOSC. The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. The resonant frequency of the LC filter expressed as : 1 fLC = 2 L OUT x C OUT
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RT9259C
The ESR zero is contributed by the ESR associated with the output capacitance. Note that this requires that the output capacitor should have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor expressed as follows : 1 fESR = 2 x COUT x ESR 2) Compensation Frequency Equations The compensation network consists of the error amplifier and the impedance networks ZC and ZF as shown in Figure 9.
ZF C1 ZC R2 C2 R1 VOUT
but often jeopardize the system stability. In order to cancel one of the LC filter poles, place the zero before the LC filter resonant frequency. In the experience, place the zero at 75% LC filter resonant frequency. Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The second pole is placed at half the switching frequency. Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature 125C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) - TA ) / JA
EA + COMP VREF
FB RF
Where T J(MAX) is the maximum operation junction temperature 125C, TA is the ambient temperature and the JA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT9259C, where T J(MAX) is the maximum junction temperature of the die (125C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance JA is layout dependent. For VQFN-16L 4x4 packages, the thermal resistance JA is 54C/W on the standard JEDEC 51-7 four-layers thermal test board. The maximum power dissipation at TA = 25C can be calculated by following formula :
Compensation Gain
Figure 9. Compensation Loop
fZ1 =
fP1 =
1 2 x R2 x C2
1 2 x R2 x C1 x C2 C1 + C2
80 80 Loop Gain 60 40 40 20
Gain (dB)
PD(MAX) = ( 125C - 25C ) / 54C/W = 1.852 W for QFN-16L 4x4 packages PD(MAX) = ( 125C - 25C) / 100C/W = 1.000 W for SOP-14 packages PD(MAX) = ( 125C - 25C ) / 110C/W = 0.909 W for SSOP-16 packages
0
0
Modulator -20 Gain
-4040
-6060 1H 0z 10db(vo) v
10z 0H v b c m 2100l ) d(op) vb o d(
1k 10k Feuny rqec Frequency (Hz)
10H .Kz
1Kz 0H
100k
10H 0Kz
10H .Mz
1M
Figure 10. Bode Plot Figure 10 shows the DC-DC converter's gain vs. frequency. The compensation gain uses external impedance networks ZC and ZF to provide a stable, high bandwidth loop. High crossover frequency is desirable for fast transient response,
The maximum power dissipation depends on operating ambient temperature for fixed TJ (MAX) and thermal resistance JA. For RT9259C packages, the Figure 11 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed.
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RT9259C
2
Maximum Power Dissipation (W)
4-Layers PCB QFN-16L 4x4
1.75 1.5 1.25 1 0.75 0.5 0.25 0 0 25 50 75 100 125
SOP-14
SSOP-16
The power components and the PWM controller should be placed firstly. Place the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to the power switches. Place the output inductor and output capacitors between the MOSFETs and the load. Also locate the PWM controller near by MOSFETs. A multi-layer printed circuit board is recommended. Figure 12 shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each of them represents numerous physical capacitors. Use a dedicated grounding plane and use vias to ground all critical components to this layer. Apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the PHASE node, but it is not necessary to oversize this particular island. Since the PHASE node is subjected to very high dV/dt voltages, the stray capacitance formed between these islands and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal routing. The PCB traces between the PWM controller and the gate of MOSFET and also the traces connecting source of MOSFETs should be sized to carry 2A peak currents.
IQ1 5V/12V Q1 IQ2
+ +
Ambient Temperature (C)
Figure 11. Derating Curves for RT9259C Packages PCB Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency and radiate noise, that results in over-voltage stress on devices. Careful component placement layout and printed circuit design can minimize the voltage spikes induced in the converter. Consider, as an example, the turn-off transition of the upper MOSFET prior to turn-off, the upper MOSFET was carrying the full load current. During turn-off, current stops flowing in the upper MOSFET and is picked up by the low side MOSFET or schottky diode. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selections, layout of the critical components, and use shorter and wider PCB traces help in minimizing the magnitude of voltage spikes. There are two sets of critical components in a DC-DC converter using the RT9259C. The switching power components are most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current.
IL VOUT
+
LOAD
Q2 GND
UGATE
GND LGATE VCC RT9259C FB
Figure 12. The connections of the critical components in the converter
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DS9259C-03 August 2007
RT9259C
Outline Dimension
A
H M
J
B
F
C I D
Symbol A B C D F H I J M
Dimensions In Millimeters Min 8.534 3.810 1.346 0.330 1.194 0.178 0.102 5.791 0.406 Max 8.738 3.988 1.753 0.508 1.346 0.254 0.254 6.198 1.270
Dimensions In Inches Min 0.336 0.150 0.053 0.013 0.047 0.007 0.004 0.228 0.016 Max 0.344 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050
14- Lead SOP Plastic Package
DS9259C-03 August 2007
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RT9259C
c D L
E
E1
e
A A1 b
A2
Symbol A A1 A2 b C D e E E1 L
Dimensions In Millimeters Min 1.346 0.102 1.499 0.203 0.178 4.801 0.635 5.791 3.810 0.406 6.198 3.988 1.270 0.305 0.254 5.004 Max 1.753 0.254
Dimensions In Inches Min 0.053 0.004 0.059 0.008 0.007 0.189 0.025 0.228 0.150 0.016 0.244 0.157 0.050 0.012 0.010 0.197 Max 0.069 0.010
16-Lead SSOP Plastic Package
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DS9259C-03 August 2007
RT9259C
SEE DETAIL A L
1
D
D2
E
E2
1
1 2
e A A1 A3
b
2
DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.
Symbol A A1 A3 b D D2 E E2 e L
Dimensions In Millimeters Min 0.800 0.000 0.175 0.250 3.950 2.000 3.950 2.000 0.650 0.500 0.600 Max 1.000 0.050 0.250 0.380 4.050 2.450 4.050 2.450
Dimensions In Inches Min 0.031 0.000 0.007 0.010 0.156 0.079 0.156 0.079 0.026 0.020 0.024 Max 0.039 0.002 0.010 0.015 0.159 0.096 0.159 0.096
V-Type 16L QFN 4x4 Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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