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| AN331 COMPE N S A T I N G T H E FE E D B A C K L O O P Si3400 A N D Si 3 4 0 1 1. Introduction The Si3400 and Si3401 reference designs are available for many output voltages (e.g., 3.3, 5, 9, 12 V) and output capacitor types. In general, Silicon Laboratories strongly recommends using these standard designs to minimize risk and ensure robust performance. Refer to the design databases posted on the Si3400/01 documentation page on the Silicon Labs website for more information: EVB Data Sheets Si3400-EVB Si3401-EVB Si3400ISO-EVB Si3401ISO-EVB FOR THE EVB Reference Design Databases (Schematics and Layout) Si3400-EVB Si3401-EVB Si3400ISO-EVB Si3401ISO-EVB However, some designers may want to consider other cases of output filtering, input filtering, inductors, etc. for a variety of reasons (cost, footprint, availability, etc.). While it would be desirable to use circuit simulation to optimize the feedback loop, it is very difficult to get reliable information about important factors such as capacitor ESR. Also, the stabilizing effect of the input side hot-swap switch and input filter ESR must be taken into account, which is not straightforward for commonly available SPICE implementations. For these reasons, the feedback loop must be experimentally optimized if a known reference design is not used. The application note outlines the general process for compensating the feedback loop experimentally. In case a predefined compensation and output filter is not used, it is strongly recommended that this procedure be followed to ensure robust performance. 1.1. Breaking the feedback loop The feedback loop is broken and a transformer is used to inject an ac signal across the break. Using a transformer allows the loop stability to be measured in a closed loop system with whatever load a filtering is present. The loop is broken at the output and at the point sensing the output voltage. The transformer ac and dc impedance must be small compared to the impedance sensing the output voltage. Figures 1 and 2 show the recommended transformer placement for the non-isolated and isolated reference designs. Rev. 0.1 9/07 Copyright (c) 2007 by Silicon Laboratories AN331 C2 C5 Connect diode and input filter caps together minimizing area of return loop and then connect to Vpos plane. R5 2.87K 2.87K 1u C1 1u C3 1u C4 1u C4 R1 1000u 12uF R6 8.66K NP NP C6 C6 R2 1 2 C20 C20 22uF 22uF 12 13 14 15 12 13 14 15 3.3n 16 15 17 18 19 C9 0.33u 150p VSS1 SWO Vposs VSS2 11 10 7 8 13 CT2 Si3400 7 SSFT Vdd ISOSSFT SP1 SP2 Vneg RCL HSO RDET PLOSSb 4 R8 CT1 2 3 9 9 8 2 D15 2 D14 D13 2 D13 1000p 1000p 1000p 1000p 2 D12 1000p 11 10 12 Vposf 11 C10 C11 C12 C12 S1B 1 S1B 1 S1B S1B 1 9 8 7 6 C18 0.1u D9 R3 D11 2 D11 2 D10 2 1000p 1000p 1000p 1000p 2 C14 C14 C15 C16 S1B S1B 1 S1B 1 S1B 1 Optional bypass diodes for >10W applications are in parallel with C10-C17 S1B 1 C17 1000p 0 Vneg is a thermal plane as wel as ESD and EMI. Use thermal vias to at least 1 inch square plane on backside 1 to 1.2mm pitch 0.3 to 0.33mm diameter. Figure 1. Non-Isolated R4 25.5K 300 ohms 2 300 ohms 1 2 L2 300 ohms 2 300 ohms D8 1 45.3 Rev. 0.1 L5 1 L3 10 5 1 L4 2 S1B 1 MagJack C13 0 R7 5 14 5 1 EROUT J5 HEADER 1 J6 HEADER 1 J7 HEADER 1 J8 HEADER 1 J9 HEADER 1 C8 100n U1 1 C19 4 Vssa 30.1K 4 1 FB RT RT 3 Vstim 3 1 20 C7 50 50 2 J11 Vpos is a EMI and ESD plane. Use top layer. 1 CON1 AN331 330 D1 PDS5100 Vout L1 33uH J12 J1 49.9K Test points NP 1 CON1 Vin 1 2 2 1 1 1 TX1 C19 Vpos is a EMI and ESD plane. Use top layer. 1000p 10:4 secondary T1 J11 D3 - Cathode pad dimensions 9.4mm x 7.2mm Anode pad dimensions 2.7mm x 1.6mm. J3 J4 HEADER 1 Vout pos plane for EMI 12,13 must be isolated from 14,15 330 1 1 6 1 HEADER 1 Connect transformer and input filter caps together minimizing area of return loop and then connect to Vpos plane. R1 anode D3 1 2 1uH L1 CON1 anode 49.9K 5 4 3 1 56 4 37 18 7 8 12 13 14 1u C1 1u C1 1u C3 1u C4 12 13 14 15 D2 DFLT15A DFLT15A RDP COILCRAFT C7 470p R10 10 12uF 12uF 1N4148W J1 15 D1 R2 C2 C2 PDS1040 2 29 10 100u C6 9 10 C5 1000u CMAX Vout J12 1 2 3 16 15 18 17 4 Vssa VSS1 SWO Vposs VSS2 5 1 14 CT1 SSFT CT2 Vdd Vposf ISOSSFT SP1 SP2 Vneg RCL HSO RDET PLOSSb 1u TDN TDP RDN CT 1 1 1 1 FB U1 Vssa 1 2 19 20 1 TX1 CON1 Vstim RT R11 4.99K 100n 100n R8 U2 C22 C22 R7 2.05K 10K C23 220n R5 36.5K C8 560p R9 3.01k 3 Vin 1 2 3 4 5 7 EROUT 13 12 11 J5 HEADER 1 J6 HEADER 1 J7 HEADER 1 J8 HEADER 1 J9 HEADER 1 11 10 7 9 9 11 10 8 8 S1B 2 1000p S1B S1B 2 1000p S1B 2 D15 1 C10 D14 D14 1 C11 D13 1 1 L4 9 8 7 6 5 Si3400 R12 100 2 10 C12 C12 D12 1 L5 C13 MagJack 1000p 1000p S1B 2 1000p R3 45.3 45.3 C21 1000p 1000p S1B 2 S1B S1B 2 1000p S1B 2 1000p S1B S1B 2 1000p 0.1u C17 C18 R4 25.5K 25.5K C15 C15 D9 1 D11 D11 1 C14 D10 1 C16 D8 D8 1 Rev. 0.1 0 Vneg is a thermal plane as well as ESD and EMI. Use thermal vias to at least 1 inch square plane on backside 1 to 1.2mm pitch 0.3 to 0.33mm diameter. 4 3 4 3 1 2 1 2 PS2911 Opto U3 Vssa C20 1000p C9 15n R6 12.1K 1 300 ohms 1 2 L3 300 ohms 1 2 L2 300 ohms 2 300 ohms 3 2 31 2 1 TLV431 Capacitors C10-C17 are for ESD immunity.. Place optional bypass diodes for high power applications (>10W) in parallel. Figure 2. Isolated 50 4 AN331 3 AN331 A commercially available phase gain meter optimized for power supply analysis is available from Venable Inc. The Venable meter can be used with an injection transformer from Venable, or an ordinary transformer can be used as long as it keeps a low ac and dc impedance. Good results have also been achieved with a Bode 100 phase gain meter from Omicron Labs and using Coilcraft BU15-7521ROBL common mode choke hooked up as a transformer (input on 1,2 output on 3,4). When terminated with a 50 resistor on the input side, this transformer gives <100 impedance on the output side from dc to well over 10 MHz insuring that the transformer itself does not impact the feedback loop. Other phase gain meters can be used as long as they are capable of operating in the 100 Hz to 40 kHz range of interest and have a provision for high impedance (1 M) probes. The phase-gain meter is used to measure the output voltage response to the input voltage that is stimulated by the transformer (see Figure 3). The magnitude and phase of the voltage (VSTIM) that the transformer produces is not critical. It should be large enough that the signals can be measured but not so large that there is distortion. In practice, a signal level of -20 to -30 dBm (50 reference) has been found to be satisfactory. The magnitude and phase of the ratio of the output voltage the input voltage is what needs to be measured to examine loop stability. In general it is good practice to have at least 50 degrees of phase margin when the gain is unity (zero dB) and 10 dB of gain margin when the phase reaches zero degrees. VIN VSTIM VOUT Figure 3. Phase and Gain of VOUT with Respect to VIN Experimental results for the standard isolated and non-isolated reference designs are shown in Figures 4 and 5 (see also AN296). 4 Rev. 0.1 AN331 dB 60 40 20 0 -20 -40 -60 -80 200 500 1000 2000 5000 10000 20000 150 100 50 0 -50 -100 -150 -200 f/Hz magnitude(Gain) in dB phase(Gain) in Figure 4. Gain and Phase for Non-Isolated Design dB 60 40 20 0 -20 -40 -60 -80 200 500 1000 2000 5000 10000 20000 150 100 50 0 -50 -100 -150 -200 f/Hz magnitude(Gain) in dB phase(Gain) in Figure 5. Gain and Phase of Isolated Design 1.2. Optimizing the feedback loop Generally, the feedback loop should be checked over the entire input voltage and load range. In practice, the maximum input voltage and maximum load is generally the worst case corner. Building in some margin for gain and phase allows for variation in components and temperature. In the case of the isolated design, a gain sorted optocoupler should be used to avoid a lot of gain variation from the opto-coupler. Also, for designs that operate at very low (-40 C) temperature and use electrolytic capacitors in the filter path, it is desirable to check at low temperature because electrolytic capacitors have substantial variation in ESR at low temperature. A low or negative gain and phase margin can give power supply output oscillation and the feedback loop crossover frequency should be reduced. An excessively large gain and phase margin means that better transient response could be obtained by increasing the crossover frequency. For the non-isolated design, the dominant pole is set by C7. A zero is introduced by R7-C7, and an optional second zero is introduced by C20-R6. The zeros in the transfer function are used to compensate for the poles introduced by the output filter and extend the frequency response of the feedback loop. The R7-C7 zero should be placed at somewhat less than the desired loop bandwidth in order to contribute the most phase boost. For example, in the Rev. 0.1 5 AN331 non-isolated reference design the R7-C7 zero is at 1.6 kHz and the loop bandwidth is about 4 kHz. C19 introduces a final pole which is required to filter noise that can be coupled to the ERout node. If used, the C20-R6 zero is placed at about the loop bandwidth (not below) so as to maximize the phase boost prior to the pole from C20-R5// R6. The optimization process for the non-isolated design is as follows: 1. R5 and R6 are fixed to set the desired output voltage (see http://www.silabs.com/public/documents/tpub_doc/ othertpubs/Wireline/High_Voltage/en/Si3400SwitcherCalcs.xls 2. Vary C7 to move the crossover frequency up and down. 3. R7 is increased to reduce the C7-R7 zero to 1/2 to 1/3 of the loop bandwidth. 4. If used, C20 is set so that C20-R6 is equal to the loop bandwidth. 5. If the phase margin and gain margin are too big or too small go back to step 2 and change C7 up (not enough margin) or down (too much margin and not enough bandwidth). For the isolated design, the C21-R11 pole compensates the zero introduced by C9 and R8+R6//R5. Therefore, the zeros of concern for loop stability are C21-R12 and C8-R5. As in the non-isolated design these zeros (in this case 7.8 kHz and 7.2 kHz) are placed at around the desired loop bandwidth (7 kHz) so as to maximize the phase boost. In this case both zeros are placed near the loop bandwidth because it is desirable to minimize R12 to reduce noise at ERout. The optimization process for the isolated design is as follows: 1. R5 and R6 are fixed to set the desired output voltage (see http://www.silabs.com/public/documents/tpub_doc/ othertpubs/Wireline/High_Voltage/ R8 is set to 10 k, R11 is set to 4.99 k and R7 is set according to the output voltage (1 k at 3.3 V 2.05 k at 5 V and 4.99 k at 9 or 12 V for example). R9 is generally set to approximately 3.01 k. 2. Vary C9 and C21 to move the crossover frequency up and down. Generally, C9 and C11 are kept as a ratio and C9 is < 1/4 of C21. 3. R12 is increased so that R12 x C21 is less than or equal to the loop bandwidth subject to the constraint that R12 <1K to filter any noise at ERout. 4. C8 is increased so that C8 x R5 is approximately equal to the loop bandwidth. 5. If the phase margin and gain margin are too big or too small, go back to step 2 and change C9 and C21 (in the same ratio) up (not enough margin) or down (too much margin and not enough bandwidth). 2. Conclusions To ensure robust performance in cases where a predefined compensation and output filter are not used, the application note outlines the general process required for experimentally compensating the Si3400/01 feedback loop. Refer to the Si3400/01 Evaluation Board User's Guides and reference designs for complete schematics for common output voltages and output filter configurations. 6 Rev. 0.1 AN331 NOTES: Rev. 0.1 7 AN331 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: PoEinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 8 Rev. 0.1 |
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