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CYK256K16MCCB MoBL3TM
4-Mbit (256K x 16) Pseudo Static RAM
Features
* Wide voltage range: 2.70V-3.30V * Access time: 55 ns, 60 ns and 70 ns * Ultra-low active power -- Typical active current: 1 mA @ f = 1 MHz -- Typical active current: 8 mA @ f = fmax (70-ns speed) * Ultra low standby power * Automatic power-down when deselected * CMOS for optimum speed/power * Offered in a 48-ball BGA package can be put into standby mode when deselected (CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE LOW) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE LOW) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the truth table for a complete description of read and write modes.
Functional Description[1]
The CYK256K16MCCB is a high-performance CMOS Pseudo static RAM organized as 256K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
256K x 16 RAM Array
SENSE AMPS
I/O0 - I/O7 I/O8 - I/O15
COLUMN DECODER
BHE WE CE OE BLE
Power- Down Circuit
A11 A12 A13 A14 A15 A16 A17
BHE BLE
CE
Note: 1. For best practice recommendations, please refer to the CY application note System Design Guidelines on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05585 Rev. *F
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised October 18, 2006
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CYK256K16MCCB MoBL3TM
Pin Configuration[2, 3, 4]
VFBGA
Top View 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15
NC
2 OE BHE I/O10 I/O11
3 A0 A3 A5 A17
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
6 NC I/O0 I/O2 Vcc Vss I/O6 I/O7
NC
A B C D E F G H
I/O12 DNU I/O13
NC
A14 A12 A9
A8
Product Portfolio
Power Dissipation Operating ICC(mA) VCC Range (V) Product CYK256K16MCCB Min. 2.70 Typ.[5] 3.0 Max. 3.30 Speed (ns) 55 60 70 8 15 f = 1MHz Typ.[5] 1 Max. 5 f = fmax Typ.[5] 14 Max. 22 Standby ISB2(A) Typ.[5] 17 Max. 40
Notes: 2. Ball H1, G2 and ball H6 for the VFBGA package can be used to upgrade to an 8-Mbit, 16-Mbit and 32-Mbit density, respectively. 3. NC "no connect" - not connected internally to the die. 4. DNU (Do Not Use) pins have to be left floating or tied to Vss to ensure proper application. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
Document #: 38-05585 Rev. *F
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CYK256K16MCCB MoBL3TM
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied ........................................... -55C to + 125C Supply Voltage to Ground Potential ................ -0.4V to 4.6V DC Voltage Applied to Outputs in High-Z State[6, 7, 8] ....................................... -0.4V to 3.7V DC Input Voltage[6, 7, 8] ....................................-0.4V to 3.7V Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature -25C to +85C VCC 2.70V to 3.30V
Electrical Characteristics Over the Operating Range
CYK256K16MCCB -55, 60, 70 Parameter VCC VOH VOL VIH VIL IIX IOZ ICC Description Supply Voltage Output HIGH Voltage IOH = -0.1 mA Output LOW IOL = 0.1 mA Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VIN < VCC GND < VOUT < VCC, Output Disabled f = fMAX = 1/tRC VCC = VCCmax IOUT = 0 mA CMOS levels VCC = 2.70V VCC = 2.70V 0.8 * Vcc -0.4 -1 -1 14 for -55 14 for -60 8 for -70 150 Test Conditions Min. 2.7 VCC - 0.4 0.4 VCC + 0.4V 0.6 +1 +1 22 for -55 22 for -60 15 for -70 250 Typ.[5] 3.0 Max. 3.3 Unit V V V V V A A mA
f = 1 MHz ISB1 Automatic CE Power-Down Current--CMOS Inputs
1 for all speeds 5 for all speeds
mA A
CE > VCC-0.2V VCC = 3.3V VIN > VCC-0.2V, VIN < 0.2V) f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = 3.30V CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.30V VCC = 3.3V
ISB2
Automatic CE Power-Down Current--CMOS Inputs
17
40
A
Thermal Resistance[9]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA/JESD51. BGA 55 17 Unit C/W C/W
Capacitance[9]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max. 8 8 Unit pF pF
Notes: 6. VIL(MIN) = -0.5V for pulse durations less than 20 ns. 7. VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns. 8. Overshoot and undershoot specifications are characterized and are not 100% tested. 9. Tested initially and after any design or process changes that may affect these parameters.
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CYK256K16MCCB MoBL3TM
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE Parameters R1 R2 RTH VTH R2 VCC GND 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Rise Time = 1 V/ns Equivalentto:
THEVENIN EQUIVALENT RTH OUTPUT VTH Unit V
3.0V VCC 22000 22000 11000 1.50
Switching Characteristics Over the Operating Range[10]
55 ns[14] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE tSK[14] Write Cycle tWC tSCE tAW tHA tSA tPWE
[12]
60 ns Min. 60 Max.
70 ns Min. 70 60 70 10 60 25 70 35 5 25 25 5 25 60 25 70 5 10 5 25 10 70 60 55 0 0 45 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to LOW OE HIGH to High CE LOW to Low Z[11, 13] Z[11, 13]
Min. 55
Max.
55 5 55 25 5 25 2 25 55 5 10 0 55 45 45 0 0 40 60 45 45 0 0 40 5 2 5 8
Z[11, 13]
CE HIGH to High Z[11, 13] BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Address Skew Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Z[11, 13] BLE/BHE HIGH to HIGH Z[11, 13]
Notes: 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 12. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 13. High-Z and Low-Z parameters are characterized and are not 100% tested. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.
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CYK256K16MCCB MoBL3TM
Switching Characteristics Over the Operating Range[10] (continued)
55 ns[14] Parameter tBW tSD tHD tHZWE tLZWE Description BLE/BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to High-Z[11, 13] 5 WE HIGH to Low-Z[11, 13] Min. 50 25 0 25 5 Max. 50 25 0 25 5 60 ns Min. Max. 55 25 0 25 70 ns Min. Max. Unit ns ns ns ns ns
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[14, 15, 16] tRC ADDRESS
tSK
tOHA
tAA DATA VALID
DATA OUT
PREVIOUS DATA VALID
Read Cycle 2 (OE Controlled)[14, 16]
ADDRESS
tSK
tRC tHZCE tACE
CE
BHE/BLE
tLZBE
OE
tDBE
tHZBE
t DOE DATA OUT VCC SUPPLY CURRENT
Notes: 15. Device is continuously selected. OE, CE = VIL. 16. WE is HIGH for Read Cycle.
tHZOE HIGH IMPEDANCE ICC ISB
t LZOE HIGH IMPEDANCE tLZCE 50%
DATA VALID
50%
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CYK256K16MCCB MoBL3TM
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[12, 13, 17, 18, 19] t WC ADDRESS tSCE
CE
tAW tSA
WE
tHA tPWE
BHE/BLE
tBW
OE
tSD DATA I/O
DON'T CARE
tHD
VALID DATA tHZOE
Write Cycle 2 (CE Controlled)[12, 13, 17, 18, 19]
t WC ADDRESS tSCE CE
tSA
tAW tPWE
tHA
WE tBW
BHE/BLE
OE t HZOE DATA I/O
DON'T CARE
tSD VALID DATA
tHD
Notes: 17. Data I/O is high-impedance if OE > VIH. 18. If Chip Enable goes INACTIVE with WE = VIH, the output remains in a high-impedance state. 19. During this period in the DATA I/O waveform, the I/Os could be in the output state and input signals should not be applied.
Document #: 38-05585 Rev. *F
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CYK256K16MCCB MoBL3TM
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)[18, 19] tWC ADDRESS tSCE
CE
BHE/BLE
tBW tAW tSA tPWE t HA
WE
tSD DATAI/O
DON'T CARE
tHD
VALID DATA t HZWE t LZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18, 19] tWC ADDRESS
CE tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O
DON'T CARE
tHA tBW
tHD
VALID DATA
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CYK256K16MCCB MoBL3TM
Truth Table [20]
CE H X L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H H L L L L H Inputs/Outputs High Z High Z Data Out (I/O0 - I/O15) Data Out (I/O0 - I/O7); High Z (I/O8 - I/O15) High Z (I/O0 - I/O7); Data Out (I/O8 - I/O15) High Z High Z High Z Data In (I/O0 - I/O15) Data In (I/O0 - I/O7); High Z (I/O8 - I/O15) High Z (I/O0 - I/O7); Data In (I/O8 - I/O15) Mode Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 55 60 70 Ordering Code CYK256K16MCCBU-55BVI CYK256K16MCBU-55BVXI CYK256K16MCCBU-60BVI CYK256K16MCCBU-70BVI CYK256K16MCBU-70BVXI
Note: 20. H = Logic HIGH, L = Logic LOW, X = Don't Care.
Package Diagram
Package Type 48-ball Fine Pitch BGA (6 mm x 8mm x 1.0 mm) (Pb-Free)
Operating Range Industrial Industrial Industrial
51-85150 48-ball Fine Pitch BGA (6 mm x 8mm x 1.0 mm) 51-85150 48-ball Fine Pitch BGA (6 mm x 8mm x 1.0 mm) 51-85150 48-ball Fine Pitch BGA (6 mm x 8mm x 1.0 mm) 48-ball Fine Pitch BGA (6 mm x 8mm x 1.0 mm) (Pb-Free)
Document #: 38-05585 Rev. *F
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CYK256K16MCCB MoBL3TM
Package Diagram
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
TOP VIEW
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B
A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C
51-85150-*D
SEATING PLANE 0.26 MAX. C 1.00 MAX
MoBL is a registered trademark, and More Battery Life and MoBL3 are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05585 Rev. *F
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CYK256K16MCCB MoBL3TM
Document History Page
Document Title: CYK256K16MCCB MoBL3TM4-Mbit (256K x 16) Pseudo Static RAM Document Number: 38-05585 REV. ** *A *B *C *D *E ECN NO. Issue Date 223482 234474 260330 298651 314013 397852 See ECN See ECN See ECN See ECN See ECN See ECN Orig. of Change REF SYT PCI PCI RKF SYT New data sheet Changed ball E3 on package pinout from NC to DNU Changed from preliminary to final Added 60-ns speed bin Added Pb-Free parts to the Ordering information Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Changed typo in ordering code from CYK256K16MCCB to CYK256K16MCCBU in the "Ordering Information" on Page#8 Updated the revision of package diagram of Spec 51-85150 from *B to *D Changed VIL Max spec from 0.4 V to 0.6 V in DC Electrical Characteristics table Description of Change
*F
522566
See ECN
NXR
Document #: 38-05585 Rev. *F
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