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| HM6268 Series 4096-word x 4-bit High-Speed CMOS Static RAM Maintenance only Features * Single 5 V supply and high density 20-pin package * High speed: fast access time 25/35/45 ns (max) * Low power -- Active: 250 mW (typ) -- Standby: 100 W (typ), 5 W (typ) (L-version) * Completely static memory: no clock or timing strobe required * Equal access and cycle times * Directly TTL compatible--all inputs and outputs * Battery back-up operation capability (L-version) Pin Arrangement A4 A5 A6 A7 A8 A9 A10 A11 CS VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC A3 A2 A1 A0 I/O1 I/O2 I/O3 I/O4 WE (Top view) Ordering Information Type No. HM6268P-25 HM6268P-35 HM6268P-45 HM6268LP-25 HM6268LP-35 HM6268LP-45 Access time 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns Package 300-mil 20-pin, plastic DIP (DP-20N) Note: This device is not available for new application. 1 HM6268 Series Block Diagram HM6268 Series A10 A4 A5 A6 A7 A8 I/O1 I/O2 I/O3 I/O4 A0 A1 A2 A3 A11 A9 Input data control Row decoder Memory array 64 x 256 VCC VSS Column I/O Column decoder CS WE Truth Table CS H L L WE x H L Mode Not Selected Read Write VCC current ISB, ISB1 ICC ICC I/O pin High-Z Dout Din Cycle -- Read cycle Write cycle Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Power dissipation Operating temperature Storage temperature Temperature under bias Note: Symbol VT PT Topr Tstg Tbias Rating -0.5 *1 to +7.0 1.0 0 to + 70 -55 to +125 -10 to + 85 Unit V W C C C 1. -3.5 V for pulse width 10 ns. 2 HM6268 Series Recommended DC Operating Conditions (Ta = 0 to + 70C) Parameter Supply voltage Symbol VCC VSS Input high (logic 1) voltage Input low (logic 0) voltage Note: VIH VIL Min 4.5 0 2.2 -0.5 *1 Typ 5.0 0 -- -- Max 5.5 0 6.0 0.8 Unit V V V V HM6268 Series 1. -3.0 V for pulse width 10 ns. DC Characteristics (VCC = 5 V 10%, VSS = 0 V, Ta = 0 to +70C) Parameter Input leakage current Symbol | ILI | Min -- -- Typ *1 -- -- Max 2.0 Unit A Test condition VCC = 5.5 V, Vin = VSS to VCC CS = VIH, VI/O = VSS to VCC CS = VIL, II/O = 0 mA, min. cycle CS = VIH, min. cycle CS VCC - 0.2 V, 0 V VIN 0.2 V or VCC - 0.2 V VIN IOL = 8 mA IOH = -4.0 mA Output leakage current | ILO | 2.0 A Operating power supply current ICC -- 50 *3 90 mA Standby power supply current ISB -- -- -- 15 0.02 1 *2 25 2.0 50 *2 mA mA A Standby power supply current (1) ISB1 Output low voltage Output high voltage VOL VOH -- 2.4 -- -- 0.4 -- V V Notes: 1. Typical limits are at VCC = 5.0 V, Ta = +25C and specified loading 2. This characteristic is guaranteed only for L-version. 3. 40 mA typical for 45 ns version. Capacitance (Ta = 25C, f = 1.0 MHz) *1 Parameter Input capacitance Input/output capacitance Note: Symbol Test conditions Cin CI/O Vin = 0 V VI/O = 0 V Min -- -- Max 6 9 Unit pF pF 1. These parameters are sampled and not 100% tested. 3 HM6268 Series AC Test Conditions: * * * * Input pulse levels: VSS to 3.0 V Input rise and fall times: 5 ns Input and output timing reference levels: 1.5 V Output load: See figure HM6268 Series AC Characteristics (VCC = 5 V + 10%, Ta = 0 to +70C, unless otherwise noted) Output Load 5V 480 5V 480 Dout 255 Dout 255 30 pF *1 5 pF *1 Output load (A) Output load (B) (tHZ , tLZ, tWZ, and tOW) Note: 1. Including scope and jig Read Cycle HM6268-25 HM6268-35 HM6268-45 ------------ ------------ ------------ Symbol Min Max Min Max Min Max Unit tRC tAA tACS tOH tLZ *1 tHZ *1 25 -- -- 5 -- 25 25 -- 35 -- -- 5 -- 35 35 -- 45 -- -- 5 -- 45 45 -- ns ns ns ns Parameter Read cycle time Address access time Chip select access time Output hold from address change Chip selection to output in low-Z Chip deselection to output in high-Z Chip selection to power up time Chip deselection to power down time Note: 10 0 -- 15 10 0 -- 20 10 0 -- 20 ns ns tPU tPD 0 -- -- 25 0 -- -- 25 0 -- -- 30 ns ns 1. Transition is measured +200 mV from steady state voltage with load (B). These parameters are sampled and not 100% tested. 4 HM6268 Series Read Timing Waveform (1) tRC Address tAA tOH Dout Valid Data tOH HM6268 Series Notes: 1. WE is high for read cycle. 2. Device is continuously selected, CS = VIL Read Timing Waveform (2) tRC CS tLZ tACS tHZ Valid Data tPD 50% High impedance Dout VCC Supply current High impedance tPU ICC ISB 50% Notes: 1. WE is high for read cycle. 2. Address valid prior to or coincident with CS transistion low. 5 HM6268 Series Write Cycle HM6268 Series HM6268-25 HM6268-35 HM6268-45 ------------ ------------ ------------ Symbol Min Max Min Max Min Max Unit tWC tCW tAW tAS tWP tWR tDW tDH tWZ *1 tOW *1 25 20 20 0 20 0 12 0 0 0 -- -- -- -- -- -- -- -- 8 -- 35 30 30 0 30 0 20 0 0 0 -- -- -- -- -- -- -- -- 10 -- 45 40 40 0 35 0 20 0 0 0 -- -- -- -- -- -- -- -- 15 -- ns ns ns ns ns ns ns ns ns ns Parameter Write cycle time Chip selection to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time Write enabled to output in high-Z Output active from end of write Note: 1. Transition is measured +200 mV from steady state voltage with load (B). These parameters are sampled and not 100% tested. 6 HM6268 Series Write Timing Waveform (1) (WE Controlled) tWC Address tCW CS tAW tAS WE tDW Din Valid Data tWZ *3 HM6268 Series tWP *1 tWR *2 tDH *4 *4 tOH *5 Dout High impedance tOW Notes: 1. A write cycle occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. During this period, I/O pins are in the output state so input signals of opposite phase to the outputs must not be applied. 4. If CS is low during this period, I/O pins are in the output state, so data input signals of opposite phase to the outputs must not be applied. 5. Dout has the same phase as write data in this write cycle, if tWR is long enough. 7 HM6268 Series Write Timing Waveform (2) (CS Controlled) HM6268 Series tWC Address tAW tAS CS tWP *1 WE tDW Din Dout Valid Data High impedance *3 tDH tCW tWR *2 Notes: 1. A write cycle occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in a high impedance state. 8 HM6268 Series Low VCC Data Retention Characteristics (0C Ta 70C) These characteristics are guaranteed only for L-version. Parameter VCC for data retention Data retention current Symbol VDR ICCDR Min 2.0 -- Typ -- -- Max -- 30 * 2 20 * 3 -- -- Unit V A HM6268 Series Test conditions CS VCC - 0.2 V, VIN VCC - 0.2 V, or 0 V VIN 0.2 V See retention waveform Chip deselect to data retention time Operation recovery time Notes: 1. Read cycle time 2. VCC = 3.0 V 3. VCC = 2.0 V tCDR tR 2.0 tRC * 1 -- -- ns ns Low VCC Data Retention Waveform Data retention mode VCC 4.5 V tCDR VDR CS VCC - 0.2 V tR 2.2 V VDR CS 0V 9 |
Price & Availability of HM6268LP-25
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