View S2060A_4111668.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
DEVICE SPECIFICATION
GIGABIT ETHERNET TRANSCEIVER GIGABIT ETHERNET TRANSCEIVER GENERAL DESCRIPTION
S2060 S2060
FEATURES
* * * * * * * * * * * * * Operating rate 1250 MHz (Gigabit Ethernet) line rates Half and full VCO output rates Functionally compliant IEEE 802.3z Gigabit Ethernet standard Transmitter incorporating Phase-Locked Loop (PLL) clock synthesis from low speed reference Receiver PLL provides clock and data recovery 10-bit parallel TTL compatible interface Low-jitter serial LVPECL compatible interface Local loopback Single +3.3 V supply, 620 mW power dissipation 64 PQFP or TQFP package Continuous downstream clocking from receiver Drives 30 m of Twinax cable directly
The S2060 transmitter and receiver chip facilitates high speed serial transmission of data over fiber optic, coax, or twinax interfaces. The device conforms to the requirements of the IEEE 802.3z Gigabit Ethernet specification, and runs at 1250.0 Mbps data rates with an associated 10-bit data word. The chip provides parallel-to-serial and serial-to-parallel conversion, clock generation/recovery, and framing for block encoded data. The on-chip transmit PLL synthesizes the high-speed clock from a lowspeed reference. The on-chip receive PLL performs clock recovery and data re-timing on the serial bit stream. The transmitter and receiver each support differential LVPECL compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a +3.3 V power supply and dissipates typically 620 mW. The S2060 can be used for a variety of applications including Gigabit Ethernet, serial backplanes, and proprietary point-to-point links. Figure 1 shows a typical configuration incorporating the chip.
APPLICATIONS
* * * * * Workstation Frame buffer Switched networks Data broadcast environments Proprietary extended backplanes
Figure 1. System Block Diagram
Gigabit Ethernet Controller
Optical Tx S2060 Optical Rx
Optical Rx S2060 Optical Tx
Gigabit Ethernet Controller
March 7, 2001 / Revision H
1
S2060 S2060 OVERVIEW
The S2060 transmitter and receiver provide serialization and deserialization functions for block encoded data to implement a Gigabit Ethernet interface. The S2060 functional block diagram is depicted in Figure 2. The sequence of operations is as follows: Transmitter 1.10-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver 1. Clock and data recovery from serial input 2. Serial-to-parallel conversion 3. Frame detection 4. 10-bit parallel output The 10-bit parallel data input to the S2060 should be from a DC-balanced encoding scheme, such as the 8B/10B transmission code, in which information to be transmitted is encoded 8 bits at a time into 10-bit trans-
GIGABIT ETHERNET TRANSCEIVER
mission characters1. For reference, Table 1 shows the mapping of the parallel data to the 8B/10B codes.
Loop Back
Local loopback provides a capability for performing off-line testing. This is useful for ensuring the integrity of the serial channel before enabling the transmission medium. It also allows for system diagnostics.
1. A.X. Widmer and P.A. Franaszek, "A Byte Oriented DC Balanced (0,4) 8B/10B Transmission Code," IBM Research Report RC 9391, May 1982.
Table 1. Data Mapping to 8B/10B Alphabetic Representation
Data Byte TX[0:9] or RX[0:9] 8B/10B
Alphabetic Representation
0 a
1 b
2 c
3 d
4 e
5 i
6 f
7 g
8 h
9 j
Figure 2. Functional Block Diagram
S2060
TX[0:9] 10 FIFO (4 x 10) 10
Shift Register
TXP TXN
TBC
PLL Clock Multiplier w/ lock detect F0 = F1 x 10
RATEN
2:1
D PLL Clock Recovery w/ lock detect
Shift Register
RXP RXN EWRAP -LCK_REF EN_CDET Control Logic
10 D Q RX[0:9]
COMMA Detect Logic
COM_DET RBC0 RBC1
2
March 7, 2001 / Revision H
GIGABIT ETHERNET TRANSCEIVER TRANSMITTER DESCRIPTION
The S2060 transmitter accepts 10-bit parallel input data and serializes it for transmission over fiber optic or coaxial cable media. The chip is fully compatible with the IEEE 802.3z Gigabit Ethernet standard, and supports the Gigabit Ethernet data rate of 1250.0 Mbps. The S2060 uses a PLL to generate the serial rate transmit clock. The transmitter runs at 10 times the TBC input clock, and operates in either full rate or half rate mode. At the full VCO rate the transmitter runs at 1.25 GHz, while in half rate mode it operates at 625 MHz.
S2060
Transmit Byte Clock (TBC)
The Transmit Byte Clock input (TBC) must be supplied from a clock source with 100 ppm tolerance to assure that the transmitted data meets the Gigabit Ethernet frequency limits. The internal serial clock is frequency locked to TBC (125.00 MHz). TBC may be 62.5 MHz or 125 MHz, determined by the state of the RATEN input. Operating rates are shown in Table 2.
Transmit Latency
The average transmit latency is 4 byte times.
Parallel-to-Serial Conversion
The parallel-to-serial converter takes in 10-bit wide data from the input latch and converts it to a serial data stream. Parallel data is latched into the transmitter on the positive going edge of TBC. The data is then clocked into the serial output shift register. The shift register is clocked by the internally generated bit clock which is 10x the TBC input frequency. TX[0] is transmitted first.
Table 2. Operating Rates
RATEN 0 1 Parallel Input Rate (Mbps) 125 62.5 TBC Frequency (MHz) 125 62.5 Serial Output Rate (Gbps) 1.25 0.625
March 7, 2001 / Revision H
3
S2060 RECEIVER DESCRIPTION
Whenever a signal is present, the receiver attempts to recover the serial clock from the received data stream. The S2060 searches the serial bit stream for the occurrence of a positive polarity COMMA sync pattern (0011111xxx positive running disparity) to perform word synchronization. Once synchronization on both bit and word boundaries is achieved, the receiver provides the decoded data on its parallel outputs.
GIGABIT ETHERNET TRANSCEIVER
propriately and quickly to a loss of signal. The runlength checker flags a condition of consecutive ones or zeros across 12 parallel words. Thus, 119 or less consecutive ones or zeros does not cause signal loss, 129 or more causes signal loss, and 120 - 128 may or may not, depending on how the data aligns across byte boundaries. If both the off-frequency detect test and the run-length test is satisfied, the CRU will attempt to lock to the incoming data. In any transfer of PLL control between the serial data and the reference clock, the RBC0 and RBC1 remain phase continuous and glitch free, assuring the integrity of downstream clocking.
Clock Recovery Function
Clock recovery is performed on the input data stream. A simple state machine in the clock recovery macro decides whether to acquire lock from the serial data input or from the reference clock. The decision is based upon the frequency and run length of the input serial data. The lock to reference frequency criteria ensure that the S2060 will respond to variations in the serial data input frequency (as compared to the reference frequency). The new lock state is dependent upon the current lock state, as shown in Table 3. The runlength criteria ensure that the S2060 will respond ap-
Reference Clock Input
The reference clock must be provided from a low jitter clock source. The frequency of the received data stream must be within 400 ppm of the reference clock to ensure reliable locking of the receiver PLL. A single reference clock is provided to both the transmit and receive PLL's.
Data Output
The S2060 provides either framed or unframed parallel output data, determined by the state of EN_CDET. With EN_CDET held ACTIVE, the S2060 will detect and align to the 8B/10B COMMA codeword anywhere in the data stream. When EN_CDET is INACTIVE, no attempt is made to synchronize on any particular incoming character. The S2060 will achieve bit synchronization within 250 bit times and begin to deliver unframed parallel output data words whenever it has received full transmission words. Upon change of state of the EN_CDET input, the COM_DET output response will be delayed by a maximum of 3 byte times.
Table 3. Lock to Reference Frequency Criteria
Current Lock State PLL Frequency (vs. TBC) < 488 ppm Locked 488 to 732 ppm > 732 ppm < 244 ppm Unlocked 244 to 366 ppm > 366 ppm New Lock State Locked Undetermined Unlocked Locked Undetermined Unlocked
4
March 7, 2001 / Revision H
GIGABIT ETHERNET TRANSCEIVER
The COM_DET output signal is ACTIVE whenever EN_CDET is active and the COMMA control character is present on the RX[0:9] parallel data outputs. The COM_DET output signal will be INACTIVE at all other times.
S2060
Fibre Channel and Gigabit Ethernet Standards require that the COMMA sync character appears on the rising edge of the RBC1 signal. In full rate mode the phase of the data is adjusted such that this requirement is met. No alignment is necessary when the S2060 is operating in half rate mode since the output clock frequency is equal to the parallel word rate (RATEN INACTIVE). In ethernet applications it is illegal for multiple consecutive COMMA characters to be generated. However, multiple consecutive COMMA characters can occur in serial backplane applications. The S2060 is able to operate properly when multiple consecutive COMMA characters are received: after the first COMMA is detected and aligned, the RBC0/RBC1 clock operates without glitches or loss of cycles. Additionally, COM_DET stays high while multiple COMMAS are being output.
Parallel Output Clock Rate and Data Stretching
The S2060 supports both full rate and half rate outputs, selected via the RATEN input. Table 4 shows the operating rate scenarios. When RATEN is INACTIVE, a data clock is provided on RBC1 at the data rate. Data should be clocked on the rising edge of RBC1. When RATEN is ACTIVE the device is in full rate mode, and complementary TTL clocks are provided on the RBC0 and RBC1 outputs at 1/2 the data rate as required by the Gigabit Ethernet Standard. Data is clocked on the rising edges of both RBC0 and RBC1. See Figures 11 and 12.
Table 4. Operating Rates
RATEN 0 1 Serial Input Rate (Gbps) 1.25 .625 RBC0 (MHz) 62.5 N/A RCB1 (MHz) 62. 5 62.5 Parallel Output Rate (Mbps) 125 62.5
Receive Latency
The average receive latency is 8 byte times.
March 7, 2001 / Revision H
5
S2060
Table 5. Pin Description and Assignment
Pin Name TX[9] TX[8] TX[7] TX[6] TX[5] TX[4] TX[3] TX[2] TX[1] TX[0] TBC Level LVTTL I/O I Pin # 13 12 11 9 8 7 6 4 3 2 22
GIGABIT ETHERNET TRANSCEIVER
Description Transmit Data. Parallel data on this bus is clocked in on the rising edge of TBC. TX[0] is transmitted first.
LVTTL
I
Transmit Byte Clock. Reference clock input to the PLL clock multiplier. The frequency of TBC is the bit rate divided by 10. When TESTEN is active, TBC replaces the VCO clock to facilitate factory test. TBC should be supplied by a crystal controlled reference since jitter on this line directly translates to jitter on the output data. Rate Select. Active Low. This signal configures the PLL's for the appropriate TBC frequency. When inactive, the device is in 1/2 rate mode. When active, the device is in full rate mode. See Tables 2 and 4. Enable Comma Detect. Active High. When active, enables detection of the COMMA sync pattern to set the word frame boundary for the data to follow. When inactive, data is treated as unframed. Enable Wrap. When active, the transmitter serial data outputs are internally routed to the receiver serial data inputs. TXP/N are static (logic 1) in this state. When inactive, the RXP/N serial inputs are selected (normal operation). (Externally Capacitively Coupled.) LVPECL Receive Serial Data Inputs. RXP is the positive differential input, RXN is negative. Internally biased to VCC -1.3 V. Active Low. Lock to Reference Input. When inactive or open, the receive PLL will lock to the incoming data (normal operation). When active, the receive PLL is forced to lock to the TBC input.
RATEN
LVTTL
I
14
EN_CDET
LVTTL
I
24
EWRAP
LVTTL
I
19
RXP RXN -LCK_REF
Diff. LVPECL LVTTL
I
54 52 27
I
6
March 7, 2001 / Revision H
GIGABIT ETHERNET TRANSCEIVER
Table 5. Pin Description and Assignment (Continued)
Pin Name RX[9] RX[8] RX[7] RX[6] RX[5] RX[4] RX[3] RX[2] RX[1] RX[0] RBC1 RBC0 Level LVTTL I/O O Pin # 34 35 36 38 39 40 41 43 44 45 30 31 Description
S2060
Receive Data Outputs. For full rate output, parallel data on this bus is valid on the rising edges of RBC0 and RBC1. RX[0] is the first bit received.
LVTTL
O
Complementary Receive Byte Clocks. In full rate mode, parallel receive data is valid on the rising edges of RBC0 and RBC1 (see Figure 8, timing diagram). For half rate, output data is valid on the rising edge of RBC1. See Table 4. Comma Detect. Active High. When EN_CDET is active, COM_DET indicates that the sync character is present on the parallel bus bits RX[0:9]. Upon detection of the COMMA sync character (0011111xxx positive polarity) this output data is valid on the rising edge of RBC1 and remains active for one RBC1 clock period. When EN_CDET is inactive, COM_DET is held inactive (logic 0). Upon change of state of the EN_CDET input, the COM_DET output response will be delayed by a maximum of 3 byte times. Transmit Serial Data. These lines are static (TXN HIGH, TXP HIGH) when EWRAP is active. These lines are static (TXN HIGH, TXP LOW) when TXRST is active. Upon startup, these outputs are held static (TXN HIGH, TXP LOW) until the TXPLL has locked to the reference clock. Each output can drive 150 to ground.
COM_DET
LVTTL
O
47
TXP TXN
Diff. LVPECL
O
62 61
S2060A, S2060B, S2060D Specific Pins
DNC 16, 17, 48, 49 Not connected. Note that pin 48 cannot be tied high. It must be open or held low.
S2060C Specific Pins
TC1 TC0 16 17 Transmit Capacitor. External capacitor connections for transmitter internal PLL filter. The recommended valueof this external capacitor is 2 nF (a value of 1 nF can also be used). If desired, the external capacitor may be omitted with no loss in performance. Receiver Capacitor. External capacitor connections for receiver internal PLL filter. The recommended value of this external capacitor is 2 nF (a value of 1 nF can also be used). If desired, the external capacitor may be omitted with no loss in performance. Note that pin 48 cannot be tied high. It must be open (as recommended with external capacitor) or held low.
RC0 RC1
48 49
Note: All TTL inputs have internal 15 K pull-up networks.
March 7, 2001 / Revision H
7
S2060
Table 6. Power and Ground Signals
Pin Name ECLVCC ECLVEE ECLIOVCC ECLIOVEE TTLVCC TTLGND AVCC AVEE VCC VEE DNC DNC Level +3.3 V GND +3.3 V GND +3.3 V GND +3.3 V GND +3.3 V GND Pin # 20, 23 Description Core Power Supply
GIGABIT ETHERNET TRANSCEIVER
21, 25, 58 Core Ground 55, 60, 63 LVPECL I/O Power Supply 56, 64 37, 42 32, 46 18, 50 15, 51 5, 10 1, 33 48 26, 28, 29, 53, 57, 59 LVPECL I/O Ground LVTTL Power Supply LVTTL Ground Analog Power Supply Analog Ground Power Ground This pin cannot be tied Low. It should be floated or tied High. Not connected.
8
March 7, 2001 / Revision H
GIGABIT ETHERNET TRANSCEIVER
Figure 3. S2060 Pinout (S2060A, S2060B, S2060D)
S2060
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ECLIOVEE ECLIOVCC TXP TXN ECLIOVCC DNC ECLVEE DNC ECLIOVEE ECLIOVCC RXP DNC RXN AVEE AVCC DNC
Thermal Management
DNC AVCC EWRAP ECLVCC ECLVEE TBC ECLVCC EN_CDET ECLVEE DNC -LCK_REF DNC DNC RBC1 RBC0 TTLGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VEE TX[0] TX[1] TX[2] VCC TX[3] TX[4] TX[5] TX[6] VCC TX[7] TX[8] TX[9] RATEN AVEE DNC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
S2060 TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
DNC COM_DET TTLGND RX[0] RX[1] RX[2] TTLVCC RX[3] RX[4] RX[5] RX[6] TTLVCC RX[7] RX[8] RX[9] VEE
Device
S2060A (10mm 64 PQFP/HS package) S2060B (14mm 64 PQFP package) S2060D (14mm 64 PQFP package with heat spreader)
Package Max Power
1.333 W 1.333 W 1.125 W
ja (Still Air)
45 C/W 45 C/W 40 C/W
jc
15 C/W 15 C/W 15 C/W
March 7, 2001 / Revision H
9
S2060
Figure 4. S2060 Pinout (S2060C)
GIGABIT ETHERNET TRANSCEIVER
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ECLIOVEE ECLIOVCC TXP TXN ECLIOVCC DNC ECLVEE DNC ECLIOVEE ECLIOVCC RXP DNC RXN AVEE AVCC RC1
Thermal Management
TC0 AVCC EWRAP ECLVCC ECLVEE TBC ECLVCC EN_CDET ECLVEE DNC -LCK_REF DNC DNC RBC1 RBC0 TTLGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VEE TX[0] TX[1] TX[2] VCC TX[3] TX[4] TX[5] TX[6] VCC TX[7] TX[8] TX[9] RATEN AVEE TC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
S2060C TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RC0 COM_DET TTLGND RX[0] RX[1] RX[2] TTLVCC RX[3] RX[4] RX[5] RX[6] TTLVCC RX[7] RX[8] RX[9] VEE
Device
S2060C (10mm 64 TQFP package)
Package Max Power
1.154 W
ja (Still Air)
52 C/W
jc
18 C/W
10
March 7, 2001 / Revision H
GIGABIT ETHERNET TRANSCEIVER
Figure 5. 10mm x 10mm 64 PQFP Package (S2060A)
S2060
TOP VIEW
March 7, 2001 / Revision H
11
S2060
Figure 6. 14 mm x 14 mm 64 PQFP Package (S2060B)
GIGABIT ETHERNET TRANSCEIVER
TOP VIEW
12
March 7, 2001 / Revision H
GIGABIT ETHERNET TRANSCEIVER
Figure 7. 10mm x 10mm 64 TQFP Package (S2060C)
S2060
TOP VIEW
March 7, 2001 / Revision H
13
S2060
Figure 8. 14 mm x 14 mm 64 PQFP Package (S2060D)
GIGABIT ETHERNET TRANSCEIVER
TOP VIEW
14
March 7, 2001 / Revision H
GIGABIT ETHERNET TRANSCEIVER
Table 7. Power and Ground Application Information
Function Pin Names Instructions
S2060
AVCC ANALOG AVEE ECLIOVCC LVPECL I/O ECLIOVEE ECLVCC CORE ECLVEE TTLVCC LVTTL I/O TTLVEE
Connect to low noise or filtered +3.3 V supply through a ferrite bead (600 at 100 MHz: Murrata BLM31B601S or equivalent). Provide dual local HF bypassing to AVEE (0.1 F, 100 pF) for low inductance and resistance. A single low inductance 0.1 F capacitor can be substituted for the pair (Vishay VJ0612 or equivalent, <0.5 nH max inductance). Connect to ground plane. Provide low impedance connection to +3.3 V. Provide dual local bypassing to GND plane (0.1 F and 100 pF in parallel, or a single low inductance Vishay VJ0612 or equivalent 0.1 F capacitor). Connect to ground plane. Provide low impedance connection to +3.3 V. Provide dual local bypassing to GND plane (0.1 F and 100 pF in parallel, or a single low inductance Vishay VJ0612 or equivalent 0.1 f capacitor). Connect to ground plane. Provide low impedance connection to +3.3 V. Provide dual local bypassing to GND plane (0.1 F and 100 pF in parallel, or a single low inductance Vishay VJ0612 or equivalent 0.1 F capacitor). Connect to ground plane.
March 7, 2001 / Revision H
15
S2060
Figure 9. Power and Ground Connection Diagram
VCC (+3.3 V) 0.1 F VCC (+3.3 V) 0.1 F
GIGABIT ETHERNET TRANSCEIVER
0.1 F
Vcc (+3.3 V) ferrite 100 pF 100 pF 100 pF 0.1 F
64
ECLIOVcc ECLVee
Vee
VCC (+3.3 V)
49
ECLIOVee ECLIOVcc ECLIOVee ECLIOVcc AVee AVcc
100 pF
1
48
VCC (+3.3 V) 0.1 F
Vcc
Vcc (+3.3 V)
TTLVee TTLVcc
S2060
Vcc AVee
(top view)
TTLVee
TTLVcc
100 pF VCC (+3.3 V) 0.1 F
ECLVcc ECLVee
ECLVee
ECLVcc
100 pF
AVcc
Vee
VCC (+3.3 V) ferrite 100 pF
16 17
0.1 F
33 32
0.1 F
0.1 F
100 pF
100 pF
VCC (+3.3 V)
16
March 7, 2001 / Revision H
GIGABIT ETHERNET TRANSCEIVER
Figure 10. Transmitter Timing
S2060
TBC
TX[0-9] T1 T2
SERIAL DATA OUT
Table 8. S2060 Transmitter Timing
Parameters T1 T2 TSDR, TSDF TJ Description Data Setup w.r.t. TBC Data Hold w.r.t. TBC Serial Data Rise and Fall Serial Data Output total jitter (p-p) Serial Data Output deterministic jitter (p-p) Min 1.2 0.25 Max 270 192 Units ns ns ps ps 20% - 80%, tested on sample basis. Peak-to-peak, measured on sample basis. Measured with K28.5 or 27-1 pattern at 1.25 GHz. Peak-to-peak, tested on a sample basis. Measured with K28.5 pattern at 1.25 GHz. See Note 1. Conditions
TDJ
-
80
ps
1. All AC measurements are made from the reference voltage level of the clock (+1.4 V) to the valid input or output data levels (+.8 V or +2.0 V).
Figure 11. Receiver Timing Full Rate Mode (RATEN Active)
SERIAL DATA IN
RBC0
RBC1
RX[9-0]
comma
T3 T4
SKEW
T3 T4
March 7, 2001 / Revision H
17
S2060
Figure 12. Receiver Timing Half Rate Mode (RATEN Inactive)
GIGABIT ETHERNET TRANSCEIVER
SERIAL DATA IN
RBC1
RX[9-0]
COMMA
T3 T4
T3 T4
Table 9. S2060 Receiver Timing
Parameters T3 T4 TRCR, TRCF Skew TDR, TDF TLOCK (startup) TLOCK (reacquire) Duty Cycle TJ TDJ Description Data valid before Data valid after RBC1 (RBC0) RBC1 (RBC0) Min 3. 0 2.0 7. 5 Data Acquisition Lock Time (1.25G) RBC1 (RBC0) Total Input Jitter Tolerance Deterministic Input Jitter Tolerance 40 59 9 370 250 60 ns % ps ps As specified in IEEE 802.3z. As specified in IEEE 802.3z. Max 2.4 8.5 2.4 2.5 100 Units ns ns ns ns ns s ns 90% input data eye (see Figure 19). 24% input data eye. Measured +.8 V to +2.0 V. Rising edge to rising edge. Measured +.8 V to +2.0 V. Conditions See Note 1.
RBC1, RBC0 Rise and Fall Time RBC1 to RBC0 Skew Data Output Rise and Fall Time Startup acquision lock time (1.25G)
1. All AC measurements are made from the reference voltage level of the clock (+1.4 V) to the valid input or output data levels (+.8 V or +2.0 V).
OTHER OPERATING MODES
Loopback Mode
The S2060 supports internal loopback mode in which the serial data from the transmitter replaces external serial data. The loopback function is enabled when the loopback enable signal, EWRAP, is set ACTIVE. The loopback mode provides the ability to perform system diagnostics and to perform off-line testing of the interface to guarantee the integrity of the serial channel before enabling the transmission medium. Figure 13 shows the basic loopback operation.
Figure 13. Loopback Operation
output disabled CSU
CRU
18
March 7, 2001 / Revision H
GIGABIT ETHERNET TRANSCEIVER
Table 10. Absolute Maximum Ratings
The following are the absolute maximum stress ratings for the S2060 device. Stresses beyond those listed may cause permanent damage to the device. Absolute maximum ratings are stress ratings only and operation of the device at the maximums stated or any other conditions beyond those indicated in the "Recommended Operating Conditions" of the document are not inferred. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
S2060
Parameter Case Temperature Under Bias Junction Temperature Under Bias Storage Temperature Voltage on VCC with Respect to GND Voltage on any TTL Input Pin except TBC Voltage on TBC Voltage on any LVPECL Input Pin TTL Output Sink Current TTL Output Source Current
Min -40 -55 -65 -0.5 -0.5 0 0
Typ
Max 125 130 150 +4.0 5.0 VCC VCC 8 8
Units C C C V V V V mA mA
Table 11. Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Junction Temperature Under Bias Voltage on TTLVCC, ECLVCC, ECLIOVCC, and AVCC with respect to GND/VEE Voltage on any TTL Input Pin except TBC Voltage on any LVPECL Input Pin Voltage on TBC
1. Commercial temperature range S2060A, S2060B, S2060C. 2. Industrial temperature range S2060D.
Min 01 -402
Typ
Max 701 852 130
Units C C V V V V
3.135 0 VCC -2.0 0
3.3 VCC
3.465 5.0 VCC VCC
March 7, 2001 / Revision H
19
S2060
Table 12. Reference Clock Requirements
Parameters FT TD1-2 TRCR, TRCF JR Description Frequency Tolerance Symmetry REFCLK Rise and Fall Time Random Jitter Min -100 40 Max +100 60 2 100
GIGABIT ETHERNET TRANSCEIVER
Units ppm % ns ps
Conditions
Duty Cycle at 50% pt. 20% - 80%. Peak to Peak.
Table 13. DC Characteristics
Parameters VOH VOL VIH VIL IIH IIL ICC PD VDIFF VOUT CIN Description Output High Voltage (TTL) Output Low Voltage (TTL) Input High Voltage (TTL) Input Low Voltage (TTL) Input High Current (TTL) Input High Current (TTL) Supply Current Power Dissipation Min. differential input voltage swing for differential LVPECL inputs Serial Output Differential Voltage Swing Input Capacitance 100 1200 2000 187 620 Min 2.4 GND 2.0 GND Typ 2.8 0.1 Max VCC 0.4 VCC 0.8 40 600 235 820 2200 2200 3 Units V V V V A A mA mW mV mV pF 150 to ground. VIN = 2.4 V, VCC = Max VIN = 0.0 V, VCC = Max Outputs open, square pattern. Outputs open, square pattern. Comments VCC = min, IOH = 4 mA VCC = min, IOL = 1 mA
20
March 7, 2001 / Revision H
GIGABIT ETHERNET TRANSCEIVER
OUTPUT LOAD
The S2060 serial outputs require a resistive load to set the output current. The recommended resistor value is 150 to ground. This value can be varied to adjust drive current, signal voltage swing, and power usage on the board.
S2060
Figure 17. High Speed Differential Inputs
Vcc - 1.3 V 0.01 F
ACQUISITION TIME
With the input eye diagram shown in Figure 19, the S2060 will recover data with a 10E-9 BER within the time specified by TLOCK in Table 9 after an instantaneous phase shift of the incoming data.
100
0.01 F
Figure 14. Serial Input Rise and Fall Time
80% 50% 20% Tr Tf 80% 50% 20%
Figure 18. Receiver Input Eye Diagram Jitter Mask
Bit Time
Amplitude
Figure 15. TTL Input/Output Rise and Fall Time
+2.0 V +0.8 V Tr Tf +2.0 V +0.8 V
24%
Figure 16. Serial Output Load
Figure 19. Acquisition Time Eye Diagram
1.3
Normalized Amplitude
1.0 0.8 0.7 0.5 0.3 0.2 0.0
0.0 0.1 0.3 0.4 0.6 0.7 0.9 1.0
0.01 F 150
150
0.01 F
Normalized Time
March 7, 2001 / Revision H
21
S2060
Ordering Information
PREFIX DEVICE
GIGABIT ETHERNET TRANSCEIVER
PACKAGE A-(64 PQFP 10mm) Commercial Temp Range B-(64 PQFP 14mm) Commercial Temp Range C-(64 TQFP 10mm) Commercial Temp Range, loop filter pins option D-(64 PQFP 14mm) Industrial Temp Range
S- Integrated Circuit
206 0
X Prefix
XXXX Device
X Package
IS
O 90 0
D
1
IFI
Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 2001 Applied Micro Circuits Corporation D50/R476
E
CE
RT
22
March 7, 2001 / Revision H

▲Up To Search▲

Price & Availability of S2060A

	To Download S2060A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .