View TB62726AFNA_4111005.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TOSHIBA
TB62726AFNA
16-bit constant current LED driver with operating supply of 3.3V to 5V
TB62726AFNA
Data Sheet Version No. 001 002 003 004 005 006 007 008 009 Date 2002-4-26 2002-5-15 2002-5-21 2002-5-28 2002-6-1 2002-6-22 2002-10-1 2002-10-11 2002-11-6 Note Target spec by AFNA The setup of the tentative Spec of Iout Evaluation set of Iout Spec. The reflection of the test Spec. Some of proofreading Some of proofreading A format is changed. IOUT Spec. reexamination Final Spec. Inspect
We agree this specification. Company Signature Date
TB62726AFNA(Ver.9) 2002,Nov.6th page00/11
TOSHIBA
TB62726AFNA
TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
TB62726AFNA
16-bit constant current LED driver with operation supply of 3.3V to 5V
The TB62726AFNA is comprised of constant-current drivers designed for LEDs and LED displays. The output current value can be set using an external resistor. As a result, all outputs will have virtually the same current levels. This driver incorporates a 16-bit constant-current output, a 16-bit shift register, a 16-bit latch and a gate circuit. These drivers have been designed using the Bi-CMOS process.
TB62726AFNA
Feature
*Output current capability and the number of output: 90 mA x 16 outputs *Constant current range : 2 to 90 mA *Application output voltage : 0.7V (output current 2 to 80mA) 0.4V (output current 2 to 40mA) *For anode common LED *Input signal voltage level : 3.3V-5.0V CMOS level (schmitt trigger input) *Power supply voltage range VDD=3.0 to 5.5V *Muximum output terminal voltage 17V *Serial and parallel data transfer rate 20 MHz (min., Cascade Connection) *Operation temperature range topr = -40 to 85 degrees *Package : P-SSOP24-150-0.635 *Current accuracy (not used dot-current correction.)
Output voltage >= 0.4V >= 0.7V Current accuracy between bits +/- 4 % between ICs +/- 12 % Output current 2 to 40 mA 2 to 90 mA
P-SSOP24-150-0.635
TB62726AFNA (Ver.9) 2002, Nov. 5th page 1/11
TOSHIBA
Package and pin layout ( Top view )
OUT14 OUT15 ENABLE SERIAL-OUT R-EXT VDD GND SERIAL-IN CLOCK LATCH OUT0 OUT1 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2
TB62726AFNA
Warnings : Short-circuiting an output terminal to GND or to the power supply terminal may broken the device. Please take care when wiring the output terminals, the power supply terminal and the GND terminals.
Block Diagram
OUT0 R-EXT I-REG OUT1 OUT15
ENABLE Q ST D LATCH Q ST D Q ST D
SERIAL-IN
DQ CK
DQ CK
DQ CK
SERIAL-OUT
CLOCK
Truth Table
CLOCK Positive edge Positive edge Positive edge Negative edge Negative edge LATCH H L H X X ENABLE L L L L H SERIAL-IN Dn Dn+1 Dn+2 Dn+3 Dn+3 OUT0 --- OUT7 --- OUT15 Dn --- Dn-7 --- Dn-15 No Change Dn+2 --- Dn-5 --- Dn-13 Dn+2 --- Dn-5 --- Dn-13 Off SERIAL-OUT Dn-15 Dn-14 Dn-13 Dn-13 Dn-13
Note 1: OUT0~OUT15=ON when Dn=H ; OUT0~OUT15=OFF when Dn=L In order to ensure that the level of the power supply voltage is correct, an external resistor have to connected between R-EXT and GND.
TB62726AFNA (Ver.09) 2002, Nov. 6th page 2/11
TOSHIBA
Timing diagram
n=01 2 3 4 5 6 7 8 9 101112131415 CLOCK
TB62726AFNA
5V 0V 5V 0V 5V 0V 5V 0V On Off On Off On Off
SERIAL-IN
LATCH
ENABLE
OUT0
OUT1
OUT3
OUT15
On Off 5V 0V
SERIAL-OUT
Warning : Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit. Note 2 : The latches circuit holds data by pulling the LATCH terminal Low. And, when LATCH terminal is a High-level, latch circuit doesn't hold data, and it passes from theInput to the output. When ENABLE terminal is Low-level, output terminal OUT0~OUT15 respond to the data, and on & off does. And, when ENABLE terminal is a High-level, it offs with the output terminal regardless of the data.
TB62726AFNA (Ver.09) 2002, Nov. 6th page 3/11
TOSHIBA
Terminal description
Pin No. 7 8 9 10 1 to 2, 11 to 24 3 4 5 6 Pin Name GND SERIAL-IN CLOCK LATCH
TB62726AFNA
Function GND terminal for control logic Input terminal for serial data for data shift register Input terminal for clock for data shift on rising edge Input terminal for data strobe When the LATCH=High-level, data is no latched. When ithe LATCH=Low-level, data is latched. Constant-current output terminals
OUT 0 to 7 Input terminal for output enable. All outputs (OUT0 ~ OUT15 ) are turned off, when the ENABLE=High-level. And are turned on, when the ENABLE=Low-level. SERIAL-OUT Output terminal for serial data input on SERIAL-IN terminal R-EXT Input terminal used to connect an external resistor. This regulated the output current. VDD 3.3V - 5V supply voltage terminal. ENABLE
Equivalent circuit of inputs and output
1. ENABLE Terminal VDD ENABLE GND 3. CLOCK,SERIAL-IN Terminal VDD CLOCK, SERIAL - IN GND 5. OUT0 to 15 Terminal OUT 0 to 15
Parasitic Diode
2. LATCH Terminal
R(UP) 200k
VDD LATCH GND
250k R(DOWN)
4. SERIAL-OUT Terminal VDD Internal data GND SERIAL - OUT
GND
TB62726AFNA (Ver.09) 2002, Nov. 6th page 4/11
TOSHIBA
Absolute maximum ratings
Characteristics Supply Voltage Input Voltage Output Current Output Voltage Power Dissipation Thermal Resistance Operating Temperature Storage Temperature Symbol VDD VIN IOUT VOUT Pd1 Rth(j-a) Topr Tstg Rating +6 -0.2 to VDD+0.2 +90 -0.2 to 17 0.89 140 (Free Air) -40 to 85 -55 to 150
TB62726AFNA
Unit V mA/ch V W degree/W degree
Note 3 : Subtract 7.10mW/degree every time an ambient temperature exceeds 25 times once.
Recommended operating condition ( VDD=4.5~5.5V, Topr = -40~85 degree, unless otherwise noted. )
Characteristics Supply Voltage Output Voltage Output Current Symbol VDD VOUT(On) IOUT IOH IOL Input Voltage Clock Frequency LATCH Pulse Width CLOCK Pulse Width ENABLE Pulse Width When the pulse of the Low level is inputted to the ENABLE terminal held in the H level. Setup Time for CLOCK Terminal Hold Time for CLOCK Terminal Setup Time for /LATCH Terminal VIH VIL fCLK tw LATCH tw CLOCK Upper IOUT=20mA tw ENABLE Lower IOUT=20 mA t SETUP1 t HOLD t SETUP2 50 3000 10 10 ns Cascade Connected Condition Each DC 1 Circuit SERIAL-OUT Min 3 2 0.7xVDD -0.15 50 25 2000 Typ 0.7 Max 5.5 4 80 -1 1 VDD+0.15 0.3xVDD 20 Unit V V mA/ch mA V MHz
TB62726AFNA (Ver.09) 2002, Nov. 6th page 5/11
TOSHIBA
Electrical characteristics ( VDD=3V to 5.5V, Topr=25degree unless otherwise noted.)
Characteristics Supply voltage Symbol VDD IOUT1 IOUT2 IOUT3 IOUT4 dIOUT1 dIOUT2 IOZ VIN VOL VOH %/VDD R(UP) R(DOWN) IDD(OFF)1 IDD(OFF)2 IDD(OFF)3 Condition Normal operation VOUT=0.4V,VDD=3.3V REXT= VOUT=0.4V,VDD=5V 490 ohm VOUT=0.7V,VDD=3.3V REXT= VOUT=0.7V,VDD=5V 250 ohm VOUT=0.4V, REXT=490 ohm All output ON VOUT=0.4V, REXT=250 ohm VOUT=15V IOL=+1 mA, Vdd=3.3V IOL=+1 mA, Vdd=5V IOH=-1 mA, Vdd=3.3V IOH=+1 mA,Vdd=5V When VDD is changed 3V to 5.5V ENABLE terminal LATCH terminal REXT=Open, VOUT=15V REXT=490ohm All output OFF, VOUT=15V REXT=250ohm All output ON, REXT=490ohm VOUT=0.7V Ta= -40degree, Same as the avobe. All output ON, REXT=250ohm VOUT=0.7V Ta= -40 degree, Same as the avobe. Min 3.0 31.96 31.59 63.63 62.75
TB62726AFNA
Output current
Typ 36.20 35.90 72.30 71.30
Max 5.5 40.54 40.20 80.97 79.95
Unit V
mA
Output current error between bits Output leakage Current Input voltage Input voltage
-
+/-1
+/-4
%
0.7VDD GND .3 4.7 . 115 .1 .4 -
-1 230 0.1 3.5 6 9 18 -
1 VDD 0.3VDD 0.3 0.3 -5 460 0.5 5 9 15 20 25 40
uA V
SOUT terminal Voltage Output current supply voltage regulation Pull up resistor Pull down resistor
V
%/V
Supply current
IDD(ON)1
Ohm
IDD(ON)2
TB62726AFNA (Ver.09) 2002, Nov. 6th page 6/11
TOSHIBA
Switching characterictics (Topr=25degree, unless otherwise noted )
Characteristics Symbol tpLH1 tpLH2 tpLH3 Propagation delay tpLH tpHL1 tpHL2 tpHL3 tpLH Output rise time tor Condition CLK-OUTn, LATCH="H", ENABLE="L" LATCH-OUTn, ENABLE="L" ENABLE-OUTn, LATCH="H" CLK-SERIALOUT CLK-OUTn, LATCH="H", ENABLE="L" LATCH-OUTn, ENABLE="L" ENABLE-OUTn, LATCH="H" CLK-SERIAL-OUT Voltage waveform 10%~90% Min 3 4 40 Typ 150 140 140 6 170 170 170 7 85
TB62726AFNA
Max 300 300 300 340 340 340 150
Unit
ns
tof Output fall time Voltage waveform 90%~10% 40 70 150 Maximum CLK 5 tr rise time us When not on PCB Maximum CLK 5 tf fall time Condition : (Refer to test circuit) Topr=25 degree, VDD=VIH=3.3V and 5V, VOUT=0.7V, VIL=0V,REXT=490ohms, VL=3.0V, RL=60ohms,CL=10.5pF Note 4 : If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing required for data transfer. Please consider the timings carefully.
Test circuit
IDD V ,V
IH
IL
VDD ENABLE CLOCK
OUT0 C
RL
Function Generator
LATCH SERIAL-IN OUT15 SERIAL-OUT GND
L
IOL
Logic input waveform Iref VDD=VIH=3.3V VIL=0V t = t = 10ns
r f
R-EXT
CL
VL
(10% to 90%)
TB62726AFNA (Ver.09) 2002, Nov. 6th page 7/11
TOSHIBA
Timing Waveform
1. CLOCK ,SERIAL-IN, SERIAL-OUT twCLK
TB62726AFNA
CLOCK
50%
50%
SERIAL-IN
50%
t SETUP1 t HOLD
50%
SERIAL-OUT
50%
tpLH / tpHL 2. CLOCK, SERIAL-IN , LATCH, ENABLE, OUTn CLOCK 50%
SERIAL-IN
LATCH
t SETUP2 50% tw LAT
50%
ENABLE
tSETUP3
50%
tw ENA
50%
OUTn tpLH1 / tpHL1 3. OUTn 90% OUTn 10% tOf 10% tOr
50%
tpLH2 / tpHL2
tpLH3 / tpHL3 90%
TB62726AFNA (Ver.09) 2002, Nov. 6th page 8/11
TOSHIBA
Output current vs duty (LEDs turn on rate)
DUTY(%)-IOUT(mA) On PCB Topr= 25 degree VDD=5.0V, Vce=1.0(V), Tj=120(degC max)
TB62726AFNA
DUTY(%)-IOUT(mA) On PCB Topr= 55 degree VDD=5.0V, Vce=1.0(V), Tj=120(degC max)
100 80 60 40 20
TB62726AFNA IOUT(mA) IOUT(mA)
100 80 60 40 20
TB62726AFNA
0
0
20
40
60
80
100
0
0
20
40
60
80
100
DUTY - Turn On Rate (%)
DUTY - Turn On Rate (%)
REXT-IOUT (Topr) VDD=3.3(V), VCE=0.7(V)
IOUT(mA)
IOUT(mA)
100 70 50 30 20 10 7 5
DUTY(%)-IOUT(mA) On PCB Topr= 85 degree VDD=5.0V, Vce=1.0(V), Tj=120(degC max)
100 80 60 40 20
TB62726AFNA
1 100
1000
REXT(Ohms)
10000
0
0
20
40
60
80
100
DUTY - Turn On Rate (%)
Ta(degree) - Pd(w)
1.2
AFNA (On PCB) Power dissipation PD (W/IC)
1 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 60 70 80 90
Ambient Temperature Ta (degree)
TB62726AFNA (Ver.09) 2002, Nov. 6th page 9/11
TOSHIBA
Package dimmension P-SSOP24-150-0.635
TB62726AFNA
TENTATIVE
24
UNIT : Inch
13
0.150 ~ 0.157
1
12
0.0325 REF 0.025 0.337 ~0.344
0.008 ~ 0.012
0.229 ~ 0.244
0.004 ~ 0.010
0.053 ~ 0.068
0.007 ~ 0.009
0.016 ~ 0.0
34
TB62726AFNA (Ver.09) 2002, Nov. 6th page 10/11
TOSHIBA
TB62726AFNA
The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patens or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within spacified operating ranges as set forth in the most recent products spacifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. The products described in the document may include products subject to foreign exchange and foreign trade control laws.
(C) 2000-2002 TOSHIBA CORPORATION ALL RIGHT Reserved
TB62726AFNA (Ver.09) 2002, Nov. 6th page 11/11

▲Up To Search▲

Price & Availability of TB62726AFNA

	To Download TB62726AFNA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .