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| 9M Network Search Engine (NSE) with Dual LA-1 Interface (QDRTM II Interface Compliant) Introduction With the expanding Internet, all levels of the network must become faster. This requires high-speed packet searches, which are essential for routing, but also necessary for higher-level functions such as Quality of Service (QoS) support and access control. To meet this need, IDT has developed network search engines that accelerate packet processing at OC-192 data rates and beyond. Datasheet Brief IDT75K62234 Device Description The 9M NSE with Dual LA-1 interface is intended to work with NPUs having a Look Aside Interface. Multiple devices including the 9M Dual LA-1 NSE can be connected to the same LA-1 interface. Each 9M Dual LA-1 NSE device may be optionally multi-drop cascaded up to four NSE devices. NSE Features External Interfaces 128K x 72 (18M) Data and Mask cells Full Ternary Content Addressable Memory Supports up to 250 Million searches per second Dynamic Database ManagementTM - Configurable Database widths - Databases are selectable per NSE command Programmable Power Management - Only the selected Database consumes power - PowerSave logic provides additional power savings Lookup (Search) Instructions - Standard Lookup - Multi-Hit Lookup - Multi-Database Lookup - Re-Issue Multi-Database Lookup - Simultaneous Multi-Database Lookup Maintenance Features - Per entry aging support with notification - Multi Hit Invalidate - Learn per Database Search with learn - Automatic learning - Duplicate learn prevention per database Multiple return index formats Flexible Associated Data Management - 0, 32, 64, or 128 bits of Associated Data per entry Instruction Completion Notification Multiple contexts per interface Pool of 72-bit Global Mask Registers (shared across contexts) Up to 4 Multi-Drop cascades to a single LA-1 interface Parity support for interfaces and CAM core Pin compatible with 18M NSE with Dual LA-1 interface 35mm x 35mm thermally efficient 900 BGA Package Two independent LA-1(QDRII compliant) interfaces - Frequency range from 133MHz up to 250 MHz - Supports burst of 2 data transfers - Echo clocks supported (CQ, CQ) - Dynamic or programmable output impedance control PCI 2.2 compliant interface - Optimized for NSE management NSE attached associated SRAM glueless ZBT(R) Interface IEEE 1149.1-2001 compliant JTAG Interface Simplified Block Diagram LA-1 Read Control Logic LA-1 Interface LA-1 Write Control Logic 1.5V HSTL LA-1 Read Control Logic LA-1 Interface LA-1 Write Control Logic CAM Core Segment 0 Segment 1 Segment 2 PCI Interface 3.3V TTL Segment n-1 Segment n ZBT Interface 2.5V LVTTL JTAG Interface 2.5V LVTTL 6461 drw00 1 MAY 2004 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. QDRTM II- Quad Data Rate DSC-6461/0A Trademark of Cypress, IDT, Micron, NEC and Samsung). All brands or products are the trademarks or registered trademarks of their respective owners. ZBT (R) and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. LA-1 refers to the approved NPF(www.npforum.org) Look Aside Interface implementation agreement `Look Aside Interface LA-1.0 (www.npforum.org/techinfo/f2001.114.14a.pdf) |
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