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VN5050J-E
Single channel high side driver for automotive applications
Features
Max supply voltage Operating voltage range Max On-State resistance (per ch.) Current limitation (typ) Off state supply current
(1) Typical value with all loads connected
VCC VCC RON ILIMH IS
41V 4.5 to 36V 50 m 19 A 2 A(1)
PowerSSO-12
Application
Main - Inrush current active management by power limitation - Very low stand-by current - 3.0V CMOS compatible input - Optimized electromagnetic emission - Very low electromagnetic susceptibility - In compliance with the 2002/95/EC European directive Diagnostic functions - Open drain status output - On state open load detection - Off state open load detection - Thermal shutdown indication
All types of resistive, inductive and capacitive loads
Description
The VN5050J-E is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). The device detects open load condition both in on and off state, when STAT_DIS is left open or driven low. Output shorted to VCC is detected in the off state. When STAT_DIS is driven high, the STATUS pin is in a high impedance condition.Output current limitation protects the device in overload condition. In case of long duration overload, the device limits the dissipated power to safe level up to thermal shut-down intervention.Thermal shutdown with automatic restart allows the device to recover normal operation as soon as fault condition disappears.
Protections - Undervoltage shut-down - Overvoltage clamp - Output stuck to VCC detection - Load current limitation - Self limiting of fast thermal transients - Protection against loss of ground and loss of VCC - Thermal shut down - Reverse battery protection (see Figure 27) - Electrostatic discharge protection Table 1. Device summary
Package
Order codes Tube PowerSSO-12 VN5050J-E Tape & Reel VN5050JTR-E
September 2007
Rev 2
1/31
www.st.com 31
Contents
VN5050J-E
Contents
1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
3.1.1 3.1.2 Solution 1: resistor in the ground line (RGND only). . . . . . . . . . . . . . . . 20 Solution 2: diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . . . 21
3.2 3.3 3.4 3.5
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MCU I/Os protection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
4
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 5.2 5.3 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
VN5050J-E
List of tables
List of tables
Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and n.c. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC = 13V; Tj = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Status pin (VSD=0V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerSSO-12TM mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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List of figures
VN5050J-E
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 On state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Openload on state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Openload off state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-12 PC Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 24 PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 25 Thermal fitting model of a single channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . . 25 PowerSSO-12TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-12 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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VN5050J-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block diagram
VCC
VCC CLAMP
UNDERVOLTAGE PwCLAMP
GND INPUT STATUS STAT_DIS
DRIVER
OUTPUT ILIM VDSLIM
LOGIC
OPENLOAD ON OPENLOAD OFF OVERTEMP. PwrLIM
Table 2.
Name VCC OUTPUT GND INPUT STATUS STAT_DIS
Pin function
Function Battery connection Power output Ground connection. Must be reverse battery protected by an external diode/resistor network Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state Open drain digital diagnostic pin Active high CMOS compatible pin, to disable the STATUS pin
5/31
Block diagram and pin description Figure 2. Configuration diagram (top view)
VN5050J-E
TAB = Vcc N.C. GND INPUT STATUS_DIS STATUS N.C. 1 2 3 4 5 6 12 11 10 9 8 7 N.C. OUTPUT OUTPUT OUTPUT OUTPUT N.C.
PowerSSO-12
Table 3.
Suggested connections for unused and n.c. pins
Status X N.R.(1) N.C. X X Output X N.R. Input X Through 10K resistor STAT_DIS X Through 10K resistor
Connection / Pin Floating To ground
(1) Not recommended
6/31
VN5050J-E
Electrical specifications
2
Electrical specifications
Figure 3. Current and voltage conventions
IS
VCC
VCC
VF
ISD STAT_DIS VSD IIN INPUT VIN GND IGND STATUS VSTAT ISTAT OUTPUT VOUT IOUT
Note:
VF = VOUT - VCC during reverse battery condition
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.
Table 4.
Symbol VCC - VCC - IGND IOUT - IOUT IIN ISTAT
Absolute maximum ratings
Parameter DC supply voltage Reverse DC supply voltage DC reverse ground pin current DC output current Reverse DC output current DC input current DC status current Maximum switching energy (L=3mH; RL=0; Vbat=13.5V; Tjstart=150C; IOUT = IlimL(Typ.)) Value 41 0.3 200 Internally limited 12 +10 / -1 +10 / -1 +10 / -1 104 Unit V V mA A A mA mA mA mJ
ISTAT_DIS DC status disable current EMAX
7/31
Electrical specifications Table 4.
Symbol
VN5050J-E
Absolute maximum ratings (continued)
Parameter Electrostatic discharge (Human Body Model: R=1.5K; C=100pF) - INPUT - STATUS - STAT_DIS - OUTPUT - VCC Charge device model (CDM-AEC-Q100-011) Junction operating temperature Storage temperature Value Unit
VESD
4000 4000 4000 5000 5000 750 -40 to 150 - 55 to 150
V V V V V V C C
VESD Tj Tstg
2.2
Thermal data
Table 5.
Symbol Rthj-case Rthj-amb
Thermal data
Parameter Thermal resistance junction-case (Max.) (with one channel ON) Thermal resistance junction-ambient (Max.) Value 2.7 See Figure 31 Unit C/W C/W
8/31
VN5050J-E
Electrical specifications
2.3
Electrical characteristics
Values specified in this section are for 8VSymbol VCC VUSD VUSDhyst Power section Parameter Operating supply voltage Undervoltage shutdown Undervoltage shut-down hysteresis On state resistance(2) Clamp voltage IOUT=1A; Tj=25C IOUT=1A; Tj=150C IOUT=1A; VCC=5V; Tj=25C IS=20mA Off State; VCC=13V; Tj=25C; VIN=VOUT=VSENSE=VCSD=0V On State; VCC=13V; VIN=5V; IOUT=0A VIN=VOUT=0V; VCC=13V; Tj=25C VIN=VOUT=0V; VCC=13V; Tj=125C 0 0 -75 41 46 Test conditions Min. 4.5 Typ. 13 3.5 0.5 50 100 65 52 Max. 36 4.5 Unit V V V m m m V
RON Vclamp
IS
Supply current
2(1) 1.9 0.01
5(1) 3.5 3 5 0 0.7
A mA
IL(off1)
Off state output current(2)
A
IL(off2) VF
Off state output current(2) VIN=0V; VOUT=4V Output - VCC diode voltage(2) -IOUT=2A; Tj=150C
V
(1) PowerMOS leakage included. (2) For each channel
Table 7.
Symbol td(on) td(off)
Switching (VCC = 13V; Tj = 25C)
Parameter Turn-on delay time Turn-off delay time Test conditions RL= 6.5 (see Figure 5) RL= 6.5 (see Figure 5) RL= 6.5 RL= 6.5 RL= 6.5 (see Figure 5) RL= 6.5 (see Figure 5) Min. Typ. 20 35 see Figure 21 see Figure 23 0.2 0.2 Max. Unit s s V/ s V/ s mJ mJ
dVOUT/dt(on) Turn-on voltage slope dVOUT/dt(off) Turn-off voltage slope WON WOFF Switching energy losses during twon Switching energy losses during twoff
9/31
Electrical specifications Table 8.
Symbol VSTAT ILSTAT CSTAT VSCL
VN5050J-E
Status pin (VSD=0V)
Parameter Status low output voltage Status leakage current Status pin input capacitance Status clamp voltage Test conditions ISTAT= 1.6 mA, VSD=0V Normal Operation or VSD=5V, VSTAT= 5V Normal Operation or VSD=5V, VSTAT= 5V ISTAT= 1mA ISTAT= -1mA 5.5 -0.7 Min Typ Max 0.5 10 100 7 Unit V A pF V V
Table 9.
Symbol IlimH IlimL TTSD TR TRS THYST tSDL VDEMAG
Protections (1) Parameter DC Short circuit current Short circuit current during thermal cycling Shutdown temperature Reset temperature Thermal reset of STATUS Thermal hysteresis (TTSD-TR) Status delay in overload conditions Turn-off output voltage clamp Output voltage drop limitation Tj>TTSD (see Figure 4) IOUT=2A; VIN=0; L=6mH IOUT = 0.1A; Tj= -40C...+150C (see Figure 6) Test conditions VCC=13V 5V7 175
TRS + 1 TRS + 5 135
VON
25
mV
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles
10/31
VN5050J-E Table 10.
Symbol IOL tDOL(on)
Electrical specifications Openload detection
Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Test conditions VIN = 5V ,8VtPOL
Delay between INPUT falling edge and STATUS = 0A (see Figure 4) I rising edge in Openload OUT condition Openload OFF State Voltage Detection Threshold Output Short Circuit to VCC Detection Delay at Turn Off VIN = 0V, 8V200
500
1000
s
VOL
2
See Figure 19
4
V
tDSTKON
(see Figure 4)
180
tPOL
s
Table 11.
Symbol VIL IIL VIH IIH VI(hyst) VICL VSDL ISDL VSDH ISDH VSD(hyst) VSDCL
Logic input
Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current VIN = 2.1 V Input Hysteresis Voltage Input Clamp Voltage STAT_DIS low level voltage Low level STAT_DIS current STAT_DIS high level voltage High level STAT_DIS current STAT_DIS hysteresis voltage STAT_DIS clamp voltage ISD=1mA ISD=-1mA VSD = 2.1 V 0.25 5.5 -0.7 7 VSD = 0.9 V 1 2.1 10 IIN = 1mA IIN = -1mA 0.25 5.5 -0.7 0.9 7 VIN =0.9 V 1 2.1 10 Test conditions Min. Typ. Max. 0.9 Unit V A V A V V V V A V A V V V
11/31
Electrical specifications Figure 4. Status timings
VN5050J-E
OPEN LOAD STATUS TIMING (without external pull-up) VIN IOUT < IOL VOUT < VOL
OPEN LOAD STATUS TIMING (with external pull-up) VIN IOUT < IOL VOUT > VOL
VSTAT tDOL(on) tPOL
VSTAT tDOL(on)
OUTPUT STUCK TO VCC VIN IOUT > IOL VOUT > VOL
OVER TEMP STATUS TIMING Tj > TTSD VIN
VSTAT tDOL(on) tDSTKON
VSTAT tSDL tSDL
Table 12.
Truth Table
Truth table
Input L H L H L H L H L H L H Output L H L X L L L L H H L H Status (VSD=0V)(1) H H H H H L X X Lv H H(2) L
Conditions Normal operation Current limitation Overtemperature Undervoltage Output voltage > VOL Output current < IOL
(1) If the VSD is high, the STATUS pin is in a high impedance. (2) The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
12/31
VN5050J-E Figure 5. Switching characteristics
VOUT
tWon tWoff
Electrical specifications
80% dVOUT/dt(on) tr 10%
90% dVOUT/dt(off) tf t
INPUT td(on) td(off)
t
Figure 6.
Output voltage drop limitation
Vcc-Vout
Tj=150oC Tj=25oC Tj=-40oC
Von Iout
Von/Ron(T)
13/31
Electrical specifications Table 13.
ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b(2) ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b(2) III C C C C C C III -75V +37V -100V +75V -6V +65V
VN5050J-E
Electrical transient requirements
Test levels IV -100V +50V -150V +100V -7V +87V Number of pulses or test times 5000 pulses 5000 pulses 1h 1h 1 pulse 1 pulse Test level results(1) IV C C C C C C Burst cycle/pulse repetition time 0.5 s 0.2 s 90 ms 90 ms 5s 5s 100 ms 100 ms Delays and Impedance 2 ms, 10 50 s, 2 0.1 s, 50 0.1 s, 50 100 ms, 0.01 400 ms, 2
(1) The above test levels must be considered referred to VCC = 13.5V except for pulse 5b (2) Valid in case of external load dump clamp: 40V maximum referred to ground.
Class C E
Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
14/31
VN5050J-E Figure 7. Waveforms
NORMAL OPERATION INPUT STAT_DIS LOAD CURRENT STATUS UNDERVOLTAGE VCC INPUT STAT_DIS LOAD CURRENT STATUS undefined
VUSDhyst VUSD
Electrical specifications
OPEN LOAD with external pull-up INPUT STAT_DIS LOAD VOLTAGE STATUS OPEN LOAD without external pull-up INPUT STAT_DIS LOAD VOLTAGE LOAD CURRENT STATUS IOUTtPOL
VOL
VOUT>VOL
RESISTIVE SHORT TO Vcc, NORMAL LOAD INPUT STAT_DIS LOAD VOLTAGE STATUS
tDSTKON
IOUT>IOL
VOUT>VOL
VOL
OVERLOAD OPERATION Tj INPUT STAT_DIS LOAD CURRENT STATUS
ILIMH ILIML TR TTSD TRS
current power limitation limitation
thermal cycling SHORTED LOAD NORMAL LOAD
15/31
Electrical specifications
VN5050J-E
2.4
Figure 8.
Iloff1 (uA)
1 0.875 0.75 0.625 0.5 0.375 0.25
Electrical characteristics curves
Off state output current Figure 9.
lih (uA)
5 4.5
High level input current
Off state Vcc= 13V Vin= Vout= 0V
4 3.5 3 2.5 2 1.5 1
Vin= 2.1V
0.125 0 -50 -25 0 25 50 75 100 125 150 175
0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
Figure 10. Input clamp voltage
Vicl (V)
8 7.75
Figure 11. Input high level
Vih (V)
4 3.5
lin= 1mA
7.5 7.25 7 6.75 6.5 6.25 6 -50 -25 0 25 50 75 100 125 150 175 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
Figure 12. Input low level
Vil (V)
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Figure 13. Input hysteresis voltage
Vihyst (V)
2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
16/31
VN5050J-E
Electrical specifications
Figure 14. Status low output voltage
Vstat (V)
0.9 0.8
On state resistance vs Tcase
Ron (mOhm)
100 90
I stat= 1.6mA
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 175
80 70 60 50 40 30 20 10 0 -50 -25
I out= 2A Vcc= 13V
0
25
50
75
100
125
150
175
Tc (C )
Tc (C )
Figure 15. Status leakage current
Ilstat (uA)
0.055
Figure 16. On state resistance vs VCC
Ron (mOhm)
100 90
0.05
80
Tc= 150C Tc= 125C
Vstat= 5V
0.045
70 60
0.04
50 40
Tc= 25C Tc= -40C
0.035
30 20 10
0.03
0.025 -50 -25 0 25 50 75 100 125 150 175
0 0 5 10 15 20 25 30 35 40
Tc (C )
Vcc (V)
Figure 17. Status clamp voltage
Vscl (V)
9 8.5 8 7.5 7 6.5 6 5.5 5 4.5 4 -50 -25 0 25 50 75 100 125 150 175
Figure 18. Openload on state detection threshold
Iol (mA)
100 90
I stat= 1mA
80 70 60 50 40 30 20 10 0 -50 -25
Vin= 5V
0
25
50
75
100
125
150
175
Tc (C )
Tc (C )
17/31
Electrical specifications
VN5050J-E
Figure 19. Openload off state voltage detection Figure 20. ILIM vs Tcase threshold
Vol (V)
5 4.5
Ilimh (A)
25 22.5
Vin= 0V
4 3.5 3 2.5 2 1.5 1 -50 -25 0 25 50 75 100 125 150 175
Vcc= 13V
20 17.5 15 12.5 10 7.5 5 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
Figure 21. Turn-on voltage slope
dVout/dt(on) (V/ms)
1000 900 800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175
Figure 22. Undervoltage shutdown
Vusd (V)
14
Vcc= 13V RI 6.5Ohm =
12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
Figure 23. Turn-off voltage slope
dVout/dt(off) (V/ms)
1000 900 800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175
Figure 24. STAT_DIS clamp voltage
Vsdcl(V)
14
Vcc= 13V RI 6.5Ohm =
12
I sd= 1mA
10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
18/31
VN5050J-E
Electrical specifications
Figure 25. High level STAT_DIS voltage
Vsdh(V)
8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175
Figure 26. Low level STAT_DIS voltage
Vsdl(V)
8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
19/31
Application information
VN5050J-E
3
Application information
Figure 27. Application schematic
+5V
+5V VCC Rprot STAT_DIS
Dld Rprot C OUTPUT Rprot STATUS GND INPUT
VGND
RGND DGND
3.1
3.1.1
GND protection network against reverse battery
Solution 1: resistor in the ground line (RGND only).
This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. 2. RGND 600mV / (IS(on)max). RGND (- CC) / (-IGND) V
where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
20/31
VN5050J-E
Application information
3.1.2
Solution 2: diode (DGND) in the ground line.
A resistor (RGND=1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift ( 600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
MCU I/Os protection:
If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k . Recommended values: Rprot =10k .
3.4
Open load detection in off state
Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1. no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RL2.
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in standby.
21/31
Application information
VN5050J-E
The values of VOLmin, VOLmax and IL(off2) are available in the Electrical characteristics section. Figure 28. Open load detection in off state
V batt. VCC RPU INP UT DRI VER + LOGI C OUT + S TATUS VOL R IL(off2) VPU
RL
G ROUND
22/31
VN5050J-E
Application information
3.5
Maximum demagnetization energy (VCC = 13.5V)
Figure 29. Maximum turn off current versus inductance
100
A B C
10
I (A) 1 0,1 1 L (mH) 10 100
A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL =0 .In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
23/31
Package and PCB thermal data
VN5050J-E
4
4.1
Package and PCB thermal data
PowerSSO-12 thermal data
Figure 30. PowerSSO-12 PC Board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 31. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(C/ W)
70 65 60 55 50 45 40 0 2 4 6 8 10
PCB Cu heatsink area (cm^ 2)
24/31
VN5050J-E
Package and PCB thermal data Figure 32. PowerSSO-12 thermal impedance junction ambient single pulse
ZTH (C/W)
100
Footprint 2 cm2 8 cm2
10
1
0,1 0,0001
0,001
0,01
0,1 1 Time (s)
10
100
1000
Equation 1: pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = tP/T Figure 33. Thermal fitting model of a single channel HSD in PowerSSO-12(a)
(a )The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered
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Package and PCB thermal data Table 14. Thermal parameter
Footprint 0.6 2.8 6.5 10 22 26 0.001 0.0025 0.022 0.2 0.27 3 0.1 0.8 6 10 15 20 2
VN5050J-E
Area/island (cm2) R1 (C/W) R2 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C)
8
9 10 15
0.1 1 9
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VN5050J-E
Package information
5
5.1
Package information
ECOPACK(R) packages
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
Package mechanical data
Figure 34. PowerSSO-12TM package dimensions
27/31
Package information Table 15. PowerSSO-12TM mechanical data
millimeters Symbol Min A A1 A2 B C D E e H h L k X Y ddd 5.800 0.250 0.400 0 2.200 2.900 1.250 0.000 1.100 0.230 0.190 4.800 3.800 0.800 Typ
VN5050J-E
Max 1.620 0.100 1.650 0.410 0.250 5.000 4.000
6.200 0.500 1.270 8 2.800 3.500 0.100
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VN5050J-E
Package information
5.3
Packing information
Figure 35. PowerSSO-12 tube shipment (no suffix)
B C
A
Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) All dimensions are in mm.
100 2000 532 1.85 6.75 0.6
Figure 36. PowerSSO-12 tape and reel shipment (suffix "TR")
REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2
End
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
29/31
Revision history
VN5050J-E
6
Revision history
Table 16.
Date 30-Mar-2006
Document revision history
Revision 1 Initial release. Document reformatted and restructured. Contents and lists of tables and figures added. Figure 2: Configuration diagram (top view) updated: pins 1-6-712 N.C. (not connected). Table 4: Absolute maximum ratings: EMAX entries updated. Table 13: Electrical transient requirements :Test level values III and IV for test pulse 5b and notes updated. Section 3.5: Maximum demagnetization energy (VCC = 13.5V) added. Figure 33: Thermal fitting model of a single channel HSD in PowerSSO-12 : note added Table 15: PowerSSO-12TM mechanical data : slug dimensions (X,Y) corrected Changes
13-Sep-2007
2
30/31
VN5050J-E
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