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PD - 96103
IRF7303QPBF
HEXFET(R) Power MOSFET
l l l l l l l l
Advanced Process Technology Ultra Low On-Resistance Dual N Channel MOSFET Surface Mount Available in Tape & Reel 150C Operating Temperature Automotive [Q101] Qualified Lead-Free
S1 G1 S2 G2
1 2
8 7
D1 D1 D2 D2
VDSS = 30V RDS(on) = 0.050
3 4
6 5
Top View
Description
Specifically designed for Automotive applications, these HEXFET(R) Power MOSFET's in a Dual SO-8 package utilize the lastest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of these Automotive qualified HEXFET Power MOSFET's are a 150C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. The efficient SO-8 package provides enhanced thermal characteristics and dual MOSFET die capability making it ideal in a variety of power applications. This dual, surface mount SO-8 can dramatically reduce board space and is also available in Tape & Reel.
SO-8
Absolute Maximum Ratings
Parameter
ID @ TA = 25C ID @ TA = 25C ID @ TA = 70C IDM PD @TA = 25C V GS dv/dt TJ, TSTG 10 Sec. Pulsed Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Junction and Storage Temperature Range
Max.
5.3 4.9 3.9 20 2.0 0.016 20 5.0 -55 to + 150
Units
A W W/C V V/ns C
Thermal Resistance Ratings
Parameter
RJA Maximum Junction-to-Ambient
Typ.
Max.
62.5
Units
C/W
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1
07/23/07
IRF7303QPBF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient V(BR)DSS RDS(ON) VGS(th) g fs IDSS IGSS Qg Q gs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. 30 1.0 5.2 Typ. 0.032 6.8 21 22 7.7 4.0 6.0 520 180 72 Max. Units Conditions V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 1mA 0.050 VGS = 10V, ID = 2.4A 0.080 VGS = 4.5V, ID = 2.0A V VDS = VGS, ID = 250A S VDS = 15V, ID = 2.4A 1.0 VDS = 24V, VGS = 0V A 25 VDS = 24V, V GS = 0V, TJ = 125 C 100 VGS = 20V nA -100 VGS = - 20V 25 ID = 2.4A 2.9 nC VDS = 24V 7.9 VGS = 10V, See Fig. 6 and 12 VDD = 15V ID = 2.4A ns RG = 6.0 RD = 6.2, See Fig. 10 nH pF
D
Between lead tip and center of die contact VGS = 0V VDS = 25V = 1.0MHz, See Fig. 5
G S
Source-Drain Ratings and Characteristics
IS
I SM
V SD t rr Q rr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol 2.5 showing the A G integral reverse 20 p-n junction diode. S 1.0 V TJ = 25C, IS = 1.8A, V GS = 0V 47 71 ns TJ = 25C, IF = 2.4A 56 84 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width 300s; duty cycle 2%.
ISD 2.4A, di/dt 73A/s, VDD V(BR)DSS,
TJ 150C
Surface mounted on FR-4 board, t 10sec.
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IRF7303QPBF
1000
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
1000
I , Drain-to-Source Current (A) D
100
I , Drain-to-Source Current (A) D
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
100
4.5V
10
4.5V
10
1 0.1
20s PULSE WIDTH TJ = 25C
1 10
A
100
1 0.1
20s PULSE WIDTH TJ = 150C
1 10 100
A
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
2.0
TJ = 25C TJ = 150C
R DS(on) , Drain-to-Source On Resistance (Normalized)
I D = 4.0A
I D , Drain-to-Source Current (A)
1.5
1.0
0.5
10 4 5 6 7
V DS = 15V 20s PULSE WIDTH
8 9 10
A
0.0 -60 -40 -20 0 20 40 60 80
VGS = 10V
100 120 140 160
A
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRF7303QPBF
1000
800
Ciss
600
Coss
400
V GS , Gate-to-Source Voltage (V)
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd
20
I D = 2.4A VDS = 24V
16
C, Capacitance (pF)
12
8
200
Crss
4
0 1 10 100
A
0 0 5 10
FOR TEST CIRCUIT SEE FIGURE 12
15 20 25
A
VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
100
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
10
ID , Drain Current (A)
TJ = 150C
100us 10
TJ = 25C
1
1ms
0.1 0.0 0.5 1.0 1.5
VGS = 0V
2.0
A
2.5
1 0.1
TA = 25 C TJ = 150 C Single Pulse
1 10
10ms 100
VSD , Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
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IRF7303QPBF
5.0
V DS
4.0
RD
VGS RG
D.U.T.
+
ID , Drain Current (A)
- VDD
3.0
10V
Pulse Width 1 s Duty Factor 0.1 %
2.0
Fig 10a. Switching Time Test Circuit
1.0
VDS 90%
0.0
25
50
75
100
125
150
TC , Case Temperature ( C)
Fig 9. Maximum Drain Current Vs. Ambient Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
100
Thermal Response (Z thJA )
D = 0.50 0.20 10 0.10 0.05 0.02 1 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJA + TA 0.001 0.01 0.1 1 10 100
0.1 0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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IRF7303QPBF
Current Regulator Same Type as D.U.T.
QG
50K 12V .2F .3F
10V
QGS VG QGD
D.U.T. VGS
3mA
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 12a. Basic Gate Charge Waveform
Fig 12b. Gate Charge Test Circuit
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IRF7303QPBF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by R G Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 13. For N-Channel HEXFETS
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IRF7303QPBF
SO-8 Package Outline
Dimensions are shown in millimeters (inches)
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8
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF7303QPBF
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 ) 11.7 ( .461 )
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00 (12.992) MAX.
14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR's Web site.
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.07/2007
9

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