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| TC9328AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC9328AF Portable Audio DTS Controller (DTS-21) The TC9328AF is a single-chip DTS microcontroller for portable audio incorporating 230 MHz prescaller, PLL, and LCD driver. In addition to a 20-bit IF counter, 6-bit A/D converter, serial interface, and buzzer function, the device supports an interrupt function, 8-bit timer/counter, and 8-bit pulse counter. The LCD driver features built-in 1/4 duty, 1/2 bias and a 3 V voltage doubler boosting circuit, implementing stable LCD. The power supply voltage ranges from 0.9 to 1.8 V. Because of its low-current consumption (CPU: 80 A (max)), the device is suitable for use in digital tuning systems in portable equipment such as headphone stereos. Weight: 0.45 g (typ.) Features * * * CMOS DTS microcontroller LSI with built-in 230 MHz prescaller, PLL, and LCD driver Operating voltage: VDD = 0.9 to 1.8 V (typ.: 1.5 V) Current dissipation: When CPU in operation: IDD = 40 A (typ.) When PLL in operation: IDD = 6 mA (typ.) (VHF mode) Operating temperature range: Ta = -10 to 60C Program memory (ROM): 16-bit x 8192 steps Data memory (RAM): 4-bit x 512 words Instruction execution time: 40 s Crystal oscillator frequency: 75 kHz Stack level: 8 General-purpose IF counter: 20-bit (CMOS input supported) A/D converter: 6-bit x 4 channel LCD driver: 1/4 duty, 1/2 bias, 88 segments (max) I/O port: CMOS I/O ports: 12 N-channel open drain I/O ports: 24 (max) Output-only port: 1 Input-only ports: 5 (max) Timer/counter: 8-bit (as timer clock: INTR1/INTR2, instruction cycle: 1 kHz selectable) Pulse counter: 8-bit up/down counter (input via INTR2 pin) Buzzer: Built-in four mode: 0.625 to 3 kHz (8 types), Continuous, Single-Shot, 10 Hz Intermittent, or 10 Hz Intermittent 1 Hz Interval Package: QFP-80 (0.5 mm pitch, 1.4 mm thick) * * * * * * * * * * * * * * 1 2004-09-13 TC9328AF Pin Assignment INTR2 (PCTRin) P5-2 (ADin3) P5-1 (ADin2) P5-0 (ADin1) DO2 (OT/N) IFin2 (IN2) IFin1 (IN1) DO1 (P) INTR1 HOLD 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P5-3 (ADin4) P6-0 P6-1 P6-2 P6-3 P7-0 P7-1 P7-2 P7-3 RESET XOUT XIN GND VDB C1 C2 VEE C3 C4 VLCD 61 62 63 TEST 40 39 38 AMin GND FMin P3-3 P3-2 P3-1 P3-0 Vreg VDD A/D converter (4-channel) PLL Interrupt input MUTE P4-3 (SCK) P4-2 (SO) P4-1 (SI) P4-0 (BUZR) (Buzzer output) P2-3 (PSC) (Prescaller PSC output) P2-2 P2-1 P2-0 VDD P1-3 P1-2 P1-1 P1-0 P9-3 (S22) P9-2 (S21) P9-1 (S20) P9-0 (S19) P8-3 (S18) P8-2 (S17) SIO 64 65 66 67 68 69 70 71 Oscillation circuit SVFP80 (0.5 mm pitch) TOP-VIEW I/O ports (CMOS:12) N-channel open drain I/O (16) 37 36 35 34 33 32 31 30 29 28 27 26 25 Doubler circuit N-channel open drain I/O (8) 24 23 22 LCD driver (1/4 duty, 1/2 bias: 88 segments max) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 72 73 74 75 76 77 78 79 80 COM1 (OT1) COM2 (OT2) COM3 (OT3) COM4 (OT4) S1 (OT5) S10 (OT14) S2 (OT6) S3 (OT7) S4 (OT8) S5 (OT9) S11 (OT15) S12 (OT16) S13 (OT17) S14 (OT18) P8-0 (S15) 2 P8-1 (S16) S6 (OT10) S7 (OT11) S8 (OT12) S9 (OT13) 2004-09-13 TC9328AF Block Diagram Peripheral XOUT XIN CPU P1-3 Port1 P1-0 Gregulator R/W Buffer PSC P2-3 (PSC) Port2 P2-0 X'tal OSC Vreg Vreg (1.5 V) DO1 (P) DO2 (OT/N) Phase Comparator RAM (4 x 512 words) ALU Port3 P3-3 P3-0 VLCD FMin AMin PLL P6-3 Port6 IFin1 (IN1) IFin2 (IN2) IF Counter Up/Down Counter Data Reg (16 bit) Port7 P6-0 P7-3 P7-0 Timer ROM INTR1 INTR2 (PCTRin) Interrupt/ Counter (16 x 8192 Steps) Instruction Decoder MUTE MUTE P9-3 (S22) Port9 P9-0 (S19) P8-3 (S18) Port8 Serial Interface LCD Driver Port4 Program Counter Reset BUZR Stack regulator (8 Level) VDB AD Converter VDD P8-0 (S15) P4-3 (SCK) P4-2 (SO) P4-1 (SI) P4-0 (BUZR) VLCD HOLD TEST RESET VDD GND VDB Doubler C1 C2 P5-3 (ADin4) P5-2 (ADin3) P5-1 (ADin2) P5-0 (ADin1) LCD Driver/Output Port VLCD Port5 VEE (1.5 V) VEE C3 Doubler C4 VLCD COM1 (OT1) COM2 (OT2) COM3 (OT3) COM4 (OT4) VLCD S1 (OT5) S2 (OT6) S10 (OT14) S11 (OT15) S12 (OT16) 3 S14 (OT18) S13 (OT17) 2004-09-13 TC9328AF Description of Pin Function Pin No. Symbol Pin Name Function and Operation Output common signals to LCD panels. Through a matrix with pins S1 to S22, a maximum 88 segments can be displayed. LCD common output/Output port 3 COM3/OT3 Three levels, VLCD, VEE, and GND, are output at 62.5 Hz every 2 ms. VEE is output after system reset and CLOCK STOP are released, and a common signal is output after the DISP OFF bit is set to "0". These pins can be programmed as output ports (Note 1). Segment signal output pins for LCD panel. Together with COM1 to COM4, a matrix is formed that can display a maximum of 88 segments. S1/OT5~ 5~18 S14/OT18 LCD segment output/Output port All pins from S1 to S14 can be programmed as output ports (Note), and all pins from S15 to S22 as I/O ports, in units of pins. When the pins function as output ports, VLCD pin potential and GND potential are output to them. When the pins function as I/O ports, drain output is N-ch open. Because power is supplied from VLCD for the I/O ports, up to VLCD voltage (3 V) can be applied. These data ports (OT1 to OT18) are incremented by 1 by instruction every time data are accessed. Therefore, they can be used for external memory address signals, facilitating data access. Note: After system reset, the output port pins are set to LCD output, the I/O port pins to I/O port input. Input instruction Remarks 1 COM1/OT1 VLCD VEE 2 COM2/OT2 4 COM4/OT4 VLCD VLCD P8-0/S15~ 19~26 P9-3/S22 LCD segment output/ I/O port VDD The input and output of these 4-bit I/O ports can be programmed in 1-bit units. These pins can be programmed to be pulled up or down. Thus, they can be used as key input pins. By altering the input of I/O ports set to input, the CLOCK STOP mode or the WAIT mode can be released, and the MUTE bit of the MUTE pin can be set to "1". VDD VDD 27~30 P1-0~P1-3 I/O port 1 RIN1 VDD Note 1: When the LCD pin is set as an output port, the "H" level output is the doubled voltage VLCD. Therefore, disconnect the voltage doubler boosting capacitor but connect the VLCD pin to the VDD pin. 4 2004-09-13 TC9328AF Pin No. Symbol Pin Name Function and Operation Remarks 32~34 P2-0~P2-2 I/O port 2 VLCD The input and output of these 4-bit I/O ports can be programmed in 1-bit units. The P2-3 pin is also used as a PLL prescaller PSC signal output pin. A PLL can be configured using an external prescaller. In such a case, set the pin to I/O port output. VDD Input instruction 35 P2-3/PSC I/O port 2 /Prescaller /PSC output 4-bit I/O ports, allowing input and output to be programmed in 1 bit units. Pins P5-0 to P5-3 can also be used for analog input to the built-in 6-bit, 4-channel AD converter. 54~57 P3-0~P3-3 I/O port 3 58~61 P5-0/ADin1~ P5-3/ADin4 62~69 P6-0~P7-3 The conversion time of the built-in AD converter using the successive I/O port 5 comparison method is 280 s. The /AD analog voltage necessary pin can be programmed to input AD analog input in 1-bit units. Up to the doubled voltage VDB (VDD x 2) can be input as the AD input voltage. I/O port 6, 7 The I/O ports are N-ch open drain output. Up to the VDB voltage can be applied to the AD input pins, and up to 3.6 V can be applied to the I/O port pins. I/O port 3 can obtain N-ch high-output current (2 mA typ.) even at low voltage. The AD converter and all associated controls are performed via sortware. Input instruction To AD converter VDD 5 2004-09-13 TC9328AF Pin No. Symbol Pin Name Function and Operation 4-bit I/O ports, allowing input and output to be programmed in 1-bit units. The P4-0 pin is also used for buzzer output. P4-1 to P4-3 are also used as serial interface circuit (SIO) input / output pins. The buzzer output can select 8 kinds of 0.625 to 3 kHz frequencies with 4 modes: continuous output, single-shot output, 10 Hz intermittent output, and 10 Hz intermittent 1 Hz interval output. SIO functions for 4-bit or 8-bit serial data inputs from the SI pin and outputs from the SO pin at the SCK pin clock edge. The clock for serial operation (SCK) is capable of internal (SCK = 37.5 kHz)/ external options and rise/fall shift options. The SO pin is also capable of switching to serial inputs (SI), facilitating the control of various LSI's and communication between controllers. When SIO interrupts are enabled, an interrupt is generated after SIO execution and the program jumps to address 4. This is useful for high-speed serial communications. All SIO inputs use built-in Schmitt circuits. P3-3 pins also functions as the output for a built-in buzzer. SIO, buzzer, and all associated controls can be programmed. 1-bit output port, normally used for muting control signal output. 40 MUTE Muting output port This pin can set the internal MUTE bit to "1" according to a change in the input of I/O port 1 and HOLD . MUTE bit output logic can be changed. Input instruction + SIOon (P4-1~P4-3) Input instruction Remarks VDD P4-0/BUZR I/O port 4 /Buzzer output (P4-0) P4-1/SI /Serial data input 36~39 P4-2/SO /Serial data output VDD P4-3/SCK /Serial clock I/O VDD Input pin used for controlling TEST mode. Test mode control input "H" (high) level indicates TEST mode, while "L" (low) indicates normal operation. The pin is normally used at low level or in NC (no connection) state. (A pull-down resistor is builtin). RIN2 VDD 41 TEST 6 2004-09-13 TC9328AF Pin No. Symbol Pin Name Function and Operation Input pin for request/release hold mode. Normally, this pin is used to input radio mode selection signals or battery detection signals. Hold mode includes CLOCK STOP mode (stops crystal oscillation) and WAIT mode (halts CPU). Setting is implemented with the CKSTP instruction or the WAIT instruction. To request Clock Stop mode, either L-level detection on the HOLD pin or forced execution can be programmed. The mode is released by H-level detection on the HOLD pin or input change, respectively. Executing the CKSTP instruction stops the clock generator and the CPU, entering memory backup state. In memory backup state, current dissipation becomes low (1 A or less) and the display output/CMOS output ports automatically become L level and N-ch open drain output Off. Remarks VDD 42 HOLD Hold mode control input Regardless of this input state, Wait mode is executed in order to lower power dissipation. Either crystal oscillator only in operation or CPU suspension can be programmed. For crystal oscillator only in operation, all displays are at L level and other pins are in hold state. For CPU suspension, the CPU stops and all others retain their states. Wait mode is released by changing HOLD input. External interrupt input pins. When interrupts are enabled and a 13.3 to 26.7 ms pulse or longer is input to the pin, interrupt INTR1/2 is generated and the program jumps to address 1/2. Input logic or rising/falling edge can be selected for each input interrupt. INTR1 43 INTR2 44 /PCTRin External interrupt input /Pulse counter input The internal 8-bit timer clock input can be selected as input to the pins. When the count value reaches the specified value, an interrupt is generated (address 3). The pin is also used for input of an 8-bit pulse counter. Input rising/falling or upcount/downcount can be selected for the counter. These inputs use built-in Schmitt circuits. The pins can also be used as input ports for input of remote control signals or a tape count. 7 2004-09-13 TC9328AF Pin No. Symbol Pin Name Function and Operation IF signal input pin for the IF counter to count the IF signals of the FM and AM bands and to detect the automatic stop position. The input frequency is between 0.3 to 12 MHz. A built-in input amp. and C coupling allow operation at low-level input. 45 46 IFin1/IN1 IFin2/IN2 IF signal input /Input port The IF counter is a 20-bit counter with optional gate times of 1, 4, 16 and 64 ms. 20 bits of data can be readily stored in memory. In Manual mode, gate On/Off can be performed using instruction. The input pin can be programmed for use as an input port (IN port). Note: When a pin is set to IF input, the input is at high impedance in PLL Off mode or if the pins are not used for input. Pins to which power is applied. Normally, VDD = 0.9~1.8 V is applied. For the PLL, power for the prescaller in the programmable counter block and IF input amp can be individually programmed. By switching to different modes depending on the power supply voltage and the frequency used, current dissipation can be lowered. Connect a stabilizing capacitor between the VDD pin and GND (4.7 F, 0.01 F typ.). Power-supply pins In backup state (at execution of the CKSTP instruction), current dissipation drops (1 A or less) and the power supply voltage can be reduced to 0.75 V. If more than 0.9 V is applied when the pin voltage is 0, the device system is reset and the program starts from address "0". (Power on reset) Note: To operate the power on reset, the power supply should start up in 10~100 ms. Note: The power-on reset function can be enabled/disabled using the AI switch. GND VDD Remarks RfIN2 VDD 47, 73 GND 8 0.01 F 4.7 F 31, 50 VDD 2004-09-13 TC9328AF Pin No. Symbol Pin Name Function and Operation Programmable counter input pin for FM/AM band. For FM input, mode can be switched between 1/2 + Pulse Swallow VHF and FM mode. For AM input, mode can be FM local oscillation switched between Pulse Swallow (HF) and Direct Dividing (LF) mode. signal input Normally, local oscillation output (Voltage-Controlled Oscillator: VCO output) of 50 to 230 MHz is input in VHF mode; 30 to 130 MHz in FM mode; 1 to 30 MHz in HF mode; 0.5 to 8 MHz in LF mode. A PLL can be configured using an external prescaller. In such a case, set the pin to LF, and connect the prescaller divider output to the AMin input pin and the PSC input to the P2-3 (PSC) output pin. RfIN1 VDD Remarks 48 FMin RfIN2 VDD 49 AMin AM local oscillation signal input With an input amp incorporated, capacitive-coupling, small-amplitude operation. Note: The input is at high impedance in PLL Off mode or if the pins are not used for input. PLL phase comparator output pins. Tristate output. When the program counter divider output is higher than the reference frequency, H level is output; when lower, L level; and when they match, high impedance. For the phase comparator power supply, a 1.5 V constant voltage supply (Vreg pin) is used. Even if the power supply voltage drops, a stable PLL can be configured. Because DO1 and DO2 are output in parallel, a filter constant can be optimally designed for each FM/AM band. Phase comparator output/output port /P output The DO2 pin can be programmed to high impedance or as an output port (OT). Therefore, using the DO1 and DO2 pins, lockup time can be improved or the pins can be effectively used as output ports. Also, the phase comparator charge pump control signal (P/N) can be output from the DO1/2 pin by program so a PLL using an external charge pump can be configured. In such a case, when the program counter divider output is higher than the reference frequency, P/N is output at H/L level; when lower, L/H level; and when they match, L/L level. When set to this mode, H level output becomes VDD level. Note: For tristate output, the H level output uses a constant voltage supply. When H level output current is required, Toshiba recommend using an external power supply. Vreg 52 DO1/P 51 DO2/OT/N Phase comparator output/output port /N output 9 2004-09-13 TC9328AF Pin No. Symbol Pin Name Function and Operation Phase comparator constant voltage supply. When the phase comparator output is tristate output, a constant voltage supply of 1.5 V (typ.) is output to the pin. For this output, connect a stabilizing capacitor (0.47 F typ.). At constant voltage operation, the H level phase comparator output uses a constant voltage. Thus, when H level output current is required, Toshiba recommend using an external power supply. In such a case, externally apply 1.8~3.6 V to the pin. When the phase comparator output is output using the charge pump control signal (P/N), the pin becomes the VDD level. Then, the phase comparator output operates using the power supply voltage. Input pin for system reset signals. RESET takes place while at low level; at high level, the program starts from address "0". 70 RESET Reset input Normally, if more than 0.9 V is supplied to VDD when the voltage is 0, the system is reset (power on reset). Accordingly, this pin should be set to high level during operation. Note: When the power-on reset function is enabled/disabled using the AI switch, reset by pin. Remarks 53 Vreg Phase comparator constant voltage supply Vreg VDD ROUT 71 XOUT Crystal oscillator pins. A reference 75 kHz crystal oscillator is connected to the XIN and XOUT pins. Crystal oscillator pin The oscillator stops oscillating during CKSTP instruction execution. The VXT pin is the power supply for the crystal oscillator. A stabilizing capacitor (0.47 F typ.) is connected. XIN XOUT RfXT VDD 72 XIN 10 2004-09-13 TC9328AF Pin No. 74 75 76 77 78 79 Symbol VDB C1 C2 VEE C3 C4 Pin Name Function and Operation Voltage doubler boosting output pins. The VDB pin doubles the VDD pin voltage using the voltage doubler boosting capacitor between C1 and C2. The doubled voltage is used for the AD converter and constant voltage circuit (Vreg, VEE) power supply. The VEE pin supplies a constant voltage of 1.5 V from the VDB voltage. The voltage is doubled (to 3 V) using the voltage doubler boosting capacitor between C3 and C4. The doubled voltage is then supplied to the VLCD pin. The VEE potential and the VLCD potential are used to drive the LCD. Connect a stabilizing capacitor between the VDB pin and GND (0.1 F, 10 F typ.), and between the VLCD pin and GND (0.1 F typ.). Connect a voltage doubler boosting capacitor (0.1 F typ.) between C1 and C2, and between C3 and C4. (Note 1) VLCD Remarks Voltage doubler boosting output pins 80 VLCD Note 1: When the LCD pin is set as an output port, the "H" level output is the doubled voltage VLCD. Therefore, disconnect the voltage doubler boosting capacitor but connect the VLCD pin to the VDD pin. 11 2004-09-13 TC9328AF Description of Operations CPU The CPU consists of a program counter, a stack register, ALU, a program memory, a data memory, G-register, a data register, DAL address register, carry F/F, a judgment circuit, and an interruption circuit. 1. Program Counter (PC) The program counter consists of a 14-bit binary up-counter and addresses the program memory (ROM). The counter is cleared when the system is reset and the programs start from the 0 address. Under normal conditions, the counter is increased in increments of one whenever an instruction is executed, but the address specified in the instruction operand is loaded when a JUMP instruction or CALL instruction is executed. Also, when an instruction that is equipped with the skip function (AIS, SLTI, TMT, RNS instructions, etc.) is executed and result of this includes a skip condition, the program counter is increased in increments of two and the subsequent instruction is skipped. Furthermore, if interruption is received, the vector address corresponding to each interruption is loaded. Note: Program memory (ROM) It is 0000H-0FFFH address. For this reason, an access setup to the address beyond this is forbidden. Contents of Program Counter (PC) PC13 PC12 PC11 PC10 JUMP ADDR1 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Instruction Operand of instruction (ADDR1) JUMP ADDR2 Power on reset RESET by reset pin DAL (DA) (DAL bit = 1) RN, RNS, RNI At the time of an interruption reception Power on reset RESET by reset pin 0 0 Operand of instruction (ADDR2) Operand of instruction (ADDR3) DAL address register (DA) Contents of general register (r) 0 0 0 0 Contents of stack register Vector address of each interruption 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Priority 1 2 3 4 Interruption Factor INTR1 pin INTR2 pin Serial inter face Timer counter Vector Address 0001H 0002H 0003H 0004H 2. Stack Register A register consisting of 8 x 14 bits which stores the contents of the program counter +1 (the return address) when a sub-routine call instruction is executed, or an interrupt is processed. The contents of the stack register are loaded into the program counter when the return instruction (RN, RNS, RNI instruction) is executed. There are eight stack levels available and nesting occurs up to eight levels. 12 2004-09-13 TC9328AF 3. ALU ALU is equipped with binary 4-bit parallel add/subtract functions, logical operation, comparison and multiple bit judgment functions. This CPU is not equipped with an accumulator, and all operations are handled directly within the data memory. 4. Program Memory (ROM) The program memory consists of 16 bits x 16384 steps and is used for storing programs. The usable address range consists of 16384 steps between address 0000H and 1FFFH. The program memory divids 16384 into 8 separate steps and consists of page 0 to 7. The JUMP instruction can be freely used throughout all 16384 steps though the Call instruction can use the address from 0000H to 0fffH from page 0 to 3. In case of setting DAL bit, arranged on I/O map, "0" (DAL ADDR3, (r) command), the program memory address 0000H to 03FFH, page 0, are used as data area and setting DAL bit "1" (DAL (DA) command), the program memory address 0000H to 0FFFH (page 0 to 3) are used as data area. The 16-bit content of this can be loaded into the data register by executing the DAL instruction. Note: Set the address for data area of program memory outside of the program loop. ROM 16 bits Page 0 (1 k step) The vector address at an interruption CALL instruction specification area (*1) 0000H 0000H 0001H 0002H 0003H 0004H JUMP address at initialization Interruption vector address INTR1 INTR2 Serial interface 8-bit timer 0400H Page 1 0800H Page 2 0C00H Page 3 1000H Page 4 1400H Page 5 1800H Page 6 1C00H Page 7 1FFFH *1: *2: DAL bit = DAL access area at setting "0" DAL bit = DAL access area at setting "1" Note: DAL bit is arranged on I/O map. DAL instruction specification area (*2) JUMP instruction specification area 13 2004-09-13 TC9328AF 5. Data Memory (RAM) The data memory consists of 4 bits x 512 words and used for storing data. These 512 words are expressed in row address (6 bits) and column addresses (4 bits). 348 words (row address = address 04H to 1FH) within the data memory are addressed indirectly by the G-register. Therefore, it is necessary to specify the row address with the G-register before the data in this area is processed. The address 00H to 0FH within the data memory are known as general registers, and these can be used simply by specifying the relevant column address (4 bits). These sixteen general registers can be used for operations and transfers with the data memory, and may also be used as normal data memories. Note: The column address (4 bits) that specifies the general register is the register number of the general register. Note: All row address (addresses 00H to 1FH) can be specified indirectly with the G-register. Note: The data memory has 512 words and the highest bit of 6 in the G-register row address must be used "0" (00H - 1FH address). Note: By using LD and ST instruction, it can be addressed directly in 256 words (row address = 00H to 0FH) in the data memory. COLMUN ADDRESS: DC 0 12 3 4 5 67 89ABCDEF General register (One from the addresses 00H to 0fH) ROW ADDRESS: DR (*) 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 Indirect specification of row addresses (04H to 2FH) with the G-register LD and ST instruction can specify row address from 00H to 0FH directly. *: The indirect specification of row address = 00H to 1FH is also possible. 1D 1E 1F 14 2004-09-13 TC9328AF 6. G-Register (G-REG) The G-register is a 6-bit register used for addressing the row addresses (DR = 04H to 2FH addresses) of the data memory's 448 words. The contents of this register are validated when the MVGD instruction or MVGS instruction are executed, and not affected through the execution of any other instructions. This register is used as one of the ports, and the contents are set when the OUT1 instruction from among the I/O instructions is executed. The 6-bit contents can be directly set by execution of STIG instruction. ( Refer to the section in Register Ports.) 7. Data Register (DATA REG) The data register consists of 1 x 16 bits and loads 16 bits of optional address data in the program memory at the DAL instruction executed. This register is used as one of the ports, and the contents are loaded into the data memory in units of 4 bits when IN1 instruction among the I/O instruction is executed. ( Refer to the section in Register Ports.) This register can be written from the data memory, and is used for the evacuation and the return processing of the data at the interruption. 8. DAL Address Register (DA) The data register consists of 1 x 14 bits. If DAL instruction is executed when the DAL bit is set to "1", 16 bits of the data of the free addresses in the program memory specified by this DAL address register are loaded. By the setting (DATA) DA bit to "1", the contents of data register (DATA REG) can be transmitted to DAL address register (DA). This register and a control bit are treated as a port, and are accessed by IN3/OUT3 instruction of an input-and-output instruction. ( Refer to the register port item) 9. Carry F/F (Ca Flag) This is set when either Carry or Borrow are issued in the result of calculation instruction execution and is reset if neither of these are issued. The contents of carry F/F can only be amended through the execution of addition and, subtraction or, CLT and, CLTC instructions, and not affected by the execution of any other instruction. The carry F/F can be accessed by IN1/OUT1 instruction of an input-and-output instruction. For this reason, the evacuation and the return at the time of interruption are performed by the input-and-output instruction between data memories. (Refer to the register port item) 10. Judgment Circuit (J) This circuit judges the skip conditions when an instruction with the skip function is executed. The program counter is increased by two when the skip conditions are satisfied, and the subsequent instruction is skipped. There are 15 instructions equipped with a wide variety of skip functions. ( Refer to the items marked with a "*" symbol in the Table Instruction Functions and Operational Instructions) 11. Interruption Circuit An interruption circuit branches into each vector address by the demand from peripheral hardware, and processes each interruption. ( Refer to the interruption functional item) 15 2004-09-13 TC9328AF 12. Instruction Set Table A total of 57 instruction sets is available, and all of these are single-word instructions. These instructions are expressed with 6-bit instruction codes. Upper 2 bits Lower 4 bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 0 1 2 3 4 5 6 7 8 9 A B C D E AI AIC SI SIB ORIM ANIM XORIM MVIM AD AC SU SB ORR ANDR XORR 00 0 M, I M, I M, I M, I M, I M, I M, I M, I r, M r, M ST r, M r, M r, M r, M r, M CLT CLTC MVGD r, M r, M r, M M*, r IN3 OUT1 OUT2 OUT3 DAL SHRC RORC STIG CAL ADDR2 1111 F MVSR M1, M2 MVGS M, r SKP, SKPN RN, RNS WAIT CKSTP XCH DI, EI, RNI NOOP M P M, C M, C M, C M, C ADDR3, r M M I* LD r, M* JUMP ADDR1 TMTR TMFR SEQ SNE 01 1 r, M r, M r, M r, M 10 2 SLTI SGEI SEQI SNEI TMTN TMT TMFN TMF IN1 IN2 11 3 M, I M, I M, I M, I M, N M, N M, N M, N M, C M, C 16 2004-09-13 TC9328AF 13. Table of Instruction Functions and Operational Instructions (Description of the symbols used in the table) ; Data memory address. Normally one of the addresses among the addresses 000H to 03FH in the data memory. M* ; Data memory address (256 words) One of the addresses among the addresses 000H to 0FFH in the data memory. (Effective only when ST and LD instruction are executed.) r ; General register One of the addresses among the addresses 000H to 00FH in the data memory. PC ; Program Counter (14 bits) STACK ; Stack register (14 bits) G ; G-register (6 bits) DATA ; Data register (16 bits) I ; Immediate data (4 bits) I* ; Immediate data (6 bits, effective only when STIG instruction is executed.) N ; Bit position (4 bits) ; ALL "0" C ; Port code No. (4 bits) CN ; Port code No. (4 bits) RN ; General register No. (4 bits) ADDR1 ; Program memory address (14 bits) ADDR2 ; Program memory address in the pages from 0 to 3 (12 bits) ADDR3 ; The upper 6 bits of the program memory address in the page 0. DA ; DAL address register (14bits, effective only when DAL instruction, DAL bit = 1, is executed.) Ca ; Carry CY ; Carry flag P ; Wait condition b ; Borrow IN1~IN3 ; The ports used during the execution of instructions from IN1 to IN3 OUT1~OUT3 ; The ports used during the execution of instructions from OUT1 to OUT3 () ; Contents of the register or data memory []C ; Contents of the port indicated by the code No. C (4 bits) [] ; Contents of the data memory indicated by the contents of the register or data memory []P ; Contents of the program memory (16 bits) IC ; Instruction code (6 bits) * ; Commands equipped with the skip function DC ; Data memory column address (4 bits) DR ; Data memory row address (2 bits) DR* ; Data memory row address (4 bits, effective only when ST and LD instruction is executed) (M) b0~(M) b3 ; Bit data of the contents of a data memory (1 bit) M 17 2004-09-13 TC9328AF Instruc -tion Group AI Addition Instructions AIC AD Mnemonic Skip Function Machine Language (16 bits) Function Description Operation Description IC (6 bits) 000000 000001 001000 A (2 bits) DR DR DR B (4 bits) DC DC DC C (4 bits) I I RN M, I M, I r, M Add immediate data to memory M (M) + I Add immediate data M (M) + I + ca to memory with carry Add memory to general register Add memory to general register with carry Subtract immediate data from memory Subtract immediate data from memory with borrow Subtract memory from general register Subtract memory from general register with borrow * Skip if memory is less than immediate data r (r) + (M) r (r) + (M) + ca M (M) - I M (M) - I - b r (r) - (M) r (r) - (M) - b AC r, M 001001 DR DC RN Subtraction Instructions SI M, I 000010 DR DC I SIB M, I 000011 DR DC I SU r, M 001010 DR DC RN SB r, M 001011 DR DC RN SLTI M, I Skip if (M) < I 110000 DR DC I SGEI M, I * Skip if memory is greater than or equal Skip if (M) > I = to immediate data Skip if memory is equal to immediate data Skip if (M) = I 110001 DR DC I SEQI Comparison Instructions M, I * 110010 DR DC I SNEI M, I * Skip if memory is not equal to immediate Skip if (M) I data Skip if general register is equal to memory Skip if general register is not equal to memory Skip if (r) = (M) 110011 DR DC I SEQ r, M * 010010 DR DC RN SNE r, M * Skip if (r) (M) 010011 DR DC RN CLT r, M Set carry flag if general register is (CY) 1 if (r) < (M) or less than memory, or (CY) 0 if (r) > (M) = reset if not Set carry flag if general register is less than memory with carry or reset if not (CY) 1 if (r) < (M) + (ca) or (CY) 0 if (r) > (M) + (Ca) = 011100 DR DC RN CLTC r, M 011101 DR DC RN 18 2004-09-13 TC9328AF Instruc -tion Group LD ST Mnemonic Skip Function Machine Language (16 bits) Function Description Operation Description IC (6 bits) 0101 0110 001111 000111 A (2 bits) DR* (4 bits) DR* (4 bits) DR DR B (4 bits) DC DC DC1 DC C (4 bits) RN RN DC2 I r, M* M*, r Load memory to general register Store memory to general register r (M*) M* (r) MVSR M1, M2 Transfer Instructions MVIM M, I Move memory to (DR, DC1) (DR, DC2) memory in same row Move immediate data MI to memory Move memory to destination memory [(G), (r)] (M) referring to G-register and general register Move source memory referring to G-register and (M) [(G), (r)] general register to memory (Note) Move immediate data G I* to G-register Input IN1 port data to M [IN1] C memory Output contents of memory to OUT1 port [OUT1] C (M) MVGD r, M 011110 DR DC RN MVGS M, r 011111 DR DC RN STIG IN1 I* M, C 111111 111000 DR I* DC 0010 CN OUT1 I/O Instructions M, C 111011 DR DC CN IN2 M, C Input IN2 port data to M [IN2] C memory Output contents of memory to OUT2 port [OUT2] C (M) 111001 DR DC CN OUT2 M, C 111100 DR DC CN IN3 M, C Input IN3 port data to M [IN3] C memory Output contents of memory to OUT3 port Logical OR of general register and memory Logical AND of general register and memory Logical OR of memory and immediate data Logical AND of memory and immediate data [OUT3] C (M) 111010 DR DC CN OUT3 M, C 111101 DR DC CN ORR r, M r (r) (M) 001100 DR DC RN ANDR Logical Instructions r, M r (r) (M) 001101 DR DC RN ORIM M, I M (M) I 000100 DR DC I ANIM M, I M (M) I 000101 DR DC I XORIM M, I Logical exclusive OR of memory and M (M) I immediate data Logical exclusive OR of general register r (r) (M) and memory 000110 DR DC I XORR r, M 001110 DR DC RN Note: The execution period for the MVGS instruction is two machine cycles. 19 2004-09-13 TC9328AF Instruc -tion Group Mnemonic Skip Function Machine Language (16 bits) Function Description Operation Description IC (6 bits) A (2 bits) B (4 bits) C (4 bits) TMTR r, M * Test general register bits by memory bits, then skip if all bits specified are true Test general register bits by memory bits, then skip if all bits specified are false Test memory bits, then skip if all bits specified are true Test memory bits, then skip if all bits specified are false Skip if r [N (M)] = all "1" 010000 DR DC RN TMFR r, M * Skip if r [N (M)] = all "0" 010001 DR DC RN Bit Judgment Instruction TMT M, N * Skip if M (N) = all "1" 110101 DR DC N TMF M, N * Skip if M (N) = all "0" 110111 DR DC N TMTN M, N * Test memory bits, then not skip if all bits Skip if M (N) = not all "1" specified are true Test memory bits, then not skip if all bits Skip if M (N) = not all "0" specified are false Skip if carry flag is true Skip if carry flag is false Call subroutine Return to main routine Return to main routine and skip unconditionally Skip if (CY) = 1 Skip if (CY) = 0 STACK (PC) + 1 and PC ADDR2 PC (STACK) PC (STACK) and skip 110100 DR DC N TMFN M, N * 110110 DR DC N SKP SKPN CAL Subroutine Instructions RN ADDR2 * * 111111 111111 1011 111111 00 01 0011 0011 ADDR2 (12 bits) 10 0011 RNS 111111 11 0011 JUMP Instructions JUMP ADDR1 Jump to address specified PC ADDR1 10 ADDR1 (14 bits) DI Interruption Instruction EI RNI Reset IMF Set IMF (Note) IMF 0 (Note) IMF 1 111111 111111 111111 00 01 11 0111 0111 0111 Return to main PC (STACK) routine and set IMF (Note) IMF 1 Note: IMF bits is an interruption master permission flag and is arranged on I/O map. ( Refer to the interruption function) 20 2004-09-13 TC9328AF Instruc -tion Group Mnemonic Skip Function Function Description Shift memory bits to right direction with carry Rotate memory bits to right direction with carry Exchange memory bits mutually Operation Description 0 (M) b3 (M) b2 (M) b1 (M) b0 (CY) (M) b3 (M) b2 (M) b1 (M) b0 (CY) (M) b3 (M) b0, (M) b2 (M) b1 Machine Language (16 bits) IC (6 bits) 111111 A (2 bits) DR B (4 bits) DC C (4 bits) 0000 SHRC M RORC M 111111 DR DC 0001 XCH M 111111 DR DC 0110 Other Instructions DAL ADDR3, r IF DAL bit = 0 then load program in page 0 to DATA register (Note) IF DAL bit = 1 then DATA [ADDR3 + (r)] p load program in page 0 memory referring to DAL address register to DATA register (Note) At P = "0" H, the condition is CPU waiting (Soft wait mode) At P = "1" H, expect for clock generator, all function is waiting (Hard wait mode) Clock generator stop No operation 111110 ADDR3 (6 bits) RN WAIT P Wait at condition P 111111 P 0100 CKSTP NOOP Stop clock generator to MODE condition 111111 111111 0101 1111 Note: The lower four bits among the ten-bit address of the program memory specified with the DAL instruction (DAL ADDR3 and r) are addressed indirectly with the contents of the general register. Note: The execution period for the DAL instruction is two machine cycles Note: DAL bit and DAL address register (DA) are arranged on I/O map. ( Refer to the register port item) Note: When "1" is set to DAL bit and DAL instruction is executed, all the operand part becomes invalid and reference address is used for DAL address register (DA). In this case, assign 0, 0 as dummy data for the operand. 21 2004-09-13 TC9328AF I/O Map (IN1 (M, C), IN2 (M, C), IN3 (M, C), OUT1 (M, C), OUT2 (M, C), OUT3 (M, C)) I/O L1 OUT1 Code Y1 HF PW0 1 P0 2 P4 P5 P6 P7 edge P1 P2 P3 AD SEL0 AD SEL1 * STA -0 -1 I/O port 3 -2 -3 F0 F1 IF data 2 F2 F3 AD4 AD5 BUSY 0 -0 -1 I/O port 3 -2 -3 PW1 Y2 Y4 Y8 FM PD0 K1 PD2 PD3 -0 -1 I/O port 2 -2 -3 BUSY MANUAL OVER Y1 Y2 L2 OUT2 Y4 Y8 Y1 Y2 I/O port 1 L3 OUT3 Y4 Y8 Y1 Y2 IF monitor 0 AD0 AD1 A/D data AD2 AD3 -0 -1 I/O port 2 -2 -3 K1 IN1 Y4 Y8 Y1 Y2 A/D data K2 IN2 Y4 Y8 Y1 Y2 I/O port 1 K3 IN3 Y4 Y8 Power control 0 I/O port 1 pull-down Programmable counter 1 A/D control IF data 1 Programmable counter 2 Serial interface control 1 SCK - INV SCK - I/O SIO-ON -0 -1 I/O port 4 -2 -3 F4 F5 IF data 3 F6 F7 Serial interface monitor 0 -0 -1 I/O port 4 -2 -3 Programmable counter 3 3 P8 4 P12 5 R0 6 R1 R2 P13 Reference select P14 P15 Programmable counter Serial interface control 2 P11 STA P9 P10 SO - I/ O 8/ 4 bit * -0 -1 I/O port 5 -2 -3 F8 F9 IF data 4 F10 F11 BUSY COUNT SIO F/F -0 -1 I/O port 5 -2 -3 Programmable counter 4 SO0 Serial interface output data 1 SO1 SO2 SO3 -0 -1 Serial interface input data 1 F14 F15 SI0 SI1 SI2 SI3 -0 -1 -2 I/O port 6 -3 F12 F13 IF data 5 -2 I/O port 6 -3 Serial interface output data 2 SO4 SO5 SO6 CKSTP mode SO7 Test port 2 #4 -0 -1 -0 -1 Serial interface input data 2 F18 F19 SI4 SI5 Timer SI6 SI7 -0 -1 P16 -2 I/O port 7 -2 I/O port 8 -3 F16 F17 -2 I/O port 7 -3 IF counter control 1 Timer reset IF1/ 2 7 PW IF1/IN1 IF2/IN2 2 Hz F/F Clock -3 2 Hz F/F 10 Hz 0 100 Hz 0 0 0 -0 -1 I/O port 8 -2 -3 IF counter control 2 Interrupt control G1 POL1 (INTR1) POL2 (INTR2) IE * HOLD -0 -1 I/O port 9 EF4 (Timer) MUTE -0 HOLD PLL off control -1 IF counter Split (DATA) DA -2 Prescaller IN OT Count Up -3 PSC ENA F/F port 1 Pull-up -2 -3 INTR1 INTR2 0 Interrupt master flag IMF STA/ STP 8 MUTE MANUAL G0 MUTE control -0 Interrupt permission flag -1 I/O port 9 -2 -3 Interrupt permission flag HOLD EF1 (INTR1) EF2 (INTR2) EF3 (SIO) MUTE control I/O Unlock detection ENA IN1 POL HOLD EF1 I/O-1 9 UNLOCK Detection RESET A BF0 B BM0 C CA Flag BM1 * POL DO2 control EF2 EF3 EF4 -0 -1 -2 -3 Interrupt latch reset M1 ILR1 (INTR1) ILR2 (INTR2) ILR3 (SIO) ILR4 (Timer) Input port IN2 IL1 Interrupt latch IL2 IL3 IL4 DAL CT0 CT1 CT2 CT3 DAL address CT7 DA0 DA1 DA2 DA3 0 0 0 PN M0 Buzzer output control 1 BF1 BF2 BEN Timer counter Interrupt detection data1 DAL ID0 ID1 ID2 ID3 Timer counter data 1 Buzzer output control 2 BUZR ON * Timer counter Interrupt detection data2 POL * DAL address DA0 DA1 DA2 DA3 CA flag 0 0 0 CT4 Timer counter data 2 CT5 CT6 ID4 ID5 ID6 ID7 Timer counter control CK0 G register 1 D G0 E G4 F #0 #1 #2 #3 COM1 COM2 COM3 COM4 d12 G5 Test port 1 * * Data register 1 CR d0 d1 d2 d3 G register 1 d7 G0 G1 G2 G3 S1 Data select S2 S3 S4 d4 d0 Data register 1 d1 d2 d3 CK1 GT Data select G3 SEL1 SEL2 SEL4 SEL8 d4 Data register 2 d5 d6 Data register 2 d5 d6 d7 G1 G2 G register 2 Segment data 1/ General-purpose output data COM1/OT COM2/OT COM3/OT COM4/OT d8 Data register 3 d9 d10 d11 G4 G register 2 G5 0 0 d8 Data register 3 d9 d10 d11 Segment data2/ Segment IO control Data register 4 d13 d14 d15 d12 Data register 4 d13 d14 d15 Refer to the next page 22 2004-09-13 TC9328AF KL2D Data Select S1 S2 S4 S8 L2D I/O L2E L2E L3B K3B OUT2 Y1 Y2 Y4 Y8 Y1 Y2 OUT2 Y4 S17 COM4 /OT4 COM1 COM2 S18 COM4 /OT8 COM1 COM2 S19 COM4 /OT12 COM1 COM2 S20 COM4 /OT16 COM1 COM2 S21 COM4 COM1 COM2 S22 COM3 COM4 COM1 COM2 COM3 COM4 CTR RESET COM3 COM4 DOWN COM3 COM4 DA12 COM3 COM4 DA8 COM3 COM4 DA4 COM3 COM4 DA0 Y8 Y1 Y2 OUT3 Y4 Y8 Y1 Y2 IN3 Y4 Y8 S1/OT1~OT4 0 COM1 /OT1 COM2 /OT2 COM3 /OT3 DAL address 1 DA1 DA2 DA3 DA0 DAL address 1 DA1 DA2 DA3 S2/OT5~OT8 1 COM1 /OT5 COM2 /OT6 COM3 /OT7 DAL address 2 DA5 DA6 DA7 DA4 DAL address 2 DA5 DA6 DA7 S3/OT9~OT12 2 COM1 /OT9 COM2 /OT10 COM3 /OT11 DAL address 3 DA9 DA10 DA11 DA8 DAL address 3 DA9 DA10 DA11 S4/OT13~OT16 3 COM1 /OT13 COM2 /OT14 COM3 /OT15 DAL address 4 DA13 * * DAL address 4 DA12 DA13 0 0 S5/OT17~OT18 4 COM1 /OT17 COM2 /OT18 S6 5 COM1 6 COM1 7 COM1 8 COM1 9 COM1 A COM1 B COM1 C COM1 COM2 S14 D COM1 COM2 S15 E COM1 COM2 S16 F COM1 COM2 COM3 COM4 DISP OFF LCD OFF COM3 COM4 COM3 COM4 COM3 COM4 COM2 S13 COM3 COM4 COM2 S12 COM3 COM4 -0 -1 COM2 S11 COM3 COM4 -0 -1 COM2 S10 COM3 COM4 -0 -1 COM2 S9 COM3 COM4 S19 S20 COM2 S8 COM3 COM4 S15 S16 COM2 S7 COM3 Pulse counter control POL * * Pulse counter data PC0 PC1 PC2 PC3 Pulse counter control OVER RESET * * Pulse counter data PC4 PC5 PC6 PC7 Segment/IO select S17 S18 OVER Pulse counter data 0 0 0 Segment/IO select S21 S22 I/O control 1 -2 -3 I/O control 2 -2 -3 I/O control 4 -2 -3 LCD control * OTB-UP 23 2004-09-13 TC9328AF I/O map All of the ports within the device are expressed with a matrix of six I/O instructions (OUT 1 to 3 instructions and IN 1 to 3 instructions) and a 4-bit code number. The allocation of these ports is shown on the following page in the form of an I/O map. The ports used in the execution of the various I/O instructions on the horizontal axis of the I/O map are allocated to the port code numbers indicated on the vertical axis. The G-register, data register, DAL address register and DAL bits are also used as ports. The OUT1 to 3 instructions are specified as output ports and the IN 1 to 3 instructions are specified as input ports. Note: The ports indicated by the angled lines on the I/O map do not actually exist within the device. The contents of other ports and data memories are not affected when data is output to a non-existent output port with the execution of the output instruction. The data loaded from data memories is unfixed when a non-existent input port has been specified with the execution of an input instruction. Note: The output ports marked with an asterisk (*) on the I/O map are not used. Data output to these ports assume the don't care's status. Note: The Y1 contents of the ports expressed in 4 bits correspond to the data memory data's low order bit and the Y8 contents correspond to the high order bits. The ports specified with the six I/O instructions and code No. C are coded in the following manner: [K/L] mn (o) Contents of the selection port (indirectly specified data, 0-F [HEX]) I/O instruction's operand CN (0~F [HEX]) The six I/O instructions are coded with the digits 1 to 3 I/O Instruction m OUT1 1 OUT2 2 OUT3 3 IN1 1 IN2 2 IN3 3 Indicates the input/output port K: Input port (IN1~IN3 instruction) L: Output port (OUT1~OUT3 instruction) (Example) The setting for the G-register is allocated to code "D" and "E" in the OUT1 instruction. The encoded expression at this time becomes "L1D"and "L1E". Crystal Oscillation Circuit 75 kHz crystal oscillator is connected to the device's crystal oscillator pin (XIN, XOUT) as indicated below. Usually, the oscillation signal is supplied to the clock generator, the reference frequency divider and other elements, and generates the various CPU timing signals and reference frequency. (XOUT) 70 R X'tal = 75 kHz 71 (XIN) 72 (GND) 73 CO X'tal CI Note: It is necessary to use a crystal oscillator with a low CI value and favorable start-up characteristics. Please adjust and determine external resistance and the constant of a capacitor as the actually used crystal oscillator. 24 2004-09-13 TC9328AF System Reset The device's system will be reset when the RESET pin is subject to the "L" level or when a voltage of 0 V 0.9 V or more is supplied to the VDD pin (power-on reset). The program will start from 0 address immediately after about 100 ms stand-by time. The RESET pin should be fixed at the "H" level as the power-on reset function is used under normal condition. Note: A power-on reset function can be forbidden with Al switch. Please specify power-on reset prohibition and use in ES order request sheet. In case of forbidden the power-on reset function, reset with a RESET pin. Note: The LCD common signal and the segment output will be fixed at the "L" level during system reset and the subsequent stand-by period. Note: Among the internal port shown in the above I/O map, the port which is not initialized after the system reset should be initialized by the program. The inside port on the I/O map, the port or bit with mark on I/O map is set to "0" after system reset and the port or bit with mark is set to "1". The port or bit with no mark is unfixed. I/O L2F OUT2 I/O L1 OUT1 L2D 8 Y1 Y2 Y4 Y8 Code Y1 Y2 Reference select Y4 Y8 Programmable counter I/O control -1 5 -0 -1 -2 -3 R0 R1 R2 P16 After system reset, this port is set to "0". After system reset, this port is set to "1". After system reset, this bit is unfixed. (Note) VDD pin (Note) GND RESET pin GND A crystal oscillator stops during the reset from a reset pin. XOUT pin Stand-by (about 100 ms) Reset CPU operation Stand-by CPU (about 100 ms) operation Stand-by (about 100 ms) CPU operation Internal reset signal Note: When power supply voltage may become below 0.9 V, set up the clock stop mode or operate the reset function. The CPU operations are reset when a power supply voltage is re-apply from 0.3 to 0.6 V. (Power-on reset) 25 2004-09-13 TC9328AF Back-up Mode By executing CKSTP instruction or WAIT instruction, three kinds of back-up mode can be activated. 1. Clock Stop Mode The clock stop mode is a function that suspends system operations and maintains the internal status immediately prior to suspension at a low level of current consumption (under 1 A). Crystal oscillations suspend simultaneously and CMOS output ports and output pins for LCD display are automatically fixed at the "L" level and N-channel open drain pins are fixed off status (high impedances) automatically. The supply voltage can be reduced to 0.75 V with the clock stop mode. Suspension is activated at the CKSTP instruction execution address when the CKSTP instruction is executed. The next address is executed after approximately 100 ms of stand-by time when the clock stop mode is cancelled. (1) Clock stop mode setting There are two types of mode setting for the clock stop mode. The required setting is selected with the CKSTP MODE bit. This bit is accessed with the OUT2 instruction for which [CN = 6H] has been specified in the operand. Y1 L26 Y2 Y4 CKSTP mode 0: MODE-0 1: MODE-1 Y8 MODE-0 By setting this mode, the clock stop mode is assumed if the CKSTP instruction is executed when the HOLD pin is in the "L" level. The same operations as the NOOP instruction will be assumed if the CKSTP instruction is executed when the HOLD pin is in the "H" level. MODE-1 By setting this mode, the clock stop mode is assumed when the CKSTP instruction is executed regardless of the HOLD pin level. Note: PLL will assume the off status during CKSTP instruction execution. Note: Before the execution of the clock stop instruction, be sure to access HOLD input pin and I/O port 1 input port and reset the 2 Hz F/F. If the clock stop mode is executed without executing the instruction, it may not be the mode. (2) Canceling the clock stop mode MODE-0 The clock stop mode is cancelled when specified in this mode by changing the "H" level of the HOLD pin or the input status of I/O port (P1-0~3) specified in the input port. MODE-1 The clock stop mode is cancelled when specified in this mode by changing the HOLD pin or the input status of I/O port (P1-0~3) specified in the input port. 26 2004-09-13 TC9328AF (3) Clock stop mode timing MODE-0 HOLD pin High impedance XOUT pin CPU operation CKSTP instruction NOOP operation CKSTP instruction execution NOOP operation Clock stop Stand-by (about 100 ms) CPU operation (The clock stop mode is assumed when the CKSTP is executed during the "L" level of the HOLD input.) MODE-1 HOLD pin High impedance XOUT pin CPU operation CKSTP instruction CKSTP instruction execution CKSTP instruction execution Clock stop Stand-by (about 100 ms) CPU operation Clock stop (The clock stop mode is assumed whenever the CKSTP instruction is executed.) (4) Example of a back-up circuit (example of a MODE-0 circuit) 0.1 F VDD 31 VDD 50 POWER VDD 31 VDD 50 POWER 470 F 0.1 F 0.1 F 4700 F 0.1 F 1 k HOLD 42 1 M HOLD 42 1 M Example of a battery back-up circuit 1 k Example of a capacitor back-up circuit 27 2004-09-13 TC9328AF 2. Wait Mode The wait mode suspends system operations, maintains the internal status immediately prior to suspension and reduces current consumption. There are two types of wait mode available; the SOFT WAIT mode and the HARD WAIT mode. It is suspended at the address of the WAIT instruction execution when the WAIT mode is activated. The next address is executed immediately after the wait mode is cancelled without entering a stand-by status. (1) SOFT WAIT mode Only the CPU operations within the device are suspended when the WAIT instruction in which [P = 0H] has been specified in the operand is executed. The crystal resonator and other elements will continue to operate normally at this time. The SOFT WAIT mode is efficient in reducing current consumption during clock operations used in programs that include clock functions. Note: Current consumption will differ in accordance with execution time of CPU operation. (2) HARD WAIT mode The operations of all elements, with the exception of the crystal resonator, can be suspended by the execution of the WAIT instruction in which [P = 1H] has been specified in the operand. This enables even greater levels of current consumption reduction than the SOFT WAIT mode. It suspends the CPU operation. Note: The output port is maintained during the HARD WAIT mode. All LCD display output pin are fixed "L" level and voltage doubler circuit (VDB), constant voltage circuit for LCD (VEE) and voltage doubler circuit for LCD (VLCD) are operated. (3) Wait mode setting The wait status is assumed whenever the WAIT instruction is executed. Note: The PLL OFF status will be assumed during the wait mode. (4) Wait mode cancellation conditions The wait mode is cancelled when the following conditions are fulfilled: When the input status of the HOLD pin changes. When the input status of the I/O port specified in the input port (P1-0~3) changes. When the 2 Hz Timer F/F is set to "1" (only with the SOFT WAIT mode) 3. HOLD Input Port Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 K17 HOLD L39 0: Input "L" level 1: Input "H" level HOLD PLL OFF control 0: Do not control PLL OFF with a HOLD pin 1: PLL OFF mode with "L" level of HOLD pin The HOLD pin can be used as an input port. This bit loads data input with IN1 instruction for which [CN = 7H] has been specified in the operand into the data memory. It is necessary to access this port prior to the execution of the Back-up instruction when the clock stop mode or WAIT mode has been set. It is necessary to note that there are cases when the clock stop mode will not be activated if the Back-up instruction is executed without this port being accessed. While HOLD PLL off control bit is set to "1", if HOLD pin input "L" level, it will become PLL off-mode. For this reason, a setup in PLL off-mode can be made quickly at the time of battery exchange. The bit is accessed with the OUT3 instruction for which [CN = 9H] has been specified in the operand. All of the reference port is "1", it also becomes PLL off mode. ( Refer to the reference frequency divider item) 28 2004-09-13 TC9328AF Interrupt Function The peripheral hardware which can use Interrupt function has INTR1 pin, INTR2 pin, Timer counter, and Serial interface. The peripheral hardware fulfill conditions, Interrupt demand signal from peripheral hardware is all input, and Interrupt demand is transmitted. When it is received, it branches out vector address determined by each Interrupt factor. Each Interrupt processing routine is started. The pretreatment for returning to the same state as the time of Interrupt, before and after usually carrying out Interrupt processing, and post-processing are required of Interrupt routine. It is necessary to perform shunting and a return for the register data memory used by ALU to the data memory for interchange. When ending Interrupt processing, a program is returned by the return command for Interrupt. 1. Interrupt Control Circuit Interrupt control circuit consists of an Interrupt enable flag, an Interrupt latch, and an Interrupt priority circuit block. This control performs setup and control by OUT2/IN2 instructions. (1) Interrupt enable flag Interrupt enable flag has an individual permission flag corresponding to a master permission flag and each Interrupt factor. An individual enable flag sets up prohibition/permission of Interrupt corresponding to each Interrupt factor. A master enable flag is a flag for which performs prohibition/permission of all Interrupts. If these enable register is set to "1", it becomes permission and is set to "0", it becomes prohibition. An individual enable flag is accessed with OUT2/IN2 instructions for which [CN = 8H] has been specified to the operand. A master enable flag can perform permission/prohibition by execution of an EI/DI instruction. A master enable flag is a flag which performs prohibition/permission of all Interrupts. If these enable register is set to "1", it becomes enable and is set to "0", it becomes prohibition. In case of forbidding Interrupt in a program, it executes DI instruction, and in case of enabling, it executes EI instruction. At this time, Interrupt is enabled during the EI instruction execution in a program, and the DI instruction execution. If master enable flag is received the Interrupt request, it is reset by "0" and all Interrupts will be in a prohibition state. By executing of Interrupt return instruction, it is set to "1". A master enable flag is read into data memory by IN2 instruction for which [CN = 7H] has been specified. Y1 Y2 EF2 Y4 EF3 Y8 EF4 LK28 EF1 An individual enable flag EF1 * * * INTR1 pin EF2 * * * INTR2 pin EF3 * * * Serial interface EF4 * * * 8-bit timer counter "0" * * * Prohibition "1" * * * Enable Y1 Y2 0 Y4 0 Y8 0 K27 IMF Master enable flag It's reset to "0" when it is able to receive interrupt or DI instruction execution. It's set to "1" by Interrupt return instruction or EI instruction execution. 29 2004-09-13 TC9328AF (2) Interrupt latch If Interrupt request generates, interrupt latch is set to "1". If Interrupt is enabled, Interrupt reception will be required of CPU and it will branch Interrupt routine. If Interrupt is received at this time, Interrupt latch is reset by data "0" automatically. Interrupt latch data can read by the program and judge individual existence or nothing of interrupt generating. By interrupt request, interrupt latch is reset from "1" from setting "0", it is able to cancel interrupt request or initialization. Y1 Y2 ILR2 Y4 ILR3 Y8 ILR4 L29 ILR1 Interrupt latch reset If it's set to "1", interrupt latch is reset to "0". Y1 Y2 ILR2 Y4 ILR3 Y8 ILR4 0: No interrupt existence 1: Interrupt existence ILR1 * * * INTR1 pin ILR2 * * * INTR2 pin ILR3 * * * Serial interface ILR4 * * * 8-bit timer counter If the interrupt request, it's set to "1", receiving interrupt, It's reset to "0". K29 ILR1 Interrupt latch data (3) Interrupt priority circuit block Interrupt priority circuit is a circuit of determined the ranking of the interrupt generating when interrupt occurs simultaneously or interrupt permit after two or more interrupts had occurred. Vector address to interrupt routine is also generated by this block. Priority 1 2 3 4 Interrupt Factor INTR1 pin INTR2 pin Serial interface Timer counter Vector Address 0001H 0002H 0003H 0004H 30 2004-09-13 TC9328AF 2. Interrupt Reception Processing Interrupt request is maintained until it receives interrupt or reset to "0" to interrupt latch by system reset operation or by the program. Interrupt reception operation is as shown below. Each peripheral hardware is output each interrupt signal and set to "1" to interrupt latch if interrupt conditions are fulfilled. Interrupt latch of Interrupt factor received resets to "0" if interrupt enable flag and the master enable flag corresponding to each Interrupt factor set to "1" Interrupt master enable flag resets to "0" and interrupt is forbidden. The contents of a stack pointer are -1. The contents of program counter (PC) evacuates stack register. At this time, the contents of a program counter become the following address, which permitted the next address or next interrupt at the time of interrupt being received. The contents of vector address corresponding to received interrupt transfers to program counter. Executes the contents of vector address. These executions ~ are executed during 1 instruction cycle. The instruction cycle is called "Interrupt cycle". Note: Stack pointer is the pointer which specifies the 8-level stack register. Reference of the contents of a stack pointer cannot be performed. In case of Interrupt enable period Instruction EI Instruc -tion Set "1" to individual enable flag Interrupt cycle IMF (Master enable flag) Interrupt signal Interrupt signal IL (Interrupt latch) EF (Individual enable flag) One instruction cycle Interrupt enable period Interrupt processing routine Interrupt reception In case of interrupt reservation period EI instruction Set "1" to individual enable flag Interrupt cycle Instruction IMF (Master enable flag) Interrupt signal Interrupt signal IL (Interrupt latch) EF (Individual enable flag) Interrupt reservation period Interrupt processing routine Interrupt reception 31 2004-09-13 TC9328AF 3. Return Processing from Interrupt Processing Routine In order to make it return to processing before receiving Interrupt from Interrupt processing routine, RNI instruction which is an exclusive command is used. Execution of RNI instruction follows the processing automatically one by one. The contents of address stack, which is specified with a stack pointer, are returned to a program counter. Set "1" to interrupt master enable and changes into an enable state. The contents of a stack pointer are done +1. RNI instruction of the above-mentioned processing is processed in 1 instruction cycle. 4. Interrupt Processing Routine Interruption is received regardless of the program currently performed when an interruption request will be done if it is the program area where interruption is enabled. Therefore, after doing interrupt processing, when making it return to the program of a basis, it is necessary to return to the state where it is performed by interrupt processing. For this reason, it is necessary to perform shunting and return operation within an interruption processing routine about a register, a data memory, etc. which may be operated within an interruption processing routine at least. (1) Shunting processing In execution of shunting processing, a carry flag surely needs to be shunted. If interruption is received during execution of arithmetic operation, the contents will change about carry flag (CY) etc. and the program after a return will mistake judgment. For this reason, the contents of a carry flag are shunted in a data memory at once by IN1 instruction in the data of the carry flag in I/O map. The contents of the data memory used by the interruption processing routine and the contents of a general register are also made to shunt if needed. Furthermore, when MVGD, MVGS or DAL instruction is used in interrupt routine, it's necessary to shunt the contents of G-register or DAL address register. Return processing Return processing should just do opposite to the above-mentioned shunting processing. If interrupt is received, interrupt master enable flag is reset by "0", before receiving interrupt, an interrupt master enable flag must have been "1". For this reason, RNI instruction is executed and a master enable flag is returned. (2) 5. Multiplex Interrupt Multiplex Interrupt is the method of processing another interrupt during interrupt processing. As shown in the figure, another interrupt factor C or D is processed during interrupt processing to a certain interrupt factor A and B. The depth of interrupt at this time is called interrupt level. Main routine Interrupt level 1 Interrupt level 2 Interrupt level 3 Interrupt level 4 MAIN B D A B C D C The example of multiplex interrupt 32 2004-09-13 TC9328AF Note the following points when using multiplex interrupt. The priority of interrupt factor Restriction of the address stack level used at the time of interrupt request issue Shunting processing of a carry flag, a data memory, etc. (1) Priority of interrupt factor The priority of multiplex interrupt is A < B < C < D in the figure. In this priority, interrupt of C must be processed prior to interrupt of A or B even if it is under processing and even if interrupt of C is under processing, interrupt of D must be given priority. For example, there are interruption factors A and B, it assumed that the factor of A requests every 10 ms and the interrupt processing time is 4 ms and the factor of B requests every 2 ms and the interrupt processing time is 1 ms. When there is no priority of A and B, if an interrupt requests of A enters during interrupt processing of B interrupt, processing of A is done and it will stop doing interrupt processing of B. In such a case, it is necessary to program that give the priority of A < B and forbid interrupt of A during interrupt processing of B, and even if interrupt of B is received under processing of interrupt of A. When all individual enable flags is setup "1" (enable state), it becomes the priority by the hardware explained according to the item of an interrupt priority circuit block, the priority of hardware is changeable by operating an individual enable flag by the program. Usually, in interrupt processing routine, received interrupt and low priority interrupt is forbidden and high priority interrupt of Interrupt is enabled. Restriction of address stack level As the item of Interrupt reception processing explained, when interrupt request was done, the return address is shunted automatically to address stack. As the register item explained, an address stack is used also for execution of a sub routine call instruction on eight levels. For this reason, if interrupt level and a sub routine call level exceed eight levels, it returns and the contents of an address stack which was recorded from the first will be destroyed, it is necessary to use it so that this may not be exceeded. Shunting processing When using multiplex interrupt, it is necessary to secure the shunting area of shunting processing separately to each Interrupt factor. (2) (3) 33 2004-09-13 TC9328AF External Interrupt and Timer Counter Function External interrupt has two types of INTR1 pin and INTR2 pin. Interrupt request is done by the rising or falling edge of a signal added to these pins. Timer counter is 8-bits binary counter and has the function of timer and external clock timer. The input of external clock timer function is used as external interrupt pin (INTR1, INTR2). 1. External Interrupt Function External interrupt has two types of INTR1 pin and INTR2 pin and the edge of these inputs is detected and Interrupt request is done. Input has noise cancel circuit, the frequency of 75 kHz is used for a noise removal clock and the pulse of under this frequency is removed as a noise. IE bit is enable bit which permits 8-bit timer counter operation or interrupt and external interrupt request. The rising or falling edge used as input edge can choose for every pin. Usually, this bit is set "1". These controls are accessed with OUT2 instruction for which [CN = 7H] has been specified in the operand. If Interrupt of INTR1 pin is received, the program will branch to 0001H address and a program will branch to 0002H address at the time of INTR2 pin. These pins are used as input port and the input status can read into data memory by execution of the IN2 instruction for which [CN = 7H] has been specified in the operand. Y1 Y2 Y4 IE Y8 L27 POL1 POL2 * INTR1 INTR2 Edge select 8-bit Timer and control external interrupt operation enable 0: Prohibition 1: Enable Usually, the bit is set to "1". 1: Rising edge 0: Falling edge Reduce less than 13.3 s pulse More than 40 s regards as a signal certainly.) Note: The edge of the external clock of timer counter is also controlled. The Timer counter input is not used the function of noise cancel function. For this reason, even if external Interrupt does not occur, it is 40 (since the clock pulse of under s is inputted into counter, cautions are required.). 1: Count by rising edge 0: Count by falling edge Select edge of timer counter Y1 Y2 INTR1 Y4 INTR2 Y8 0 0: Input "L" level 1: Input "H" level K27 The each input state Note: Interrupt request may be transmitted if edge is changed by POL bits. For this reason, when changing edge, it changes after forbidding Interrupt, and Interrupt latch is reset, and it returns to usual operation. 34 2004-09-13 TC9328AF 2. Timer Counter Function Timer counter are consists of 8-bit binary counter, counter coincidence register, digital comparator and controlled the control circuit. If timer counter is coincided with the contents of counter coincidence register, timer counter is outputted a coincidence signal pulse and interrupt request is done by inputting timer clock to 8-bit binary counter timer clock. Reset of Timer counter is possible with a coincidence pulse and a program, and it can perform enable and prohibition of reset by the coincidence pulse. As a clock of timer, it can be selected INTR1/2 input and an instruction cycle and 1 kHz. (1) Timer counter register configuration The register of timer counter consists of counter data, coincidence register and control register. Y1 Y2 ID1 Y4 ID2 Y8 ID3 Y1 Y2 ID5 Y4 ID6 Y8 ID7 L2A ID0 L2B ID4 Timer counter coincidence data A coincidence pulse will be output in accordance with timer counter. Y2 ID5 Y4 ID6 Y8 ID7 Y1 Y2 ID1 Y4 ID2 Y8 ID3 Y1 K2A ID0 K2B ID4 Timer counter data Timer counter data is read into data memory as a binary data. Y1 Y2 CK1 Y4 GT Y8 CR L2C CK0 Select timer clock Timer counter reset * * * "Whenever sets "1", counter is reset. Enable counter reset by coincidence pulse. 0: Enable 1: Prohibition CK0 0 0 1 1 CK1 0 1 0 1 Timer clock INTR1 pin input INTR2 pin input Instruction cycle clock (40 s) 1 kHz Select clock edge by POL bit 0: Count by raising edge 1: Count by falling edge Note: It's necessary to set "1" to IE bit when it uses timer counter. 35 2004-09-13 TC9328AF (2) Timer mode Timer mode is detected fixed time. Interrupt request is done and reset to counter whenever it detects fixed time. At this time, control bit is set to 1 kHz or an instruction as timer clock, "0" to GT bit and "0" (it does not reset) to CR bit. Timer coincidence data is Timer time = IDn (coincidence data) x Timer clock cycle It sets up the data which corresponding to time. In addition, although an external pin can be used for Timer clock, a clock frequency should use the frequency below 25 kHz. If GT bit is setup "1", it can also be integrated of an external clock. It is used by inputting more than 40 s cycle at the time of an external clock input. Timer clock Timer data IDn 00H 01H 02H 03H ID (n - 1) IDn 00H 01H 02H 03H Coincidence pulse Coincidence pulse Request for interrupt and reset timer counter. 36 2004-09-13 TC9328AF Internal Interrupt and Interrupt Function Interrupt has two types of timer counter and serial interface. 1. Interrupt of Timer Counter If timer counter value is the same as coincidence register value, interrupt of timer counter is transmitted interruption. Refer to the item of timer counter function for details. 2. Interrupt of Serial Interface Interrupt of serial interface is transmitted interruption at the time of finishing operation of serial interface. Refer to the item of serial interface function for details. 3. Interruption Block Configuration Serial interface interrupt 75 kHz ILR1 INTR1 43 POL1 INTR2 44 Noise canceller Noise canceller ILR1 ILR1 ILR1 S IL1 R S IL2 R S IL3 R S IL4 R 1 kHz Instruction cycle clock INTR2 INTR1 POL2 EF1 EF2 EF3 EF4 Decoder Priority determination * Vector address generate circuit La Vector address Interrupt receiving signal CK0 CK1 Selector CT0~CT7 CR 8-bit binary counter R Coincidence pulse Coincidence register (ID0~ID7) GT DI instruction RNI instruction EI instruction S IMF R 37 2004-09-13 TC9328AF Programmable Counter The programmable counter consists of two modulus prescaller, a 4-bit + 13-bit programmable counter and a port to control these elements. The programmable counter controls the ON/OFF functions for the contents of the reference port and HOLD input status. By using external prescaller (TD6134AF/TD7101/04F) or 1 chip tuner IC that is built-in for 1/16 prescaller (TA2142FN), it's possible to reduce the emission from the tuner portion and consumption current. 1. Programmable Counter Control Port This port is controlling for division frequency, division method and operating current and gain of prescaller. Y1 L10 HF Y2 PW0 Y4 PW1 Y8 FM Power control Division method setting L11 Y1 P0 Y2 P1 Y4 P2 Y8 P3 L12 Y1 P4 Y2 P5 Y4 P6 Y8 P7 L13 Y1 P8 Y2 P9 Y4 Y8 L14 Y1 Y2 Y4 Y8 L15 Y1 Y2 Y4 Y8 P16 P10 P11 P12 P13 P14 P15 LSB A setup of the number of division of programmable counter MSB The division method and power control of prescaller are accessed with the OUT1 instruction for which [CN = 0H] has been specified in the operand. The division frequency setting is accessed with the OUT1 instruction for which [CN = 1~5H] has been specified and setting is by writing in the P16 bit (L15). All data between P0 to P16 are updated when P16 is set. It is therefore necessary to access P16 even when updating only certain items of data and to perform setting as the final process. Y1 L39 Y2 Y4 Prescaller IN Y8 PSC ENA 0: PSC output prohibition 1: PSC output permission PSC output permission setup Prescaller IF counter input setup 0: Regular PLL composition 1: Prescaller division output is inputted to IF counter. PSC output permission setup is used at the time of connection of external prescaller. In the setup to prescaller IF input, if the bit is set to "1", a programmable counter stops and prescaller 1/15 and 16 are fixed to 16 division. Usually, consisting of PLL, the bit is set to "0". ( Refer IF counter item) 38 2004-09-13 TC9328AF 2. Division Method Setting The pulse swallow method or direct method are selected with the HF and FM bit. The power control bits (PW0/1) are controlled the gain of amplifier and prescaller (1/2 + 1/15*16). Although the power bit in each mode has five methods, set up it as shown in the table. By using 1 chip tuner IC that is built-in for 1/16 prescaller (TA2142FN), set up to the LF mode and set the division value after 1/16 division frequency. Example of Receiving Band MW/LW SW FM TV (1 ch~12 ch) Operation Frequency Range 0.5~8 MHz 3~30 MHz 1~10 MHz 30~130 MHz FMin 50~230 MHz 2*n AMin n Division Number (Note) Mode LF HF1 HF2 FM VHF HF 0 1 1 1 1 PW0 1 1 0 1 0 PW1 0 0 1 0 1 FM 0 0 0 1 1 Division Method Direct division method Pulse swallow method (1/15*16) Pulse swallow method (1/2 + 1/15*16) Input Pin Note: "n" represents the number of divisions programmed. Note: It may not operate normally with abnormal current dissipation or unlocked PLL etc. 3. Frequency Division Number Setting The frequency division number for the programmable counter is set in bits P0 to P16 in binary. * Pulse swallow method (17 bits) MSB P16 P15 P14 P13 P12 P11 P10 2 16 LSB P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 2 0 The range of frequency division number setting (n = 210H~1FFFFH (528~131071)) * Direct division method (13 bits) MSB P16 P15 P14 P13 P12 P11 P10 12 LSB P9 P8 P7 P6 P5 P4 0 P3 P2 P1 P0 2 2 The range of frequency division number setting (n = 10H~1FFFH (16~8191)) Don't care 39 2004-09-13 TC9328AF 4. PSC Output Permission Setting In case of using the external pre-sccaler (TD6134AF/TD7101/04F), PSC output permission bit is setup to "1". At this time, a swallow counter will be operating and prescaller will be in a stop state, and PSC output is outputted P2-3 pin. A division method is set as LF mode, and AM VCO input and an external prescaller output are changed and inputted into AMin input pin. P2-3 pin is used by setting it as an output port. TC9328AF TD6134AF PSC 35 7 PSC AMin 49 0.01 F 0.001 F 0.001 F AM VCO FM/TV VCO 5 OUT 2 FMin 3 VHFin The example of an external prescaller connection circuit 5. Programmable Counter Circuit Configuration * Pulse swallow method circuit configuration This circuit consists of amplifier, 1/2 prescaller, two 1/15*16 modulus prescallers, the 4-bit swallow counter and a 13-bit binary programmable counter. A 1/2 frequency divider is added to the front stage of the prescaller in the VHF/FM mode. P0~P3 PW0/1 4-bit swallow counter Pre-set 13-bit programmable counter To the phase comparator FMin 0.01 F 48 AMin 0.01 F 49 Amplifier 1/2 1/16 1/15*16 1/15 P4~P16 40 2004-09-13 TC9328AF * Direct division method circuit configuration The prescaller is not required if this is selected, and instead, the13-bit programmable counter is used. PW0/1 Amplifier AMin 49 Pre-set 13-bit programmable counter To the phase comparator P4~P16 Note: FMin and AMin contain the amplifier, and small-size width operation can be performed by connecting them to a capacitor. In the division method, when non-selected input pins are in PLL off mode, the input becomes high impedance. Therefore FMin and AMin can be used as wired-OR configuration as shown below. Note: If it becomes PLL off-mode, all programmable counter parts will be stopped. The contents of each control port are held at this time. FM/TV VCO 0.001 F 48 FMin AM/FM/TV VCO 0.001 F 48 FMin AM VCO 0.001 F 49 AMin 49 AMin The example of connection circuit using VSO for each FM and AM band The example of connection circuit using VSO with FM and AM bands 41 2004-09-13 TC9328AF Reference Frequency Divider The reference frequency divider divides the oscillation frequency of the external 75-kHz crystal and generates the following seven types of PLL reference frequency signals; 1 kHz, 3 kHz, 3.125 kHz, 5 kHz, 6.25 kHz, 12.5 kHz and 25 kHz. These signals are selected with reference port data. The selected signal is supplied as a reference frequency for the phase comparator as described below. Also, the PLL is switched on and off with the contents of the reference port. 1. Reference Port The reference port is an internal port for selecting the seven reference frequency signals. This port is accessed with the OUT1 instruction for which [CN = 5H] has been specified in the operand (L15). Operations for the programmable counter, the If counter, reference counter and the phase comparator are suspended and the PLL assumes the off mode when the contents of the reference port are all "1". As the frequency division setting data for the programmable counter is updated when the reference port is set, it is necessary to set the frequency division number of the programmable counter prior to setting the reference port. Y1 L15 R0 Y2 R1 Y4 R2 Y8 R2 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 Reference Frequency 1 kHz 3 kHz 3.125 kHz 5 kHz 6.25 kHz 12.5 kHz 25 kHz PLL off mode Reference frequency selection code 42 2004-09-13 TC9328AF Phase Comparator and Lock Detection Port The phase comparator compares the difference in phasing between the reference frequency signal supplied from the reference frequency divider and frequency division output of the programmable counter and outputs the result. Then it controls the VCO (Voltage control oscillator) via a low pass filter in order to ensure that the two frequency signals and the phase difference match. Two tristate buffer DO1 and DO2 are outputted in parallel from the phase comparator, the filter constant can be designed for each VHF and AM bands. A charge pump output uses constant voltage Vreg potential (1.5 V) so that a stabilized phase comparison machine can be used when VDD potential is 0.9 V. Also DO2 pin can be used with DO2 control port as general-purpose output port and charge pump signal (P, N) can be outputted from DO1 and DO2 pins. Therefore it is possible to use an external charge pump. 1. DO1 control Port and the Unlock Detection Port Y1 L19 UNLOCK RESET Y2 Y4 DO2 control Y8 PN M1 0 0 0 1 1 * 0 1 0 1 * M1 M0 DO2 Output Status DO1 Output Status DO output "L" level "H" level "HZ" N output P output DO output PN M0 DO2 output setting PN output setting 0 0 0 1 Unlock F/F and unlock enable are reset whenever the data is set to "1". Y1 K19 Y2 Y4 Y8 UNLOCK F/F ENA Unlock enable 0: PLL unlock detection stand-by 1: PLL unlock detection enabled Unlock detection bit 0: PLL lock status 1: PLL unlock status M0 and M1 bit of DO2 control ports perform a general-purpose output port setup of DO2 output, and a setup of high impedance. PN bit performs control setup of an external charge pump for DO1/2 pins as P/N output. Unlock F/F detects the phase difference of a programmable counter division output and reference frequency to the timing from which about 180 degrees of phases shifted. When a phase does not suit at this time (that is unlock status), unlock F/F is set. The unlock F/F status is reset whenever the UNLOCK RESET bit is set to "1". It is necessary to access to UNLOCK F/F after establishing more time than is required for the reference frequency cycle after the unlock F/F has been reset in order to detect the phase difference with the reference frequency cycle. It is for this purpose that the enable bit has been made available, but the unlock F/F must not be accessed before it has been confirmed that the unlock enable has been set at "1". Note: When P/N output and DO output are set up in PLL off-mode state, these outputs are high impedance. This state is held when PLL off-mode or clock stop mode is set up at outputting "L" or "H" level of DO2 pin. Note: When PN output is setup, "H" level of DO1/2 pin is output as VDD level and Vreg potential (1.5 V) is output as "H" level for other settings. 43 2004-09-13 TC9328AF 2. Phase Comparator and Unlock Port timing Reference frequency Programmable counter output High impedance DO output "H" level (Vreg) "L" level (GND) Phase difference Lock detection strobe Unlock reset execution Unlock F/F Unlock enable When PN = "1" is set up P output (DO1 pin) N output (DO2 pin) "H" level (VDD) "L" level (GND) "H" level (VDD) "L" level (GND) 3. Phase Comparator and the Unlock Port Circuit Configuration Vreg Reference frequency Phase comparator Programmable counter output PN bit Vreg UNLOCK ENABLE UNLOCK RESET UNLOCK F/F Decoder 31 DO2/OT/N Decoder 32 DO1/P M1, M0, PN bit VDB (VDD x 2 doubler power supply) PN bit Constant voltage circuit 33 Vreg PN bit Note: When PLL is off mode and PN bit is set to "1", Vreg pin becomes VDD level. 44 2004-09-13 TC9328AF C1 R2 DO1/P 32 R1 FM/VHF VCO C2 R4 DO2/OT/N 31 R3 LPF 0.47 F (typ.) Vreg 33 AM VCO DO2/OT/N 31 R2 VCO LPF Vreg 33 0.47 F (typ.) DO1/P 32 R1 C1 R3 When filter constant is set up for each band When LPF is used in common (Set DO2 as high impedance and switch the filter constant) DC-DC converter DO1/P 32 DC-DC converter 100 k 0.01 F 1 F DO2/OT/N 31 To the VCO variable capacitor 0.1 F To the VCO variable capacitor 10 k 4.7 k 32 DO1/P Vreg 33 Example of an active low pass filter circuit (for reference) Example of external charge pump circuit (when PN = "1" is set up) Note: The filter circuits illustrated in the above diagrams are for reference purposes only. It is necessary to examine the system band configuration and characteristic and design actual circuits in accordance with requirements. 0.47 F (typ.) 4.7 k 45 2004-09-13 TC9328AF IF Counter The IF counter is 20-bit general-purpose IF counter that calculates FM and AM intermediate frequencies (IF) during auto-tuning and can be used for detecting auto-stop signals, etc. VCO of an analog tuner is measured and detection of received frequency and detection of CR oscillation frequency can be performed. 1. IF Counter Control Port and Data Port Y1 L16 IF1/ 2 Y2 PW Y4 IF1/IN1 Y8 IF2/IN2 Selection of IF input /Input port 0: Set input port 1: Set IF input port Set IF amplifier gain set up "0" Selection IF input 0: Set IFin2 input 1: Set IFin1 input Note: At the time of an input port setup, the pin becomes CMOS input type and be able to detect frequency by IF counter. Selection of the gate time for frequency measurements (measurement time) G1 0 0 1 1 G0 0 1 0 1 Gate Time 1 ms 4 ms 16 ms 64 ms Y1 Y2 MANUAL Y4 G0 Y8 G1 L17 STA/ STP Selection of frequency measurements automatic/manual mode switching bit 0: Automatic mode (measurement is performed with the above-mentioned gate time) 1: Manual mode (Starts/stops measurements with the STA/ STP bits) IF counter start/stop control bit 0: Counter stop 1: Counter start Y1 Y2 IF counter Split Y4 Prescaller IN Y8 L39 FMin/AMin prescaller input setup at IF counter 0: Set IFin pin input 1: Set FMin/AMin pin input IF counter division operation setup 0: IF counter 20-bit operation 1: Inputs into 8 bits of IF counter higher ranks from INTR2 pin. Note: When a prescaller input is set as IF counter input, at the time of a setup of a pulse-swallow system, pre-scsler; 1/15*16 are fixed to 16 division, and this frequency is inputted into IF counter. Note: When a division operation setup of the IF counter is carried out, the counter of 8 bits of higher ranks is inputted from INTR2 pin. However, only 8 bits of this higher rank cannot perform a gate setup by the auto mode. Reset of this counter is reset by setting up "1" to STA/ STP bit. 46 2004-09-13 TC9328AF Y1 Y2 MANUAL Y4 OVER Y8 0 0: IF counter calculation value < 220 - 1 = 1: IF counter calculation value > 220 (overflow status) = 0: IF counter automatic mode 1: IF counter manual mode 0: IF counter calculation ended 1: IF counter calculation in progress K10 BUSY Overflow detection Operation mode Operation monitor K11 Y1 F0 20 LSB Y2 F1 Y4 F2 Y8 F3 K12 Y1 F4 Y2 F5 Y4 F6 Y8 F7 K13 Y1 F8 Y2 F9 Y4 Y8 K14 Y1 Y2 Y4 Y8 K15 Y1 Y2 Y4 Y8 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 219 IF counter data MSB Note: When it is set as IF input, in PLL off-mode, IF input amplifier is turned off in PLL-off mode. In using IF counter in PLL off-mode, it sets it as an input port (CMOS input). Note: The input amplifier un-chosen by IF1/2 bit. If input amplifier turns off, this input will serve as high impedance. (1) IF counter automatic mode A setup in the auto mode of IF counter is set "0" to MANUAL bit and gate time is set up according to the frequency band to measure. If the STA/ STP is set "1", operation of IF counter will be started and the set-up clock in gate time will be inputted, and this number of input pulses is counted and it ends. An end of the calculation of IF counter can be judged by referring to BUSY bit. When more 220 pulses are inputted for a total numerical value, OVER bit is set to "1". BUSY bit and OVER bit are judged "0" and the frequency inputted can be measured by taking in IF data of F0-F19. IF counter manual mode By internal time base (10 Hz etc.), it is used when gate time is controlled and it measures frequency. The manual mode is set "1" to MANUAL bit. At this time, a gate time setup serves as don't care. In STA/ STP bit is set to "1", it starts calculation. In STA/ STP bit is set to "0", it will end and calculation will take in data by the binary. An input setup and division setup of IF counter Usually, intermediate frequency (IF) Measurement is inputted into IFin1 or IFin2 pin input, and measures this frequency. These pins contain input amplifier and small-size width operation is possible. In addition, the following setup is possible to the input to IF counter, and use it for it according to specification. IF1/IN1 0 1 IF2/IN2 IF counter Split 0 0 0 0 Prescaller IN 0 0 0 0 IFin1 input (Amplifier operation) IN1 (IFin1) input (CMOS input) IFin2 input (Amplifier operation) IN2 (IFin2) input (CMOS input) VHF mode FMin input (32-divided frequency) FM mode (Note) (Note) (Note) IF Input Setup (2) (3) IF1/ 2 1 1 0 0 * * 0 1 * * * * * 0 1 HF1/2 mode LF mode AMin input (16-divided frequency) AMin input (inputted frequency) * * * 1 * Only 8 bits of higher ranks are inputted from INTR2 pin. Note: Refer to the programmable counter item for the input frequency range at the time of prescaller input setup. 47 2004-09-13 TC9328AF 2. IF Counter Circuit Configuration The IF counter consists of the input amplifier, the gate time control circuit and the 12 + 8 bits binary counter. The clock of FMin/AMin prescaller and can be inputted as an IF counter. PW0/1 FMin 0.001 F 48 amplifier 1/2 1/15*16 To programmable counter PSC AMin 0.001 F 49 Prescaller IN PW IF1/IN1 IFin1 0.001 F 45 IF2/IN2 IFin2 0.001 F 46 IF1/ 2 IN2 IN1 Prescaller IN F0~F11 12-bit binary counter IF counter Split F12~F19 8-bit binary counter OVER OVER Gate 1 kHz Gate time control circuit Manual G0 G1 INTR2 44 STA/ STP Note: All the binary counters of IF counter operate in a standup. Note: At inputting IF counter, dividing frequency of prescaller 1/15, 16 is fixed to 1/16. 1/32 for FMin input, and 1/16 or the direct input for AMin are enabled. IF counter input "1" Data set to STA/ STP bit BUSY bit 1 kHz Gate Binary counter input The example of IF counter auto mode operation timing 48 2004-09-13 TC9328AF LCD Driver The LCD driver uses the 1/4 duty and 1/2 bias drive method (62.5-Hz frame frequency). The common output outputs the VLCD, VLCD/2 (VEE) and the GND electrical potential, and the segment output outputs the VLCD and GND electrical potential. A combination of four common outputs and 22 segment outputs enables a maximum of 88 segments to be illuminated. The S15 to S22 pin for LCD driver are also used as the I/O port, after system reset is set as an I/O Port, and can perform a change of an I/O Port and a segment output per 1 bit. All LCD output pins (COM1-S14) can be changed to an output port. The LCD driver is built-in a constant voltage circuit (VEE = 1.5 V) for display purposes and a voltage doubler circuit (VLCD = 3.0 V), The constant voltage circuit for display (VEE) is used as for twice doubler voltage (VDB) is used. For this reason, LCD display stabilized even if power supply voltage was set to 0.9 V is possible. 1. LCD Driver Port Y1 Y2 SEL2 Y4 SEL4 Y8 SEL8 L2D SEL1 Data select Segment-1 data Y1 Y2 Y4 Y8 Y1 Segment-2 data Y2 Y4 Y8 L2E Y1 Y2 Y4 Y8 COM1 COM2 COM3 COM4 Y1 Y2 Y4 Y8 0 S1 1 2 S2 S3 L2F Y1 Y2 Y4 Y8 COM1 COM2 COM3 COM4 Y1 Y2 Y4 Y8 0 S17 1 2 S18 S19 COM1 COM2 COM3 COM4 5 Y1 S15 Y2 S22 S16 Y4 S17 Y8 S18 Y8 S22 Segment data 0: Illuminated 1: Extinguished COM1 COM2 COM3 COM4 F S16 Change for segment and I/O port 0: I/O port 1: Segment output 6 Y1 Y2 Y4 Segment /IO select S19 7 S20 S21 Segment /IO select LCD display off control bit 0: All LCD display illuminated 1: All LCD display extinguished LCD off control bit 0: LCD output setting 1: Output port setting Buffer capacity bit of output port (OT) 0: Low output buffer 1: High output buffer F DISP OFF LCD OFF OTB -UP * Note: It is available only when output port is set. When LCD is output, low buffer output is available. Note: When "1" is set at DISP OFF bit, common output becomes VEE level and all displays are turned off. Different from the situation in which all segment data is set to "0" at display status, the contrast slightly becomes bad. If extinguished status by DISP OFF bit is not favorable, set "0" to DISP OFF bit and all segment data, or set "1" to LCD bit and output "L" level at output port. Note: Segment data controls lighting/putting out lights of the segment corresponding to a common output and a segment output. Note: At the time of clock stop mode and about 100 ms after system reset, all the common output and segment output are fixed at "L" level. 49 2004-09-13 TC9328AF The LCD driver control port consists of the segment data selection port and the segment data port. These ports are accessed with OUT2 instruction for which [CN = DH~FH] has been specified in the operand. The segment data for LCD driver is set with the segment data ports (L2E, L2F). The LCD display will be extinguished when the segment data port is set at "0", and will be illuminated when set at "1". Also, the segment-2 data (L2FF) specified with FH in the segment selection port becomes the DISP OFF bit and LCD OFF bit without setting the segment data. It is possible to extinguish all LCD display with DISP OFF bit without setting the segment data. In this bit, if "1" is set, a common output and non selection wave form (fixed at VEE level) and LCD display all puts out the light. In that time, segment data is held and if DISP OFF bit is set "0", former display is stilled display on LCD. In addition, rewriting of segment data is possible during DISP OFF. Moreover, after reset and CKSTP instruction execution, DISP off-bit is set to "1". LCD OFF-bit can set all LCD output pins as an output port. In LCD display, this bit is set "0". ( Refer to output port item) S15 to S22 pin is used as I/O Port. This control is done at segment I/O port select port (L2F6, L2F7). If the port is set "1", it will become segment output port and set "0", It will become an I/O Port. ( Refer to output port item) These data is divided and undirected setting by data selects port (L2D). Set the data of a specification port of a segment data port in advance and access data port corresponding to it. A data select port is +1 increment whenever accessing data port (L2E, L2F). For this reason, after setting up a data selection port, it can set up continuously. Note: The data select port is +1 increment automatically by accessing L2E, L2F, L3B, K3B on I/O map. 2. LCD Driver Circuit Configuration COM1/OT1 COM2/OT2 COM3/OT3 COM4/OT4 S14/OT18 P8-0/S15 P8-1/S16 P9-2/S21 25 I/O-8*9 Port 75 kHz/2 1 2 3 4 5 6 7 18 19 20 26 DISP OFF 500 Hz Common output circuit Segment driver Segment data VLCD OFF 75 kHz/2 VDD Power supply voltage Double voltage circuit (VDD x 2) Constant voltage circuit (VEE = 1.5 V) Voltage doubler circuit (VEE x 2) To A/D converter Constant voltage circuit (Vreg) 76 72 74 77 78 79 0.47 F 0.1 F VLCD VDB C2 C1 VEE C3 C4 80 0.1 F 0.1 F Note: In case of setting I/O port, this output port is Nch open drain. Note: In case of setting segment output as output port in setup "1" to VLCD OFF bit, "H" level of all output becomes VLCD potential output. When "H" output is made into VDD remove the capacitor between C3/C4, and connect VLCD and VDD. Note: During the clock stop mode and reset, the potential of VLCD/VEE/VDB becomes as VDD level. 0.1 F 10 F 50 2004-09-13 P9-3/S22 S1/OT5 S2/OT6 S3/OT7 TC9328AF COM1 COM2 0 COM3 S1 S2 COM4 1 (S2) COM1 COM2 COM3 COM4 1 1 0 1 (S1) The example of segment data Segment data -1 (L2E) Y1 Y2 Y4 Y8 COM1 COM2 COM3 COM4 1 Y1 0 Y2 1 Y4 0 Y8 Segment data selection (L2D) DISP OFF 16 ms (62.5 Hz) 2 ms COM1 VLCD VEE GND VLCD COM2 VEE GND VLCD COM3 VEE GND VLCD COM4 VEE GND VLCD S1 GND VLCD S2 GND VLCD COM1-S1 (ON waveform) GND -VLCD VLCD COM2-S1 (OFF waveform) GND -VLCD The potential of LCD driver waveform outputs the potential of VLCD and GND, and the middle potential level. 51 2004-09-13 TC9328AF Serial Interface The serial interface is the serial I/O port which transmits and receives 4 bits or 8 bits data synchronizing with the internal or external serial clock. SI, SO and SCK pins perform the transmission and reception with LSI for extension and a microcomputer, etc. When a serial interface operation is finished, interruption is occurred. 1. The Serial Interface's Control Port and Data Port Y1 Y2 Y4 Y8 L22 edge SCK-INV SCK - I/ O SIO-ON Selection of the I/O port-4 and serial interface 0: I/O port-4 selection (P4-1~P4-3) 1: Serial interface function selection SCK clock external/internal selection 0: External clock output 1: Internal clock output Inversion of the SCK Clock signal 0: SCK clock output from "H" level 1: SCK clock output from "L" level Edge selection of serial data shift operation 0: Shift at the SCK rising edge 1: Shift at the SCK falling edge Y1 Y2 SO - I/ O Y4 8/4 bit Y8 L23 STA * Selection of the data length of serial data 0: 4-bit data 1: 8-bit data Selection of input and output of SO pin 0: SO output 1: SI input Serial operation start and internal port reset 0: don't care 1: Reset COUNT, SIO F/F and the serial output data in the shift register. Serial operation is started when the internal SCK clock is selected. 52 2004-09-13 TC9328AF Y1 Y2 SO1 Y4 SO2 Y8 SO3 Y1 Y2 SO5 Y4 SO6 Y8 SO7 L24 SO0 L25 SO4 Serial output data: The data set in these ports is output in the serial format Y1 Y2 SI1 Y4 SI2 Y8 SI3 Y1 Y2 SI5 Y4 SI6 Y8 SI7 K24 SI0 K25 SI4 Serial input data: It is possible to load data input in the serial format into data memory Note: At serial data input, the contents of shift register are accessed as they are. Y1 Y2 Y4 SIO F/F Y8 0 K23 BUSY COUNT SIO start flag 0: SIO operations performed 1: SIO operations not performed SCK clock count detection 0: Clock count normal (SCK clock count is in multiple of four) 1: Clock count abnormal (SCK clock count is not in multiple of four) SIO operation monitor 0: SIO operations ended 1: SIO operation in progress Serial interface control and data are accessed with the OUT2 an IN2 instruction for which [CN = 2H~5H] has been specified in the operand. The serial interface pin is used together with the I/O-4 P4-1, P4-2, P4-3 pins, and each of the I/O port-4 pins are switched across to the SI, SO and SCK pins by setting "1" in the SIO ON bit. Note: All the inputs of a serial interface build in the Schmidt circuit. Note: Since SI (P4-1) pin can be used as an I/O Port even when a serial interface is chosen, it can be used for the strike robe signal of SIO etc. In case of using this pin as a serial input, change into an input state for I/O control bit of P4-1. 53 2004-09-13 TC9328AF (1) edge, SCK-INV, SCK-I/O bit The edge bit setups the edge of a shift and the SCK-INV bit sets up the input-and-output waveform of a shift clock. If the edge bit is set "0", (SCK) shift operation is done at rising edge and set "1", (SCK) Shift operation is done at falling edge. SCK-INV bit sets the bit of serial clock output from "H" or L". In case of setting "0", it starts shift operation from "H" output, and setting "1", it starts shift operation from "L" output. These bits perform serial operation as shown in the following table by setup. Set up by the serial format to control. SCK-I/O bit setups the input-output of serial clock. Usually, when this product is used as a master, set "1" to SCK-I/O bit and then it used as serial clock output and in the case of a slave, set to "0" and then it used as serial input. SCK-INV = 0 SCK INV = 1 STA bit set as "1" SCK pin SO pin SI pin BUSY SO0 SI0 1 SO1 SI1 2 SO2 SI2 3 SO3 SI3 4 SCK pin SO pin SI pin BUSY 1 STA bit set as "1" 2 SO0 SI0 SO1 SI1 3 SO2 SI2 4 SO3 SI3 edge = 0 Interrupt Interrupt STA bit set as "1" SCK pin 1 SO0 SI0 SI1 2 SO1 SI2 3 SO2 SI3 4 SO3 SCK pin STA bit set as "1" 1 SO0 SI0 SO1 SI1 2 SO2 SI2 3 SO3 SI3 4 edge = 1 SO pin SI pin BUSY SO pin SI pin BUSY Interrupt Interrupt 54 2004-09-13 TC9328AF (2) 8/4 bit The 8/4 bit selects the length of the serial data. The length of the serial data is set at 4 bits when this bit is "0", and at 8 bits when this bit is "1". If SIO is started when a serial clock is set as an internal clock, a clock (4 bits or 8 bits) will be continuously outputted by the state of this bit. STA bit set as "1" SCK pin 1 2 3 4 5 6 7 8 SO pin SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SI pin SI0 SI1 SI2 SI3 SI4 SI5 SI6 SI7 BUSY Interrupt The example of serial operation at the time of setting it as 8 bits (3) SO - I/ O bit The bit sets the serial I/O for the SO pin. The SO pin outputs serial data when the bit is set at "0", and the SO pin is used for serial data input when this bit is set at "1". This control is used as the serial bus system which outputs and inputs serial data with one pin. Changing edge SCK pin 1 2 3 4 1 2 3 4 SO pin SO0 SO1 SO2 SO3 (Note) SI0 SI1 SI2 SI3 Set STA bit to "1" Set SO-I/O bit to "0" Set STA bit to "1" Set SO-I/O bit to "1" Example for Serial input-output operation Note: Usually insert pull-up or pull-down in SO pin to prevent floating. (4) Serial interface operation monitor The operational status of the serial interface is determined by referring to the BUSY, COUNT, SIO F/F bits. As the BUSY bit becomes "1" during SIO operations, control data switching and serial data access are performed when the BUSY bit is "0". It interrupts in falling of BUSY bit and a demand is transmitted. COUNT bit determines if the data sending/receiving has been performed per 4 bits. When shift operation performs with the four multiple, "0" is outputted. When it performs without the four multiple, "1" is outputted. "1" is set in the SIO F/F bit when the SCK pin starts shift operations. Both COUNT bit and SIO F/F bits are reset to "0" when "1" is set in the STA bit. These two bits are mainly used when the SCK pin sets external clocks (slave mode). An external clock is inputted and it can be judged to be the information that serial data was transmitted and received whether operation was performed normally. Usually, since interruption is transmitted, interruption processing performs a serial interface end. 55 2004-09-13 TC9328AF (5) STA bit STA bit is a bit of starting serial interface operation. Serial operation is started whenever STA bit sets "1". If STA bit setups "1", serial output data will be transferred to a shift register, and COUNT bit and SIO F/F bit will be reset. When SCK clock is made an internal setup, a serial clock is outputted, and when an external setup of the SCK clock is carried out, it will be in the state waiting for a serial clock input. 56 2004-09-13 TC9328AF 2. Configuration of the Serial Interface STA SCK - I/ O Interrupt requirement COUNT BUSY SIO F/F Control circuit SCK-INV 39 SCK (P4-3) SO - I/ O edge 38 SO (P4-2) 8/ 4 bit 4-bit shift register 4-bit shift register 37 SI (P4-1) SO0 SO1 SO2 SO3 Serial output data SI0~SI3 SO4 SO5 SO6 SO7 -3 SI4~SI7 -2 -1 -0 I/O port-4 I/O control data Serial input data -3 -2 -1 -0 I/O port-4 data The serial interface consists of a control circuit, a shift register, and an I/O Port. Note: SI pin can be used as I/O Port -4 (P4-1). Note: As for data and serial input data, the contents of a shift register are taken in by the data memory. For this reason, the contents of the data set to serial output data and serial input data are not in agreement. Note: All serial input pins are the Schmitt input type. 57 2004-09-13 TC9328AF 3. Serial Interface Timing The clock frequency outputted from SCK pin when SCK clock is set as an internal clock is 37.5 kHz (Duty. = 50%). When SCK clock is considered as an external input, the clock of a maximum of 200 kHz can be inputted. At external clock: Tcyc = 5 s min, Th = 2.5 s min, TPLH/TPLL = 2 s max At internal clock: Tcyc = 26.6 s typ., Th = 13.3 s typ., TPLH/TPLL = 2 s max Tcyc SCK pin TPLH/TPLL SO pin SO0 SO1 SO2 SO3 a At internal clock 26.6 s Th SI pin a b c d Y8 Serial input Data port (K24) Y4 Y2 Y1 x x x x SO3 SO2 SO1 SO0 a SO3 SO2 SO1 b a SO3 SO2 c b a SO3 d c b a x: Unfixed STA bit Set "1" Interrupt Set "1" BUSY bit COUNT bit SIO F/F bit 58 2004-09-13 TC9328AF A/D Converter The A/D converter is used for measuring the strength of electric fields and the voltage of batteries with 4-channel 6-bit resolution. 1. A/D Converter Control Port and Data Port Y1 L21 AD SEL0 Y2 AD SEL1 Y4 * Y8 STA A/D converter start bit A/D conversion is performed whenever this bit is set at "1". A/D input selection SEL0 0 0 1 1 SEL1 0 1 0 1 AD INPUT ADin1 ADin2 ADin3 ADin4 Y1 K20 AD0 Y2 AD1 Y4 AD2 Y8 AD3 K21 Y1 AD4 Y2 AD5 Y4 BUSY Y8 0 A/D converter operation monitor LSB A/D Conversion data MSB 0: A/D conversion ended 1: A/D conversion in progress A/D converter is the serial comparison systems of 6-bit decomposition ability. The standard voltage of A/D conversion is an internal power supply (VDD). The voltage which divided this power supply into 64 and A/D input voltage is compared, and data is outputted to A/D conversion data port. A/D conversion input follows multiplex method for the 4-external input pins (ADin1~ADin4 pin), and selected by AD SEL0/1 bit. The A/D converter performs A/D conversion whenever the STA bit is set at "1", and this is ended after seven machine cycles (280 s). A/D conversion completion is determined by referring the BUSY bit, and the A/D conversion data is loaded into the data memory after conversion has finished. The result of A/D conversion is required for by the following calculation. V DD x n - 0.5 n + 0.5 (63 > n > 1) < A/D Input voltage < V DD x (62 > n > 0) == = = == 64 64 (n is A/D conversion data value. [decimal]) These control are accessed with the OUT2/IN2 instruction for which [CN = 0H, 1H] has been specified in the operand. 59 2004-09-13 TC9328AF 2. A/D Converter Circuit Configuration Comparator A/D conversion data latch A/D conversion data 39 ADin1 (P5-0) Sample hold 38 ADin2 (P5-1) VDD SEL0/1 37 ADin3 (P5-2) BUSY 36 ADin4 (P5-3) AD0 ~ AD5 Control circuit Decoder R R R STA BUSY R VDB (VDD x 2 doubler power supply) 3R/2 The A/D converter consists of a 6-bit D/A converter, a comparator, an A/D conversion latch and control circuit. Only when BUSY bit is "1", 6 bit D/A converter and a comparator part is in order to operate, there is no current consumption of A/D converter when it is not operating. A/D converter part is driving using by doubler voltage VDB (two times to VDD). Note: To the output data of I/O Port -5 (Nch open drain) corresponding to A/D input pin to use set up "1" and use it by changing into an input state. 60 2004-09-13 TC9328AF Buzzer Output The buzzer output can be used to output tones and alarm tones to confirm key operations and the tuning scan mode. Buzzer type can be selected from a combination of four output modes and eight different frequencies. 1. Buzzer Control Port Y1 L1A BF0 Y2 BF1 Y4 BF2 Y8 BEN BF2 0 Buzzer frequency selection port 0 0 0 1 1 1 1 BF1 0 0 1 1 0 0 1 1 BF0 0 1 0 1 0 1 0 1 Buzzer Frequency 0.625 kHz 0.75 kHz 1 kHz 1.25 kHz 1.5 kHz 2.08 kHz 2.5 kHz 3 kHz Duty 1/2 1/2 2/3 1/2 1/2 2/3 1/2 2/3 Buzzer output enable bit 0: Buzzer output fixed (at POL = "0", "L" level, at POL = "1", "H" level) 1: Buzzer output enabled Y1 L1B BM0 Y2 BM1 Y4 BUZR ON Y8 POL Buzzer output logic setup Buzzer output mode setup 0: Positive logic output. Buzzer frequency is outputted in positive logic from "L" level 1: Negative logic output. Buzzer output is outputted in negative logic from "H" level P4-0 of I/O port-4 and buzzer output selection 0: I/O port-4 (P4-0) selection 1: Buzzer output selection BM1 0 0 1 1 BM0 0 1 0 1 Continual output Staggered output 10-Hz intermittent output 10-Hz intermittent output with 1Hz intervals Buzzer Output Mode (mode A) (mode B) (mode C) (mode D) The buzzer output is also used P4-0 I/O Port. In order to set it as a buzzer output, BUZR ON bit is set to "1" and it changes to a buzzer output by setting it as an output by the P4-0 I/O control port. After logic setting up of buzzer frequency, mode setup and a logic setup, buzzer enable bit is set to "1", it outputs buzzer. At the time of condition setup, buzzer enable bit is setup "0". In Continuation output mode (mode A), if buzzer enable bit is set "1", buzzer frequency will be outputted continuously, and if "0" is set, a buzzer output will stop. In staggered output mode, whenever buzzer enable bit is set to "1", buzzer is outputted for 50 ms and stopped. In this mode, when "1" is reset to the buzzer enable bit during buzzer output (50 ms), 50 ms is extended and the buzzer of 100 ms can be outputted. If it is reset during the extra 50 ms, 150 ms is extended and the buzzer output time can be easily set up. If 10 Hz intermittence output mode (mode C) sets "1" to the buzzer enable bit, 50-ms buzzer output and 50-ms buzzer pause are performed continuously. And a set of "0" stops a buzzer output. 61 2004-09-13 TC9328AF 10-Hz intermittent output with 1 Hz intervals mode (mode D), if buzzer enable bit is set "1", 50-ms buzzer output and 50-ms buzzer pause will carry out 500-ms output, after that 500-ms pause output of 50-ms buzzer output and the 50-ms buzzer pause is carried out again, and this operation is repeated. A set of "0" stops a buzzer output. At mode B, C, and D, a buzzer is in an output state, even if it sets "0" to buzzer enable bit and it makes it stop, the buzzer of 50 ms is outputted and stops. In addition, a buzzer output state can be judged according to the contents of a timer port. The timer port 10-Hz bit is "0", buzzer is an output state and it is in a pause state at the time of "1". The control of buzzer is accessed by the OUT 1 instruction for which [CN = AH, BH] has been specified in the operand. 2. Buzzer Circuit Configuration 10 Hz 1 Hz 0.625 kHz~3 kHz Multiplexer Buzzer output circuit 36 BUZR (P4-0) BF0~BF2 BEN BM0~BM2 3. Buzzer Output Timing Buzzer frequency "1" Data set to BEN bit "1" "0" 10 Hz Buzzer output (mode A) During a buzzer output, If "1" is set to BEN bit again, 50 ms extension will be carried out. 50 ms Buzzer output (mode C) 50 ms Period of buzzer frequency output Period of non-output Buzzer output (mode B) The output state in mode C Buzzer output (mode D) Period of non-output 500 ms 500 ms Period of output Note: When making a buzzer output, it sets up an output state about P4-0 (set "1" to I/O control port) 62 2004-09-13 TC9328AF Pulse Counter The pulse counter is 8-bit up/down counter and the number of clocks can be detected with CMOS input from INTR2 pin. It can be used for counting and detecting tape run. 1. Pulse Counter Control Port, Data Port Y1 L2D SEL1 Y2 SEL2 Y4 SEL4 Y8 SEL8 Data select DAL Address data Y1 L3B 0 1 2 3 Y1 DA0 Y2 Y2 DA1 Y4 Y4 DA2 Y8 Y8 DA3 Y8 Y8 K3B 0 1 2 3 * 4 * 5 Y1 Y1 DA0 DAL Address data Y2 Y2 DA1 Y4 Y4 DA2 Y8 Y8 DA3 Y8 Y8 Y1 Y2 Y4 DAL Address data 1 Y1 Y2 Y4 DAL Address data 2 DAL Address data 3 Y1 Y2 Y4 DAL Address data 1 Y1 Y2 Y4 DAL Address data 2 DAL Address data 3 DAL Address data 4 DOWN POL 4 * DAL Address data 4 PC0 PC1 PC2 PC3 Pulse counter control CTR OVER RESET RESET 5 * Pulse counter data PC4 PC5 PC6 PC7 Data Control Pulse counter control Pulse counter data OVER 6 0 0 0 Pulse counter control * DOWN bit............................. Set up 8-bit up/down counter 0: Up count action 1: Down count action * POL bit................................. Set up input pin (INTR2 pin) counter input edge 0: Cont for input fallig edge 1: Count for input rising edge * * CTR RESET bit .................... Whenever it sets "1", a 8-bit rise down counter is reset. OVER RESET bit ................. Whenever it sets "1", OVER F/F is reset. PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 2 0 OVER 2 Pulse counter data 7 LSB MSB OVER F/F bit ................. Detected of overflow 0: Counter calculation value < 28 - 1 = 1: Counter calculation value > 28 = (Overflow status) 63 2004-09-13 TC9328AF The pulse counter measures pulse number of INTR2 pin. POL bit set up the clock edge of input pin. If "0" is set, it will count in the falling of an input and it will set to "1", it will count in the rising of an input. Usually, this bit is used fixed. DOWN bit sets up a up/down of 8-bit counter. If it sets to "0" and it will set to rise count operation and "1", down count operation will be done. A change of a up/down can be performed freely. However, if a clock pulse is inputted during change command execution, since it is canceled, be careful of this count. When 28 or more pulses are inputted, OVER F/F bit is set to "1". When performing count operation of 8-bits or more, this OVER F/F are detected, and on a data memory, only the number of times of overflow is added and subtracted, and can correspond. After detection by this bit, and OVER RESET bit is set "1" and OVER F/F is reset.CTR RESET bit resets only 8-bit counter. The counter is reset whenever it sets "1". Counter data loaded data in a data memory by the binary. The control of pulse counter and data loading is accessed with the OUT3/IN3 instructions for which [CN = BH] have been specified in the operand and arranges in DAL address register port. This port is set up by data select port (L2D), which specified the division. The data of a specification port is set beforehand and the data port corresponding to it can be accessed. The data select port is +1 increments whenever it accesses DAL address port (L3B, K3B). For this reason, after setting up a data selection port, it can set up continuously. Note: If POL bit is changed, a clock pulse may enter. Reset data by the reset bit after changing. Note: If data select port is +1 increments when it accesses L2E, L2F, L3B, K3B on the I/O map. 2. Pulse Counter Circuit Configuration OVER RESET CTR RESET To interrupt circuit DOWN F/F 8-bit up/down counter POL 44 PCTRin (INTR2) OVER F/F PC0~PC7 Note: Pulse input is the Schmitt input type. Note: It can be used as pulse counter and interrupt function (INTR2 pin input) together. 3. Example for Pulse Counter Timing CTR/OVER RESET execution Data set to pulse counter control bit DOWN bit Pulse width 1 s (min) OVER RESET execution DOWN bit set to "1" PCTRin input Counter data 01H 02H 03H FFH 00H 01H 02H N N+1 N-1 N-2 OVER F/F 64 2004-09-13 TC9328AF Input and Output Port (I/O Port) There are 36 I/O ports available between I/O port-1~-9 which are used to input and output control signals. Of these 36 I/O ports, 12 I/O ports are CMOS type and 24 I/O ports are Nch open drain type. The combination function and the functional feature of each I/O port are as follows. I/O Port I/O port-1 P2-0~-2 P2-3 I/O port-3 P4-0 I/O port-4 P4-1~3 I/O port-5 I/O port-6 I/O port-7 I/O port-8 I/O port-9 Combination and Additional Function It's possible to set pull-up/pull-down. But, mixture of a pull-up pull down is impossible. Structure I/O port-2 Pre-scaller PSC output Nch high output buffer Output withstand voltage 3.6 V (max) Buzzer output CMOS Nch open drain CMOS Serial interface input/output port 6-bit A/D converter analog input The potential to VDB (VDD x 2) can be inputted. Output withstand voltage 3.6 V (max) Nch open drain The potential to VLCD (3 V) can be inputted. 1. I/O Port Control, I/O Port Data Y1 L2D SEL1 Y2 SEL2 Y4 SEL4 Y8 SEL8 Data select Segment-2 data Y1 L2F 6 S15 Y2 S16 Y4 S17 Y8 S18 Y8 Segment and I/O port changing S19 7 S20 S21 S22 Y8 -3 Y8 -3 Y8 -3 I/O control data (Input/output setting) 0: I/O port input 1: I/O port output Y1 Segment /IO select Y2 Y4 -0 8 Y1 -0 9 Y1 -0 A -1 -2 0: I/O port 1: Segment output Y1 Segment /IO select Y2 Y4 I/O control-1 Y2 Y4 -1 -2 I/O control-2 Y2 Y4 -1 -2 I/O control-4 Note: I/O-1, I/O-2, - - - - - is correspond to the pin name of P1-0~-3, P2-0~-3, - - - - - . 65 2004-09-13 TC9328AF Y1 LK30 LK31 LK32 LK33 LK34 LK35 LK36 LK37 LK38 -0 Y1 -0 Y1 -0 Y1 -0 Y1 -0 Y2 -1 Y4 -2 Y8 -3 Y8 -3 Y8 -3 Y8 -3 Y8 -3 I/O port data -3 Y8 -3 Control bit of pull-up/pull-down of I/O port-1 -3 Y8 -3 CMOS I/O port 0: I/O pin "L" level 1: I/O pin "H" level 0: I/O pin "L" level 1: I/O pin "H" level output pin is high impedance 0: Set up pull-down 1: Set up pull-up L3A Y1 Y2 Y4 Y8 Port 1 Pull up : Control pull-down or pull-up of I/O port-1 0: Pull-up or pull-down off 1: Pull-up or pull-down on L20 Y1 PD0 Y2 PD1 Y4 PD2 Y8 PD3 Y2 port-1 Y4 I/O -1 -2 Y2 port-2 Y4 I/O -1 -2 Y2 port-3 Y4 I/O -1 -2 Y2 port-4 Y4 I/O -1 -2 I/O port-1 pull-down Note: PD0~PD3 is correspond to P1-0~P1-3 I/O port-5 -0 Y1 -0 -1 -2 Y2 port-6 Y4 I/O -1 -2 I/O port-7 -0 Y1 -0 -1 -2 Y2 port-8 Y4 I/O -1 -2 I/O port-9 Nch open drain I/O port The I/O port for the I/O ports is set with the contents of the I/O control data port. "0" is set in the I/O control data port bit which corresponds to the relevant port when setting the input port, and "1" is set when setting the output port. I/O control data port is arranged segment-2 data port and set up by data select port (L2D), which specified the division. The data of a specification port to set beforehand is set and the data port corresponding to it can be accessed. The data select port is +1 increments whenever it accesses DAL address port (L2F). For this reason, after setting up a data selection port, it can set up continuously. The output status of the I/O port is controlled by executing the OUT3 instruction for which corresponds to each I/O port during output port setting. The contents of the data currently output can also be loaded into the data memory by executing the IN3 instruction. In addition, the data read by the IN3 command is not surely in agreement with the data outputted by the OUT3 instruction and, in order to read the state of a pin. The data input in the I/O port is loaded into the data memory by executing the IN3 instruction for which corresponds to each I/O port during input port setting. The contents of the output latch will have no effect on the input data at this point. Nch open drain I/O ports have not I/O control data. When it makes an input, it is set "1" in I/O data port, the status becomes high impedance and read the input status into data memory by IN3 instruction. When output state becomes "L" level, it set "0" in I/O data port by OUT3 command. The execution of the WAIT instruction and CKSTP instruction is cancelled and CPU operations are re-started when the status of the I/O port input specified in the input port changes with I/O port-1. Also, the MUTE port and MUTE bit are forcibly set to "1" during changes in the input status when the MUTE port's I/O bit is set at "1". By control port of I/O port-1 pull-down, it sets up pull-down or pull-up status. It can set up a pull-down or pull-up for every pin and if the port is set up "1", it will become a pull-up or a pull-down. The pull-up/pull-down control bit of I/O Port -1 perform a change of a pull-up and a pull down. If the bit is set up"0", the status becomes pull-down and set up "1", it becomes pull-up. 66 2004-09-13 TC9328AF Set up the pull-up and pull-down is used for key matrix configuration. I/O Port-1 with a pull down or a pull-up is considered for a usual I/O Port output as an input as an output of a key matrix, and a key matrix is configured. It is able to configure the key matrix of a low noise by the following methods. In setting pull-down to I/O port-1, the output side of a key matrix is usually high impedance (input state), output and scan to "H" level on key loaded line, detected key input or non by loading input status of I/O port-1. In the case of a pull-up, "L" level is outputted and it detected on a key loading line. During executing of CKSTP instruction and WAIT instruction, the existence of this key input can also be judged and restarted. When restarting at the time of CKSTP command execution, I/O Port-1 is used by changing into a pull-up state. For the clock stop mode, since the outputs of an I/O Port are outputted all "L" level, I/O Port-1 stands by in the state of a pull-up, and if a key is inputted, I/O Port-1 input will change and restart. In this case, since the standby time of about 100 ms occurs as time lag after being canceled of a clock stop. Since release of WAIT instruction holds the output state, restarting is possible by the method of both a pull-up and a pull down, and since there is no time lag from release, detection and operation of a key are quickly possible. Using these backup modes together can reduce consumption current. Since the input of I/O Port-1 is an inverter input, the usage that serves as middle potential cannot be done to this input. But, only at the time of execution of the input instruction, since an input will be in an ON state, even if middle potential is inputted, as for other I/O Port inputs, unusual consumption current does not occur. For this reason, use of the pull-up in potential lower than VDD potential, the three value output of an output level, etc. is possible. I/O Port -2, -4 pins are the I/O Ports of CMOS structure, P2-3 pin is the prescaller PSC output, P4-0 pin is the buzzer output and P4-1-3 pins are the serial interface serve a double purpose, respectively. I/O port-3, -5~-9 are Nch open drain I/O port. I/O Port -3 uses VLCD (3 V) for the gate potential of Nch output buffer. For this reason, the output current by which power supply voltage was stabilized also in the time of low voltage can be obtained. This port can perform the input and output to 3.6 V. I/O port-5 is used as 6-bit A/D converter input. This port is able to inputted VDB potential (the potential to VDD x 2). I/O Port -8, -9 are also used as LCD driver. VLCD (3 V) is used for the gate potential of an Nch open output buffer. For this reason, the output current by which power supply voltage was stabilized also in the time of low voltage can be obtained. These pins can perform the input and output to VLCD (3 V). These pins are set as the input of an I/O Port after reset. Note: The data select port is +1 increments automatically when it accesses L2E, L2F, L3B, K3B on the I/Omap. VDD P1-3 30 P1-2 29 P1-1 28 P1-0 27 P9-3 26 The following is an example of key input matrix circuit configuration. Without key input, it pulled-up and key is pushed, it inputted "L" level from sauce side(I/O port-9). It is necessary to take into consideration the shift time to the pull-up of a key input from "L". They are all about a key sauce side at the time of WAIT instruction execution and "L" WAIT instruction can be lifted, whenever a key input will be pushed, if it stands by on the level. P1-3 P1-2 P1-1 P1-0 P9-3 Pull-up Pull-up Pushing of P9-3 and P1-1 keys P9-2 25 P9-1 24 P9-0 23 Pull-up High impedance P9-2 P9-1 Example for key input matrix circuit configuration P9-0 I/O port-1 Loaded into data 67 2004-09-13 TC9328AF Register Port The G-register and data register outlined in the explanation on the CPU are also used as a single internal port. 1. G-register (KL1D, KL1E) This register addresses the data memory's row addresses (DR = 04H~3FH) during execution of the MVGD instruction and MVGS instruction. This register is accessed with the OUT1/IN1 instruction for which [CN = DH~EH] has been specified in the operand. Moreover, if STGI instruction is used, data can be set to this register by one instruction. Note: The contents of this register are only valid when the MVGD instruction and MVGS instruction are executed and are ineffective when any other instruction is executed. Moreover, it does not have the influence on this register by MVGD instruction and MVGS instruction. Note: All of the data memory row addresses can be specified indirectly by setting data 00H to 3FH in the G-register. (DR = 00H~3FH) Note: For a reason with a RAM capacity of 512 words, this product will become unfixed if 20H-3FH is specified to be G-register. Note: Writing and read-out are possible for this register. Please evacuate and return in a data memory if needed at the time of interruption. KL1D Y1 G0 Y2 G1 Y4 G2 Y8 G3 KL1E Y1 G4 Y2 G5 Y4 * Y8 * G5 0 Data memory row address specification STGI instruction I0 I1 I2 I* I3 Transmit I4 I5 0 1 1 0 1 0 1 0 1 0 1 0 1FH 20H Can't specified in this area 0 0 G4 0 0 0 G3 0 0 0 G2 1 1 1 G1 0 0 1 G0 0 1 0 DR 04H 05H 06H 1 1 1 1 1 1 1 1 1 1 0 1 3EH 3FH 68 2004-09-13 TC9328AF 2. Data Register (KL3C~KL3F), DAL Address Register (KL3B0~KL3B3) and Control Bit L2D Y1 SEL1 Y2 SEL2 Y4 SEL4 Y8 SEL8 0 1 Data select 2 L/K3B Y1 Y2 Y4 Y8 Y8 DAL L/K3B Y2 Y1 DAL address1 Y4 L/K3A Y1 Y2 (data) DA/0 Y4 /0 Y8 /0 DA0Y1 DALY2 DA2Y41DA3Y8 DA1 DA4Y1 DALY2 DA6Y41DA7Y8 DA5 DA8 DAL DA9 DA10 1 DA11 */0 */0 3 DA12 DA13 0: DAL ADD3, (r) instruction select 1: DAL DA instruction select DAL address register DA13 DA12 MSB DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 LSB DAL instruction indirect specification KL3F Y1 d15 MSB Y2 d14 Y4 d13 Y8 d12 KL3E Y1 d11 Y2 d10 Y4 d9 Y8 d8 KL3D Y1 d7 Whenever it sets "1", the contents of a data register are transmitted to DAL address register. 1: KL3C Y2 d6 Y4 d5 Y8 d4 Y1 d3 Y2 d2 Y4 d1 Y8 d0 LSB Data register 16-bit data It transmits 16 bits of program memories by DAL instruction b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Program memory 16-bit data 69 2004-09-13 TC9328AF The data register is 16-bit register for which load the program memory data when the DAL instruction is executed. The contents of this register are loaded into the data memory in 4-bit units with the execution of the OUT1/IN1 instructions for which [CN = CH~FH] has been specified in the operand. This register can be used for loading LCD segment decoding operations, radio band edge data and the data related to binary to BCD conversion. The DAL address register (DA) is 14-bit register for which specified the program memory indirectly when the DAL instruction is executed. There are two kinds of operation methods of DAL instruction. The control is selected by DAL bit. When DAL bit is set "0", ADDR3 (6 bits) of the operand and contents of general register (r) becomes the reference address of program memory and when DAL bit is set "1", 14 bit of DAL address register becomes reference address. At the time of setting DAL bit is "0" and execution of DAL instruction, only program memory area (0000H~03FF) becomes reference area and DAL bit is set "1" and execution of DAL instruction, all program memory area (0000H~3FFFH) becomes reference area. If (DATA) DA bit is set to "1", it can transfer from the contents of data register to 14-bit DAL address register by executing of single instruction. The contents of DAL address register are accessed the data in 4-bit units with the execution of the OUT3/IN3 instruction for which [CN = BH] have been specified in the operand. DAL address register port is setup by data select port (L2D) for which divides and indirect specified. The data of a specification port to set beforehand is set and the data port corresponding to it is accessed. Data select port is +1 incremented whenever is accessed this port (L3B, K3B). For this reason, after setting up a data selection port, it can access continuously. DAL bit and (DATA) DA bit are accessed with the execution of OUT3/IN3 instruction for which [CN = AH] has been specified in the operand. Note: DAL address register becomes effective only execution of DAL instruction when setting "1" and becomes unrelated at the time of other instruction execution. It does not have the influence on this register by DAL instruction. Note: For this product have 8 K step of ROM Capacity, If 2000H - 3FFFH is specified to be DAL address register and DAL instruction is executed, the contents of a data register will become unfixed. Note: It's possible to write in and read out for data registeter and DAL address register. Please evacuate and return in a data memory if needed at the time of interruption. Note: There is no action when (DATA) DA bit is set "0". When it accesses to K3A, it only read out only the DAL bit. (The other bit is "0".) 3. Carry F/F (Ca flag, KL1C) This is set when Carry or Borrow is issued in the result of calculation instruction execution and is reset if neither of these is issued. The carry F/F is accessed with OUT1/IN1 instructions for which [CN = CH] have been specified. For this reason, evacuation and a return of the carry F/F at the time of interruption can be performed easily. Carry F/F is written in a data memory by IN1 instruction at the time of evacuation, it is evacuated, and the data evacuated by OUT1 instruction is transmitted to carry F/F from a data memory after the time of a return. Y1 L/K1C CA flag Y2 */0 Y4 */0 Y8 */0 Carry F/F 70 2004-09-13 TC9328AF Timer Port The timer is equipped with 100-Hz, 10-Hz and 2-Hz F/F bits and used for counting clock operations and tuning scan mode, etc. 1. Timer Port Y1 L26 2 Hz F/F Y2 Timer Y4 Y8 The 10 Hz, 100 Hz and under 1 kHz bits are reset whenever "1" is set. The 2 Hz F/F is reset whenever "1" is set. Reset port Y1 K26 2 Hz F/F Y2 Y4 Y8 10 Hz 100 Hz Timer The timer ports are accessed with the OUT2/IN2 instructions for which [CN = 6H] has been specified in the operand 2. Timer Port Timing The 2-Hz timer F/F is set with the 2-Hz (500 ms) signal and is reset by setting "1" in the reset port's 2-Hz F/F. This bit is usually used as a clock counter. The 2-Hz timer F/F can only by reset with the reset port's 2 Hz F/F, and incorrect counts will be output and correct timers not acquired if not reset within a 500 ms cycle. 2-Hz F/F output 2-Hz F/F reset execution t < 500 ms 2-Hz clock 500 ms t The 10-Hz and 100-Hz timers are outputted to 10-Hz and 100-Hz bits with a duty 50% of 100-ms and 10-ms cycles respectively. Counters at 1 kHz or below will be reset whenever the reset port's timer bit is set at "1". 100 Hz 5 ms 10 ms 10 Hz 50 ms 100 ms 71 2004-09-13 TC9328AF Output Port (Used as LCD Driver Pin) There are 18-output ports of CMOS type. These output port are used as LCD driver and changed output port by VLCD OFF bit. If VLCD OFF bit is set to "1", this port becomes output port. The outputted data to output port is used as segment data port-1 (L2E). This data is accessed with OUT2 instruction for which [CN = EH] is specified and is setup by data select port (L2D) for which divides and indirect specified like segment data. The data of a specification port to set a segment data port is set beforehand, and the data port corresponding to it is accessed. The data select port is +1 incremented whenever it accesses segment data port-1 (L2E). For this reason, after setting up a data selection port, it can set up continuously. Output data is +1 increment with OT count UP bit by executing one instruction. For this reason, it can use as an address signal output when using an external memory etc. Output buffer capability can be changed at the time of an output setup. If OTB-UP bit is set "0", it becomes low output buffer (same performance of LCD output driver) and set "1", it becomes high output buffer. Usually, at the time of an output port setup, this bit is set to "1". The power supply of this output port is used VLCD dobuler potential, when using it as an output port, remove for the capacitor of VLCD doubler potential (between C3-C4) and connect VLCD pin with VDD pin. Note: Data select port is +1 increment automatically whenever it accesses L2E, L2F, L3B, K3B on I/O map. Note: If set "0" to OT count UP bit, it does not perform count-up. Note: Refer to LCD driver item. L2D Y1 SEL1 Y2 SEL2 Y4 SEL4 Y8 SEL8 0 L2E Y1 Y2 Y4 Y8 Y8 If VLCD off-bit is set to "1", segment output data will turn into output port data. L/K3B Y2 port data Y1 Output Y4 OT1Y1 DALY2 OT3Y41OT4Y8 OT2 1 OT5Y1 DALY2 OT7Y41OT8Y8 OT6 2 Y4 OT12 Y8 DALY2 OT9Y1 OT10 OT11 1 DAL 3 OT13 OT14 4 OT17 OT18 OT15 1 OT16 * * Data select L3A Y1 Y2 Y4 OT count up Y8 Whenever this bit is set to "1", all the OT1 - OT18 is count up (+1). OT1 bit is lower bit; OT18 bit is upper bit and are counted up from OT1 bit. L2FF Y1 Y2 Y4 OTB -UP Y8 Control bit for output port (OT) buffer performance 0: Low-output buffer 1: High-output buffer At setting up output port, set "1". 72 2004-09-13 TC9328AF MUTE Output This is a 1-bit CMOS output port for muting control purposes. 1. MUTE Port L/K18 Y1 MUTE Y2 I/O Y4 POL Y8 HOLD Control by change of HOLD input state changing 0: Even if HOLD input status changes, MUTE output does not change. 1: By changing HOLD input status, MUTE bit is set to "1". MUTE output polarity control 0: Positive logic: MUTE bit output without modification 1: Negative logic: MUTE bit inversed and output Control selection by changes in the I/O port-1input status 0: Even if I/O port -1 status changes, MUTE output doesn't change. 1: By changing I/O port -1 status, MUTE bit is set to "1". MUTE output setting 0: MUTE output set at "L" level during positive logic and "H" level during negative logic. 1: MUTE output set at "H" level during positive logic and "L" level during negative logic. This port is accessed with the OUT1/IN1 instruction for which [CN = 8H] has been specified in the operand. MUTE output is used for muting control. Setting the MUTE bit to "1" suppresses the generation of noise when the linear circuit is switched, for example when the equipment is powered down, or when the I/O Port 1 input or HOLD input is used to switch band. This control is set up according to the contents of I/O bit and HOLD bit. POL bit sets up the logic of MUTE output. Please set up according to specification. 2. Circuit Configuration of MUTE Output MUTE bit S POL bit 30 MUTE I/O bit The signal of input change of I/O Port -1 Reset signal HOLD bit The signal of HOLD input pin changing 73 2004-09-13 TC9328AF Test Port This internal port is to test device function. It is accessed with OUT1 instruction specifying [CN = FH] and OUT2 instruction specifying [CN = 6H] in the operand. Y1 Y2 #1 Y4 #2 Y8 #3 Y1 Y2 Y4 Y8 #4 L1F #0 L26 Test port Test port Application to an Emulator Tip If TEST pin is supplied "H" level (Test mode), the device operates as an emulator chip. Three kinds of test modes are prepared and can constitute a soft development tool by using three devices. Radio operation can be checked by the connection between this soft development tool and IC for tuners, performing soft development. Please refer to TC9328FA software development tool specifications of a development tool. 74 2004-09-13 TC9328AF Maximum Ratings (Ta = 25C) Characteristics Supply voltage Voltage doubler boosting voltage Output voltage 1 (N-channel open drain) Output voltage 2 (N-channel open drain) Output voltage 3 (N-channel open drain) Input voltage Power dissipation Operating temperature Storage temperature Symbol VDD VDB VO1 (*) VO2 (*) VO3 (*) VIN PD Topr Tstg Rating Unit V V V V V V mW C C -0.3~4.0 -0.3~4.0 -0.3~4.0 -0.3~VDB + 0.3 -0.3~VLCD + 0.3 -0.3~VDD + 0.3 100 -10~60 -65~150 *: VO1: P3-0~P3-3, P6-0~P6-3, P7-0~P7-3 pin VO2: P5-0~P5-3 pin VO3: P8-0~P8-3, P9-0~P9-3 pin Electrical Characteristics (unless otherwise noted, Ta = 25C, VDD = 1.8 V) Characteristics Range of operating supply voltage Symbol VDD1 VDD2 Range of memory retention voltage VHD Test Circuit Test Condition Under CPU operation Under PLL operation (*) (*) Min 0.9 0.9 0.75 Typ. ~ ~ ~ Max 1.8 1.8 1.8 V Unit V Crystal oscillation stopped (CKSTP instruction executed) (*) PLL operation (VHF mode) at input FMin = 230 MHz Under CPU operation only (PLL off, display turned on) Hard wait mode (crystal oscillator operating only) Soft wait mode (CPU stopped, PLL off) Crystal oscillation stopped (CKSTP instruction executed) (*) Crystal oscillation fXT = 75 kHz IDD1 IDD2 Operating current IDD3 6 40 10 80 mA 20 40 A IDD4 Memory retention current Crystal oscillation frequency Crystal oscillation start-up time IHD fXT tst 30 0.1 75 1.0 A kHz s 1.0 For conditions marked by an asterisk (*), guaranteed when VDD = 0.9~1.8 V, Ta = -10~60C 75 2004-09-13 TC9328AF Voltage Doubler Boosting Circuit Characteristics Doubled voltage Doubled voltage output current Doubled voltage reference voltage Constant voltage for phase comparator Constant voltage temperature characteristic Power supply output current for phase comparator Doubled voltage Doubled voltage output current Symbol VDB IDB VEE Vreg Dv Ireg VLCD ILCD Test Circuit Test Condition GND reference (VDB) VOH = VDB - 0.1 V (VDB) GND reference (VEE) GND reference (Vreg) GND reference (VDD, Vreg) VOH = Vreg - 0.1 V (Vreg) (Note 1) GND reference (VLCD) VOH = VLCD - 0.1 V (VLCD) (Note 1) Min Typ. VDD x2 Max Unit V -50 1.35 1.35 1.65 1.65 -200 1.50 1.50 A V V mV/C -5 -50 2.7 3.3 -200 3.0 A V -50 -200 A Note 1: The "H" level output current of the pin using the Vreg/VLCD power supply must not exceed the power supply (doubled voltage: VDB) output current. Programmable Counter/IF Counter Operating Frequency Range Characteristics FMin (VHF mode) FMin (FM mode) AMin (HF mode) f HF2 AMin (LF mode) IFin1, IFin2 PSC transfer delay time f LF f IF tpd Symbol f VHF f FM f HF1 Test Circuit Test Condition VIN = 0.1 Vp-p VIN = 0.1 Vp-p VIN = 0.1 Vp-p VIN = 0.1 Vp-p VIN = 0.1 Vp-p VIN = 0.1 Vp-p (PSC) CL = 15 pF, VDD = 1.1~1.8 V (*) (*) (*) (*) (*) (*) (*) Min 50 30 3.0 1.0 0.5 0.3 Typ. ~ ~ ~ ~ ~ ~ Max 230 130 30 MHz 10 8 12 400 MHz MHz ns Unit MHz MHz *: Guaranteed when VDD = 0.9~1.8 V, Ta = -10~60C Programmable Counter/IF Counter Input Amplitude Range Characteristics FMin (VHF mode) FMin (FM mode) AMin (HF mode) AMin (LF mode) IFin1, IFin2 Symbol V VHF V FM V HF V LF V IF Test Circuit Test Condition Same as for f VHF Same as for f FM Same as for f HF1~2 Same as for f LF Same as for f IF (*) (*) (*) (*) (*) Min 0.1 0.1 0.1 0.1 0.1 Typ. ~ ~ ~ ~ ~ Max 0.6 0.6 0.6 0.6 0.6 Unit Vp-p Vp-p Vp-p Vp-p Vp-p *: Guaranteed when VDD = 0.9~1.8 V, Ta = -10~60C 76 2004-09-13 TC9328AF LCD Common Output/Segment Output (COM1~COM4, S1~S22) Characteristics Symbol Test Circuit Test Condition VLCD = 3 V, VOH = VLCD - 0.3 V (COM1~COM4) VLCD = 3 V, VOH = VLCD - 0.3 V (S1~S22) VLCD = 3 V, VOL = 0.3 V (COM1~COM4) VLCD = 3 V, VOL = 0.3 V (S1~S22) No load (COM1~COM4) Min Typ. Max Unit IOH1 "H" level Output current IOH2 IOL1 "L" level IOL2 Output voltage 1/2 level VBS -0.10 -0.05 0.10 0.05 1.35 -0.20 -0.10 0.30 0.15 1.5 1.65 V mA Output Port, I/O Port (OT1~OT18, P8-0~P8-3, P9-0~P9-3) Characteristics Symbol Test Circuit Test Condition VLCD = 3 V, VOH = VLCD - 0.3 V (Note 1, except I/O port) VLCD = 3 V, VOL = 0.3 V VIH = VLCD, VIL = 0 V (P8-0~P8-3, P9-0~P9-3) (P8-0~P8-3, P9-0~P9-3) (P8-0~P8-3, P9-0~P9-3) Min Typ. Max Unit Output current "H" level "L" level IOH3 IOL3 ILI -1.5 1.5 -3.0 3.0 1.0 VDD mA Input leak current "H" level Input voltage "L" level VDD x 0.8 0 ~ ~ A VIH VIL V VDD x 0.2 Note 1: The "H" level output current is the current when the pin power supply is fixed. Make sure that pins using Vreg/VLCD power supply do not exceed the power supply (doubled voltage: VDB) output current. 77 2004-09-13 TC9328AF I/O Port (P1-0~P7-3) Characteristics Symbol Test Circuit Test Condition VDD = 1.5 V, VOH = VDD - 0.2 V (I/O port P2, P4) VDD = 0.9 V, VOH = VDD - 0.2 V (I/O port P2, P4) VDD = 1.5 V, VOL = 0.2 V (except I/O port P3) VDD = 0.9 V, VOL = 0.2 V (except I/O port P3) VDD = 0.9~1.8 V, VOL = 0.2 V (I/O port P3) VIH = VDD, VIL = 0 V (I/O port P1, P2, P4) VIH = 3.6 V, VIL = 0 V (I/O port P3, P6, P7) VIH = VDB, VIL = 0 V (I/O port P5) Min Typ. Max Unit IOH4 "H" level IOH5 Output current IOL4 "L" level IOL5 IOL6 -0.4 -0.8 -0.04 -0.2 mA 0.5 0.1 1.0 1.0 0.3 2.0 1.0 1.0 1.0 VDD V VDD x 0.2 120 200 k kHz VDD x 0.8 0 30 ~ ~ 60 Input leak current ILI A "H" level Input voltage "L" level Input pull-down resistor SCK clock external input frequency VIH VIL RIN1 fSIO When P1-0~P1-3 are set to pull-down or pull-up When I/O port P4-3 are set to serial clock input For conditions marked by an asterisk (*), guaranteed when VDD = 1.8~3.6 V, Ta = -10~60C Note 1: The "H" level output current is the current when the pin power supply is fixed. Make sure that pins using Vreg/VLCD power supply do not exceed the power supply (doubled voltage: VDB) output current. MUTE Output Characteristics Symbol IOH4 "H" level Output current "L" level IOL5 IOH5 IOL4 Test Circuit Test Condition VDD = 1.5 V, VOH = VDD - 0.2 V VDD = 0.9 V, VOH = VDD - 0.2 V VDD = 1.5 V, VOL = 0.2 V VDD = 0.9 V, VOL = 0.2 V Min Typ. Max Unit -0.4 -0.04 0.5 0.1 -0.8 -0.2 1.0 0.3 mA HOLD , INTR1/2, IN1/2 Input Port, RESET Input Characteristics Input leak current "H" level Input voltage "L" level VIL3 Symbol ILI VIH3 Test Circuit Test Condition VIH = VDD, VIL = 0 V Min Typ. Max Unit VDD x 0.8 0 ~ ~ 1.0 VDD A V VDD x 0.2 78 2004-09-13 TC9328AF AD Converter (ADin1~ADin4) Characteristics Analog input voltage range Resolution Conversion total error Analog input leak Symbol VAD VRES Test Circuit Test Condition ADin1~ADin4 Min 0 Typ. ~ 6 Max VDB Unit V bit LSB VDD = VDB, VIH = VDB, VIL = 0 V (ADin1~ADin4) 1.0 1.0 ILI 0.5 A DO1, DO2 Output Characteristics "H" level "L" level Output off leak current Symbol IOH4 IOL4 ITL Test Circuit Test Condition Vreg = 1.5 V, VOH = Vreg - 0.2 V Min Typ. Max Unit Output current (Note 1) -0.4 0.5 -0.8 1.0 100 mA Vreg = 1.5 V, VOL = 0.2 V VDD = 1.5 V, VTLH = 1.5 V, VTLL = 0 V nA Others Characteristics Input pull-down resistance XIN amp. feedback resistance XOUT output resistance Input amp. feedback resistance Symbol RIN2 RfXT ROUT RfIN1 RfIN2 Test Circuit Test Condition (TEST) (XIN-XOUT) (XOUT) (FMin) (AMin, IFin1, IFin2) Min 5 Typ. 10 20 4 200 600 Max 30 Unit k M k k 300 1200 100 400 For conditions marked by an asterisk (*), guaranteed when VDD = 1.8~3.6 V, Ta = -10~60C Note 1: The "H" level output current is the current when the pin power supply is fixed. Make sure that pins using Vreg/VLCD power supply do not exceed the power supply (doubled voltage: VDB) output current. 79 2004-09-13 TC9328AF Typical TC9328AF product IDD (Ta = 25C) in different modes at PLL operation 10 9 8 7 VHF mode (fin = 230 MHz) Typical TC9328AF product IDD (Ta = 25C) in different modes at CPU operation 50 At CPU operation (IDD2) 40 In Soft Wait mode (Note) (IDD4) IDD (mA) 6 5 4 3 2 1 0 0.5 1 1.5 LF mode (fin = 8 MHz) 2 2.5 FM mode (fin = 130 MHz) HF1 mode (fin = 30 MHz) HF2 mode (fin = 10 MHz) IDD (mA) 30 20 In Hard Wait mode (IDD3) 10 0 0.5 1 1.5 2 2.5 VDD (V) VDD (V) Note: The IDD (operating current) in Soft Wait mode is the current dissipation value. The actual current dissipation value differs depending on the CPU execution state. 80 2004-09-13 TC9328AF Typical TC9328AF product input sensitivity VHF mode (VDD = 1.5 V, Ta = 25C) 280 240 Typical TC9328AF product input sensitivity VHF mode VDD - fmax/fmin (Vin = 35 mVrms, Ta = 25C) 1000 (mVrms) 100 200 160 120 80 40 0 0.1 Specification 50~230 MHz @35 mVrms VHF mode specification: 50~230 MHz Input amplitude (MHz) fmax/fmin 10 1 1 10 100 1000 0.1 0.5 1 1.5 2 2.5 fin (MHz) VDD (V) Typical TC9328AF product input sensitivity FM mode (VDD = 1.5 V, Ta = 25C) 280 240 Typical TC9328AF product input sensitivity FM mode VDD - fmax/fmin (Vin = 35 mVrms, Ta = 25C) 1000 (mVrms) 100 200 160 120 80 40 0 0.1 0.1 0.5 Specification 30~130 MHz @35 mVrms Input amplitude (MHz) FM mode specification: 30~130 MHz fmax/fmin 10 1 1 10 100 1000 1 1.5 2 2.5 fin (MHz) VDD (V) Typical TC9328AF product input sensitivity HF1 mode (VDD = 1.5 V, Ta = 25C) 280 240 Typical TC9328AF product input sensitivity HF1 mode VDD - fmax/fmin (Vin = 35 mVrms, Ta = 25C) 1000 (mVrms) 100 200 160 120 80 40 0 0.1 Specification 3~130 MHz @35 mVrms Input amplitude (MHz) fmax/fmin 10 HF1 mode specification: 3~30 MHz 1 1 10 100 1000 0.1 0.5 1 1.5 2 2.5 fin (MHz) VDD (V) 81 2004-09-13 TC9328AF Typical TC9328AF product input sensitivity HF2 mode (VDD = 1.5 V, Ta = 25C) 280 240 200 160 120 80 40 0 0.1 Specification 1~10 MHz @35 mVrms Typical TC9328AF product input sensitivity HF2 mode VDD - fmax/fmin (Vin = 35 mVrms, Ta = 25C) 1000 (mVrms) 100 (MHz) 10 HF2 mode specification: 1~10 MHz 1 Input amplitude fmax/fmin 0.1 1 10 100 1000 0.01 0.5 1 1.5 2 2.5 fin (MHz) VDD (V) Typical TC9328AF product input sensitivity LF mode (VDD = 1.5 V, Ta = 25C) 280 240 200 160 120 80 40 0 0.1 Specification 0.5~8 MHz @35 mVrms Typical TC9328AF product input sensitivity LF mode VDD - fmax/fmin (Vin = 35 mVrms, Ta = 25C) 1000 (mVrms) 100 (MHz) 10 LF mode specification: 1~10 MHz 1 Input amplitude fmax/fmin 0.1 1 10 100 1000 0.01 0.5 1 1.5 2 2.5 fin (MHz) VDD (V) Typical TC9328AF product input sensitivity IFin mode (VDD = 1.5 V, Ta = 25C) 280 240 200 160 120 80 40 0 0.1 Specification 0.3~12 MHz @35 mVrms Input amplitude (mVrms) 1 10 100 1000 fin (MHz) 82 2004-09-13 TC9328AF Package Dimensions Weight: 0.45 g (typ.) 83 2004-09-13 TC9328AF RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 030619EBA * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. 84 2004-09-13 |
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