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EMC2103 RPM-Based Fan Controller with HW Thermal Shutdown
PRODUCT FEATURES
The EMC2103 is an SMBus compliant fan controller with up to up to 3 external and 1 internal temperature channels. The fan driver can be operated using two methods each with two modes. The methods include an RPM based Fan Speed Control Algorithm and a direct PWM drive setting. The modes include manually programming the desired settings or using the internal programmable temperature look-up table to select the desired setting based on measured temperature. The temperature monitors offer 1C accuracy (for external diodes) with sophisticated features to reduce errors introduced by series resistance and beta variation of substrate thermal diode transistors commonly found in processors. The EMC2103 also includes a hardware programmable temperature limit and dedicated system shutdown output for thermal protection of critical circuitry.
Datasheet
Features
Programmable Fan Control circuit
-- 4-wire fan compatible -- High and low frequency PWM
RPM based fan control algorithm
-- 2.5% accuracy from 500RPM to 16k RPM -- Detects fan aging and variation
Temperature Look-Up Table
-- -- -- -- Allows programmed fan response to temperature Controls fan speed or PWM drive setting Allows externally set temperature data to drive fan Supports DTS data from CPU
Up to Three External Temperature Channels (EMC2103-2 only)
-- Supports 45nm, 60nm, and 90nm CPU diodes -- Automatically detects and supports CPUs requiring BJT or Transistor models -- Resistance error correction -- Supports discrete transistors (i.e. 2N3904) -- 1C accurate (60C to 125C) -- 0.125C resolution
Applications
Notebook Computers Projectors Graphics Cards Industrial and Networking Equipment
Hardware Programmable Thermal Shutdown Temperature
-- Cannot be altered by software -- 65C to 127C Range
Programmable High and Low Limits for all channels Internal Temperature Monitor
-- 2C accuracy -- 0.125C resolution
3.3V Supply Voltage SMBus 2.0 Compliant
-- SMBus Alert compatible
Two dedicated GPIOs (EMC2103-2 and EMC2103-4 only) Available in 12-pin, QFN Lead-Free RoHS Compliant Package (EMC2103-1 and EMC2103-3) or 16-pin, QFN Lead-Free RoHS Compliant Package (EMC2103-2 and EMC2103-4)
SMSC EMC2103
DATASHEET
Revision 0.85 (01-29-08)
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
ORDER NUMBERS:
ORDERING NUMBER EMC2103-1-KP PACKAGE 12 pin, QFN Lead-Free, ROHS Compliant FEATURES One external diode, RPM based Fan Speed Control Algorithm, High Frequency PWM driver, HW Thermal / Critical shutdown, EEPROM Load disabled Up to three external diodes, RPM based Fan Speed Control algorithm, High Frequency PWM driver, HW Thermal / Critical shutdown, 2 GPIOs, EEPROM Load disabled One external diode, RPM based Fan Speed Control Algorithm, High Frequency PWM driver, HW Thermal / Critical shutdown, EEPROM Load enabled Up to three external diodes, RPM based Fan Speed Control algorithm, High Frequency PWM driver, HW Thermal / Critical shutdown, 2 GPIOs, EEPROM Load enabled
EMC2103-2-AP
16 pin, QFN Lead-Free, ROHS Compliant
EMC2103-3-KP
12 pin, QFN Lead-Free, ROHS Compliant
EMC2103-4-AP
16 pin, QFN Lead-Free, ROHS Compliant
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 0.85 (01-29-08)
2
SMSC EMC2103
DATASHEET
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
Table of Contents
Chapter 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2 Pin Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 3.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SMBus Electrical Specifications (Client Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 4 Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 18 18 18 18 19 19
Chapter 5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 Critical/Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 SHDN_SEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 TRIP_SET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Control Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Fan Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Control Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Programming the Look Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 DTS Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RPM based Fan Speed Control Algorithm (FSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Programming the RPM Based Fan Speed Control Algorithm . . . . . . . . . . . . . . . . . . . . . Tachometer Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Stalled Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Aging Fan or Invalid Drive Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11.1 Dynamic Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11.2 Resistance Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11.3 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11.4 Digital Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12.1 Diode Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 22 22 24 25 25 26 27 27 28 29 29 29 30 31 31 32 32 32 32 33 33 33 34 34
5.2 5.3 5.4
5.5 5.6
5.7 5.8 5.9 5.10 5.11
5.12 5.13
Chapter 6 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 6.2 6.3 6.4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Lock Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Critical/Thermal Shutdown Temperature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pushed Temperature Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
35 41 42 43 43
SMSC EMC2103
Revision 0.85 (01-29-08)
DATASHEET
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 6.28 6.29 6.30 6.31 6.32 6.33 6.34 6.35 6.36 6.37 6.38 6.39 6.40 6.41 6.42 6.43 6.44
TRIP_SET Voltage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ideality Factor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Beta Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Critical Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.1 Tcrit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Base Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Setting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Divide Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Configuration 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Spin Up Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Step Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Minimum Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Drive Fail Band Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACH Target Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACH Reading Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Look Up Table Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Look Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Direction Register (EMC2103-2 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Output Configuration Register (EMC2103-2 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Input Register (EMC2103-2 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Output Register (EMC2103-2 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Interrupt Enable Register (EMC2103-2 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Status Register (EMC2103-2 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Features Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manufacturer ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44 44 45 46 47 47 48 49 50 50 51 51 52 52 53 53 54 54 55 56 58 58 60 60 61 61 62 62 63 64 65 66 66 66 67 67 68 68 69 69 69
Chapter 7 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.1 7.2 EMC2103-1 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 EMC2103-2 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Appendix A Look Up Table Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
A.1 A.2 Example #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Example #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Appendix B RPM to Tachometer Count Look Up Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
B.1 1k RPM Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Revision 0.85 (01-29-08)
4
SMSC EMC2103
DATASHEET
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
List of Figures
Figure 1.1 Figure 2.1 Figure 2.2 Figure 4.1 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Figure 7.6 EMC2103 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 EMC2103-1 Pin Diagram (12 Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 EMC2103-2 Pin Diagram (16 pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System Diagram for EMC2103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Diagram of Critical / Thermal Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Fan Control Look-Up Table Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 RPM based Fan Speed Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Diode Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Preliminary 12 pin QFN 4mm x 4mm Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 70 Preliminary 12 Pin QFN 4mm x 4mm Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Recommended PCB Footprint 12-pin QFN 4mm x 4mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Preliminary 16 Pin QFN 4mm x 4mm Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 73 Preliminary 16 Pin QFN 4mm x 4mm Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Recommended PCB Footprint 16-pin QFN 4mm x 4mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SMSC EMC2103
5
Revision 0.85 (01-29-08)
DATASHEET
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
List of Tables
Table 2.1 Pin Description for EMC2103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.1 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.2 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.3 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.4 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.5 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.6 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.1 SHDN_SEL Pin Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.2 TRIP_SET Resistor Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.3 Fan Controls Active for Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.4 Dynamic Averaging Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.1 EMC2103 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.4 Critical/Thermal Shutdown Temperature Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.5 Critical / Thermal Shutdown Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.6 Pushed Temperature Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.7 TRIP_SET Voltage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.8 Ideality Factor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.9 Ideality Factor Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.10 Beta Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.11 Beta Compensation Look Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.12 REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.13 Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.14 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.15 Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.16 Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.17 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.18 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.19 Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.20 Fan Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.21 Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.22 Fan Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.23 PWM Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.24 PWM Base Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.25 PWM_BASEx[1:0] it Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.26 Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.27 Fan Driver Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.28 PWM Divide Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.29 Fan Configuration 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.30 Range Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.31 Minimum Edges for Fan Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.32 Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.33 Fan Configuration 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.34 Derivative Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.35 Error Range Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.36 Gain Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.37 Gain Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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10 12 13 14 15 17 17 18 18 18 18 22 23 24 32 35 42 42 43 43 43 44 44 44 45 46 46 47 47 48 49 49 49 50 51 51 52 52 53 53 53 54 54 55 55 56 56 56 57 58 58 58
SMSC EMC2103
DATASHEET
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
Table 6.38 Fan Spin Up Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.39 DRIVE_FAIL_CNT[1:0] Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.40 Spin Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.41 Spin Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.42 Fan Step Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.43 Minimum Fan Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.44 Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.45 Fan Drive Fail Band Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.46 TACH Target Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.47 TACH Reading Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.48 Look Up Table Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.49 Look Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.50 GPIO Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.51 GPIO Output Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.52 GPIO Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.53 GPIO Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.54 GPIO Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.55 GPIO Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.56 Software Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.57 Product Features Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.58 SHDN_SEL[2:0] Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.59 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.60 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.61 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.1 Look Up Table Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.2 Look Up Table Example #1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.3 Fan Speed Control Table Example #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.4 Fan Speed Determination for Example #1 (using settings in Table A.3) . . . . . . . . . . . . . . . . . Table A.5 Look Up Table Example #2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.6 Fan Speed Control Table Example #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.7 Fan Speed Determination for Example #2 (using settings in Table A.6) . . . . . . . . . . . . . . . . . Table B.1 Tachometer Count to RPM Look Up Table (Range = 1000 RPM). . . . . . . . . . . . . . . . . . . . . .
58 59 59 60 60 60 61 61 62 62 63 64 65 66 66 66 67 67 68 68 68 69 69 69 76 77 77 77 78 78 79 80
SMSC EMC2103
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Revision 0.85 (01-29-08)
DATASHEET
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
Chapter 1 Block Diagram
SYS_SHDN SHDN_SEL
TRIP_SET
GPIO1*
DP1 DN1 DP2 / DN3* DN2 / DP3*
External Temp Diodes Analog Mux
Thermal Shutdown Logic
GPIO
Temp Limit Registers 11 bit ADC SMBus Slave Protocol SMCLK SMDATA ALERT
Internal Temp Diode Configuration
Temp Registers
PWM
PWM driver
TACH
Tach
Lookup Table / RPM Control
* denote EMC2103-2 pins only
Figure 1.1 EMC2103 Block Diagram
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8
GPIO2*
GND
VDD
SMSC EMC2103
DATASHEET
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
Chapter 2 Pin Layout
11 SHDN_SEL
12 TRIP_SET
10
GND
DN DP VDD
1 2 3 4 5 6 EMC2103-1 12-QFN
9 8 7
PWM TACH SMCLK
ALERT
Figure 2.1 EMC2103-1 Pin Diagram (12 Pin QFN)
SMSC EMC2103
SYS_SHDN
9
SMDATA
Revision 0.85 (01-29-08)
DATASHEET
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
16
15
14
DN1 DP1 VDD GPIO1
1 2 3 4 5 6 7 8 EMC2103-2 16-QFN
13
SHDN_SEL
DP2 / DN3
DN2 / DP3
TRIP_SET
12 11 10 9
GND PWM TACH SMCLK
ALERT
Figure 2.2 EMC2103-2 Pin Diagram (16 pin QFN)
Table 2.1 Pin Description for EMC2103 PIN NUMBER EMC2103-1 1 2 3 PIN NUMBER EMC2103 -2 1 2 3
PIN NAME DN1 DP1 VDD
SYS_SHDN
SMDATA
PIN FUNCTION Negative (cathode) analog input for External Diode 1. Positive (anode) analog input for External Diode 1. Power Supply GPI1 - General Purpose Input (default)
GPIO2
PIN TYPE AIO AIO Power DI (5V) OD (5V) DO
N/A
4
GPIO1
GPO1 - Open Drain digital output GPO1 - Push-pull digital output
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SMSC EMC2103
DATASHEET
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
Table 2.1 Pin Description for EMC2103 (continued) PIN NUMBER EMC2103-1 PIN NUMBER EMC2103 -2
PIN NAME
PIN FUNCTION GPI2 - General Purpose Input (default)
PIN TYPE DI (5V) OD (5V) DO OD (5V)
N/A
5
GPIO2
GPO2 - Open Drain digital output GPO2 - Push-pull digital output
4
6
ALERT
Active low interrupt - requires external pull-up resistor. Active low Critical / Thermal Shutdown output - requires external pull-up resistor SMBus data input/output - requires external pull-up resistor SMBus clock input - requires external pull-up resistor Tachometer input for the Fan PWM - Open Drain PWM drive output for the Fan (default) PWM - Push-Pull PWM drive output for the Fan
5
7
SYS_SHDN
OD (5V)
6 7 8
8 9 10
SMDATA SMCLK TACH
DIOD (5V) DI (5V) DI (5V) OD (5V)
9
11
PWM
DO Power AIO AIO
10 11 12
12 13 14
GND SHDN_SEL TRIP_SET
Ground connection Selects the hardware shutdown channel and operating mode Voltage input to set the Critical / Thermal Shutdown threshold Negative (cathode) analog input for External Diode 2 and positive (anode) analog input for External Diode 3 Positive (anode) analog input for External Diode 2 and negative (cathode) connection for External Diode 3
N/A
15
DN2 / DP3
AIO
N/A
16
DP2 / DN3
AIO
The pin type are described in detail below. All pins labelled with (5V) are 5V tolerant.
SMSC EMC2103
11
Revision 0.85 (01-29-08)
DATASHEET
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
Table 2.2 Pin Types PIN TYPE Power DI AIO DO DESCRIPTION This pin is used to supply power or ground to the device. Digital Input - this pin is used as a digital input. This pin is 5V tolerant. Analog Input / Output - this pin is used as an I/O for analog signals. Push / Pull Digital Output - this pin is used as a digital output. It can both source and sink current. Digital Input / Open Drain Output this pin is used as an digital I/O. When it is used as an output, It is open drain and requires a pull-up resistor. This pin is 5V tolerant. Open Drain Digital Output - this pin is used as a digital output. It is open drain and requires a pull-up resistor. This pin is 5V tolerant.
DIOD
OD
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SMSC EMC2103
DATASHEET
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
Chapter 3 Electrical Characteristics
Table 3.1 Absolute Maximum Ratings Voltage on 5V tolerant pins Voltage on VDD pin Voltage on any other pin to GND Package Power Dissipation Junction to Ambient (JA) Operating Ambient Temperature Range Storage Temperature Range ESD Rating, All Pins, HBM -0.3 to 5.5 -0.3 to 4 -0.3 to VDD + 0.3 0.8W up to TA = 85C 50 -40 to 125 -55 to 150 2000 V V V W C/W C C V
Note: Stresses above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. Note: All voltages are relative to ground. Note: JA numbers are based on a recommended four 12 mil vias connecting the thermal pad to PCB ground.
SMSC EMC2103
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Revision 0.85 (01-29-08)
DATASHEET
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
3.1
Electrical Specifications
Table 3.2 Electrical Specifications VDD = 3V to 3.6V, TA = -40C to 125C, all Typical values at TA = 27C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
DC Power Supply Voltage VDD 3 3.3 3.6 V 4 Conversions / second, Fan Driver active at maximum PWM frequency, Dynamic Averaging Enabled (EMC2103-2) 4 Conversions / second, Fan Driver active at maximum PWM frequency, Dynamic Averaging Enabled (EMC2103-1) 1 Conversions / second, Fan Driver not active, Dynamic Averaging Disabled Time after power up before all channels updated Time before SMBus communications should be sent by host
1.3
1.8
mA
Supply Current
IDD
1
1.5
mA
450 First Conversion Ready SMBus Delay
750
uA
tCONV_T
300
ms
tSMB_D
10 External Temperature Monitors
ms
Temperature Accuracy Temperature Resolution Diode decoupling capacitor Resistance Error Corrected CFILTER RSERIES
0.5 1 0.125 2200 100
1 2
C C C
60C < TDIODE < 125C 30C < TA < 100C -40C < TDIODE < 125C
2700
pF Ohm
Connected across external diode, CPU, GPU, or AMD diode Sum of series resistance in both DP and DN lines
Internal Temperature Monitor Temperature Accuracy Temperature Resolution TDIE 1 0.125 PWM Fan Driver PWM Resolution PWM Duty Cycle PWM DUTY 0 256 100 TRIP_SET Measurement Voltage Accuracy
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C C
Steps %
VTRIP
0.5
14
1
%
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Table 3.2 Electrical Specifications (continued) VDD = 3V to 3.6V, TA = -40C to 125C, all Typical values at TA = 27C unless otherwise noted. CHARACTERISTIC Temperature Decode Accuracy SYMBOL TTRIP MIN TYP MAX 0.5 1 2 UNIT C C CONDITIONS 1% external resistor 5% external resistor
RPM Based Fan Controller Tachometer Range Tachometer Setting Accuracy TACH 480 2.5 16000 5 RPM %
TACH
Digital I/O pins Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Leakage Current VIH VIL VOH VOL ILEAK VDD 0.4 0.4 5 2.0 0.8 V V V V uA 8 mA current drive 8 mA current sink ALERT and SYS_SHDN pins Device powered or unpowered TA < 85C
3.2
SMBus Electrical Specifications (Client Mode)
Table 3.3 SMBus Electrical Specifications VDD= 3V to 3.6V, TA = -40C to 125C Typical values are at TA = 27C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
SMBus Interface Input High/Low Current Input Capacitance IIH / IIL CIN 4 5 10 uA pF Device powered or unpowered TA < 85C
SMBus Timing Clock Frequency Spike Suppression Bus free time Start to Stop Setup Time: Start Setup Time: Stop Data Hold Time Data Setup Time fSMB tSP tBUF tSU:STA tSU:STP tHD:DAT tSU:DAT 1.3 0.6 0.6 0.6 0.6 6 72 10 400 50 kHz ns us us us us us
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Table 3.3 SMBus Electrical Specifications (continued) VDD= 3V to 3.6V, TA = -40C to 125C Typical values are at TA = 27C unless otherwise noted. CHARACTERISTIC Clock Low Period Clock High Period Clock/Data Fall time Clock/Data Rise time Capacitive Load SYMBOL tLOW tHIGH tFALL tRISE CLOAD MIN 1.3 0.6 300 300 400 TYP MAX UNITS us us ns ns pF Min = 20+0.1CLOAD ns Min = 20+0.1CLOAD ns Total per bus line CONDITIONS
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Chapter 4 Communications
4.1 System Management Bus Interface Protocol
The EMC2103 communicates with a host controller, such as an SMSC SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 4.1. Stretching of the SMCLK signal is supported, however the EMC2103 will not stretch the clock signal.
TLOW
THIGH
THD:STA TSU:STO
SMCLK
THD:STA
TRISE
TFALL
THD:DAT
TSU:DAT
TSU:STA
SMDATA
TBUF
P
S
S - Start Condition
S
P - Stop Condition P
Figure 4.1 SMBus Timing Diagram The EMC2103 contains a single SMBus interface. The EMC2103 client interfaces are SMBus 2.0 compatible and support Send Byte, Read Byte, Receive Byte and the Alert Response Address as valid protocols. These protocols are used as shown below. All of the below protocols use the convention in Table 4.1.
Table 4.1 Protocol Format DATA SENT TO DEVICE # of bits sent DATA SENT TO THE HOST # of bits sent
4.2
Write Byte
The Write Byte is used to write one byte of data to the registers as shown below Table 4.2:
Table 4.2 Write Byte Protocol SLAVE ADDRESS 0101_110 REGISTER ADDRESS 0 -> 1 REGISTER DATA XXh
START 0 -> 1
WR 0
ACK 0
ACK 0
ACK 0
STOP 1 -> 0
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4.3
Read Byte
The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4.3.
Table 4.3 Read Byte Protocol SLAVE ADDRESS 0101_110 REGISTER ADDRESS XXh SLAVE ADDRESS 0101_110 REGISTER DATA XXh
START 0 -> 1
WR 0
ACK 0
ACK 0
START 0 -> 1
RD 1
ACK 0
NACK 1
STOP 1 -> 0
4.4
Send Byte
The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 4.4.
Table 4.4 Send Byte Protocol SLAVE ADDRESS 0101_110 REGISTER ADDRESS XXh
START 0 -> 1
WR 0
ACK 0
ACK 1
STOP 1 -> 0
4.5
Receive Byte
The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in Table 4.5.
Table 4.5 Receive Byte Protocol SLAVE ADDRESS 0101_110
START 0 -> 1
RD 1
ACK 0
REGISTER DATA XXh
NACK 1
STOP 1 -> 0
4.6
Alert Response Address
The ALERT output can be used as a processor interrupt or as an SMBus Alert when configured to operate as an interrupt. When it detects that the ALERT pin is asserted, the host will send the Alert Response Address (ARA) to the general address of 0001_100b. All devices with active interrupts will respond with their client address as shown in Table 4.6. Table 4.6 Alert Response Address Protocol ALERT RESPONSE ADDRESS 0001_100
START 0 -> 1
RD 1
ACK 0
DEVICE ADDRESS 0101_1100
NACK 1
STOP 1 -> 0
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The EMC2103 will respond to the ARA in the following way if the ALERT pin is asserted. 1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication from the device was not prematurely stopped due to a bus contention event). 2. Set the MASK bit to clear the ALERT pin.
4.7
SMBus Address
The EMC2103 SMBus Address is fixed at 0101_110xb. Other addresses are available. Contact SMSC for details. Attempting to communicate with the EMC2103 SMBus interface with an invalid slave address or invalid protocol will result in no response from the device and will not affect its register contents.
4.8
SMBus Time-out
The EMC2103 includes an SMBus time-out feature. Following a 30ms period of inactivity on the SMBus, the device will time-out and reset the SMBus interface.
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Chapter 5 General Description
The EMC2103 is an SMBus compliant fan controller with one external (EMC2103-2 offers up to three external diode channels) and one internal temperature channels. The fan driver can be operated using two methods each with two modes. The methods include an RPM based Fan Speed Control Algorithm and a direct PWM drive setting. The modes include manually programming the desired settings or using the internal programmable temperature look-up table to select the desired setting based on measured temperature. The temperature monitors offer 1C accuracy (for external diodes) with sophisticated features to reduce errors introduced by series resistance and beta variation of substrate thermal diode transistors commonly found in processors (including support of the BJT or transistor model for a CPU diode). The EMC2103 allows the user to program temperatures generated from external sources to control the fan speed. This functionality also supports DTS data from the CPU. By pushing DTS or standard temperature values into dedicated registers, the external temperature readings can be used in conjunction with the external diode(s) and internal diode to control the fan speed. The EMC2103 also includes a hardware programmable temperature limit and dedicated system shutdown output for thermal protection of critical circuitry. Figure 5.1 shows a system diagram of the EMC2103.
* denotes EMC2103-2 only VDD VDD EMC2103 HOST CPU DP1 Thermal diode DN1 SMCLK SMDATA VDD SMBus Interface
ALERT GPIO1* DP2 / DN3* DN2 / DP3* 1.5V PWM Fan Drive Circuitry GPIO2*
Optional antiparallel diode
1.2k
TACH VDD
TRIP_SET
SYS_SHDN
Figure 5.1 System Diagram for EMC2103
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5.1
Critical/Thermal Shutdown
The EMC2103 provides a hardware Critical/Thermal Shutdown function for systems. Figure 5.2 is a block diagram of this Critical/Thermal Shutdown function. The Critical/Thermal Shutdown function accepts configuration information from the fixed states of the SHDN_SEL pin as described in Section 5.1.1. Each of the software programmed temperature limits can be optionally configured to act as inputs to the Critical / Thermal Shutdown independent of the hardware shutdown operation. When configured to operate this way, the SYS_SHDN# pin will be asserted when the temperature meets or exceeds the limit. The pin will be released when the temperature drops below the limit however the individual status bits will not be cleared if set (see Section 6.13). The analog portion of the Critical/Thermal Shutdown function monitors the hardware determined shutdown channel (see Section 5.1.1). This measured temperature is then compared with TRIP_SET point. This TRIP_SET point is set by the system designer with a single external resistor divider as described in Section 5.1.2. The SYS_SHDN is asserted when the indicated temperature meets or exceeds the temperature threshold (TP) established by the TRIP_SET input pin for a number of consecutive measurements defined by the fault queue. If the HW_SHDN output is asserted and the temperature drops below the threshold, then it will be set to a logic `0' state.
Critical / Thermal Shutdown
SMBus Traffic
Temperature Conversion
Software Shutdown Enable
VDD
H/W Thermal Shutdown Sensor Temperature Conversion SW_SHDN
Resistor Decode
SHDN_SEL
HW_SHDN
SYS_SHDN
TRIP_SET
Figure 5.2 Block Diagram of Critical / Thermal Shutdown
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5.1.1
SHDN_SEL Pin
The EMC2103 has a `strappable' input (SHDN_SEL) allowing for configuration of the hardware Critical/Thermal Shutdown input channel. The pull-up resistor used on this pin identifies which configuration setting is used as shown in Table 5.1.
.
Table 5.1 SHDN_SEL Pin Decode PULL UP RESISTOR MODE OF OPERATION External Diode 1 Simple Mode Beta compensation disabled, REC disabled - recommended for AMD CPU diodes External Diode 1 Diode Mode Beta compensation disabled, REC enabled External Diode 1 Transistor Mode Beta compensation enabled, REC enabled - recommended for Intel 45nm and 65mn CPU diodes Internal Diode External Diode 2 Transistor Mode Beta Compensation enabled, REC enabled (EMC2103-2 only) See Note 5.1 External Diode 1 Transistor Mode Beta compensation enabled, REC enabled CONFIGURATION MECHANISM Host control via SMBus
< 4.7k Ohm
Host control via SMBus
6.8k Ohm
Host control via SMBus
10k Ohm
15k Ohm
Host control via SMBus Host control via SMBus
22k Ohm
Host control via SMBus
> 33k Ohm
Note 5.1
For the EMC2103-1, the decode for a 22k Ohm resistor on the SHDN_SEL pin will be to use the External Diode 1 channel in Diode Mode (the same as the decode for a 6.8k Ohm resistor) as the hardware shutdown device.
5.1.2
TRIP_SET Pin
The EMC2103's TRIP_SET pin is an analog input to the Critical/Thermal Shutdown block which sets the Thermal Shutdown temperature. The system designer creates a voltage level at the input through a simple resistor connected to GND as shown in Figure 5.2. The value of this resistor is used to create an input voltage on the TRIP_SET pin which is translated into a temperature ranging from 65C to 127C as shown in Table 5.2
APPLICATION NOTE: Current only flows when the TRIP_SET pin is being monitored. At all other times, the internal reference voltage is removed and the TRIP_SET pin will be pulled down to ground. APPLICATION NOTE: The TRIP_SET pin circuitry is designed to use a 1% resistor externally. Using a 1% resistor will result in the Thermal / Critical Shutdown temperature being decoded correctly. If a 5% resistor is used, then the Thermal / Critical Shutdown temperature may be decoded with as much as 1C error.
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Table 5.2 TRIP_SET Resistor Setting TTRIP (C) 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
SMSC EMC2103
RSET (1%) 0.0 28.7 48.7 69.8 90.9 113 137 158 182 210 237 261 294 324. 348 383 412 453 487 523 562 604 649 698 750 787 845 909 953 1020 1100 1150
23
TTRIP (C) 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 65
RSET (1%) 1240 1330 1400 1500 1580 1690 1820 1960 2050 2210 2370 2550 2740 2940 3160 3480 3740 4120 4530 4990 5490 6040 6810 7870 9090 10700 12700 15800 20500 29400 49900 Open
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5.2
Fan Control Modes of Operation
The EMC2103 has four modes of operation for the fan driver. Each mode uses Ramp Rate control and the Spin Up Routine 1. PWM Setting Mode - in this mode of operation, the user directly controls the PWM duty cycle setting. Updating the Fan Driver Setting Register (see Section 6.20) will instantly update the fan drive. This is the default mode. The PWM Setting Mode is enabled by clearing both the EN_ALGO bit in the Fan Configuration Register (see Section 6.22) and the LUT_LOCK bit in the Look Up Table Configuration Register (see Section 6.32). Whenever the PWM Setting Mode is enabled the current drive will be changed to what was last written into the Fan Driver Setting Register. 2. Fan Speed Control Mode (FSC) - in this mode of operation, the user determines a fan speed and the drive setting is automatically updated to achieve this target speed. This mode is enabled by clearing the LUT_LOCK bit in the Look Up Table (LUT) Configuration Register and setting the EN_ALGO bit in the Fan Configuration Register. 3. Using the Look Up Table with Fan Drive Settings (PWM Setting w/ LUT Mode) - In this mode of operation, the user programs the Look Up Table with PWM duty cycle settings and corresponding temperature thresholds. The fan drive is set based on the measured temperatures and the corresponding drive settings. This mode is enabled by programming the Look Up Table then setting the LUT_LOCK bit while the RPM / PWM bit is set to a `1' (see Section 6.32) 4. Using the Look Up Table with Fan Speed Control algorithm (FSC w/ LUT Mode)- In this mode of operation, the user programs the Look Up Table with fan speed target values and corresponding temperature thresholds. The TACH Target Register will be set based on the measured temperatures and the corresponding target settings. The PWM drive settings will be determined automatically based on the RPM based Fan Speed Control Algorithm This mode is enabled by programming the Look Up Table then setting the LUT_LOCK bit while the RPM / PWM bit is set to `0' (see Section 6.32).
Table 5.3 Fan Controls Active for Operating Mode DIRECT PWM SETTING MODE Fan Driver Setting (read / write) EDGES[1:0] UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Step DIRECT PWM SETTING W/ LUT MODE Fan Driver Setting (read only) EDGES[1:0] UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Step
FSC MODE Fan Driver Setting (read only) EDGES[1:0] (Fan Configuration) RANGE[1:0] (Fan Configuration) UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Step Fan Minimum Drive
FSC W/ LUT MODE Fan Driver Setting (read only) EDGES[1:0] RANGE[1:0] (Fan Configuration) UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Step Fan Minimum Drive
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Table 5.3 Fan Controls Active for Operating Mode (continued) DIRECT PWM SETTING MODE Valid TACH Count TACH Reading DIRECT PWM SETTING W/ LUT MODE Valid TACH Count TACH Reading Look Up Table Drive / Temperature Settings (read only) -
FSC MODE Valid TACH Count TACH Target (read / write) TACH Reading -
FSC W/ LUT MODE Valid TACH Count TACH Target (read only) TACH Reading Look up Table Drive / Temperature Settings (read only) DRIVE_FAIL_CNT [1:0] (Spin Up Configuration) + Fan Drive Fail Band
-
DRIVE_FAIL_CNT [1:0] (Spin Up Configuration) + Fan Drive Fail Band
5.3
PWM Fan Driver
The EMC2103 supports a high or low frequency PWM driver. The output can be configured as either push-pull or open drain and the frequency ranges from 9.5Hz to 26kHz in four programmable frequency bands.
5.4
Fan Control Look-Up Table
The EMC2103 uses a look-up table to apply a user-programmable fan control profile based on measured temperature to the fan driver. In this look-up table, each temperature channel is allowed to control the fan drive output independently (or jointly) by programming up to eight pairs of temperature and drive setting entries. The user programs the look-up table based on the desired operation. If the RPM based Fan Speed Control Algorithm is to be used (see Section 5.5), then the user must program a fan speed target for each temperature setting of interest. Alternately, if the RPM based Fan Speed Control Algorithm is not to be used, then the user must program a PWM setting for each temperature setting of interest. If the measured temperature on the External Diode channel meets or exceeds any of the temperature thresholds for any of the channels, the fan output will be automatically set to the desired setting corresponding to the exceeded temperature. In cases where multiple temperature channel thresholds are exceeded, the highest fan drive setting will take precedence. Figure 5.3 shows an example of this behavior using a single channel. When the measured temperature drops to a point below a lower threshold minus the hysteresis value, the fan output will be set to the corresponding lower set point.
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Temp T6 T6 - Hyst T5 T5 - Hyst T4 T4 - Hyst Averaged Temperature
Fan Setting S6
S5
S4
T3 T3 - Hyst Fan Setting
S3 S2
T2 T2 - Hyst T1
Measurement taken
S1
Time
Figure 5.3 Fan Control Look-Up Table Example
5.4.1
Programming the Look Up Table
When the Look Up Table is used, it must be loaded and configured correctly based on the system requirements. The following steps outline the procedure. 1. Determine whether the Look Up Table will drive a PWM duty cycle or a tachometer target value and set the RPM / PWM bit in the Fan LUT Configuration Register (see Section 6.32). 2. Determine which measurement channels (up to four) are to be used with the Look Up Table and set the TEMP3_CFG and TEMP4_CFG bits accordingly in the Fan LUT Configuration Register. 3. For each step to be used in the LUT, set the Fan Setting (either PWM or TACH Target as set by the RPM / PWM bit). If a setting is not used, then set it to FFh (if a PWM) or 00h (if a TACH Target). Load the lowest settings first in ascending order (i.e. Fan Setting 1 is the lowest setting greater than "off". Fan Setting 2 is the next highest setting, etc.). See Section 6.33. 4. For each step to be used in the LUT, set each of the measurement channel thresholds. These values must be set in the same data format that the data is presented. If DTS is to be used, then the format should be in temperature with a maximum threshold of 100C (64h). If a measurement channel is not used, then set the threshold at FFh. 5. Update the threshold hysteresis to be smaller than the smallest table step. 6. Configure the RPM based Fan Speed Control Algorithm if it is to be used. See Section 5.5.1 for more details.
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7. Set the LUT_LOCK bit to enable the Look Up Table and begin fan control in the Fan LUT Configuration Register.
5.4.2
DTS Support
The EMC2103 supports DTS (Intel's Digital Temperature Sensor) data in the Fan Control Look Up Table. Intel's DTS data is a positive number that represents the processor's relative temperature below a fixed value called TCONTROL which is generally equal to 100C for Intel Mobile processors. For example, a DTS value of 10C means that the actual processor temperature is 10C below TCONTROL or equal to 90C. Either or both of the Pushed Temperature Registers can be written with DTS data and used to control the fan driver. When DTS data is entered, then the USE_DTS_Fx bit must be set in the Fan LUT Configuration register. Once this bit is set, the DTS data entered is automatically subtracted from a value of 100C. This delta value is then used in the Look Up Table as standard temperature data.
APPLICATION NOTE: The device is designed with the assumption that TCONTROL is 100C. As such, all DTS related conversions are done based on this value including Look Up Table comparisons. If TCONTROL is adjusted (i.e. TCONTROL is shifted to 105C), then all of the Look Up Table thresholds should be adjusted by a value equal to TCONTROL - 100C.
5.5
RPM based Fan Speed Control Algorithm (FSC)
The EMC2103 includes an RPM based Fan Speed Control Algorithm. This fan control algorithm uses Proportional, Integral, and Derivative terms to automatically approach and maintain the system's desired fan speed to an accuracy directly proportional to the accuracy of the clock source. Figure 5.4 shows a simple flow diagram of the RPM based Fan Speed Control Algorithm operation. The desired tachometer count is set by the user inputting the desired number of 32.768KHz cycles that occur per fan revolution. This is done by either manually setting the TACH Target Register or by programming the Temperature Look-Up Table. The user may change the target count at any time. The user may also set the target count to FFh in order to disable the fan driver for lower current operation. For example, if a desired RPM rate for a 2-pole fan is 3000 RPM then the user would input the hexidecimal equivalent of 1296 (51h in the TACH Target Register). This number represents the number of 32.768KHz cycles that would occur during the time it takes the fan to complete a single revolution when it is spinning at 3000RPMs. See Section 6.30 for RPM -> TACH calculations or Appendix B for a complied table showing this information (for default conditions). The EMC2103's RPM based Fan Speed Control Algorithm has programmable configuration settings for parameters such as ramp-rate control and spin up conditions. The fan driver automatically detects and attempts to alleviate a stalled/stuck fan condition while also asserting the ALERT pin. The EMC2103 works with fans that operate up to 16,000 RPMs and provides a valid tachometer signal.
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S e t T A C H T a rg e t C ount
M e a su re F a n S p e e d
S p in U p R e q u ire d ? No
Yes
P e rfo rm S p in U p R o u tin e
Yes M a in ta in F a n D rive
TACH R e a d in g = TACH T a rg e t?
No
Y es
TACH R e a d in g < TACH T a rg e t?
No
R a m p R a te C o n tro l
R e d u ce F a n D riv e
In cre a s e F a n D rive
Figure 5.4 RPM based Fan Speed Control Algorithm
5.5.1
Programming the RPM Based Fan Speed Control Algorithm
The RPM based Fan Speed Control Algorithm powers-up disabled. The following registers control the algorithm. The EMC2103 fan control registers are pre-loaded with defaults that will work for a wide variety of fans so only the TACH Target Register is required to set a fan speed. The other fan control registers can be used to fine-tune the algorithm behavior based on application requirements. Note that steps 1 - 7 are optional and need only be performed if the default settings do not provide the desired fan response. 1. Set the Valid TACH Count Register to maximum number of tach counts to indicate the fan is spinning. 2. Set the Spin Up Configuration Register to the Spin Up Level and Spin Time desired.
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3. Set the Fan Step Register to the desired step size. 4. Set the Fan Minimum Drive Register to the minimum drive value that will maintain fan operation. 5. Set the Update Time, and Edges options in the Fan Configuration Register. 6. Set the valid TACH count setting at the highest count that indicates that the fan is spinning. 7. Set the TACH Target Register to the desired tachometer count. 8. Enable the RPM based Fan Speed Control Algorithm by setting the EN_ALGO bit.
5.6
Tachometer Measurement
The tachometer measurement circuitry is used in conjunction with the RPM based Fan Speed Control Algorithm to update the fan driver output. Additionally, it can be used in Direct Setting mode as a diagnostic for host based fan control. This method monitors the TACH signal in real time. It constantly updates the tachometer measurement by reporting the number of clocks between a user programmed number of edges on the TACH signal (see Table 8.5) Using the Tach Period Measurement method provides fast response times for the RPM based Fan Speed Control Algorithm and the data is presented as a count value that represents the fan RPM period. When this method is used, all fan target values must be input as a count value for proper operation.
APPLICATION NOTE: The Tach Period Measurement method works independently of the drive settings. If the device is put into Direct Setting and the fan drive is set at a level that is lower than the fan can operate (including zero drive), then the tachometer measurement may signal a Stalled Fan condition and assert an interrupt.
5.6.1
Stalled Fan
A Stalled fan is detected differently based on which tach method is enabled. If the Tach Period Measurement measurement method is implemented, and if the tach counter exceeds the userprogrammable Valid TACH Count setting then it will flag the fan as stalled and trigger an interrupt. If the RPM based Fan Speed Control Algorithm is enabled, the algorithm will automatically attempt to restart the fan until it detects a valid tachometer level or is disabled. The FAN_STALL Status bit indicates that a stalled fan was detected. This bit is checked conditionally depending on the mode of operation. When the Direct Setting Mode or Direct Setting with LUT Mode are enabled or the Spin Up Routine is initiated, the FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time (see Table 8.16). This is to allow the fan opportunity to reach a valid speed without generating unnecessary interrupts. When the Direct Setting Mode or Direct Setting w/ LUT Mode are activated then whenever the TACH Reading Register value exceeds the Valid TACH Count Register setting, the FAN_STALL status bit will be set. When using the RPM based Fan Speed Control Algorithm (either FSC Mode or LUT with FSC Mode), the stalled fan condition is checked whenever the Update Time is met and the fan drive setting is updated. It is not a continuous check.
5.6.2
Aging Fan or Invalid Drive Detection
The EMC2103 contains circuitry that detects that the programmed fan speed can be reached by the fan. If the target fan speed cannot be reached within a user defined band of tach counts at maximum drive then the DRIVE_FAIL status bit is and the ALERT pin is asserted. This is useful to detect aging fan conditions (where the fan's natural maximum speed degrades over time) or incorrect fan speed settings.
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5.7
Spin Up Routine
The EMC2103 also contains programmable circuitry to control the spin up behavior of the fan driver to ensure proper fan operation. The Spin Up Routine is initiated under the following conditions when the Tach Period Measurement method of tach measurement is used. This applies to either the RPM based Fan Speed Control Algorithm mode or the Direct Setting mode (with or without the Look Up Table). 1. The TACH Target Register value changes from a value of FFh to a value that is less than the Valid TACH Count (see Section 8.10 and Section 8.12). 2. The RPM based Fan Speed Control Algorithm's measured TACH Reading Register value is greater than the Valid TACH Count setting. When the Spin Up Routine is operating, the fan driver is set to full scale (optional) for one quarter of the total user defined spin up time. For the remaining spin up time, the fan driver output is set a a user defined level (30% through 65% drive). After the Spin Up Routine has finished, the EMC2103 measures the TACH signal. If the measured TACH Reading Register value is higher than the Valid TACH Count Register setting, the FAN_SPIN status bit is set and the Spin Up Routine will automatically attempt to restart the fan. Figure 5.5 shows an example of the Spin Up Routine in response to a programmed fan speed change based on the first condition above.
100% (optional)
30% through 65% Fan Step
New Target Count Algorithm controlled drive Prev Target Count = FFh 1/4 of Spin Up Time
Update Time Spin Up Time
Target Count Changed
Check TACH
Figure 5.5 Spin Up Routine
Target Count Reached
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5.8
Ramp Rate Control
The PWM output drive can be configured with automatic ramp rate control. If the RPM based Fan Speed Control Algorithm is used, then this ramp rate control is automatically used based on the fan control derivative option settings. See Section 6.23, "Fan Configuration 2 Register". The user programs a maximum step size for the PWM setting and an update time. The update time varies from 100ms to 1.6s while the PWM maximum step can vary from 1 PWM count to 31 PWM counts. When a new PWM is entered, the delta from the next PWM and the previous PWM is determined. If this delta is greater than the Max Step settings, then the PWM is incrementally adjusted every 100ms to 1.6s as determined by the Update Time until the target PWM setting is reached. See Figure 5.6.
Next Desired Setting Max Step Max Step
Previous Setting
Update Time
Update Time
Setting Changed
Figure 5.6 Ramp Rate Control
5.9
Watchdog Timer
The EMC2103 contains an internal Watchdog Timer. Once the device has powered up the watchdog timer monitors the bus traffic for signs of activity. The Watchdog Timer starts when the internal supply has reached its operating point. The Watchdog Timer only starts immediately after power-up and once it has been triggered or deactivated will not restart. If four (4) seconds elapse without the system host programming the device, then the watchdog will be triggered and the following will occur: 1. The WATCH status bit will be set. 2. The fan driver will be set to full scale drive. It will remain at full scale drive until one of the three conditions listed below are met. If the Watchdog Timer is triggered, the following three operations will disable the timer and return the device to normal operation. Alternately, if the Watchdog Timer has not yet been triggered performing any one of the following will disable it. 1. Writing the Fan Setting Register will disable the Watchdog Timer. 2. Enabling the RPM based Fan Speed Control Algorithm by setting the EN_ALGO bit will disable the Watchdog Timer. The fan driver will be set based on the RPM based Fan Speed Control Algorithm.
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3. Setting the LUT_LOCK bit will disable the Watchdog Timer. The fan driver will be set based on the Look Up Table settings. Writing any other configuration registers will not disable the Watchdog Timer. APPLICATION NOTE: Disabling the Watchdog will not automatically set the fan drive. This must be done manually (or via the Look Up Table).
5.10
Fault Queue
The EMC2103 contains a programmable fault queue on all fault conditions. The fault queue defines how many consecutive out-of-limit conditions must be reported before the corresponding status bit is set (and the ALERT pin asserted).
5.11
Temperature Monitoring
The EMC2103 can monitor the temperature of up to three (3) externally connected diodes as well as the internal or ambient temperature. Each channel is configured with the following features enabled or disabled based on user settings and system requirements.
5.11.1
Dynamic Averaging
The EMC2103 supports dynamic averaging. When enabled, this feature changes the conversion time for all channels based on the selected conversion rate. This essentially increases the averaging factor as shown in Table 5.4. The benefits of Dynamic Averaging are improved noise rejection due to the longer integration time as well as less random variation on the temperature measurement.
Table 5.4 Dynamic Averaging Behavior
AVERAGING FACTOR (RELATIVE TO 11-BIT CONVERSI0N) CONVERSION RATE DYNAMIC AVERAGING ENABLED 8x 4x 2x 1x DYNAMIC AVERAGING DISABLED 1x 1x 1x 1x
1 / sec 2 / sec 4 / sec Continuous
5.11.2
Resistance Error Correction
The EMC2103 includes active Resistance Error Correction to remove the effect of up to 100 ohms of series resistance. Without this automatic feature, voltage developed across the parasitic resistance in the remote diode path causes the temperature to read higher than the true temperature is. The error induced by parasitic resistance is approximately +0.7C per ohm. Sources of parasitic resistance include bulk resistance in the remote temperature transistor junctions, series resistance in the CPU, and resistance in the printed circuit board traces and package leads. Resistance error correction in the EMC2103 eliminates the need to characterize and compensate for parasitic resistance in the remote diode path.
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5.11.3
Beta Compensation
The forward current gain, or beta, of a transistor is not constant as emitter currents change. As well, it is not constant over changes in temperature. The variation in beta causes an error in temperature reading that is proportional to absolute temperature. This correction is done by implementing the BJT or transistor model for temperature measurement. For discrete transistors configured with the collector and base shorted together, the beta is generally sufficiently high such that the percent change in beta variation is very small. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute approximately 0.25C error at 100C. However for substrate transistors where the base-emitter junction is used for temperature measurement and the collector is tied to the substrate, the proportional beta variation will cause large error. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 0.5 would contribute approximately 8.25C error at 100C. The Beta Compensation circuitry in the EMC2103 corrects for this beta variation to eliminate any error which would normally be induced. It automatically detects the appropriate beta setting to use.
5.11.4
Digital Averaging
The external diode channels support a 4x digital averaging filter. Every cycle, this filter updates the temperature data based an a running average of the last 4 measured temperature values. The digital averaging reduces temperature flickering and increases temperature measurement stability. The digital averaging can be disabled by setting the DIS_AVG bit in the Configuration 2 Register (see Section 6.11).
5.12
Diode Connections
The External Diode 1 channel can support a diode-connected transistor (such as a 2N3904) or a substrate transistor requiring the BJT or transistor model (such as those found in a CPU or GPU) as shown in Figure 5.7. The External Diode 2 channel supports any diode connection shown or it can be configured to operate in anti-parallel diode (APD) mode. When configured in APD mode, a third temperature channel is available that shares the DP2 and DN2 pins. When in this mode, both the external diode 2 channel and external diode 3 channel thermal diodes must be connected as diodes.
to DP to DN
to DP
to DP
to DN Local Ground Typical remote substrate transistor i.e. CPU substrate PNP Typical remote discrete PNP transistor i.e. 2N3906
Figure 5.7 Diode Connections
to DN
Typical remote discrete NPN transistor i.e. 2N3904
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5.12.1
Diode Faults
The EMC2103 actively detects an open and short condition on each measurement channel. When a diode fault is detected, the temperature data MSByte is forced to a value of 80h and the FAULT bit is set in the Status Register. When the External Diode 2 channel is configured to operate in APD mode, the circuitry will detect independent open fault conditions, however a short condition will be shared between the External Diode 2 and External Diode 3 channels. If a diode fault occurs on the hardware defined shutdown channel, then no temperature comparison is performed. The SYS_SHDN pin will not be asserted.
5.13
GPIOs
The EMC2103-2 contains two dedicated GPIO pins. The GPIO pins can be individually configured as an input or an output and as a push-pull or open-drain output. Additionally, each GPIO pin, when configured as an input, can be individually enabled to trigger an interrupt when they change states.
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Chapter 6 Register Set
6.1 Register Map
The following registers are accessible through the SMBus Interface. All register bits marked as `-' will always read `0'. A write to these bits will have no effect. APPLICATION NOTE: All registers denoted with a ** are specific to the EMC2103-2 only. Writing to these registers by the EMC2103-1 will have no affect and reading from them will return `00h'.
Table 6.1 EMC2103 Register Set REGISTER NAME DEFAULT VALUE
ADDR
R/W
FUNCTION Temperature Registers
LOCK
PAGE
00h
R
Internal Temp Reading High Byte Internal Temp Reading Low Byte External Diode 1 Temp Reading High Byte External Diode 1 Temp Reading Low Byte External Diode 2 Temp Reading High Byte ** External Diode 2 Temp Reading Low Byte ** External Diode 3 Temp Reading High Byte ** External Diode 3 Temp Reading Low Byte ** Critical/Thermal Shutdown Temperature Pushed Temperature 1 Pushed Temperature 2 TRIP_SET Voltage
Stores the integer data of the Internal Diode Stores the fractional data of the Internal Diode Stores the integer data of External Diode 1 Stores the fractional data of External Diode 1 Stores the integer data of External Diode 2 Stores the fractional data of External Diode 2 Stores the integer data of External Diode 3 Stores the fractional data of External Diode 3 Stores the calculated Critical/Thermal Shutdown temperature high limit derived from TRIP_SET pin voltage Stores the integer data for Pushed Temperature 1 to drive the LUT Stores the integer data for Pushed Temperature 2 to drive the LUT Stores the measured voltage on the TRIP_SET pin
00h
No
Page 42
01h 02h
R R
00h 00h
No No
Page 42 Page 42
03h
R
00h
No
Page 42
04h **
R
00h
No
Page 42
05h **
R
00h
No
Page 42
06h **
R
00h
No
Page 42
07h **
R
00h
No
Page 42
0Ah
R
N/A
No
Page 43
0Ch 0Dh 10h
R/W R/W R
00h 00h FFh
No No No
Page 43 Page 43 Page 44
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Table 6.1 EMC2103 Register Set (continued) REGISTER NAME DEFAULT VALUE
ADDR
R/W
FUNCTION Diode Configuration
LOCK
PAGE
11h 12h **
R/W R/W
External Diode 1 Ideality Register External Diode 2 Ideality Register ** External Diode 1 Beta Configuration External Diode 2 Beta Configuration ** External Diode REC Configuration External Diode 1 Tcrit Limit External Diode 2 Tcrit Limit ** External Diode 3 Tcrit Limit ** Internal Diode Tcrit Limit
Stores the Ideality Factor used for External Diode 1 Stores the Ideality factor used for External Diode 2 and External Diode 3 Configures the beta compensation settings for External Diode 1 Configures the beta compensation settings for External Diode 2 Configures the Resistance Error Correction functionality for all external diodes Stores the critical temperature limit for External Diode 1 Stores the critical temperature limit for External Diode 2 Stores the critical temperature limit for External Diode 3 Stores the critical temperature limit for the Internal Diode Configuration and control
12h 12h
SWL SWL
Page 44 Page 44
14h 15h **
R/W R/W
10h 10h
SWL SWL
Page 45 Page 45
17h
R/W
07h
SWL
Page 46
19h 1Ah ** 1Bh ** 1Dh
R/W once R/W once R/W once R/W once
64h (100C) 64h (100C) 64h (100C) 64h (100C)
Write Once Write Once Write Once Write Once
Page 47 Page 47 Page 47 Page 47
1Fh 20h 21h 23h 24h 25h 26h 27h 28h 29h
R R/W R/W R-C R-C R-C R-C R-C R/W R/W
Tcrit Status Configuration Configuration 2 Interrupt Status High Limit Status Low Limit Status Diode Fault Fan Status Interrupt Enable Register Fan Interrupt Enable Register
Stores the status bits for all temperature channel tcrit limits Configures the Thermal / Critical Shutdown masking options Controls the conversion rate for monitoring of all channels Stores the status bits for temperature channels Stores the status bits for all temperature channel high limits Stores the status bits for all temperature channel low limits Stores the status bits for all temperature channel diode faults Stores the status bits for the RPM based Fan Speed Control Algorithm Controls the masking of interrupts on all temperature channels Controls the masking of interrupts for the Fan Driver
36
00h 00h 0Eh 00h 00h 00h 00h 00h 00h 00h
No SWL SWL No No No No No No No
Page 50 Page 47 Page 48 Page 49 Page 50 Page 50 Page 50 Page 51 Page 51 Page 52
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Table 6.1 EMC2103 Register Set (continued) REGISTER NAME PWM Config PWM Base Frequency DEFAULT VALUE 00h 03h
ADDR 2Ah 2Bh
R/W R/W R/W
FUNCTION Configures the PWM driver Controls the base frequency of the PWM driver Temperature Limit Registers
LOCK No No
PAGE Page 52 Page 53
30h 31h ** 32h ** 34h 38h 39h ** 3Ah ** 3Ch
R/W R/W R/W R/W R/W R/W R/W R/W
External Diode 1 Temp High Limit External Diode 2 Temp High Limit ** External Diode 3 Temp High Limit ** Internal Diode High Limit External Diode 1 Temp Low Limit External Diode 2 Temp Low Limit ** External Diode 3 Temp Low Limit ** Internal Diode Low Limit
High limit for External Diode 1 High limit for External Diode 2 High limit for External Diode 3 High Limit for Internal Diode Low Limit for External Diode 1 Low Limit for External Diode 2 Low Limit for External Diode 3 Low Limit for Internal Diode Fan Control Registers
55h (+85C) 55h (+85C) 55h (+85C) 55h (85C) 00h (0C) 00h (0C) 00h (0C) 00h (0C)
SWL SWL SWL SWL SWL SWL SWL SWL
Page 53 Page 53 Page 53 Page 53 Page 53 Page 53 Page 53 Page 53
40h
R/W
Fan Setting
Always displays the most recent fan driver input setting for Fan. If the RPM based Fan Speed Control Algorithm is disabled, allows direct user control of the fan driver. Stores the divide ratio to set the frequency for the Fan Sets configuration values for the RPM based Fan Speed Control Algorithm for the Fan Sets additional configuration values for the Fan driver Holds the gain terms used by the RPM based Fan Speed Control Algorithm for the Fan Sets the configuration values for Spin Up Routine of the Fan driver Sets the maximum change per update for the Fan Sets the minimum drive value for the the Fan driver
00h
No
Page 54
41h 42h
R/W R/W
PWM Divide Fan Configuration 1 Fan Configuration 2 Gain
01h 2Bh
No No
Page 54 Page 55
43h 45h
R/W R/W
38h 2Ah
SWL SWL
Page 56 Page 58
46h 47h 48h
R/W R/W R/W
Fan Spin Up Configuration Fan Step Fan Minimum Drive
19h 10h 66h (40%)
SWL SWL SWL
Page 58 Page 60 Page 60
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Table 6.1 EMC2103 Register Set (continued) REGISTER NAME Fan Valid TACH Count Fan Drive Fail Band Low Byte Fan Drive Fail Band High Byte TACH Target Low Byte TACH Target High Byte TACH Reading High Byte TACH Reading Low Byte DEFAULT VALUE F5h
ADDR 49h
R/W R/W
FUNCTION Holds the minimum tachometer reading that indicates the fan is spinning properly Stores the number of Tach counts used to determine how the actual fan speed must match the target fan speed at full scale drive
LOCK SWL
PAGE Page 61
4Ah 4Bh 4Ch 4Dh 4Eh 4Fh
R/W R/W R/W R/W R R
00h 00h F8h FFh FFh F8h
SWL SWL No No No No
Page 61
Holds the target tachometer reading low byte for the Fan Holds the target tachometer reading for the Fan Holds the tachometer reading for the Fan Holds the tachometer reading low byte for the Fan Look Up Table (LUT)
Page 62 Page 62 Page 62 Page 62
50h 51h 52h
R/W R/W R/W
LUT Configuration LUT Drive 1 LUT Temp 1 Setting 1 LUT Temp 2 Setting 1 LUT Temp 3 Setting 1
Stores and controls the configuration for the LUT Stores the lowest programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 1 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 1 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 1 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 1 value Stores the second programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 2 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 2 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 2 value
00h FBh 7Fh (127C) 7Fh (127C) 7Fh (127C)
No LUT Lock LUT Lock LUT Lock LUT Lock
Page 63 Page 64 Page 64
53h
R/W
Page 64
54h
R/W
Page 64
55h
R/W
LUT Temp 4 Setting 1
7Fh (127C)
LUT Lock
Page 64
56h 57h
R/W R/W
LUT Drive 2 LUT Temp 1 Setting 2 LUT Temp 2 Setting 2 LUT Temp 3 Setting 2
E6h 7Fh (127C) 7Fh (127C) 7Fh (127C)
LUT Lock LUT Lock LUT Lock LUT Lock
Page 64 Page 64
58h
R/W
Page 64
59h
R/W
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Table 6.1 EMC2103 Register Set (continued) REGISTER NAME LUT Temp 4 Setting 2 DEFAULT VALUE 7Fh (127C)
ADDR 5Ah
R/W R/W
FUNCTION Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 2 value Stores the third programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 3 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 3 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 3 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 3 value Stores the fourth programmed drive setting for the LUT Stores the threshold level for the External Diode 1channel that is associated with the Drive 4 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 4 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 4 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 4 value Stores the fifth programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 5 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 5 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 5 value
LOCK LUT Lock
PAGE Page 64
5Bh 5Ch
R/W R/W
LUT Drive 3 LUT Temp 1 Setting 3 LUT Temp 2 Setting 3 LUT Temp 3 Setting 3
D1h 7Fh (127C) 7Fh (127C) 7Fh (127C)
LUT Lock LUT Lock LUT Lock LUT Lock
Page 64 Page 64
5Dh
R/W
Page 64
5Eh
R/W
Page 64
5Fh
R/W
LUT Temp 4 Setting 3
7Fh (127C)
LUT Lock
Page 64
60h 61h
R/W R/W
LUT Drive 4 LUT Temp 1 Setting 4 LUT Temp 2 Setting 4 LUT Temp 3 Setting 4
BCh 7Fh (127C) 7Fh (127C) 7Fh (127C)
LUT Lock LUT Lock LUT Lock LUT Lock
Page 64 Page 64
62h
R/W
Page 64
63h
R/W
Page 64
64h
R/W
LUT Temp 4 Setting 4
7Fh (127C)
LUT Lock
Page 64
65h 66h
R/W R/W
LUT Drive 5 LUT Temp 1 Setting 5 LUT Temp 2 Setting 5 LUT Temp 3 Setting 5
A7h 7Fh (127C) 7Fh (127C) 7Fh (127C)
LUT Lock LUT Lock LUT Lock LUT Lock
Page 64 Page 64
67h
R/W
Page 64
68h
R/W
Page 64
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Table 6.1 EMC2103 Register Set (continued) REGISTER NAME LUT Temp 4 Setting 5 DEFAULT VALUE 7Fh (127C)
ADDR 69h
R/W R/W
FUNCTION Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 5 value Stores the sixth programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 6 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 6 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 6 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 6 value Stores the seventh programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 7 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 7 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 7 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 7 value Stores the highest programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 8 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 8 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 8 value
LOCK LUT Lock
PAGE Page 64
6Ah 6Bh
R/W R/W
LUT Drive 6 LUT Temp 1 Setting 6 LUT Temp 2 Setting 6 LUT Temp 3 Setting 6
92h 7Fh (127C) 7Fh (127C) 7Fh (127C)
LUT Lock LUT Lock LUT Lock LUT Lock
Page 64 Page 64
6Ch
R/W
Page 64
6Dh
R/W
Page 64
6Eh
R/W
LUT Temp 4 Setting 6
7Fh (127C)
LUT Lock
Page 64
6Fh 70h
R/W R/W
LUT Drive 7 LUT Temp 1 Setting 7 LUT Temp 2 Setting 7 LUT Temp 3 Setting 7
92h 7Fh (127C) 7Fh (127C) 7Fh (127C)
LUT Lock LUT Lock LUT Lock LUT Lock
Page 64 Page 64
71h
R/W
Page 64
72h
R/W
Page 64
73h
R/W
LUT Temp 4 Setting 7
7Fh (127C)
LUT Lock
Page 64
74h 75h
R/W R/W
LUT Drive 8 LUT Temp 1 Setting 8 LUT Temp 2 Setting 8 LUT Temp 3 Setting 8
92h 7Fh (127C) 7Fh (127C) 7Fh (127C)
LUT Lock LUT Lock LUT Lock LUT Lock
Page 64 Page 64
76h
R/W
Page 64
77h
R/W
Page 64
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Table 6.1 EMC2103 Register Set (continued) REGISTER NAME LUT Temp 4 Setting 8 DEFAULT VALUE 7Fh (127C)
ADDR 78h
R/W R/W
FUNCTION Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 8 value Stores the hysteresis that is shared for all temperature inputs Controls the GPIO direction for GPIOs 1 and 2 Controls the output type of GPIOs 1 and 2 Stores the inputs for GPIOs 1 and 2 Controls the output state of GPIOs 1 and 2 Enables interrupts for GPIOs 1 and 2 Indicates when the GPIOs change state Lock Register
LOCK LUT Lock
PAGE Page 64
79h E1h ** E2h **
R/W R/W R/W
LUT Temp Hysteresis GPIO Direction Register ** GPIO Output Configuration Register ** GPIO Input Register ** GPIO Output Register ** GPIO Interrupt Enable Register ** GPIO Status **
0Ah (10C) 00h 00h
LUT Lock No No
Page 64 Page 65 Page 66
E3h ** E4h ** E5h ** E6h **
R/W R/W R/W R/W
00h 00h 00h 00h
No No No No
Page 66 Page 66 Page 67 Page 67
EF
R/W
Software Lock
Locks all SWL registers Revision Registers
00h
SWL
Page 68
FCh FDh
R R
Product Features Product ID EMC2103-1 Product ID EMC2103-2
Indicates which pin selected options are enabled Stores the unique Product ID
00h 24h 26h
No No No No No
Page 68 Page 69
FEh FFh
R R
Manufacturer ID Revision
Manufacturer ID Revision
5Dh 00h
Page 69 Page 69
During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect.
6.1.1
Lock Entries
The Lock Column describes the locking mechanism, if any, used for individual registers. All SWL registers are Software Locked and therefore made read-only when the LOCK bit is set.
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6.2
Temperature Data Registers
Table 6.2 Temperature Data Registers
ADDR 00h 01h
R/W R R
REGISTER Internal Diode High Byte Internal Diode Low Byte External Diode 1 High Byte External Diode 1 Low Byte External Diode 2 High Byte ** External Diode 2 Low Byte ** External Diode 3 High Byte ** External Diode 3 Low Byte **
B7 Sign 0.5 Sign
B6 64 0.25 64
B5 32 0.125 32
B4 16 16
B3 8 8
B2 4 4
B1 2 2
B0 1 1
DEFAULT 00h 00h 00h
02h
R
0.5
0.25
0.125
-
-
-
-
-
00h
03h
R
Sign
64
32
16
8
4
2
1
00h
04h **
R
0.5
0.25
0.125
-
-
-
-
-
00h
05h **
R
Sign
64
32
16
8
4
2
1
00h
06h **
R
0.5
0.25
0.125
-
-
-
-
-
00h
07h **
R
The temperature measurement range is from -64C to +127.875C. The data format is a signed two's complement number as shown in Table 6.3.
Table 6.3 Temperature Data Format HEX (AS READ BY REGISTERS) 80_00h C0_20h C1_00h FF_00h FF_E0h 00_00h 00_20h 01_00h 3F_00h 40_00h
TEMPERATURE (C) Diode Fault -63.875 -63 -1 -0.125 0 0.125 1 63 64
BINARY 1000_0000_000b 1100_0000_001b 1100_0001_000b 1111_1111_000b 1111_1111_111b 0000_0000_000b 0000_0000_001b 0000_0001_000b 0011_1111_000b 0100_0000_000b
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Table 6.3 Temperature Data Format (continued) HEX (AS READ BY REGISTERS) 41_00h 7F_00h 7F_E0h
TEMPERATURE (C) 65 127 127.875
BINARY 0100_0001_000b 0111_1111_000b 0111_1111_111b
6.3
Critical/Thermal Shutdown Temperature Register
Table 6.4 Critical/Thermal Shutdown Temperature Register
ADDR 0Ah
R/W R
REGISTER Critical/Thermal Shutdown Temperature
B7 128
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 7Fh (+127C)
The Critical/Thermal Shutdown Temperature Register is a read-only register that stores the Voltage Programmable Threshold temperature used in the Thermal / Critical Shutdown circuitry. The contents of the register reflect the calculated temperature determined by the voltage on the TRIP_SET pin (see Section 5.1.2). The data format is shown in Table 6.5. Table 6.5 Critical / Thermal Shutdown Data Format TEMPERATURE (C) 0 1 63 64 65 127 BINARY 0000_0000b 0000_0001b 0011_1111b 0100_0000b 0100_0001b 0111_1111b HEX 00h 01h 3Fh 40h 41h 7Fh
6.4
Pushed Temperature Registers
Table 6.6 Pushed Temperature Register
ADDR 0Ch 0Dh
R/W R/W R/W
REGISTER Pushed Temperature 1 Pushed Temperature 2
B7 Sign Sign
B6 64 64
B5 32 32
B4 16 16
B3 8 8
B2 4 4
B1 2 2
B0 1 1
DEFAULT 00h 00h
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The Pushed Temperature Registers store user programmed temperature values that can be used by the look-up table to update the fan control algorithm. Data written in these registers is not compared against any limits and must match the data format shown in Table 6.3.
6.5
TRIP_SET Voltage Register
Table 6.7 TRIP_SET Voltage Register
ADDR
R/W
REGISTER TRIP_SET Voltage Register
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
10h
R/W
750.0
375.0
187.5
93.75
46.88
23.43
11.72
5.89
FFh
The TRIP_SET Voltage Register stores data that is measured on the TRIP_SET Voltage input. Each bit weight represents mV of resolution so that the final voltage can be determined by adding the weighting of the set bits together.
6.6
Ideality Factor Registers
Table 6.8 Ideality Factor Registers
ADDR
R/W
REGISTER External Diode 1 Ideality External Diode 2 Ideality **
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
11h
R/W
0
0
0
1
0
B2
B1
B0
12h
12h **
R/W
0
0
0
1
0
B2
B1
B0
12h
These registers store the ideality factors that are applied to the external diodes. The External Diode 3 channel will use the settings for the External Diode 2 channel. Beta Compensation and Resistance Error Correction automatically correct for most diode ideality errors, therefore it is not recommended that these settings be updated without consulting SMSC. Only the lower three bits can be written. Writing to any other bit will be ignored. The Ideality Factor Registers are software locked.
Table 6.9 Ideality Factor Look-Up Table SETTING 10h 11h 12h 13h 14h 15h
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Table 6.9 Ideality Factor Look-Up Table (continued) SETTING 16h 17h FACTOR 1.0133 1.0146
6.7
Beta Configuration Register
Table 6.10 Beta Configuration Register
ADDR
R/W
REGISTER External Diode 1 Beta Configuration External Diode 2 Beta Configuration **
B7
B6
B5
B4 AUT O1 AUT O2
B3
B2
B1
B0
DEFAULT
14h
RW
-
-
-
-
BETA1[2:0]
10h
15h **
R/W
-
-
-
-
BETA2[2:0]
10h
The Beta Configuration Register controls advanced temperature measurement features of the External Diode channels. If External Diode 1 is selected as the hardware shutdown measurement channel (see Section 5.1.1) then the External Diode 1 Beta register will be read only. If the internal diode is selected, then this register can be written normally. Likewise, if the External Diode 2 channel is selected (EMC2103-2 only) then this register can be written normally. Finally, if External Diode 2 is selected as the hardware shutdown measurement channel (EMC2103-2 only), then the External Diode 2 Beta Configuration Register will be read only. Writing to a read only register will have no affect. The data will be ignored. Bit 4 - AUTOx - Enables the Automatic Beta detection algorithm for the External Diode X channel. `0' - The Automatic Beta detection algorithm is disabled. The BETAx[3:0] bit settings will be used to control the beta compensation circuitry. `1' (default) - The Automatic Beta detection algorithm is enabled. The circuitry will automatically detect the transistor type and beta values and configure the BETAx[3:0] bits for optimal performance. Bits 2 - 0 - BETAx[2:0] - hold a value that corresponds to a range of betas that the Beta Compensation circuitry can compensate for. These three bits will always show the current beta setting used by the circuitry. If the AUTO bit is set (default), then these bits may be overwritten with every temperature conversion. If the AUTO bit is not set, then the value of these bits is used to drive the beta compensation circuitry. In this case, these bits should be set with a value corresponding to the lowest expected value of beta for the PNP transistor being used as a temperature sensing device. See Table 6.11 for supported beta ranges. A value of 111b indicates that the beta compensation circuitry is disabled. In this condition, the diode channels will function with default current levels and will not automatically adjust for beta variation. This mode is used when measuring a discrete 2N3904 transistor or AMD thermal diode. If the External Diode 3 channel is enabled, it will always use a beta setting of 111b. The Beta Configuration Registers are Software Locked.
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Table 6.11 Beta Compensation Look Up Table BETAX[2:0] 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 MINIMUM BETA < 0.08 < 0.111 < 0.176 < 0.29 < 0.48 < 0.9 < 2.33 Disabled
6.8
REC Configuration Register
Table 6.12 REC Configuration Register
ADDR 17h
R/W R/W
REGISTER REC Configuration
B7 -
B6 -
B5 -
B4 -
B3 -
B2 REC3
B1 REC2
B0 REC1
DEFAULT 07h
The REC Configuration Register determines whether Resistance Error Correction is used for each external diode channel. Bit 2 - REC3 (EMC2102-2 only)- Controls the Resistance Error Correction functionality of External Diode 3 (if enabled) `0' - the REC functionality for External Diode 3 is disabled `1' (default) - the REC functionality for External Diode 3 is enabled. Bit 1 - REC2 (EMC2103-2 only)- Controls the Resistance Error Correction functionality of External Diode 2. If External Diode 2 is selected as the hardware shutdown channel then this bit is read only and determined by the SHDN_SEL pin (see Section 5.1.1). `0' - the REC functionality for External Diode 2 is disabled `1' (default) - the REC functionality for External Diode 2 is enabled. Bit 0 - REC1 - Indicates the Resistance Error Correction functionality of External Diode 1. If External Diode 1 is selected as the hardware shutdown channel then this bit is read only and determined by the SHDN_SEL pin (see Section 5.1.1). `0' - the REC functionality for External Diode 1 is disabled `1' (default) - the REC functionality for External Diode 1 is enabled. The REC Configuration Register is software locked.
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6.9
Critical Temperature Limit Registers
Table 6.13 Limit Registers
ADDR 19h 1Ah 1Bh 1Dh
R/W R/W once R/W once R/W once R/W once
REGISTER External Diode 1 Tcrit Limit External Diode 2 Tcrit Limit External Diode 3 Tcrit Limit Internal Diode Tcrit Limit
B7 Sign Sign Sign Sign
B6 64 64 64 64
B5 32 32 32 32
B4 16 16 16 16
B3 8 8 8 8
B2 4 4 4 4
B1 2 2 2 2
B0 1 1 1 1
DEFAULT 64h (+100C) 64h (+100C) 64h (+100C) 64h (+100C)
The Critical Temperature Limit Registers store the Critical Temperature Limit. At power up, none of the respective channels are linked to the SYS_SHDN pin or the Hardware set Thermal/Critical Shutdown circuitry. Whenever one of the registers is updated, two things occur. First, the register is locked so that it cannot be updated again without a power on reset. Second, the respective temperature channel is linked to the SYS_SHDN pin and the Hardware set Thermal/Critical Shutdown Circuitry. At this point, if the measured temperature channel exceeds the Critical limit, the SYS_SHDN pin will be asserted, the appropriate bit set in the Tcrit Status Register, and the TCRIT bit in the Interrupt Status Register will be set.
6.10
Configuration Register
Table 6.14 Configuration Register
ADDR 20h
R/W R/W
REGISTER Configuration
B7 MASK -
B6 -
B5 -
B4
B3 SYS3
B2 SYS2
B1 SYS1
B0 APD
DEFAULT 00h
The Configuration Register controls the basic functionality of the EMC2103. The bits are described below. Bit 7 - MASK - Blocks the ALERT pin from being asserted. `0' (default) - The ALERT pin is unmasked. If any bit in either status register is set, the ALERT pin will be asserted (unless individually masked via the Mask Register) `1' - The ALERT pin is masked and will not be asserted. Bit 3 - SYS3 (EMC2103-2 only) - Enables the high temperature limit for the External Diode 3 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 5.1). `0' (default) - the External Diode 3 channel high limit will not be linked to the SYS_SHDN pin. If the temperature meets or exceeds the limit, the ALERT pin will be asserted normally. `1' - the External Diode 3 channel high limit will be linked to the SYS_SHDN pin. If the temperature meets or exceeds the limit then the SYS_SHDN pin will be asserted. The SYS_SHDN# pin will be released when the temperature drops below the high limit. The ALERT pin will be asserted normally. Bit 2 - SYS2 (EMC2103-2 only) - Enables the high temperature limit for the External Diode 2 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 5.1).
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`0' (default) - the External Diode 2 channel high limit will not be linked to the SYS_SHDN pin. If the temperature meets or exceeds the limit, the ALERT pin will be asserted normally. `1' - the External Diode 2 channel high limit will be linked to the SYS_SHDN pin. If the temperature meets or exceeds the limit then the SYS_SHDN pin will be asserted. The ALERT pin will be asserted normally. Bit 1 - SYS1 - Enables the high temperature limit for the External Diode 1 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 5.1). `0' (default) - The External Diode 1 channel high limit will not be linked to the SYS_SHDN pin. If the temperature meets or exceeds the limit, the ALERT pin will be asserted normally. `1' - The External Diode 1 channel high limit will be linked to the SYS_SHDN pin. If the temperature meets or exceeds the limit then the SYS_SHDN pin will be asserted. The ALERT pin will be asserted normally. Bit 0 - APD (EMC2103-2 only) - This bit enables the Anti-parallel diode functionality on the External Diode 3 pins (DP3 and DN3). `0' (default) - The Anti-parallel diode functionality is disabled. The External Diode 2 channel can be configured for any type of diode `1' - The Anti-parallel diode functionality is enabled. Both the External Diode 2 and 3 channels are configured to support a diode or diode connected transistor (such as a 2N3904). APPLICATION NOTE: When the APD diode is enabled, there will be a delay of a full temperature update before any comparisons and functionality associated with the External Diode 3 channel will be implemented. This includes the SYS3 bit operation, limit comparisons, and look up table comparisons. The Configuration Register is software locked.
6.11
Configuration 2 Register
Table 6.15 Configuration 2 Register
ADDR 21h
R/W R/W
REGISTER Config 2
B7 -
B6 DIS_D YN
B5 DIS_ TO
B4 DIS_ AVG
B3
B2
B1
B0
DEFAULT 0Eh
QUEUE[1:0]
CONV[1:0]
The Configuration 2 Register controls conversion rate of the temperature monitoring as well as the fault queue. Bit 6 - DIS_DYN - Disables the Dynamic Averaging Feature. `0' (default) - The Dynamic Averaging function is enabled. The conversion time for all temperature channels is scaled based on the chosen conversion rate to maximize accuracy and immunity to random temperature measurement variation. `1' - The Dynamic Averaging function is disabled. The conversion time for all temperature channels is fixed regardless of the chosen conversion rate. Bit 5 - DIS_TO - Disables the SMBus time out function. `0' (default) - The SMBus time out function is enabled. `1' - The SMBus time out function is disabled allowing the device to be fully I2C compliant. Bit 4 - DIS_AVG - Disables digital averaging of the External Diode channels. `0' (default) - The External Diode channels have digital averaging enabled. The temperature data is the average of the previous four measurements.
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`1' - The External Diode channels have digital averaging disabled. The temperature data is the last measured data. Bits 3-2 - QUEUE[1:0] - Determines the number of consecutive out of limit conditions that are necessary to trigger an interrupt. Each measurement channel has a separate fault queue associated with the high limit, low limit, and diode fault condition. APPLICATION NOTE: If the fault queue for any channel is currently active (i.e. an out of limit condition has been detected and caused the fault queue to increment) then changing the settings will not take effect until the fault queue is zeroed. This occurs by the ALERT pin asserting or the out of limit condition being removed.
Table 6.16 Fault Queue QUEUE[1:0] 1 0 0 1 1 0 0 1 0 1 NUMBER OF CONSECUTIVE OUT OF LIMIT CONDITIONS 1 (disabled) 2 3 4 (default)
Bit 1 - 0 - CONV[1:0] - determines the conversion rate of the temperature monitoring. This conversion rate does not affect the fan driver. The supply current from VDD_3V is nominally dependent upon the conversion rate and the average current will increase as the conversion rate increases.
Table 6.17 Conversion Rate CONV[1:0] 1 0 0 1 1 0 0 1 0 1 The Configuration 2 Register is software locked. CONVERSION RATE 1 / sec 2 / sec 4 / sec (default) Continuous
6.12
Interrupt Status Register
Table 6.18 Interrupt Status Register
ADDR
R/W
REGISTER Interrupt Status Register
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
23h
R-C
-
TCRIT
GPIO
FAN
HIGH
LOW
FAULT
00h
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The Interrupt Status Register reports the operating condition of the EMC2103. If any of the bits are set to a logic `1' (other than HWS) then the ALERT pin will be asserted low if the corresponding channel is enabled. Reading from the status register clears all status bits if the error conditions is removed. If there are no set status bits, then the ALERT pin will be released. The bits that cause the ALERT pin to be asserted can be masked based on the channel they are associated with unless stated otherwise. Bit 5 - TCRIT - This bit is set to `1' if any bit in the Tcrit Status Register is set. This bit is automatically cleared when the Tcrit Status Register is read and the bits are cleared. Bit 4 - GPIO (EMC2103-2 only) - This bit is set to `1' if any bit in the GPIO Status Register is set. This bit is automatically cleared when the GPIO Status Register is read. Bit 3 - FAN - This bit is set to `1' if any bit in the Fan Status Register is set. This bit is automatically cleared when the Fan Status Register is read and the bits are cleared. Bit 2 - HIGH - This bit is set to `1' if any bit in the High Status Register is set. This bit is automatically cleared when the High Status Register is read and the bits are cleared. Bit 1- LOW - This bit is set to `1' if any bit in the Low Status Register is set. This bit is automatically cleared when the Low Status Register is read and the bits are cleared. Bit 0 - FAULT - This bit is set to `1' if any bit in the Diode Fault Register is set. This bit is automatically cleared when the Diode Fault Register is read and the bits are cleared.
6.13
Error Status Registers
Table 6.19 Error Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3 EXT3 _TCR IT
B2 EXT2 _TCR IT EXT2 _HI EXT2 _LO EXT2 _FLT
B1 EXT1 _TCR IT EXT1 _HI EXT1 _LO EXT1 _FLT
B0 INT_T CRIT INT_ HI INT_L O -
DEFAULT
1Fh
R-C
Tcrit Status
HWS
00h
24h 25h 26h
R-C R-C R-C
High Status Low Status Diode Fault
-
-
--
-
EXT3 _HI EXT3 _LO EXT3 _FLT
00h 00h 00h
The Error Status Registers report the specific error condition for all measurement channels with limits. If any bit is set in the High, Low, or Diode Fault Status register, the corresponding High, Low, or Fault bit is set in the Interrupt Status Register. Reading the Interrupt Status Register does not clear the Error Status bit. Reading from any Error Status Register that has bits set will clear the register and the corresponding bit in the Interrupt Status Register if the error condition has been removed. If the error condition is persistent, reading the Error Status Registers will have no affect.
6.13.1
Tcrit Status Register
The Tcrit Status Register stores the event that caused the SYS_SHDN pin to be asserted. Each of the temperature channels must be associated with the SYS_SHDN pin before they can be set (see Section 6.9). Once the SYS_SHDN# pin is asserted, it will be released when the temperature drops below the threshold level however the individual status bit will not be cleared until read.
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6.14
Fan Status Register
Table 6.20 Fan Status Register
ADDR 27h
R/W R-C
REGISTER Fan Status Register
B7 WATCH
B6 -
B5 DRIVE _FAIL
B4 -
B3 -
B2 -
B1 FAN_ SPIN
B0 FAN_ STALL
DEFAULT 00h
The Fan Status Register contains the status bits associated with each fan driver. Bit 7 - WATCH - This bit is asserted `1' if the host has not programmed the fan driver within four (4) seconds after power up (i.e. the Watchdog Timer has timed out. See Section 5.9. Bit 5 - DRIVE_FAIL - Indicates that the RPM based Fan Speed Control Algorithm cannot drive the Fan to the desired target setting at maximum drive. This bit can be masked from asserting the ALERT pin. `0' - The RPM based Fan Speed Control Algorithm can drive Fan to the desired target setting. `1' - The RPM based Fan Speed Control Algorithm cannot drive Fan to the desired target setting at maximum drive. Bit 1- FAN_SPIN - This bit is asserted `1' if the Spin up Routine for the Fan cannot detect a valid tachometer reading within its maximum time window. This bit can be masked from asserting the ALERT pin. Bit 0 - FAN_STALL - This bit is asserted `1' if the tachometer measurement on the Fan detects a stalled fan. This bit can be masked from asserting the ALERT pin.
6.15
Interrupt Enable Register
Table 6.21 Interrupt Enable Register
ADDR 28
R/W R/W
REGISTER Interrupt Enable
B7 -
B6 -
B5 -
B4 -
B3 EXT3_I NT_EN
B2 EXT2_I NT_EN
B1 EXT1_I NT_EN
B0 INT_IN T_EN
DEFAULT 00h
The Interrupt Enable Register controls the masking for each temperature channel. When a channel is masked, it will not cause the ALERT pin to be asserted when an error condition is detected. Bit 3 - EXT3_INT_EN (EMC2103-2 only) - Allows the External Diode 3 to assert the ALERT pin. `0' (default) - The ALERT pin will not be asserted for any error condition associated with External Diode 3 channel. `1' - The ALERT pin will be asserted for an error condition associated with External Diode 3 channel. Bit 2 - EXT2_INT_EN (EMC2103-2 only) - Allows the External Diode 2 to assert the ALERT pin. `0' (default) - The ALERT pin will not be asserted for any error condition associated with External Diode 2 channel. `1' - The ALERT pin will be asserted for an error condition associated with External Diode 2 channel. Bit 1 - EXT1_INT_EN - Allows the External Diode 1 to assert the ALERT pin. `0' (default) - The ALERT pin will not be asserted for any error condition associated with External Diode 1 channel.
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`1' - The ALERT pin will be asserted for an error condition associated with External Diode 1 channel. Bit 0 - INT_INT_EN - Allows the Internal Diode to assert the ALERT pin. `0' (default) - The ALERT pin will not be asserted for any error condition associated with the Internal Diode. `1' - The ALERT pin will be asserted for an error condition associated with the Internal Diode.
6.16
Fan Interrupt Enable Register
Table 6.22 Fan Interrupt Enable Register
ADDR
R/W
REGISTER Fan Interrupt Enable
B7
B6
B5
B4
B3
B2
B1 SPIN_ INT_EN
B0 STALL_ INT_EN
DEFAULT
29
R/W
-
-
-
-
-
-
00h
The Fan Interrupt Enable Register controls the masking for errors generated by the Fan Driver. When a channel is masked, it will not cause the ALERT pin to be asserted when an error condition is detected. Bit 1 - SPIN_INT_EN - Allows the FAN_SPIN bit to assert the ALERT pin. `0' (default) - the FAN_SPIN bit will not assert the ALERT pin though it will still update the Status Register normally. `1' - the FAN_SPIN bit will assert the ALERT pin. Bit 0 - STALL_INT_EN - Allows the FAN_STALL bit or DRIVE_FAIL bit to assert the ALERT pin. `0' (default) - the FAN_STALL bit or DRIVE_FAIL bit will not assert the ALERT pin though will still update the Status Register normally. `1' - the FAN_STALL bit will assert the ALERT pin.
6.17
PWM Configuration Register
Table 6.23 PWM Configuration Register
ADDR 2Ah
R/W R/W
REGISTER PWM Config
B7 -
B6 -
B5 -
B4 PWM_ OT
B3 -
B2 -
B1 -
B0 POLA RITY
DEFAULT 00h
The PWM Config Register controls the output type and polarity of the PWM output. Bit 4 - PWM_OT - Determines the output type for the PWM pin. `0' (default) - The PWM pin is configured as an open drain output. `1' - The PWM pin is configured as a push-pull output.
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Bit 0 - POLARITY1 - Determines the polarity of PWM1 (if enabled). `0' (default) - the Polarity of the PWM driver is normal. A drive setting of 00h will cause the output to be set at 0% duty cycle and a drive setting of FFh will cause the output to be set at 100% duty cycle. `1' - The Polarity of the PWM driver is inverted. A drive setting of 00h will cause the output to be set at 100% duty cycle and a drive setting of FFh will cause the output to be set at 0% duty cycle.
6.18
PWM Base Frequency Register
Table 6.24 PWM Base Frequency Register
ADDR 2Bh
R/W R/W
REGISTER PWM Base Frequency
B7 -
B6 -
B5 -
B4 -
B3 -
B2 -
B1
B0
DEFAULT 03h
PWM_BASE[1:0 ]
The PWM Base Frequency Register controls base frequency of the PWM output. Bits 1-0 - PWM_BASE[1:0] - Determines the base frequency of the PWM driver (PWM).
Table 6.25 PWM_BASEx[1:0] it Decode PWM_BASE[1:0] 1 0 0 1 1 0 0 1 0 1 BASE FREQUENCY 26.00kHz 19.531kHz 4,882Hz 2,441Hz (default)
6.19
Limit Registers
Table 6.26 Limit Registers
ADDR 30h 31h ** 32h ** 34h 38h
R/W R/W R/W R/W R/W R/W
REGISTER External Diode 1 High Limit External Diode 2 High Limit ** External Diode 3 High Limit ** Internal Diode High Limit External Diode 1 Low Limit
B7 Sign Sign Sign Sign Sign
B6 64 64 64 64 64
B5 32 32 32 32 32
B4 16 16 16 16 16
B3 8 8 8 8 8
B2 4 4 4 4 4
B1 2 2 2 2 2
B0 1 1 1 1 1
DEFAULT 55h (+85C) 55h (+85C) 55h (+85C) 55h (+85C) 00h (0C)
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Table 6.26 Limit Registers (continued) ADDR 39h ** 3Ah ** 3Ch R/W R/W R/W R/W REGISTER External Diode 2 Low Limit ** External Diode 3 Low Limit ** Internal Diode Low Limit B7 Sign Sign Sign B6 64 64 64 B5 32 32 32 B4 16 16 16 B3 8 8 8 B2 4 4 4 B1 2 2 2 B0 1 1 1 DEFAULT 00h (0C) 00h (0C) 00h (0C)
The EMC2103 contains high limits for all temperature channels. If any measurement meets or exceeds the high limit then the appropriate status bit is set and the ALERT pin is asserted (if enabled). Additionally, the EMC2103 contains low limits for all temperature channels. If the temperature channel drops below the low limit, then the appropriate status bit is set and the ALERT pin is asserted (if enabled). All Limit Registers are Software Locked.
6.20
Fan Setting Registers
Table 6.27 Fan Driver Setting Register
ADDR 40h
R/W R/W
REGISTER Fan Setting
B7 128
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 00h
The Fan Setting Register always displays the current setting of the Fan Driver. Reading from the register will report the current fan speed setting of the fan driver regardless of the operating mode. Therefore it is possible that reading from this register will not report data that was previously written into this register. While the RPM based Fan Speed Control Algorithm or the Look Up Table are active (or both), then the register is read only. Writing to the register will have no affect and the data will not be stored. If both the RPM based Fan Control Algorithm and the Look Up Table are disabled, then the register will be set with the previous value that was used. The register is read / write and writing to this register will affect the fan speed. The contents of the register represent the weighting of each bit in determining the final duty cycle. The output drive for a PWM output is given by Equation [1].
VALUE Drive = -------------------- x 100% 255
[1]
6.21
PWM Divide Register
Table 6.28 PWM Divide Register
ADDR 41h
R/W R/W
REGISTER PWM Divide
B7 128
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 01h
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The PWM Divide Register determines the final frequency of the PWM driver. The driver base frequency is divided by the value of the PWM Divide Register to determine the final frequency. The duty cycle settings are not affected by these settings, only the final frequency of the PWM driver. A value of 00h will be decoded as 01h. The final PWM frequency is derived as the base frequency divided by the value of this register as shown in Equation [2]. PWM base freqeuncy f PWM = -------------------------------------------------------------PWM Divide Setting [2]
6.22
Fan Configuration 1 Register
Table 6.29 Fan Configuration 1 Register
ADDR 42h
R/W R/W
REGISTER Fan Configuration 1
B7 EN_ ALGO
B6
B5
B4
B3
B2
B1
B0
DEFAULT 2Bh
RANGE[1:0]
EDGES[1:0]
UPDATE[2:0]
The Fan Configuration 1 Register controls the general operation of the RPM based Fan Speed Control Algorithm used on the PWM pin. Bit 7 - EN_ALGO - enables the RPM based Fan Speed Control Algorithm. Based on the setting of the RPM / PWM bit, this bit is automatically set or cleared when the LUT_LOCK bit is set (see Section 6.32). `0' - (default) the control circuitry is disabled and the fan driver output is determined by the Fan Driver Setting Register. `1' - the control circuitry is enabled and the Fan Driver output will be automatically updated to maintain the programmed fan speed as indicated by the TACH Target Register. Bits 6- 5 - RANGE[1:0] - Adjusts the range of reported and programmed tachometer reading values. The RANGE bits determine the weighting of all TACH values (including the Valid TACH Count, TACH Target, and TACH reading) as shown in Table 6.30.
Table 6.30 Range Decode RANGE[1:0] 1 0 0 1 1 0 0 1 0 1 REPORTED MINIMUM RPM 500 1000 (default) 2000 4000 TACH COUNT MULTIPLIER 1 2 4 8
Bits 4-3 - EDGES[1:0] - determines the minimum number of edges that must be detected on the TACH signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan). For more accurate tachometer measurement, the minimum number of edges measured may be increased. Increasing the number of edges measured with respect to the number of poles of the fan will cause the TACH Reading registers to indicate a fan speed that is higher or lower than the actual speed. In order for the FSC Algorithm to operate correctly, the TACH Target must be updated by the user to accommodate this shift. The Effective Tach Multiplier shown in Table 6.31 is used as a direct multiplier
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term that is applied to the Actual RPM to achieve the Reported RPM. It should only be applied if the number of edges measured does not match the number of edges expected based on the number of poles of the fan (which is fixed for any given fan). Contact SMSC for recommended settings when using fans with more or less than 2 poles.
Table 6.31 Minimum Edges for Fan Rotation EDGES[1:0] 1 0 0 1 1 0 1 0 1 0 MINIMUM TACH EDGES 3 5 7 9 NUMBER OF FAN POLES 1 pole 2 poles (default) 3 poles 4 poles EFFECTIVE TACH MULTIPLIER (BASED ON 2 POLE FANS) 0.5 1 1.5 2
Bit 2-0 - UPDATE - determines the base time between fan driver updates. The Update Time, along with the Fan Step Register, is used to control the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan speed changes. The Update Time is set as shown in Table 6.32.
Table 6.32 Update Time UPDATE[2:0] 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 UPDATE TIME 100ms 200ms 300ms 400ms (default) 500ms 800ms 1200ms 1600ms
6.23
Fan Configuration 2 Register
Table 6.33 Fan Configuration 2 Register
ADDR
R/W
REGISTER Fan Configuration 2
B7
B6 EN_ RRC
B5 GLITCH _EN
B4
B3
B2
B1
B0
DEFAULT
43h
R/W
-
DER_OPT [1:0]
ERR_RNG:0]
-
38h
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The Fan Configuration 2 Register controls the tachometer measurement and advanced features of the RPM based Fan Speed Control Algorithm. Bit 6 - EN_RRC - Enables ramp rate control when the fan driver is operated in the Direct Setting mode or the Direct Setting with LUT mode. `0' (default) - Ramp rate control is disabled. When the fan driver is operating in Direct Setting mode or Direct Setting with LUT mode, the PWM setting will instantly transition to the next programmed setting. `1' - Ramp rate control is enabled. When the fan driver is operating in Direct Setting mode or Direct Setting with LUT mode, the PWM setting will follow the ramp rate controls as determined by the Fan Step and Update Time settings. The maximum PWM step is capped at the Fan Step setting and is updated based on the Update Time as given by Table 6.32. Bit 5 - GLITCH_EN - Disables the low pass glitch filter that removes high frequency noise injected on the TACH pin. `0' - The glitch filter is disabled. `1' (default) - The glitch filter is enabled. Bits 4 - 3 - DER_OPT[1:0] - Control some of the advanced options that affect the derivative portion of the RPM based Fan Speed Control Algorithm as shown in Table 6.34. Note that the default derivative options disable the ramp rate control maximum step settings. To take advantage of the full ramp rate control, limit derivative options to the disabled or basic derivative settings.
Table 6.34 Derivative Options DER_OPT[1:0] 1 0 0 0 OPERATION No derivative terms used Basic derivative. The derivative of the error from the current drive setting and the target is added to the iterative Fan Drive setting (in addition to proportional and integral terms) Step derivative. The derivative of the error from the current drive setting and the target is added to the iterative Fan Drive setting and is not capped by the maximum Fan Step Register setting. Both the basic derivative and the step derivative are used effectively causing the derivative term to have double the effect of the derivative term (default).
0
1
1
0
1
1
Bit 2 - 1 - ERR_RNG[1:0] - Control some of the advanced options that affect the error window. When the measured fan speed is within the programmed error window around the target speed, then the fan drive setting is not updated. The algorithm will continue to monitor the fan speed and calculate necessary drive setting changes based on the error, however these changes are ignored.
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Table 6.35 Error Range Options ERR_RNG[1:0] 1 0 0 1 1 0 0 1 0 1 OPERATION 0 RPM (default) 50 RPM 100 RPM 200 RPM
The Fan Configuration 2 Register is Software Locked.
6.24
Gain Register
Table 6.36 Gain Register
ADDR 45h
R/W R/W
REGISTER Gain Register
B7 -
B6 -
B5
B4
B3
B2
B1
B0
DEFAULT 2Ah
GAIND[1:0]
GAINI[1:0]
GAINP[1:0]
The Gain Register stores the gain terms used by the proportional and integral portions of the RPM based Fan Speed Control Algorithm. These terms will affect the FSC closed loop acquisition, overshoot, and settling as would be expected in a classic PID system.
Table 6.37 Gain Decode GAIND OR GAINP OR GAINI [1:0] 1 0 0 1 1 0 0 1 0 1 RESPECTIVE GAIN FACTOR 1x 2x 4x (default) 8x
6.25
Fan Spin Up Configuration Register
Table 6.38 Fan Spin Up Configuration Register
ADDR 46h
R/W R/W
REGISTER Fan Spin Up Configuration
B7
B6
B5 NOK ICK
B4
B3
B2
B1
B0
DEFAULT 19h
DRIVE_FAIL _CNT [1:0]
SPIN_LVL[2:0]
SPINUP_TIME [1:0]
The Fan Spin Up Configuration Register controls the settings of Spin Up Routine.
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Bit 7 - 6 - DRIVE_FAIL_CNT[1:0] - Determines how many update cycles are used for the Drive Fail detection function as shown in Table 6.39. This circuitry determines whether the fan can be driven to the desired tach target.
Table 6.39 DRIVE_FAIL_CNT[1:0] Bit Decode DRIVE_FAIL_CNT[1:0] 1 0 0 1 1 0 0 1 0 1 NUMBER OF UPDATE PERIODS Disabled - the Drive Fail detection circuitry is disabled 16 - the Drive Fail detection circuitry will count for 16 update periods 32 - the Drive Fail detection circuitry will count for 32 update periods 64 - the Drive Fail detection circuitry will count for 64 update periods
Bit 5 - NOKICK - Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before driving it at the programmed level. `0' (default) - The Spin Up Routine will drive the PWM to 100% for 1/4 of the programmed spin up time before reverting to the programmed spin level. `1' - The Spin Up Routine will not drive the PWM to 100%. It will set the drive at the programmed spin level for the entire duration of the programmed spin up time. Bits 4 - 2 - SPIN_LVL[2:0] - Determines the final drive level that is used by the Spin Up Routine as shown in Table 6.40.
Table 6.40 Spin Level SPIN_LVL[2:0] 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 SPIN UP DRIVE LEVEL 30% 35% 40% 45% 50% 55% 60% (default) 65%
Bit 1 -0 - SPINUP_TIME[1:0] - determines the maximum Spin Time that the Spin Up Routine will run for (see Section 5.7). If a valid tachometer measurement is not detected before the Spin Time has elapsed, then an interrupt will be generated. When the RPM based Fan Speed Control Algorithm is active, the fan driver will attempt to re-start the fan immediately after the end of the last spin up attempt. The Spin Time is set as shown in Table 6.41.
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Table 6.41 Spin Time SPINUP_TIME[1:0] 1 0 0 1 1 0 0 1 0 1 TOTAL SPIN UP TIME 250 ms 500 ms (default) 1 sec 2 sec
The Fan Spin Up Configuration Register is software locked.
6.26
Fan Step Register
Table 6.42 Fan Step Register
ADDR 47h
R/W R/W
REGISTER Fan Max Step
B7 -
B6 -
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 10h
The Fan Step Register, along with the Update Time, control the ramp rate of the fan driver response. The value of the registers represents the maximum step size each fan driver will take between update times (see Section 6.22). All modes of operation have the options to use the Fan Step Register (and update times) for ramp rate control based on the Fan Configuration 2 Register settings. The Fan Speed Control Algorithm will always use the Fan Step Register settings (but see application note below). APPLICATION NOTE: If the Fan Speed Control Algorithm is used, the default settings in the Fan Configuration 2 Register will cause the maximum fan step settings to be ignored. The Fan Step Register is software locked.
6.27
Fan Minimum Drive Register
Table 6.43 Minimum Fan Drive Register
ADDR 48h
R/W R/W
REGISTER Fan Minimum Drive
B7 128
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 66h (40%)
The Fan Minimum Drive Register stores the minimum drive setting for the RPM based Fan Speed Control Algorithm. This register is not used if the FSC is not active. The RPM based Fan Speed Control Algorithm will not drive the fan at a level lower than the minimum drive unless the target TACH Target is set at FFh (see Section 6.30) During normal operation, if the fan stops for any reason (including low drive), the RPM based Fan Speed Control Algorithm will attempt to restart the fan. Setting the Fan Minimum Drive Registers to a
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setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control circuitry attempts to drive it at a level that cannot support fan operation. The Fan Minimum Drive Register is software locked.
6.28
Valid TACH Count Register
Table 6.44 Valid TACH Count Register
ADDR 49h
R/W R/W
REGISTER Valid TACH Count
B7 4096
B6 2048
B5 1024
B4 512
B3 256
B2 128
B1 64
B0 32
DEFAULT F5h
The Valid TACH Count Register store the maximum TACH Reading Register value to indicate that the the fan is spinning properly. The value is referenced at the end of the Spin Up Routine to determine if the fan has started operating and decide if the device needs to retry. See Equation [4] for translating the count to an RPM. If the TACH Reading Register value exceeds the Valid TACH Count Register (indicating that the Fan RPM is below the threshold set by this count), then a stalled fan is detected. In this condition, the algorithm will automatically begin its Spin Up Routine. APPLICATION NOTE: The automatic invoking of the Spin Up Routine only applies if the Fan Speed Control Algorithm is used. If the FSC is disabled, then the device will only invoke the Spin Up Routine when the PWM setting changes from 00h. If a TACH Target setting is set above the Valid TACH Count setting, then that setting will be ignored and the algorithm will use the current fan drive setting. The Valid TACH Count Register is software locked.
6.29
Fan Drive Fail Band Registers
Table 6.45 Fan Drive Fail Band Registers
ADDR
R/W
REGISTER Fan Drive Fail Band Low Byte Fan Drive Fail Band High Byte
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
4Ah
R/W
16
8
4
2
1
-
-
-
00h
4Bh
R/W
4096
2048
1024
512
256
128
64
32
00h
The Fan Drive Fail Band Registers store the number of tach counts used by the Fan Drive Fail detection circuitry. This circuitry is activated when the fan drive setting high byte is at FFh. When it is enabled, the actual measured fan speed is compared against the target fan speed. This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually capable of reaching. If the measured fan speed does not exceed the target fan speed minus the Fan Drive Fail Band Register settings for a period of time longer than set by the DRIVE_FAIL_CNTx[1:0] bits then the DRIVE_FAIL status bit will be set and an interrupt generated.
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6.30
TACH Target Register
Table 6.46 TACH Target Register
ADDR
R/W
REGISTER Fan TACH Target Low Byte TACH Target
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
4Ch 4Dh
R/W R/W
16 4096
8 2048
4 1024
2 512
1 256
128
64
32
F8h FFh
The TACH Target Register holds the target tachometer value that is maintained by the RPM based Fan Speed Control Algorithm. The value in the TACH Target Register will always reflect the current TACH Target value. If the Look Up Table is active and configured to operate in RPM Mode, then this register will be read only. Writing to this register will have no affect and the data will not be stored. If the algorithm is enabled then setting the TACH Target Register to FFh will disable the fan driver (set the PWM duty cycle to 0%). Setting the TACH Target to any other value (from a setting of FFh) will cause the algorithm to invoke the Spin Up Routine after which it will function normally.
6.31
TACH Reading Register
Table 6.47 TACH Reading Register
ADDR 4Eh 4Fh
R/W R R
REGISTER Fan TACH Fan TACH Low Byte
B7 4096 16
B6 2048 8
B5 1024 4
B4 512 2
B3 256 1
B2 128 -
B1 64 -
B0 32 -
DEFAULT FFh F8h
The TACH Reading Register contents describe the current tachometer reading for the fan. By default, the data represents the fan speed as the number of 32kHz clock periods that occur for a single revolution of the fan. Equation [3] shows the detailed conversion from TACH measurement (COUNT) to RPM while Equation [4] shows the simplified translation of TACH Reading Register count to RPM assuming a 2-pole fan, measuring 5 edges, with a frequency of 32.768kHz. See Appendix B for a table enumerating the RPM to TACH conversion for the default settings.
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where: 1(n - 1) RPM = ------------------- x --------------------------------- x 1,966,080 ( poles ) 1COUNT x ---m poles = number of poles of the fan (typically 2) n = number of edges measured (typically 5) m = the multiplier defined by the RANGE bits [4] COUNT = TACH Reading Register value (in decimal) [3]
3,932,160 x m RPM = ------------------------------------COUNT
6.32
Look Up Table Configuration Register
Table 6.48 Look Up Table Configuration Register
ADDR 50h
R/W R/W
REGISTER LUT Configuration
B7 USE_D TS_F1
B6 USE_D TS_F2
B5 LUT_L OCK
B4 RPM / PWM
B3 -
B2 TEMP3 _CFG
B1 -
B0 TEMP4 _CFG
DEFAULT 00h
The Look Up Table Configuration Register controls the setup information for the temperature to fan drive look up table. Bit 7 - USE_DTS_F1 - This bit determines whether the Pushed Temperature 1 Register is using DTS data. `0' (default) - The Pushed Temperature 1 Register is not using DTS data. The contents of the Pushed Temperature 1 registers is standard temperature data. `1' - The Pushed Temperature 1 Register is loaded with DTS data. The contents of this register is automatically subtracted from a fixed value of 100C before being compared to the Look Up Table threshold levels. Bit 6 - USE_DTS_F2 - This bit determines whether the Pushed Temperature 2 Register is using DTS data. `0' (default) - The Pushed Temperature 2 Register is not using DTS data. The contents of this register is standard 2's complement temperature data. `1' - The Pushed Temperature 2 Register is loaded with DTS data. The contents of this register is automatically subtracted from a fixed value of 100C before being compared to the Look Up Table threshold levels. Bit 5 - LUT_LOCK - This bit locks updating the Look Up Table entries and determines whether the look up table is being used. `0' (default) - The Look Up Table entries can be updated normally. The Look Up Table will not be used while the Look Up Table entries are unlocked. During this condition, the PWM output will not change states regardless of temperature or tachometer variation. `1' - The Look Up Table entries are locked and cannot be updated. The Look Up Table is fully active and will be used based on the loaded values. The PWM output will be updated depending on the temperature and / or TACH variations. APPLICATION NOTE: When the LUT_LOCK bit is set at a logic `0', the PWM drive setting will be set at whatever value was last used by the RPM based Fan Speed Control Algorithm or the Look Up Table.
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Bit 4 - RPM / PWM - This bit selects the data format for the LUT drive settings. `0' (default) - The Look Up Table drive settings are RPM TACH count values for use by the RPM based Fan Speed Control Algorithm. The Look Up Table drive settings should be loaded highest value to lowest value (to coincide with the inversion between TACH counts and actual RPM). `1' - The Look Up Table drive settings are PWM duty cycle values and are used directly. The drive settings should be loaded lowest value to highest value. Bit 2 - TEMP3_CFG - Determine the temperature channel that is used for the Temperature 3 inputs to the Look Up Table. If the External Diode 3 channel is not enabled, then the Temperature 3 inputs are not used by the Look Up Table. `0' (default) - The External Diode 3 channel is used by the Fan Look Up Table (if enabled). `1' - The data written into the Pushed Temperature 1 Register is used by the Fan Look Up Table. Bit 0 - TEMP4_CFG - Determine the temperature channel that is used for the Temperature 4 inputs to the Look Up Table. `0' (default) - The Internal channel is used by the Fan Look Up Table. `1' - The data written into the Pushed Temperature 2 Register is used by the Fan Look Up Table.
6.33
Look Up Table Registers
Table 6.49 Look Up Table Registers RPM / PWM `0' `1' X
ADDR 51h
R/W R/W
REGISTER LUT Drive Setting 1 LUT Ext Diode 1 Setting 1 LUT Ext Diode 2 Setting 1 LUT Temp 3 Setting 1 LUT Temp 4 Setting 1 ... LUT Drive Setting 8 LUT Ext Diode 1 Setting 8 LUT Ext Diode 2 Setting 8 LUT Temp 3 Setting 8
B7 4096 128 -
B6 2048 64 64
B5 1024 32 32
B4 512 16 16
B3 256 8 8
B2 128 4 4
B1 64 2 2
B0 32
DEFAULT FBh
1 1 7Fh (127C) 7Fh (127C) 7Fh (127C) 7Fh (127C) ... 92h
52h
R/W
53h
R/W
X
-
64
32
16
8
4
2
1
54h 55h ... 74h
R/W R/W ... R/W
X X ... `0' `1' X
... 4096 128 -
64 64 ... 2048 64 64
32 32 ... 1024 32 32
16 16 ... 512 16 16
8 8 ... 256 8 8
4 4 ... 128 4 4
2 2 ... 64 2 2
1 1 ... 32 1 1
75h
R/W
7Fh (127C) 7Fh (127C) 7Fh (127C)
76h
R/W
X
-
64
32
16
8
4
2
1
77h
R/W
X
-
64
32
16
8
4
2
1
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Table 6.49 Look Up Table Registers (continued) RPM / PWM X X
ADDR 78h 79h
R/W R/W R/W
REGISTER LUT Temp 4 Setting 8 LUT Temp Hysteresis
B7 -
B6 64 -
B5 32 -
B4 16 16
B3 8 8
B2 4 4
B1 2 2
B0 1 1
DEFAULT 7Fh (127C) 0Ah
The Look Up Table Registers hold the 40 entries of the Look Up Table that controls the drive of the PWM. As the temperature channels are updated, the measured value for each channel is compared against the respective entries in the Look Up Table and the associated drive setting is loaded into an internal shadow register and stored. The bit weighting for temperature inputs represents C and is compared against the measured data. Note that the LUT entry does not include a sign bit. The Look Up Table does not support negative temperature values and the MSBit should not be set for a temperature input. Each temperature channel threshold shares the same hysteresis value. When the measured temperature for any of the channels meets or exceeds the programmed threshold, the drive setting associated with that threshold is used. The temperature must drop below the threshold minus the hysteresis value before the drive setting will be set to the previous value. If the RPM based Fan Speed Control Algorithm is used, the TACH Target is updated after every conversion. It is always set to the minimum TACH Target that is stored by the Look Up Table. The PWM duty cycle is updated based on the RPM based Fan Speed Control Algorithm configuration settings. If the RPM based Fan Speed Control Algorithm is not used, then the PWM duty cycle is updated after every conversion. It is set to the maximum duty cycle that is stored by the Look Up Table.
6.34
GPIO Direction Register (EMC2103-2 Only)
Table 6.50 GPIO Direction Register
ADDR E1h
R/W R/W
REGISTER GPIO Direction 1 -
B7 -
B6
B5
B4
B3
B2
B1 GPIO 2_DIR
B0 GPIO 1_DIR
DEFAULT 00h
The GPIO Direction Register controls the direction of GPIOs 1 and 2. Bit 1 - GPIO2_DIR - Determines the direction of GPIO2. `0' (default) - GPIO2 is configured as an input. `1' - GPIO1 is configured as an output. Bit 0 - GPIO2_DIR - Determines the direction of GPIO1. `0' (default) - GPIO1 is configured as an input. `1' - GPIO1 is configured as an output.
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6.35
GPIO Output Configuration Register (EMC2103-2 Only)
Table 6.51 GPIO Output Configuration Register
ADDR
R/W
REGISTER GPIO Output Config
B7
B6
B5
B4
B3
B2
B1 GPIO 2_OT
B0 GPIO 1_OT
DEFAULT
E2
R/W
-
00h
The GPIO Output Configuration Register controls the output pin type of each GPIO pin. Bit 1 - GPIO2_OT - Determines the output type for GPIO2. `0' (default) - GPIO2 is configured as an open drain output (if enabled as an output). `1' - GPIO2 is configured as a push-pull output (if enabled as an output). Bit 0 - GPIO1_OT - Determines the output type for GPIO1. `0' (default) - GPIO1 is configured as an open drain output (if enabled as an output). `1' - GPIO1 is configured as a push-pull output (if enabled as an output).
6.36
GPIO Input Register (EMC2103-2 Only)
Table 6.52 GPIO Input Register
ADDR E3h
R/W R
REGISTER GPIO Input
B7 -
B6 -
B5
B4
B3
B2
B1 GPIO 2_IN
B0 GPIO 1_IN
DEFAULT 00h
The GPIO Input Register indicates the state of the corresponding GPIO pin. When a GPIO is configured as an input, any change of state will assert the ALERT# pin (unless GPIO interrupts are masked, see Section 6.15). Bit 1 - GPIO2_IN - Indicates the pin state of the GPIO2 pin regardless of the pin functionality. Bit 0 - GPIO1_IN - Indicates the pin state of the GPIO1 pin regardless of the pin functionality.
6.37
GPIO Output Register (EMC2103-2 Only)
Table 6.53 GPIO Output Register
ADDR E4h
R/W R/W
REGISTER GPIO Output 1
B7 -
B6 -
B5
B4
B3
B2
B1 GPIO2 _OUT
B0 GPIO1 _OUT
DEFAULT 00h
The GPIO Output Register controls the state of the corresponding pins when they are configured as outputs. If the output is configured as an open-drain output, then it requires a pull-up resistor to VDD. Setting the corresponding bit to a `1' will act to disable the output allowing the pull-up resistor to pull the output high. Setting the corresponding bit to a `0' will enable the output and drive the pin to a logical `0' state.
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If the output is configured as a push-pull output, then output pin will immediately be driven to match the corresponding bit setting. Bit 1 - GPIO2_OUT - Controls the pin state of the GPIO2 pin when it is configured as a GPIO output. Bit 0 - GPIO1_OUT - Controls the pin state of the GPIO1 pin when it is configured as a GPIO output.
6.38
GPIO Interrupt Enable Register (EMC2103-2 Only)
Table 6.54 GPIO Interrupt Enable Register
ADDR
R/W
REGISTER GPIO Interrupt Enable
B7
B6
B5
B4
B3
B2
B1 GPIO2_ INT_EN
B0 GPIO1_ INT_EN
DEFAULT
E5h
R/W
-
-
00h
The GPIO Interrupt Enable Register enables the GPIOs to assert the ALERT pin when they change state. When the GPIO pins are configured as outputs, then these bits are ignored. Bit 1 - GPIO2_INT_EN - Allows the ALERT pin to be asserted when the GPIO2 pin changes state (when configured as an input). `0' (default) - The ALERT pin will not be asserted when the GPIO2 pin changes state (when configured as an input). `1' - The ALERT pin will be asserted when the GPIO2 pin changes state (when configured as an input) Bit 0 - GPIO1_INT_EN - Allows the ALERT pin to be asserted when the GPIO1 pin changes state (when configured as an input). `0' (default) - The ALERT pin will not be asserted when the GPIO1 pin changes state (when configured as an input). `1' - The ALERT pin will be asserted when the GPIO1 pin changes state (when configured as an input)
6.39
GPIO Status Register (EMC2103-2 Only)
Table 6.55 GPIO Status Register
ADDR E6h
R/W R-C
REGISTER GPIO Status
B7 -
B6 -
B5
B4
B3
B2
B1 GPIO2_ STS
B0 GPIO1_ STS
DEFAULT 00h
The GPIO Status Register indicates which GPIO has changed states to cause the ALERT pin to be asserted. This register is cleared when it is read. The bits in this register are set whenever the corresponding GPIO changes states regardless if the ALERT pins are asserted. Once a bit is set, it will remain set until read. If any bit in this register is set, then the GPIO status bit will be set. Bit 1 - GPIO2_STS - Indicates that the GPIO2 pin has changed states from a `0' to a `1' or a `1' to a `0' (when configured as a GPIO input). Bit 0 - GPIO1_STS - Indicates that the GPIO1 pin has changed states from a `0' to a `1' or a `1' to a `0' (when configured as a GPIO input).
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6.40
Software Lock Register
Table 6.56 Software Lock
ADDR EFh
R/W R/W
REGISTER Software Lock
B7 -
B6 -
B5 -
B4 -
B3 -
B2 -
B1 -
B0 LOCK
DEFAULT 00h
The Software Lock Register controls the software locking of critical registers. This register is software locked. Bit 0 - LOCK - this bit acts on all registers that are designated SWL. When this bit is set, the locked registers become read only and cannot be updated. `0' (default) - all SWL registers can be updated normally. `1' - all SWL registers cannot be updated and a hard-reset is required to unlock them.
6.41
Product Features Register
Table 6.57 Product Features Register
ADDR FCh
R/W R
REGISTER Product Features
B7 -
B6 -
B5 -
B4 -
B3 -
B2
B1
B0
DEFAULT 00h
SHDN_SEL[2:0]
The Product Features Register indicates which pin selected functionality is enabled.
Table 6.58 SHDN_SEL[2:0] Encoding SHDN_SEL[2:0] 2 0 1 0 0 0 DIODE MODE External Diode 1 Simple Mode - Beta compensation disabled, REC disabled recommended for AMD CPU diodes External Diode 1 Diode Mode - Beta compensation disabled, REC enabled External Diode 1 Transistor Mode - Beta compensation enabled, REC enabled - recommended for Intel 45nm and 65mn CPU diodes Internal Diode Transistor Mode - Beta compensation enabled, REC enabled External Diode 2 Transistor Mode - Beta compensation enabled, REC enabled (EMC2103-2 only) External Diode 1 Diode mode (EMC2103-1 only) 1 0 1 External Diode 1 Transistor Mode - Beta compensation enabled, REC enabled
68
OTHER FEATURES none
0 0
0 1
1 0
none none
0 1
1 0
1 0
none none
none
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6.42
Product ID Register
Table 6.59 Product ID Register
ADDR
R/W
REGISTER Product ID Register (EMC2103-1)
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
0
0
1
0
0
1
0
0
24h
FDh
R Product ID Register (EMC2103-2) 0 0 1 0 0 1 1 0 26h
The Product ID Register contains a unique 8-bit word that identifies the product.
6.43
Manufacturer ID Register
Table 6.60 Manufacturer ID Register
ADDR FEh
R/W R
REGISTER Manufacturer ID
B7 0
B6 1
B5 0
B4 1
B3 1
B2 1
B1 0
B0 1
DEFAULT 5Dh
The Manufacturer ID Register contains an 8-bit word that identifies SMSC.
6.44
Revision Register
Table 6.61 Revision Register
ADDR FFh
R/W R
REGISTER Revision
B7 0
B6 0
B5 0
B4 0
B3 0
B2 0
B1 0
B0 1
DEFAULT 01h
The Revision Register contains an 8-bit word that identifies the die revision. `0' - The lower 3 bits are writable for a range of 1.0053 to 1.0146 `1' - The lower 4 bits are writable for a range of 1.0053 to 1.0253 DBh - IDCF Trim Register - sets the default value for the IDCF1 Register.
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Chapter 7 Package Drawing
7.1 EMC2103-1 Package Information
Figure 7.1 Preliminary 12 pin QFN 4mm x 4mm Package Dimensions
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SMSC EMC2103
Figure 7.2 Preliminary 12 Pin QFN 4mm x 4mm Package Drawing
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Figure 7.3 Recommended PCB Footprint 12-pin QFN 4mm x 4mm
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7.2
EMC2103-2 Package Information
Figure 7.4 Preliminary 16 Pin QFN 4mm x 4mm Package Dimensions
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SMSC EMC2103
Figure 7.5 Preliminary 16 Pin QFN 4mm x 4mm Package Drawing
RPM-Based Fan Controller with HW Thermal Shutdown Datasheet
Figure 7.6 Recommended PCB Footprint 16-pin QFN 4mm x 4mm
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Appendix A Look Up Table Operation
The EMC2103 uses a look-up table to apply a user-programmable fan control profile based on measured temperature to the fan driver. In this look-up table, each temperature channel is allowed to control the fan drive output independently (or jointly) by programming up to eight pairs of temperature and drive setting entries. The user programs the look-up table based on the desired operation. If the RPM based Fan Speed Control Algorithm is to be used (see Section 5.5), then the user must program an RPM target for each temperature setting of interest. Alternately, if the RPM based Fan Speed Control Algorithm is not to be used, then the user must program a drive setting for each temperature setting of interest. If the measured temperature on the External Diode channel meets or exceeds any of the temperature thresholds for any of the channels, the fan output will be automatically set to the desired setting corresponding to the exceeded temperature. In cases where multiple temperature channel thresholds are exceeded, the highest fan drive setting will take precedence. When the measured temperature drops to a point below a lower threshold minus the hysteresis value, the fan output will be set to the corresponding lower set point. The following sections show examples of how the Look Up Table is used and configured. Each Look Up Table Example uses the Fan 1 Look Up Table Registers configured as shown in Table A.1.
Table A.1 Look Up Table Format STEP 1 2 3 4 5 6 7 8 TEMP 1 LUT Temp 1 Setting 1 (52h) LUT Temp 1 Setting 2 (57h) LUT Temp 1 Setting 3 (5Ch) LUT Temp 1 Setting 4 (61h) LUT Temp 1 Setting 5 (66h) LUT Temp 1 Setting 6 (6Bh) LUT Temp 1 Setting 7 (70h) LUT Temp 1 Setting 8 (75h) TEMP 2 LUT Temp 2 Setting 1 (53h) LUT Temp 2 Setting 2 (58h) LUT Temp 2 Setting 3 (5Dh) LUT Temp 2 Setting 4 (62h) LUT Temp 2 Setting 5 (67h) LUT Temp 2 Setting 6 (6Ch) LUT Temp 2 Setting 7 (71h) LUT Temp 2 Setting 8 (76h) TEMP 3 LUT Temp 3 Setting 1 (54h) LUT Temp 3 Setting 2 (59h) LUT Temp 3 Setting 3 (5Eh) LUT Temp 3 Setting 4 (63h) LUT Temp 3 Setting 5 (68h) LUT Temp 3 Setting 6 (6Dh) LUT Temp 3 Setting 7 (72h) LUT Temp 3 Setting 8 (77h) TEMP 4 LUT Temp 4 Setting 1 (55h) LUT Temp 4 Setting 2 (5Ah) LUT Temp 4 Setting 3 (5Fh) LUT Temp 4 Setting 4 (64h) LUT Temp 4 Setting 5 (69h) LUT Temp 4 Setting 6 (6Eh) LUT Temp 4 Setting 7 (73h) LUT Temp 4 Setting 8 (78h) LUT DRIVE LUT Drive Setting 1 (51h) LUT Drive Setting 2 (56h) LUT Drive Setting 3 (5Bh) LUT Drive Setting 4 (60h) LUT Drive Setting 5 (65h) LUT Drive Setting 6 (6Ah) LUT Drive Setting 7 (6Fh) LUT Drive Setting 8 (74h)
A.1
Example #1
This example does not use the RPM based Fan Speed Control Algorithm. Instead, the Look Up Table is configured to directly set a PWM setting based on the temperature of four of its measured inputs. The configuration is set as shown in Table A.2. Once configured, the Look Up Table is loaded as shown in Table A.3. Table A.3 shows three temperature configurations using the settings in Table A.3 and the final PWM output drive setting that the Look Up Table will select.
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Table A.2 Look Up Table Example #1 Configuration ADDR REGISTER LUT 1 Configuration B7 USE_D TS_F1 0 B6 USE_D TS_F2 0 B5 LUT_L OCK 1 B4 RPM / PWM 1 B3 0 B2 TEMP3 _CFG 0 B1 0 B0 TEMP4 _CFG 0 SETTING
50h
C0h
Table A.3 Fan Speed Control Table Example #1 EXTERNAL DIODE 2 TEMPERATURE (GPU) 60oC 70oC 75oC 80oC 85oC 90oC 95oC 100oC
FAN SPEED STEP # 1 2 3 4 5 6 7 8
EXTERNAL DIODE 1 TEMPERATURE (CPU) 35oC 40
oC
EXTERNAL DIODE 3 TEMPERATURE (SKIN) 30oC 35oC 40oC 45oC 50oC 55oC 60oC 65oC
INTERNAL DIODE TEMPERATURE (AMBIENT) 40oC 45oC 50oC 55oC 60oC 65oC 70oC 75oC
PWM SETTINGS 0% 30% 40% 50% 60% 70% 80% 100%
50oC 60oC 70oC 80oC 90oC 100oC
Note: The values shown in Table A.3 are example settings. All the cells in the look-up table are programmable via SMBus.
Table A.4 Fan Speed Determination for Example #1 (using settings in Table A.3)
EXTERNAL DIODE 1 TEMPERATURE (CPU) EXTERNAL DIODE 2 TEMPERATURE (GPU) EXTERNAL DIODE 3 TEMPERATURE (SKIN)
INTERNAL DIODE TEMPERATURE (AMBIENT)
PWM RESULT
Example 1: Example 2: Example 3:
82C
82C 82C
82C
48C
58C 58C
70% (CPU temp requires highest drive) 80% (GPU and Skin require highest drive) 100% (Internal temp requires highest drive)
97C
97C
62C
62C
75C
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A.2
Example #2
This example uses the RPM based Fan Speed Control Algorithm. The Spin Level (used by the Spin Up Routine) should be changed to 50% drive for a total Spin Time of 1 second. For all other RPM configuration settings, the default conditions are used. For control inputs, it uses the External Diode 1 channel normally, the External Diode 2 channel normally, and both Pushed Temperature registers in DTS format. The configuration is set as shown in Table A.5 while Table A.6 shows how the table is loaded. Note that when using DTS data, the USE_DTS_F1 and / or USE_DTS_F2 bits should be set. The Pushed Temperature Registers are loaded with the normal DTS values as received by the processor. When the DTS value is used by the Look Up Table, the value that is stored in the Pushed Temperature Register is subtracted from a fixed temperature of 100C. This resultant value is then compared against the Look Up Table thresholds normally. When programming the Look Up Table, it is necessary to take this translation into account or else incorrect settings may be selected.
Table A.5 Look Up Table Example #2 Configuration ADDR REGISTER Fan 1 Configuration 1 Fan 1 Spin Up Configuration B7 EN_ ALGO 1 B6 B5 B4 B3 B2 B1 UPDATE[2:0] CBh 1 0 NOKICK 1 0 LUT_LO CK 1 0 RPM / PWM 0 0 1 SPIN_LVL[2:0] 1 0 0 TEMP3 _CFG 1 0 0 1 1 B0 SETTING
RANGE[1:0]
EDGES[1:0]
42h
46h
DRIVE_FAIL_CNT1 [1:0] 0 USE_DT S_F1 1 0 USE_D TS_F2 1
SPINUP_TIME [1:0] 1 0 TEMP 3_CFG 1
0Ah
50h
LUT 1 Configuration
E5h
Table A.6 Fan Speed Control Table Example #2 EXTERNAL DIODE 1 TEMPERATURE (CPU) 35oC 40oC 50oC 60oC 70oC 80oC EXTERNAL DIODE 2 TEMPERATURE (GPU) 65oC 75oC 85oC 90oC 95oC 100oC
FAN SPEED STEP # 1 2 3 4 5 6
PUSHED TEMPERATURE SETTING (DTS1) 50oC 55oC 60oC 65oC 70oC 75oC
PUSHED TEMPERATURE SETTING (DTS2) 40oC 45oC 50oC 55oC 60oC 65oC
TACH TARGET 3Dh (1007 RPM) 1Eh (2048 RPM) 14h (3072 RPM) 0Fh (4096 RPM) 0Ch (5120 RPM) 0Ah (6144 RPM)
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Table A.6 Fan Speed Control Table Example #2 (continued) EXTERNAL DIODE 1 TEMPERATURE (CPU) 90oC 100oC EXTERNAL DIODE 2 TEMPERATURE (GPU) 105oC 110oC
FAN SPEED STEP # 7 8
PUSHED TEMPERATURE SETTING (DTS1) 80oC 85oC
PUSHED TEMPERATURE SETTING (DTS2) 80oC 100oC
TACH TARGET 09h (6826 RPM) 08h (7680 RPM)
Note: The values shown in Table A.6 are example settings. All the cells in the look-up table are programmable via SMBus.
Table A.7 Fan Speed Determination for Example #2 (using settings in Table A.6) EXTERNAL DIODE 1 TEMPERATURE (CPU) EXTERNAL DIODE 2 TEMPERATURE (GPU)
PUSHED TEMPERATURE (DTS1) 35C (translated as 65C)
PUSHED TEMPERATURE (DTS2) 50C (translated as 50C) 20C (translated as 80C)
PWM RESULT 0Ch (5120 RPM) CPU requires highest target 08h (7680 RPM) DTS1 requires highest target 09h (6826 RPM) DTS2 requires highest target
Example 1:
75C
75C
Example 2:
75C
90C
15C (translated as 85C)
30C (translated as 70C)
Example 3:
75C
97.25C
5C (translated as 95C)
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Appendix B RPM to Tachometer Count Look Up Tables
B.1 1k RPM Range
The Look Up Table is an example based on the assumption that the fan being measured has 2-poles and is measuring 5 edges using the 1k RPM range settings. The data presented in the reading is only the high byte data and the decimal count value only represents high byte data.
Table B.1 Tachometer Count to RPM Look Up Table (Range = 1000 RPM) REGISTER READING (HEX) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98
TACH COUNT (DECIMAL) 0 32 64 96 128 160 192 224 256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768
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REGISTER READING (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18
FAN SPEED (RPM) Disabled 245760 122880 81920 61440 49152 40960 35109 30720 27307 24576 22342 20480 18905 17554 16384 15360 14456 13653 12935 12288 11703 11171 10685 10240
80
TACH COUNT (DECIMAL) 4096 4128 4160 4192 4224 4256 4288 4320 4352 4384 4416 4448 4480 4512 4544 4576 4608 4640 4672 4704 4736 4768 4800 4832 4864
FAN SPEED (RPM) 1920 1905 1890 1876 1862 1848 1834 1820 1807 1794 1781 1768 1755 1743 1731 1719 1707 1695 1683 1672 1661 1649 1638 1628 1617
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Table B.1 Tachometer Count to RPM Look Up Table (Range = 1000 RPM) (continued) REGISTER READING (HEX) 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8
TACH COUNT (DECIMAL) 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792
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REGISTER READING (HEX) 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38
FAN SPEED (RPM) 9830 9452 9102 8777 8474 8192 7928 7680 7447 7228 7022 6827 6642 6467 6302 6144 5994 5851 5715 5585 5461 5343 5229 5120 5016 4915 4819 4726 4637 4551 4468 4389
81
TACH COUNT (DECIMAL) 4896 4928 4960 4992 5024 5056 5088 5120 5152 5184 5216 5248 5280 5312 5344 5376 5408 5440 5472 5504 5536 5568 5600 5632 5664 5696 5728 5760 5792 5824 5856 5888
FAN SPEED (RPM) 1606 1596 1586 1575 1565 1555 1546 1536 1526 1517 1508 1499 1489 1480 1472 1463 1454 1446 1437 1429 1421 1412 1404 1396 1388 1381 1373 1365 1358 1350 1343 1336
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Table B.1 Tachometer Count to RPM Look Up Table (Range = 1000 RPM) (continued) REGISTER READING (HEX) B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7
TACH COUNT (DECIMAL) 1824 1856 1888 1920 1952 1984 2016 2048 2080 2112 2144 2176 2208 2240 2272 2304 2336 2368 2400 2432 2464 2496 2528 2560 2592 2624 2656 2688 2720 2752 2784
REGISTER READING (HEX) 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57
FAN SPEED (RPM) 4312 4237 4165 4096 4029 3964 3901 3840 3781 3724 3668 3614 3562 3511 3461 3413 3367 3321 3277 3234 3192 3151 3111 3072 3034 2997 2961 2926 2891 2858 2825
TACH COUNT (DECIMAL) 5920 5952 5984 6016 6048 6080 6112 6144 6176 6208 6240 6272 6304 6336 6368 6400 6432 6464 6496 6528 6560 6592 6624 6656 6688 6720 6752 6784 6816 6848 6880
FAN SPEED (RPM) 1328 1321 1314 1307 1300 1293 1287 1280 1273 1267 1260 1254 1248 1241 1235 1229 1223 1217 1211 1205 1199 1193 1187 1182 1176 1170 1165 1159 1154 1148 1143
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Table B.1 Tachometer Count to RPM Look Up Table (Range = 1000 RPM) (continued) REGISTER READING (HEX) D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7
TACH COUNT (DECIMAL) 2816 2848 2880 2912 2944 2976 3008 3040 3072 3104 3136 3168 3200 3232 3264 3296 3328 3360 3392 3424 3456 3488 3520 3552 3584 3616 3648 3680 3712 3744 3776 3808
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REGISTER READING (HEX) 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77
FAN SPEED (RPM) 2793 2761 2731 2701 2671 2643 2614 2587 2560 2534 2508 2482 2458 2433 2409 2386 2363 2341 2318 2297 2276 2255 2234 2214 2194 2175 2156 2137 2119 2101 2083 2065
83
TACH COUNT (DECIMAL) 6912 6944 6976 7008 7040 7072 7104 7136 7168 7200 7232 7264 7296 7328 7360 7392 7424 7456 7488 7520 7552 7584 7616 7648 7680 7712 7744 7776 7808 7840 7872 7904
FAN SPEED (RPM) 1138 1133 1127 1122 1117 1112 1107 1102 1097 1092 1087 1083 1078 1073 1069 1064 1059 1055 1050 1046 1041 1037 1033 1028 1024 1020 1016 1011 1007 1003 999 995
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Table B.1 Tachometer Count to RPM Look Up Table (Range = 1000 RPM) (continued) REGISTER READING (HEX) F8 F9 FA FB FC FD FE FF
TACH COUNT (DECIMAL) 3840 3872 3904 3936 3968 4000 4032 4064
REGISTER READING (HEX) 78 79 7A 7B 7C 7D 7E 7F
FAN SPEED (RPM) 2048 2031 2014 1998 1982 1966 1950 1935
TACH COUNT (DECIMAL) 7936 7968 8000 8032 8064 8096 8128 8160
FAN SPEED (RPM) 991 987 983 979 975 971 968 964
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