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EL5210, EL5410
Data Sheet July 5, 2007 FN7185.3
30MHz Rail-to-Rail Input-Output Op Amps
The EL5210 and EL5410 are low power, high voltage rail-torail input-output amplifiers. The EL5210 contains two amplifiers in one package and the EL5410 contains four amplifiers. Operating on supplies ranging from 5V to 15V, while consuming only 2.5mA per amplifier, the EL5410 and EL5210 have a bandwidth of 30MHz (-3dB). They also provide common mode input ability beyond the supply rails, as well as rail-to-rail output capability. This enables these amplifiers to offer maximum dynamic range at any supply voltage. The EL5410 and EL5210 also feature fast slewing and settling times, as well as a high output drive capability of 30mA (sink and source). These features make these amplifiers ideal for high speed filtering and signal conditioning application. Other applications include battery power, portable devices, and anywhere low power consumption is important. The EL5410 is available in a space-saving 14 Ld TSSOP package, as well as the industry-standard 14 Ld SOIC. The EL5210 is available in the 8 Ld MSOP and 8 Ld SOIC packages. Both feature a standard operational amplifier pin out. These amplifiers operate over a temperature range of -40C to +85C.
Features
* 30MHz -3dB bandwidth * Supply voltage = 4.5V to 16.5V * Low supply current (per amplifier) = 2.5mA * High slew rate = 33V/s * Unity-gain stable * Beyond the rails input capability * Rail-to-rail output swing * Available in both standard and space-saving fine pitch packages * Pb-free plus anneal available (RoHS compliant)
Applications
* Driver for A-to-D Converters * Data Acquisition * Video Processing * Audio Processing * Active Filters * Test Equipment * Battery Powered Applications * Portable Equipment
Pinouts
EL5410 (14 LD TSSOP, SOIC) TOP VIEW
VOUTA 1 VINA- 2 VINA+ 3 VS+ 4 VINB+ 5 + VINB- 6 VOUTB 7 + 9 VINC8 VOUTC + + 12 VIND+ 11 VS10 VINC+ VINA+ 3 VS- 4 14 VOUTD 13 VIND-
EL5210 (8 LD MSOP, SOIC) TOP VIEW
VOUTA 1 VINA- 2 + + 5 VINB+ 6 VINB8 VS+ 7 VOUTB
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003-2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5210, EL5410 Ordering Information
PART NUMBER EL5210CS EL5210CS-T7* EL5210CS-T13* EL5210CSZ (Note) EL5210CSZ-T7* (Note) EL5210CSZ-T13* (Note) EL5210CY EL5210CY-T7* EL5210CY-T13* EL5210CYZ (Note) EL5210CYZ-T7* (Note) EL5210CYZ-T13* (Note) EL5410CS EL5410CS-T7* EL5410CS-T13* EL5410CSZ (Note) EL5410CSZ-T7* (Note) EL5410CSZ-T13* (Note) EL5410CR EL5410CR-T7* EL5410CR-T13* EL5410CRZ (Note) EL5410CRZ-T7* (Note) EL5410CRZ-T13* (Note) PART MARKING 5210CS 5210CS 5210CS 5210CSZ 5210CSZ 5210CSZ J J J BATAA BATAA BATAA 5410CS 5410CS 5410CS 5410CSZ 5410CSZ 5410CSZ 5410CR 5410CR 5410CR 5410CRZ 5410CRZ 5410CRZ 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP (Pb-free) 8 Ld MSOP (Pb-free) 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC (Pb-free) 14 Ld SOIC (Pb-free) 14 Ld SOIC (Pb-free) 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 14 Ld TSSOP (Pb-free) 14 Ld TSSOP (Pb-free) PACKAGE PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0044 MDP0044 MDP0044 M14.173 M14.173 M14.173
*"-T7" or "-T13" suffix is for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN7185.3 July 5, 2007
EL5210, EL5410
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS + 0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN CMIR CMRR AVOL
VS+ = +5V, VS- = -5V, RL = 1k and CL = 12pF to 0V, TA = +25C unless otherwise specified. CONDITION MIN (Note 4) TYP MAX (Note 4) UNIT
DESCRIPTION
Input Offset Voltage Average Offset Voltage Drift (Note 1) Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open-Loop Gain
VCM = 0V
3 7
15
mV V/C
VCM = 0V
2 1 2 -5.5
60
nA GW pF
+5.5 70 80
V dB dB
for VIN from -5.5V to 5.5V -4.5V VOUT 4.5V
50 65
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short Circuit Current Output Current IL = -5mA IL = 5mA 4.8 -4.9 4.9 120 30 -4.8 V V mA mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (Per Amplifier) VS is moved from 2.25V to 7.75V No Load 60 80 2.5 3.75 dB mA
DYNAMIC PERFORMANCE SR tS BW GBWP PM CS dG dP Slew Rate (Note 2) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation Differential Gain (Note 3) Differential Phase (Note 3) f = 5MHz RF = RG = 1k and VOUT = 1.4V RF = RG = 1k and VOUT = 1.4V -4.0V VOUT 4.0V, 20% to 80% (AV = +1), VO = 2V Step 33 140 30 20 50 110 0.12 0.17 V/s ns MHz MHz dB %
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FN7185.3 July 5, 2007
EL5210, EL5410
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN CMIR CMRR AVOL Input Offset Voltage Average Offset Voltage Drift (Note 1) Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open-Loop Gain for VIN from -0.5V to 5.5V 0.5V VOUT 4.5V -0.5 45 65 66 80 VCM = 2.5V VCM = 2.5V 3 7 2 1 2 +5.5 60 15 mV V/C nA GW pF V dB dB VS+ = 5V, VS- = 0V, RL = 1k and CL = 12pF to 2.5V, TA = +25C unless otherwise specified. CONDITION MIN (Note 4) TYP MAX (Note 4) UNIT
DESCRIPTION
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short Circuit Current Output Current IL = -5mA IL = 5mA 4.8 100 4.9 120 30 200 mV V mA mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (Per Amplifier) VS is moved from 4.5V to 15.5V No Load 60 80 2.5 3.75 dB mA
DYNAMIC PERFORMANCE SR tS BW GBWP PM CS dG dP Slew Rate (Note 2) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation Differential Gain (Note 3) Differential Phase (Note 3) f = 5MHz RF = RG = 1k and VOUT = 1.4V RF = RG = 1k and VOUT = 1.4V 1V VOUT 4V, 20% to 80% (AV = +1), VO = 2V Step 33 140 30 20 50 110 0.30 0.66 V/s ns MHz MHz dB %
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FN7185.3 July 5, 2007
EL5210, EL5410
Electrical Specifications
PARAMETER VS+ = 15V, VS- = 0V, RL = 1k and CL = 12pF to 7.5V, TA = +25C unless otherwise specified. CONDITION MIN (Note 4) TYP MAX (Note 4) UNIT
DESCRIPTION
INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN CMIR CMRR AVOL Input Offset Voltage Average Offset Voltage Drift (Note 1) Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open-Loop Gain for VIN from -0.5V to 15.5V 0.5V VOUT 14.5V -0.5 53 65 72 80 VCM = 7.5V VCM = 7.5V 3 7 2 1 2 +15.5 60 15 mV V/C nA GW pF V dB dB
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short Circuit Current Output Current IL = -7.5mA IL = 7.5mA 14.65 170 14.83 120 30 350 mV V mA mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (Per Amplifier) VS is moved from 4.5V to 15.5V No Load 60 80 2.5 3.75 dB mA
DYNAMIC PERFORMANCE SR tS BW GBWP PM CS dG dP NOTES: 1. Measured over operating temperature range 2. Slew rate is measured on rising and falling edges 3. NTSC signal generator used 4. Parts are 100% tested at +25C. Over temperature limits established by characterization and are not production tested. Slew Rate (Note 2) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation Differential Gain (Note 3) Differential Phase (Note 3) f = 5MHz RF = RG = 1k and VOUT = 1.4V RF = RG = 1k and VOUT = 1.4V 1V VOUT 14V, 20% to 80% (AV = +1), VO = 2V Step 33 140 30 20 50 110 0.10 0.11 V/s ns MHz MHz dB %
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FN7185.3 July 5, 2007
EL5210, EL5410 Typical Performance Curves
EL5410 Input Offset Voltage Distribution 500 VS=5V TA=25C Typical Production Distortion Quantity (Amplifiers) 25 VS=5V 20 Typical Production Distortion EL5410 Input Offset Voltage Drift
400 Quantity (Amplifiers)
300
15
200
10
100
5
0 2 4 6 -8 -6 -4 -2 -0 8 10 -12 -10 12 Input Offset Voltage (mV)
0 1 3 5 7 9 11 13 15 17 19 Input Offset Voltage Drift, TCVOS (V/C) 21 150 150
Input Offset Voltage vs Temperature 5 0.008
Input Bias Current vs Temperature
Input Offset Voltage (mV)
4 Input Bias Current (A)
0.004
VS=5V
3
0
2
-0.004
1
-0.008
0 -50
-10
30
70
110
150
-0.012 -50
-10
30
70
110
Temperature (C)
Temperature (C)
Output High Voltage vs Temperature 4.96 -4.85
Output Low Voltage vs Temperature
4.95 Output High Voltage (V) VS=5V IOUT=5mA 4.94 Output Low Voltage (V)
-4.87 VS=5V IOUT=5mA -4.89
4.93
-4.91
4.92
-4.93
4.91 -50
-10
30
70
110
150
-4.95 -50
-10
30
70
110
Temperature (C)
Temperature (C)
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FN7185.3 July 5, 2007
EL5210, EL5410 Typical Performance Curves
(Continued)
Open-Loop Gain vs Temperature 90 33.85 33.80 Open-Loop Gain (dB) 85 VS=5V RL=1k Slew Rate (V/S) 33.75 33.70 33.65 33.60
Slew Rate vs Temperature
VS=5V
80
75
70 -50
-10
30
70
110
150
33.55 -40
0
40
80
120
160
Temperature (C)
Temperature (C)
EL5410 Supply Current per Amplifier vs Supply Voltage 2.9 2.7 Supply Current (mA) 2.5 2.3 2.1 1.9 1.7 1.5 4 8 12 Supply Voltage (V) 16 20 TA=25C Supply Current (mA) 2.7 2.65 2.6 2.55 2.5 2.45
EL5410 Supply Current per Amplifier vs Temperature
VS=5V
2.4 -50
-10
30
70
110
150
Temperature (C)
Differential Gain and Phase 0.25 Diff Gain (%) 0.15 0.05 Distortion (dB) -0.05 0 100 200 -50 VS=5V AV=2 RL=1k -30
Harmonic Distortion vs VOP-P
-40
VS=5V AV=1 RL=1k FIN = 1MHz
HD3
HD2 -60
Diff Phase ()
0.20 0.10 0 -0.10 0 100 IRE 200
-70
-80 0 2 4 VOP-P (V) 6 8 10
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FN7185.3 July 5, 2007
EL5210, EL5410 Typical Performance Curves
(Continued)
Open Loop Gain and Phase vs Frequency 140 Phase Magnitude (Normalized) (dB) 100 150 3 250 5
Frequency Response for Various RL
10k 1k 1 0 -1 AV=1 VS=5V CL=12pF 560
Gain (dB)
20
Gain VS=5V TA=25C RL=1k to GND CL=12pF to GND
-50
-20
-150
Phase ()
60
50
-3
150
-60 10 100 1k 10k 100k 1M 10M Frequency (Hz)
-250 100M
-5 100k 1M Frequency (Hz) 10M 100M
Frequency Response for Various CL 20 100pF Magnitude (Normalized) (dB) 10 1000pF Output Impedance () 47pF 10pF 160 200
Closed Loop Output Impedance vs Frequency
AV=1 VS=5V TA=25C
0
120
-10 RL=1k AV=1 VS=5V
80
-20
40
-30 100k
1M Frequency (Hz)
10M
100M
0 10k
100k
1M Frequency (Hz)
10M
30M
Maximum Output Swing vs Frequency 10 80
CMRR vs Frequency
Maximum Output Swing (VP-P)
8
70
4
2
VS=5V TA=25C AV=1 RL=1k CL=12pF Distortion <1%
CMRR (dB)
6
60
50 VS=5V TA=25C
40
0 10k
30 100k Frequency (Hz) 1M 10M 10 100 1k 10k 100k 1M 10M 30M Frequency (Hz)
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FN7185.3 July 5, 2007
EL5210, EL5410 Typical Performance Curves
(Continued)
PSRR vs Frequency 80 PSRR+ PSRR1000
Input Voltage Noise Spectral Density vs Frequency
Voltage Noise (nV/Hz)
60
100
PSRR (dB)
40
20
VS=5V TA=25C
10
0 100 1k 10k 100k 1M 10M Frequency (Hz)
1 100 1k 10k 100k Frequency (Hz) 1M 10M 100M
Total Harmonic Distortion + Noise vs Frequency 0.010 -60
Channel Separation vs Frequency Response
0.008
-80
Dual measured Channel A to B Quad measured Channel A to D or B to C Other combinations yield improved rejection
THD+ N (%)
0.004 VS=5V RL=1k AV=1 VIN=0.5VRMS
XTalk (dB)
0.006
-100
-120 VS=5V RL=1k AV=1 VIN=110mVRMS 1k 10k 100k Frequency (Hz) 1M 10M 30M
0.002
-140
0 1k 10k Frequency (Hz) 100k
-160
Small-Signal Overshoot vs Load Capacitance 100 VS=5V AV=1 RL=1k VIN=50mV TA=25C Step Size (V) 5 4 3 2 1 0 -1 -2 20 -3 -4 0 10 100 Load Capacitance (pF) 1000
Settling Time vs Step Size
80
VS=5V AV=1 RL=1k CL=12pF TA=25C
0.1%
Overshoot (%)
60
40
0.1%
-5 70
90
110
130
150
170
190
210
230
Settling Time (ns)
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FN7185.3 July 5, 2007
EL5210, EL5410 Typical Performance Curves
Large Signal Transient Response
(Continued)
Small Signal Transient Response
1V
200ns
50mV
100ns
VS=5V TA=25C AV=1 RL=1k CL=12pF
VS=5V TA=25C AV=1 RL=1k CL=12pF
Pin Descriptions
EL5210 1 EL5410 1 Name VOUTA Function Amplifier A Output
VS+
Equivalent Circuit
GND Circuit 1
VS-
2
2
VINA-
Amplifier A Inverting Input
VS+
VSCircuit 2
3 8 5 6 7
3 4 5 6 7 8 9 10
VINA+ VS+ VINB+ VINBVOUTB VOUTC VINCVINC+ VSVIND+ VINDVOUTD
Amplifier A Non-Inverting Input Positive Power Supply Amplifier B Non-Inverting Input Amplifier B Inverting Input Amplifier B Output Amplifier C Output Amplifier C Inverting Input Amplifier C Non-Inverting Input Negative Power Supply Amplifier D Non-Inverting Input Amplifier D Inverting Input Amplifier D Output
(Reference Circuit 2)
(Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 1) (Reference Circuit 1) (Reference Circuit 2) (Reference Circuit 2)
4
11 12 13 14
(Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 1)
10
FN7185.3 July 5, 2007
EL5210, EL5410 Applications Information
Product Description
The EL5210 and EL5410 voltage feedback amplifiers are fabricated using a high voltage CMOS process. They exhibit Rail-to-Rail input and output capability, are unity gain stable and have low power consumption (2.5mA per amplifier). These features make the EL5210 and EL5410 ideal for a wide range of general-purpose applications. Connected in voltage follower mode and driving a load of 1k and 12pF, the EL5210 and EL5410 have a -3dB bandwidth of 30MHz while maintaining a 33V/S slew rate. The EL5210 is a dual amplifier while the EL5410 is a quad amplifier. continuous current never exceeds 30mA. This limit is set by the design of the internal metal interconnects.
Output Phase Reversal
The EL5210 and EL5410 are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 2 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur.
1V 10s
Operating Voltage, Input, and Output
The EL5210 and EL5410 are specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5210 and EL5410 specifications are stable over both the full supply range and operating temperatures of -40C to +85C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The input common-mode voltage range of the EL5210 and EL5410 extends 500mV beyond the supply rails. The output swings of the EL5210 and EL5410 typically extend to within 100mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 1 shows the input and output waveforms for the device in the unity-gain configuration. Operation is from 5V supply with a 1k load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.8VP-P.
5V 10s
VS=2.5V TA=25C AV=1 VIN=6VP-P 1V
FIGURE 2. OPERATION WITH BEYOND-THE-RAILS INPUT
Power Dissipation
With the high-output drive capability of the EL5210 and EL5410 amplifiers, it is possible to exceed the 125C 'absolute-maximum junction temperature' under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
VS=5V TA=25C AV=1 VIN=10VP-P
Input
Output
Where: TJMAX = Maximum Junction Temperature TAMAX= Maximum Ambient Temperature
5V
FIGURE 1. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT
JA = Thermal Resistance of the Package PDMAX = Maximum Power Dissipation in the Package. The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or:
P DMAX = i [ V S x I SMAX + ( V S + - V OUT i ) x I LOAD i ]
Short Circuit Current Limit
The EL5210 and EL5410 will limit the short circuit current to 120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output
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FN7185.3 July 5, 2007
EL5210, EL5410
when sourcing, and
P DMAX = i [ V S x I SMAX + ( V OUT i - V S - ) x I LOAD i ]
1200 MAX TJ=125C 1000 Power Dissipation (mW) 800 600 400 200 0 0 25 50 75 85 100 125 150 Ambient Temperature (C) 485mW SO8 JA=160C/W MSOP8 JA=206C/W SO14 JA=120C/W TSSOP14 JA=165C/W Packages Mounted on a JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
when sinking. Where: i = 1 to 2 for Dual and 1 to 4 for Quad VS = Total Supply Voltage ISMAX = Maximum Supply Current Per Amplifier VOUTi = Maximum Output Voltage of the Application ILOADi = Load current If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. Figure 3 and Figure 4 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. To ensure proper operation, it is important to observe the recommended derating curves shown in Figure 3 and Figure 4.
Packages Mounted on a JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 1200 1000 Power Dissipation (mW) 800 600 400 200 0 0 25 50 75 85 100 125 150 Ambient Temperature (C) MSOP8 JA=115C/W TSSOP14 JA=100C/W SO14 JA=88C/W 1.136W 1.0W 909mW 833mW MAX TJ=125C
833mW 606mW
625mW
FIGURE 4. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Unused Amplifiers
It is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground plane.
Driving Capacitive Loads
The EL5210 and EL5410 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The amplifiers drive 10pF loads in parallel with 1k with just 1.2dB of peaking, and 100pF with 6.5dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5 and 50) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a "snubber" circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150 and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain.
SO8 JA=110C/W
FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Power Supply Bypassing and Printed Circuit Board Layout
The EL5210 and EL5410 can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1F ceramic capacitor should be placed from VS+ to pin to VS- pin. A 4.7F tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. One 4.7F capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used.
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FN7185.3 July 5, 2007
EL5210, EL5410 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN7185.3 July 5, 2007
EL5210, EL5410 Mini SO Package Family (MSOP)
0.25 M C A B D N A (N/2)+1
MDP0043
MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included.
E
E1
PIN #1 I.D.
A2 b c
B
1 (N/2)
D E E1
e C SEATING PLANE 0.10 C N LEADS b
H
e L L1 N
0.08 M C A B
L1 A c SEE DETAIL "X"
2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A2 GAUGE PLANE L DETAIL X
0.25
A1
3 3
14
FN7185.3 July 5, 2007
EL5210, EL5410 Thin Shrink Small Outline Package Family (TSSOP)
0.25 M C A B D N (N/2)+1 A
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
A A1 A2 b c D E E1 e
H
1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00
Max 0.05 0.05 +0.05/-0.06 +0.05/-0.06 0.10 Basic 0.10 Basic 0.15 Reference Rev. F 2/07
E
E1
1 B TOP VIEW
(N/2)
0.20 C B A 2X N/2 LEAD TIPS
C SEATING PLANE
e
0.05
L L1 NOTES:
b 0.10 C N LEADS SIDE VIEW
0.10 M C A B
1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions "D" and "E1" are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SEE DETAIL "X"
c
END VIEW
L1
A
A2 GAUGE PLANE 0.25 A1 DETAIL X L 0 - 8
15
FN7185.3 July 5, 2007
EL5210, EL5410 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN7185.3 July 5, 2007

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