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| ISL9301 Data Sheet February 25, 2008 FN6435.0 High Input Voltage Charger With Power Path Management The ISL9301 is a fully integrated high input voltage single-cell Li-ion battery charger with power path management function. This charger performs the CC/CV charge function required by Li-ion batteries. The charger accepts an input voltage up to 28V but is disabled when the input voltage exceeds 10.5V OVP threshold. The 28V rating eliminates the overvoltage protection circuit required in a low-voltage charger. The charge current and the end-of-charge (EOC) current are programmable with external resistors. When the battery voltage is lower than 2.8V, the charger preconditions the battery with 16% of the programmed charge current. When the charge current reduces to the programmable EOC current level during the CV charge phase, the EOC indicator (CHG) will toggle to logic LOW to indicate the end-of-charge condition. The charger will continue to charge until the user programmed timeout interval has elapsed, then the charger is terminated. The ISL9301 uses separate power paths to supply the system load and charge the battery. This feature allows the system to immediately operate with a completely discharged battery. This feature also allows the charge to terminate when the battery is full while continuing to supply the system with the input source, thus minimizing unnecessary charge/discharge cycles and improving the battery life. Two indication pins (PPR and CHG) allow simple interface to a microprocessor or LEDs. Features * Complete Charger for Single-Cell Li-ion/Polymer Batteries * Power Path Management Optimize Charge and System Currents * Intelligent Timeout Interval Based on Actual Charge Current * Integrated Disconnect Switch to Disconnect the Battery * 1% Charger Output Voltage Accuracy * Programmable Charge Current * Programmable End-of-Charge Current * Charge Current Thermal Foldback for Thermal Protection * Trickle Charge for Fully Discharged Batteries * 28V Maximum Voltage at VIN pin * Power Presence and Charge Indications * Ambient Temperature Range: -40C to +85C * 10 Ld 3x3 DFN Package * Pb-Free (RoHS Compliant) Applications * Mobile Phones * Blue-Tooth Devices * PDAs * MP3 Players Ordering Information PART NUMBER (Note) ISL9301IRZ PART MARKING 9301 TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. # * Stand-Alone Chargers * Other Handheld Devices Pinout ISL9301 (10 LD DFN) TOP VIEW -40 to +85 10 Ld 3X3 DFN L10.3X3C -40 to +85 10 Ld 3X3 DFN L10.3X3C ISL9301IRZ-T 9301 * Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. VIN VBAT PPR CHG TIME 1 2 3 4 5 10 VOUT 9 8 7 6 BATON IREF IMIN GND 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL9301 Absolute Maximum Ratings (Reference to GND) VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 30V All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Thermal Information Thermal Resistance (Typical) JA (C/W) JC (C/W) DFN Package (Notes 1, 2) . . . . . . . . . . 40 2.5 Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40C to +85C Maximum Supply Voltage (VIN Pin). . . . . . . . . . . . . . . . . . . . . . 28V Operating Supply Voltage (VIN Pin). . . . . . . . . . . . . . . . 4.3V to 10V Programmed Charge Current . . . . . . . . . . . . . . . . . 50mA to 450mA Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mA to 800mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For theta JC, the "case temp" location is the center of the exposed metal pad on the package underside. Electrical Specifications Typical values are tested at VIN = 5V and the ambient temperature at +25C. All maximum and minimum values are established under the recommended operating supply voltage range and ambient temperature range, unless otherwise noted. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PARAMETER POWER-ON RESET Rising POR Threshold Falling POR Threshold VOUT-BAT OFFSET VOLTAGE Rising Edge Falling Edge VIN OVERVOLTAGE PROTECTION Over Voltage Protection Threshold OVP Threshold Hysteresis STANDBY CURRENT BAT Pin Sink Current BAT Pin Supply Current VIN Pin Supply Current VOLTAGE REGULATION Output Voltage Output PPM Threshold Voltage Charger Output Voltage IREF PIN Voltage MOSFET ON-RESISTANCE Regulator MOSFET rDS(ON) Charger MOSFET rDS(ON) RECHARGE THRESHOLD Recharge Voltage Threshold CURRENT REGULATION (Note 4) Input Current Limit Constant Charge Current VPOR VPOR VBAT = 3.0V, use PPR to indicate the comparator output. 3.3 3.1 3.9 3.6 4.3 4.15 V V VOS VOS VBAT = 4.0V, use CHG pin to indicate the comparator output (Note 3) 10 110 100 250 - mV mV VOVP 10 Use PPR to indicate the comparator output 200 10.5 400 13 500 V mV ISTANDBY IVBAT IVIN Charger disabled or the input is floating No supply at VIN, BATON = HI Charger enabled - 10 1 1.0 - A A mA VOUT VDPPM VBAT VIREF System current + charge current = 15mA 4.40 4.22 4.50 4.35 4.20 1.20 4.62 4.45 4.242 1.245 V V V V Charge current = 10mA VBAT = 3.8V 4.158 1.165 rDS(ON) rDS(ON) VOUT = 4.4V, Total current = 0.3A VBAT = 3.8V, charge current = 0.2A - 0.8 0.1 1.2 0.15 VRECHG Relative to VBAT -200 -150 -100 mV ILIM ICHG VOUT = 4.5V RIREF = 26.7k, VBAT = 2.8V - 4.0V 600 130 800 145 1200 160 mA mA 2 FN6435.0 February 25, 2008 ISL9301 Electrical Specifications Typical values are tested at VIN = 5V and the ambient temperature at +25C. All maximum and minimum values are established under the recommended operating supply voltage range and ambient temperature range, unless otherwise noted. (Continued) SYMBOL ITRK IMIN TEST CONDITIONS RIREF = 26.7k, VBAT = 2.4V RIMIN = 137k MIN 17 18 TYP 23 23 MAX 30 28 UNITS mA mA PARAMETER Trickle Charge Current End-of-Charge Current PRECONDITIONING CHARGE THRESHOLD Preconditioning Charge Threshold Voltage Preconditioning Voltage Hysteresis VMIN VMINHYS 2.7 40 2.8 100 3.0 150 V mV INTERNAL TEMPERATURE MONITORING (Note 5) Charger Current Thermal Foldback Threshold TFOLD 115 C OVER-TEMPERATURE PROTECTION (Note 5) Shutdown Rising Threshold Shutdown Falling Threshold OSCILLATOR PERIOD Oscillator Period LOGIC INPUT AND OUTPUTS BATON Pin Logic Input High BATON Pin Logic Input Low BAT Pin Internal Pull-Down Resistance PPR, CHG Driving Capability when LOW Leakage Current When HIGH NOTES: 3. The 4.0V VBAT is selected so that the CHG output can be used as the indication for the offset comparator output indication. If the VBAT is lower than the POR threshold, no output pin can be used for indication. 4. The input current charge current can be affected by the thermal foldback function if the IC under the test setup cannot dissipate the heat. 5. Limits established by characterization and are not production tested. Pin Voltage = 1V Pin Voltage = 6.5V 10 1 mA A VBAT < 4.5V VBAT > 2V 1.1 800 1000 0.4 1200 V V k tOSC RTIME = 1M 60 75 90 s TR TF 142 110 C C 3 FN6435.0 February 25, 2008 ISL9301 Block Diagram To system load VIN VOUT 1000 IOUT IBAT RILIM 1 VBAT 1000 IREF ILIM_REF 1 VOUT VOUT_REF Cell1 Die Temp IBAT_REF 142 oC VBAT VCC VBAT VBAT_REF Die Temp 1V 115 oC TIME COMP SQ R SHUTDOWN VIN VBAT SHUTDOWN PPM CTRL POR Timer EOC Re-charge OVP DispIay Logic 0.2V COMP IOUT IBAT CLK CHG PPR IMIN To uP GND Pin Descriptions VIN - Power input. The absolute maximum input voltage is 28V. A 10F or larger value capacitor is recommended to be placed very close to the input pin for decoupling purposes. Additional capacitance may be required to provide a stable input voltage. VBAT - Charger output pin. Connect this pin to the battery. A 1F or larger X5R ceramic capacitor is recommended for decoupling and stability purposes. When the BATON pin is pulled to logic LOW or left floating, the VBAT pin is disconnected from the IC. TIME - Timing resistor pin. The TIME pin determines the oscillation period by connecting a timing resistor between this pin and GND. The oscillator also provides a time reference for the charger calculated in Equation 1. t OSC = 75 x R TIME ( s ) (EQ. 1) PPR - Open-drain power presence indication. The open-drain MOSFET turns on when the input voltage is above the POR threshold but below the OVP threshold and off otherwise. This pin is capable to sink 10mA (minimum) current to drive a LED. The maximum voltage rating for this pin is 7V. CHG - Open-drain charge indication pin. This pin outputs a logic LOW when a charge cycle starts and turns to HIGH when the end-of-charge (EOC) condition is qualified. This pin is capable to sink 10mA min. current to drive an LED. When the charger is disabled, the CHG outputs high impedance. IMIN - End-of-charge (EOC) current program pin. Connect a resistor between this pin and the GND pin to set the EOC current. The EOC current IMIN can be programmed by Equation 3: 3151 I MIN = ---------------R IMIN ( mA ) (EQ. 3) Where RTIME is in M. The nominal timeout interval is given by Equation 2: 2 x t OSC t TIMEOUT = ---------------------------3600 28 ( Hour ) (EQ. 2) Where RIMIN is in k. The programmable range covers 5% (or 10mA, whichever is higher) to 50% of IREF when programmed to less than 5% or 10mA. Where tOSC is in seconds. For an 1M RTIME, the nominal timeout interval is approximately 5.6 hours. 4 FN6435.0 February 25, 2008 ISL9301 IREF - Charge-current program and monitoring pin. Connect a resistor between this pin and the GND pin to set the charge current limit determined by Equation 4: 3886 I REF = ---------------R IREF ( mA ) (EQ. 4) Where RIREF is in k. The IREF pin voltage also monitors the actual charge current during the entire charge cycle, including the trickle, constant-current, and constant-voltage phases. When disabled, VIREF = 0V. BATON - Battery disconnect pin. The BATON pin is a logic input pin to allow the disconnection of the battery from the system to eliminate the unwanted drainage current from the battery. There is an internal 1M pull-down resistor at this pin. Drive to HIGH to connect the battery to the system. When this pin is driven to LOW or left floating, the battery is disconnected from the system. VOUT - Output connection to the system. This pin provides a 4.5V regulated voltage for the system when a valid input power is present. If no valid input is present, and BATON is driven HI, the VOUT pin is connected to VBAT through an internal MOSFET. If no valid input is present and BATON is LOW, the voltage at VOUT pin is zero. A 4.7F or larger X5R ceramic capacitor is recommended for decoupling and stability purposes. EPAD - Exposed pad. Connect as much copper as possible to this pad either on the component layer or other layers through thermal vias to enhance the thermal performance. Trickle 4.2V IREF CC CV Charge Voltage Charge Current 2.8V Timeout 16%IREF IMIN VREC CHG CHG Indication TIME FIGURE 1. TYPICAL CHARGING CYCLE 5 FN6435.0 February 25, 2008 ISL9301 Typical Application Circuit INPUT VIN C1 VBAT R3 ISL9301 R1 R2 IREF RIREF IMIN RIMIN TIME RTIME GND BATON TO P PRESS AND HOLD 2s TO TURN ON CHG PPR D2 D1 C2 BATT VOUT C3 TO SYS PART C1 C2 C3 R3 RIREF RIMIN RTIME R1, R2 D1, D2 DESCRIPTION 10F X5R ceramic cap 1F X5R ceramic cap 4.7F X5R ceramic cap 1, 5% resistor 26.7k, 1%, for 150mA charge current 137k, 1%, for 23mA EOC current 1M, 1% resistor for 75s clock period 470, 5% resistor LEDs for indication Theory of Operation When a valid input voltage is applied at VIN, the ISL9301 first regulates VOUT at 4.5V for system power need. In the mean time, if the battery is attached, the ISL9301 also charges the battery while supplying current to the system. When the system exceeds the maximum available current, either limited by the IC or by the input power supply, the charger FET is operated in a reverse mode, i.e. it discharges current to the system instead of charging. The charger function is similar to other Li-ion battery chargers, i.e. it charges the battery at a constant current (CC) or a constant voltage (CV) depending on the battery terminal voltage. The constant current IREF is set with the external resistor RIREF, as shown in the "Typical Application Circuit" on page 6. The constant voltage is fixed at 4.2V. If the battery voltage is below a typical 2.8V trickle charge threshold, the ISL9301 charges the battery with a trickle current (~16% of the programmed constant current) until the battery voltage rises above the trickle charge threshold. When the battery voltage reaches the final voltage of 4.2V, the charger enters the CV mode and regulates the battery voltage at 4.2V to fully charge the battery without the risk of overcharging. Upon reaching an end-of-charge (EOC) current, the charger indicates the charge completion with the CHG pin, but the charger continues to deliver 4.2V at the VBAT pin until the timeout limit has reached. Figure 1 shows the typical charge profile with the EOC/reset events. The EOC current level IMIN is programmable with the external resistor RIMIN. The CHG signal turns to LO when the trickle charge starts and rises to HIGH at an EOC event. After the EOC is reached, the CHG status is latched at HI. The CHG status will be reset to logic LO when the VBAT voltage drops to below the recharge threshold (4.05V), as shown in Figure 1. A thermal foldback function reduces the charge current anytime when the die temperature reaches typically +115C. This function guarantees safe operation when the printed-circuit board (PCB) is not capable of dissipating the heat generated by the linear charger. 6 FN6435.0 February 25, 2008 ISL9301 The ISL9301 accepts an input voltage up to 28V but will be disabled when the input voltage exceeds the OVP threshold, minimum 10V, to protect against unqualified or faulty AC adapters. Charge Termination, Recharge and Timeout When an EOC condition is reached, the CHG pin changes to logic HI to indicate the end-of-charge. However the charger continues to deliver current to the battery until the timeout interval has elapsed, then the charging will be terminated. The setting of the timeout interval is described in "Intelligent Timer" on page 8. When a recharge condition is met after a timeout event, the timer will be reset to zero and the charging re-starts. In the event when the timeout interval has elapsed before the EOC condition is reached, a timeout fault condition is triggered. The timeout fault condition is indicated by the CHG pin being toggled between HI and LO every 3s (RTIME = 1M). The timeout fault condition can be cleared by removing and reapplying the input power to the IC. Under the EOC, timeout and timeout fault conditions, the power delivery to VOUT is not impacted. The battery continues to supply current to VOUT if needed, as described in "Dynamic Power Path Management" on page 8. PPR Indication The PPR pin is an open-drain output to indicate the presence of the AC adapter. Whenever the input voltage is higher than the POR threshold, the PPR pin turns on the internal open-drain MOSFET to indicate a logic LOW signal. When the internal open-drain FET is turned off, the PPR pin should leak less than 1A current. When turned on, the PPR pin should be able to sink at least 10mA current under all operating conditions. The PPR pin can be used to drive an LED (see "Typical Application Circuit" on page 6) or to interface with a microprocessor. Power-Good Range The power-good range is defined by the following three conditions: 1. VIN > VPOR 2. VIN - VOUT > VOS 3. VIN < VOVP where VOS is the offset voltage for the input and output voltage comparator and the VOVP is the overvoltage protection threshold given in the "Electrical Specifications" starting on page 2. All VPOR, VOS, and VOVP have hysteresis. The IC will not deliver any output if the input voltage is not in the power-good range. Battery Disconnection The BATON pin provides an option for disconnection of the battery from the system if battery power is not needed and no power source is applied at VIN. The disconnection will prevent the IC leakage current from draining the battery for an extended period of time. To reconnect the battery, pull the BATON pin to logic HI for 2s. Once the system is powered on, the host micro process will send a logic signal to keep BATON at logic HI level. The BATON pin has a 1M internal pull-down resistor thus, when left floating, the input is equivalent to a logic LOW state. The logic threshold levels are given in the "Electrical Specifications" table starting on page 2. CHG Indication The CHG is an open-drain output. The open drain FET turns on when the charger starts to charge and turns off when the EOC condition is qualified. Once the EOC condition is qualified, the CHG signal is latched in off state. The EOC condition is qualified when both of the following conditions are satisfied: 1. VBAT > VRECHG 2. ICHG < IMIN The CHG indication will not be turned on again until a recharge condition is qualified. A recharge condition is reached under one of the three conditions: 1. Input power being re-cycled 2. Enable signal being toggled 3. A recharge cycle starts when the battery voltage drops below the recharge threshold The CHG signal can be interfaced either with a micro-processor GPIO or a LED for indication. A de-glitch delay of 1ms for both edges is required to prevent nuisance triggering due to some transient conditions. BATON Interlock When a valid voltage source is applied at VIN, the BATON function is disabled. This prevents the battery from being connected to a 4.5V regulated voltage source and generating a large circulating current. If the VIN supply is removed, the BATON function will resume immediately to allow the battery to supply the system. IREF Pin Function The IREF pin has the two functions as described in "Pin Descriptions" on page 4. When setting the fast charge current, the charge current is trimmed to have 10% accuracy at 145mA, excluding the programming resistor error. The percent error decreases as the set charge current is higher but increases as the set charge current is lower than 145mA. The trickle charge current is 16% of the programmed fast charge current. When monitoring the charge current, the accuracy of the IREF pin voltage vs the actual charge current has the same accuracy as the gain from the IREF pin current to the actual charge current. The IREF pin voltage vs the charge current FN6435.0 February 25, 2008 7 ISL9301 when IREF is set to 145mA is shown in Figure 2. Figure 3 shows a typical time domain charge current curve vs time and its accuracy limits for a complete cycle. The accuracy is compared against the voltage on the IREF pin. Thermal foldback may affect the charge current curve as well as the accuracy. 150 current until VOUT is regulated. In the event that the system needs more than the available current, VOUT will continue to drop. When VOUT drops to below the battery voltage, the DPPM control will turn on the charge control FET, allowing the battery to supply current to the system load. Thus the battery may be charged at a current smaller than the programmed constant current. Intelligent Timer The internal timer in the ISL9301 provides a time reference for the maximum charge time limit. The nominal clock cycle for the reference time is set by the external resistor connected between the TIME pin and GND and is given by Equation 1. The nominal maximum charge time interval is calculated based on the assumption that the programmed charge current is always available during the entire charging cycle. However, due to the PPM control or due to the current limit of the input source, or thermal foldback, the actual charge current maybe reduced during the constant current charge period. Under such conditions, the Intelligent Timer control will increase the timeout interval accordingly to allow approximately the same mAh product as the original timeout interval at the programmed current. CHARGE CURRENT (mA) 0 IR E F P IN V O L T A G E (V ) 1 .2 FIGURE 2. IREF PIN VOLTAGE vs CHARGE CURRERNT (IREF IS SET TO 150mA. THE DOTTED LINES SHOW THE UPPER AND LOWER LIMITS OF THE TOLERANCE) . ICHG TRICKLE CC CV 1.1IREF IREF 0.9IREF Thermal Foldback The thermal foldback function starts to reduce the charge current when the internal temperature reaches a typical value of +115C. When thermal foldback is encountered, the charge current will be reduced to a value where the die temperature stops rising. Figure 5 shows the thermal foldback operation whereas the current signals at the summing node of the current error amplifier CA are shown in Figure 4. IR is the reference. IT is the temperature tracking current generated from the Temperature Monitoring block. The IT has no impact on the charge current until the internal temperature reaches approximately +115C; then IT starts to rise. In the mean time, as IT rises, ISEN will fall at the same rate (as the sum is a constant current IR). As a result, the charging current, which is proportional to ISEN, also decreases, keeping the die temperature constant at +115C. The system output current, however, is not impacted by the thermal foldback. Thus, when the charge current is reduced to zero, if the die temperature still rises, the IC will shut down to prevent damage to the IC. 0.22IREF 0.16IREF 0.12IREF 1.3IMIN 1.0IMIN 0.7IMIN TIME FIGURE 3. CHARGE CURRENT ACCURACY WHEN IREF = 145mA Dynamic Power Path Management The power path management function of the ISL9301 controls the charge current and the system current when charging with system load. This is based on the available input current, which is either limited by the IC (800mA) or by the input power source, whichever is smaller. When the output voltage drops to the DPPM threshold (4.35V typical), the dynamic power path management starts to function. The DPPM control will first allocate the available current to the system load, using the remaining current to charge the battery. This is achieved by dynamically reducing the charge 8 FN6435.0 February 25, 2008 ISL9301 Q1 VIN X3 Q2 X3 VBAT X3 VOUT TEMPERATURE MONITORING IT ISEN IR + CA VA + VREF REF IREF CONTROL IREF FIGURE 4. CHARGE CURRENT THERMAL FOLDBACK CIRCUIT VOUT and VBAT Capacitor Selection IR IT I SEN -40mA/C The criteria for selecting the capacitor at the VOUT and VBAT pins is to maintain the stability as well as to bypass any transient load current. The recommended capacitance is a 4.7F X5R ceramic capacitor for VOUT and 1F for VBAT. The actual capacitance connected to the output is dependent on the actual application requirement. Layout Guidance The ISL9301 uses a thermally-enhanced DFN package that has an exposed thermal pad at the bottom side of the package. The layout should connect as much as possible to copper on the exposed pad. Typically, the component layer is more effective in dissipating heat. The thermal impedance can be further reduced by using other layers of copper connecting to the exposed pad through a thermal via array. Each thermal via is recommended to have 0.3mm diameter and 1mm distance from other thermal vias. 115C TEMPERATURE FIGURE 5. CHARGE CURRENT FOLDBACK Applications Information Input Bypass Capacitor The input capacitor is required to suppress the power supply transient response during transitions. Typically, a 10F or larger capacitor should be sufficient to suppress the power supply noise. Due to the inductance of the power leads of the wall adapter or USB source, the input capacitor type must be properly selected to prevent high voltage transient during a hot-plug event. A tantalum capacitor is a good choice for its high ESR, providing damping to the voltage transient. Multi-layer ceramic capacitors, however, have a very low ESR and hence when chosen as input capacitor, a 1 series resistor must be used (as shown in the "Typical Application Circuit" on page 6) to provide adequate damping. Input Power Sources The input power source is typically a well-regulated wall cube with 1m length wire or a USB port. The input voltage ranges from 4.3V to 10V. The ISL9301 can withstand up to 28V on the input without damaging the IC. If the input voltage is higher than the OVP threshold, the IC is disabled. State Diagram The state diagram is shown in Figure 6. There are 8 states to cover all the operation modes, including the Trickle Charge, Batt Discharge, PPM, CV Charge, Charge Fault, Charge Complete, Disabled and OTP states. The IC starts with a trickle charge or constant current charge state depending on VBAT when input power is applied. In the Trickle Charge state, the PPR is LO and the CHG is LO, FN6435.0 February 25, 2008 9 ISL9301 VOUT is regulated at 4.5V, the charger is ON, delivering a trickle charge current. The IC moves to a fast charge constant current mode when VBAT reaches the VMIN threshold. There are 3 possible states in this mode depending on the output current. When the sum of the output current and the fast charge current is smaller than the input current limit, the IC enters the Fast Charge state with the charge current set by RIREF. When the output current and the fast charge current are greater than the input current limit, the IC will enter the PPM mode, where the charging current is reduced to a point such that the sum of output current and the charging current equals to the input current limit. If the output current by itself is greater than the input current limit, the IC enters the Battery Discharge state, where the battery is discharged to the system to supply a part of the output demand. When the battery voltage reaches 4.2V, the IC enters the CV Charge state, where PPR is LO, CHG is LO and VOUT is regulated at 4.5V. The battery is being charged at a constant voltage while the charging current decreases. When the charging current is reduced to the IMIN threshold, the IC enters a Charge Complete state, where PPR is LO, CHG is HI, VOUT is regulated at 4.5V and the charger continues to charge the battery. When the timeout interval has elapsed after the Charge Complete state, the IC will enter the Disabled state, where the PPR is LO, CHG is HI, VOUT is regulated at 4.5V and the charger is OFF. After the Charge Complete state, if VBAT is below the re-charge threshold, the IC will re-initialize and start a new cycle. If the timeout limit is reached before the Charge Complete state, the IC enters the Charger Fault state, where PPR is LO, CHG is blinking, VOUT is regulated at 4.5V and the charger is OFF. This state is latched until the input power is removed and re-applied to start a new cycle. Any time during the operation, if the die temperature reaches the OTP threshold, the IC will enter the OTP state, where PPR is LO, CHG is HI, and the charger is OFF. VOUT is disconnected from VIN and connected to VBAT internally to maintain system power need. Summary of Output States The output states under various fault conditions are summarized in Table 1. TABLE 1. OUTPUT STATES UNDER FAULT CONDITIONS OTP Y Y N Y Y N N NOTES: BATON: BATON Pin OVP: Input Over Voltage Protection OTP: Over Temperature Protection M1: Output Path MOSFET M2: Battery Path MOSFET OVP Y N Y Y N Y N BATON H H H L L L X M1 OFF OFF OFF OFF OFF OFF Regulating M2 ON ON ON OFF OFF OFF Charging 10 FN6435.0 February 25, 2008 ISL9301 P ow er Up Y N IO U T > IL IM ? V IN > V P O R ? N Y IR E F + IO U T > IL IM ? V IN < V O V P ? N Y POR B A T T D IS C H A R G E VOUT = ON IC H G = -(IO U T - IL IM ) C h a rg e r = R e v e rs e d CHG = HI T im e r R e s e t FAST CHARGE VOUT = ON IC H G = IR E F C h a rg e r = O N C H G = LO PPM VOUT = ON IC H G = (IL IM - IO U T ) C h a rg e r = O N C H G = LO Y N N V IN > V O U T + V O S ? Y N VBAT = 4 .2 V ? Y CV CHARGE VOUT = ON C h a rg e r = O N C H G = LO In itia liz a tio n R e s e t T im e r V B A T > V M IN N Y T R IC K L E C H A R G E PPR = L CHG = L V O U T = 4 .5 V C h a rg e r = O N T im e o u t? N Y CHARGER FAULT VOUT = ON C h a rg e r = O F F C H G = B lin k in g I C H G < I M IN ? Y N Pow er dow n CHARGE COM PLETE VOUT = ON C h a rg e r = O N CHG = HI To Power U p N T im e o u t? Y A n y tim e D ie te m p e ra tu re e x c e e d s 1 4 2 oC O TP VOUT = VBAT C h a rg e r = O F F CHG = HI D IS A B L E D VOUT = ON C h a rg e r = O F F CHG = HI T d ie < 1 1 0 o C ? N VOUT < VRECH? N Y Y FIGURE 6. STATE DIAGRAM 11 FN6435.0 February 25, 2008 ISL9301 Dual Flat No-Lead Plastic Package (DFN) 2X 0.10 C A A D 2X 0.10 C B L10.3x3C 10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A E MIN 0.85 - NOMINAL 0.90 0.20 REF MAX 0.95 0.05 NOTES - A1 A3 b D 6 INDEX AREA TOP VIEW B 0.20 0.25 3.00 BSC 0.30 5, 8 - D2 // 0.10 C 0.08 C 2.33 2.38 3.00 BSC 2.43 7, 8 - E E2 e k L 0.20 0.35 1.59 A C SEATING PLANE SIDE VIEW A3 1.64 0.50 BSC 0.40 10 5 1.69 7, 8 - 0.45 8 2 3 Rev. 1 4/06 D2 (DATUM B) 1 2 D2/2 7 8 N Nd NOTES: NX k E2 6 INDEX AREA (DATUM A) 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. E2/2 NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) 9L 5 0.10 M C A B 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2. FOR ODD TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN6435.0 February 25, 2008 |
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