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PRELIMINARY
FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR
ICS844021I-01
GENERAL DESCRIPTION
The ICS844021I-01 is an Ethernet Clock Generator IC S and a member of the HiPerClocksTM family of high HiPerClockSTM performance devices from IDT. The ICS844021I01 uses an 18pF parallel resonant crystal over the range of 24.5MHz - 34MHz. For Ethernet applications, a 25MHz crystal is used. The ICS844021I-01 has excellent <1ps phase jitter performance, over the 1.875MHz - 20MHz integration range. The ICS844021I-01 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
FEATURES
* One Differential LVDS output * Crystal oscillator interface, 18pF parallel resonant crystal (24.5MHz - 34MHz) * Output frequency range: 122.5MHz - 170MHz * VCO range: 490MHz - 680MHz * RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.32ps (typical) @ 3.3V * 3.3V or 2.5V operating supply * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
COMMON CONFIGURATION TABLE - Gb ETHERNET
Inputs Crystal Frequency (MHz) 25 26.666 33.33 M 20 20 20 N 4 4 4 Multiplication Value M/N 5 5 5 Output Frequency (MHz) 125 133.33 166.66
BLOCK DIAGRAM
OE
Pullup
PIN ASSIGNMENT
VDDA GND XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q nQ OE
XTAL_IN
OSC
XTAL_OUT
Phase Detector
VCO
490MHz - 680MHz
N = /4 (fixed)
Q nQ
ICS844021I-01
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
M = /20 (fixed)
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4 5 6, 7 8 Name VDDA GND XTAL_OUT, XTAL_IN OE nQ, Q VDD Power Power Input Input Output Power Pullup Type Description Analog supply pin. Power supply ground. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Output enable pin. When HIGH, Q/nQ output is active. When LOW, the Q/nQ output is in a high impedance state. LVCMOS/LVTTL interface levels. Differential clock outputs. LVDS interface levels. Core supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO (LVDS) Continuous Current Surge Current 4.6V -0.5V to VDD + 0.5 V 10mA 15mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 129.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VDD - 0.08 Typical 3.3 3.3 55 8 Maximum 3.465 VDD Units V V mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 2.375 VDD - 0.08 Typical 2.5 2.5 52 8 Maximum 2.625 VDD Units V V mA mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -150 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 5 Units V V V V A A
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PRELIMINARY
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 400 10 1.3 10 Maximum Units mV mV V mV
NOTE: Please refer to Parameter Measurement Information for output information.
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = 2.5V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 400 10 1.2 10 Maximum Units mV mV V mV
NOTE: Please refer to Parameter Measurement Information for output information.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 24.5 Test Conditions Minimum Typical Fundamental 34 50 7 100 MHz pF W Maximum Units
TABLE 5A. AC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency 125MHz @ Integration Range: 1.875MHz - 20MHz 133.33MHz @ Integration Range: 1.875MHz - 20MHz 166.66MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Test Conditions Minimum 122.5 0.32 TBD TBD 300 50 Typical Maximum 170 Units MHz ps ps ps ps %
t jit(O)
RMS Phase Jitter ( Random); NOTE 1
tR / tF
Output Rise/Fall Time
o dc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section.
TABLE 5B. AC CHARACTERISTICS, VDD = 2.5V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency 125MHz @ Integration Range: 1.875MHz - 20MHz 133.33MHz @ Integration Range: 1.875MHz - 20MHz 166.66MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Test Conditions Minimum 122.5 0.31 TBD TBD 320 50 Typical Maximum 170 Units MHz ps ps ps ps %
t jit(O)
RMS Phase Jitter ( Random); NOTE 1
tR / tF
Output Rise/Fall Time
o dc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section.
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PRELIMINARY
TYPICAL PHASE NOISE AT 125MHZ @ 3.3V
125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.32ps (typical)

OFFSET FREQUENCY (HZ)
5
Ethernet Filter
NOISE POWER dBc Hz
Raw Phase Noise Data
TYPICAL PHASE NOISE AT 125MHZ @ 2.5V
125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.32ps (typical)
Phase Noise Result by adding Ethernet Filter to raw data OFFSET FREQUENCY (HZ) Ethernet Filter
NOISE POWER dBc Hz
Raw Phase Noise Data
Phase Noise Result by adding Ethernet Filter to raw data
IDT TM / ICSTM LVDS CLOCK GENERATOR
ICS844021BGI-01 REV. C SEPTEMBER 27, 2007
ICS844021I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
SCOPE
3.3V5% POWER SUPPLY + Float GND -
SCOPE
2.5V5% POWER SUPPLY + Float GND -
VDD VDDA
Qx
VDD VDDA
Qx
LVDS
nQx
LVDS
nQx
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT
nQ
Noise Power
Q
t PW
Phase Noise Mask
t
PERIOD
odc =
f1 Offset Frequency f2
t PW t PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD VDD
out
80% Clock Outputs
80% VOD
DC Input
LVDS
out
20% tR tF
20%
VOS/ VOS
OUTPUT RISE/FALL TIME
VDD VDD
OFFSET VOLTAGE SETUP
DC Input
LVDS
100
VOD/ VOD out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
IDT TM / ICSTM LVDS CLOCK GENERATOR
out
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PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844021I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V or 2.5V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844021I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
FIGURE 2. CRYSTAL INPUt INTERFACE
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PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the
VDD
series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER
TO
XTAL INPUT INTERFACE
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4 In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V or 2.5V VDD LVDS + R1 100
-
100 Differential Transmission
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844021I-01 Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844021I-01 is the sum of the core power plus the analog plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
*
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (55mA + 8mA) = 218.3mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.218W * 129.5C/W = 113.2C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
8-LEAD TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 129.5C/W
1
125.5C/W
2.5
123.5C/W
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 129.5C/W
1
125.5C/W
2.5
123.5C/W
TRANSISTOR COUNT
The transistor count for ICS844021I-01 is: 2533
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PRELIMINARY
PACKAGE OUTLINE - G SUFFIX
FOR
8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS844021BGI-01 ICS844021BGI-01T ICS844021BGI-01LF ICS844021BGI-01LFT Marking 2BI01 2BI01 BI01L BI01L Package 8 lead TSSOP 8 lead TSSOP 8 lead "Lead-Free" TSSOP 8 lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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