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| PI6C557-03 PCI Express Clock Product Features * LVDS compatible outputs * Supply voltage of 3.3V 10% * 25MHz input frequency * HCSL outputs, 0.7V Current mode differential pair * Jitter 60ps cycle-to-cycle (typ) * Spread of 0.25%, -0.5%, -0.75%, and no spread * Industrial temperature range * Packaging: (Pb-free and Green) --16-pin, 173 mils wide TSSOP Description The PI6C557-03 is a spread spectrum clock generator supporting PCI Express and Ethernet requirements. The device is used for PC or embedded systems to substantially reduce Electromagnetic Interference (EMI). The PI6C557-03 provides two differential (HCSL) spread spectrum outputs. The PI6C557-03 is configured to select spread and clock selection. Using Pericom's patented Phase-Locked Loop (PLL) techniques, the device takes a 25MHz crystal input and produces two pairs of differential outputs (HCSL) at 25MHz, 100MHz, 125MHz and 200MHz clock frequencies. It also provides spread selection of 0.25%, -0.5%, -0.75%, and no spread. Block Diagram VDD 2 SS1:SS0 2 CLK0 Control Logic Phase Lock Loop CLK1 Crystal Driver CLK1 CLK0 S1:S0 2 X1/CLK 25 MHz crystal or clock X2 Pulling Capacitors 2 GND OE RR Pin Configuration S0 S1 SS0 X1/CLK X2 OE GNDX SS1 07-0274 1 2 3 4 5 6 7 8 1 16 15 14 13 12 11 10 9 VDDX CLK0 CLK0 GNDA VDDA CLK1 CLK1 IREF PS8824C 12/14/07 PI6C557-03 PCI Express Clock Pin Description Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name S0 S1 SS0 X1/CLK X2 OE GNDX SS1 IREF CLK1 CLK1 VDDA GNDA CLK0 CLK0 VDDX I/O Type Input Input Input Input Output Input Power Input Output Output Output Power Power Output Output Power Description Select pin 0 (Internal pull-up resistor). See Table 1. Select pin 1 (Internal pull-up resistor). See Table 1. Spread Select pin 0 (Internal pull-up resistor). See Table 2. Crystal or clock input. Connect to a 25MHz crystal or single ended clock. Crystal connection. Leave unconnected for clock input. Output enable. Internal pull-up resistor. Crystal ground pin. Spread Select pin 1 (Internal pull-up resistor). See Table 2. Precision resistor attached to this pin is connected to the internal current reference. HCSL compliment clock output HCSL clock output Connect to a +3.3V source. Output and analog circuit ground. HCSL compliment clock output HCSL clock output Connect to a +3.3V source. Table 1: Output Select Table S1 0 0 1 1 S0 0 1 0 1 CLK(MHz) 25 100 125 200 Table 2: Spread Selection Table SS1 0 0 1 1 SS0 0 1 0 1 Spread Center 0.25 Down -0.5 Down -0.75 No Spread 07-0274 2 PS8824C 12/14/07 PI6C557-03 PCI Express Clock Application Information Decoupling Capacitors Decoupling capacitors of 0.01F should be connected between each VDD pin and the ground plane and placed as close to the VDD pin as possible. Crystal Use a 25MHz fundamental mode parallel resonant crystal with less than 300PPM of error across temperature. Crystal Capacitors CL = Crystals's load capacitance in pF Crystal Capacitors (pF) = (CL - 8) *2 For example, for a crystal with 16pF load caps, the external effective crystal cap would be 16 pF. (16-8)*2=16. Current Source (Iref) Reference Resistor - RR If board target trace impedance is 50, then RR = 475 providing an IREF of 2.32 mA. The output current (IOH) is 6*IREF. Output Termination The PCI-Express differential clock outputs of the PI6C557-03 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The PI6C557-03 can be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. Output Structures IREF =2.3mA 6*IREF R R=475 See Output Termination Sections 07-0274 3 PS8824C 12/14/07 PI6C557-03 PCI Express Clock PCI-Express Layout Guidelines Common Recommendations for Differential Routing L1 length, route as non-coupled 50 trace. L2 length, route as non-coupled 50 trace. L3 length, route as non-coupled 50 trace. RS RT Differential Routing on a Single PCB L4 length, route as coupled microstrip 100 differential trace. L4 length, route as coupled stripline 100 differential trace. Differential Routing to a PCI Express connector L4 length, route as coupled microstrip 100 differential trace. L4 length, route as coupled stripline 100 differential trace. Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Dimension or Value 0.25 min to 14 max 0.225 min to 12.6 max Unit inch inch inch Unit inch inch Unit inch inch PCI-Express Device Routing L1 RS L1' RS L2 L4 L4' RT L3' RT L3 L2' PI6C557-03 Output Clock PCI-Express Load or Connector Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 0.52 V 0.175 V 500 ps 500 ps tOF 0.52 V 0.175 V 07-0274 4 PS8824C 12/14/07 PI6C557-03 PCI Express Clock Application Information LVDS Recommendations for Differential Routing L1 length, route as non-coupled 50 trace. L2 length, route as non-coupled 50 trace. RP RQ RT L3 length, route as non-coupled 50 trace. L3 length, route as non-coupled 50 trace. Dimension or Value 0.5 max 0.2 max 100 100 150 Unit inch inch LVDS Device Routing L1 RQ L1' L3 L3' RP RT PI6C557-03 Clock Output L2' L2 RT LVDS Device Load Typical LVDS Waveform 1325 mV 1000 mV tOR 500 ps 500 ps tOF 1250 mV 1150 mV 1250 mV 1150 mV 07-0274 5 PS8824C 12/14/07 PI6C557-03 PCI Express Clock Electrical Specifications Maximum Ratings Supply Voltage to Ground Potential......................................................... 5.5V All Inputs and Outputs ..................................................... -0.5V to VDD+0.5V Ambient Operating Temperature ................................................ -40 to +80C Storage Temperature ................................................................. -65 to +150C Junction Temperature ............................................................................150C Soldering Temperature ..........................................................................260C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. -40 +3.0 Typ. Max. +85 +3.6 Unit C V DC Characteristics (VDD = 3.3V 10%, TA = -40C to +85oC) Symbol VDD VIH VIL IIL Parameter Supply Voltage Input High Voltage(1) Input Low Voltage(1) Input Leakage Current Conditions Min. 3.0 2.0 GND -0.3 -20 -5 Typ. 3.3 Max. 3.60 VDD +0.3 0.8 20 5 65 35 7 6 5 3.0 mA mA pF pF nH k Unit V V V A IDD IDDOE CIN COUT LPIN ROUT S0, S1, OE, CLK, SS0, SS1 S0, S1, OE, CLK, SS0, SS1 0 < Vin < VDD With input pull-up and pull-downs Without input pull-up and pull-downs Operating Supply Current RL = 50, CL = 2pF OE = LOW Input Capacitance Input pin capacitance Output Capacitance Output pin capacitance Pin Inductance Output Resistance CLK Outputs Notes: 1. Single edge is monotonic when transitioning through region. 07-0274 6 PS8824C 12/14/07 PI6C557-03 PCI Express Clock AC Characteristics (VDD = 3.3V 10%, TA = -40C to +85oC) Symbol FIN VOUT VOH VOL VCPA VCN JCC MF tOR tOF TR/T TSKEW TDUTYCYCLE Parameter Input Frequency Output Frequency Output High Voltage (1,2) Output Low Voltage(1,2) Crossing Point Voltage(1,2) Crossing Point Voltage(1,2,4) Jitter, Cycle-to-Cycle(1,3) Modulation Frequency Rise Time(1,2) Fall Time(1,2) Rise/Fall Time Variation(1,2) Skew between outputs Duty Cycle(1,3) Output Enable Time(5) Output Disable Time(5) From power-up to VDD=3.3V Setting period after spread change Conditions Min. 25 660 -150 250 Typ. 25 700 0 350 60 31.5 332 344 Max. 200 850 550 140 100 33 700 700 125 50 55 @VDD = 3.3V Absolute Variation over all edges Spread Spectrum From 0.175V to 0.525V From 0.525V to 0.175V VDD/2 30 175 175 45 All outputs All outputs 1.6 0.1 0.1 3.0 3.0 Unit MHz MHz mV mV mV mV ps kHz ps ps ps ps % s s ms ms TOE TOT tSTABLE tSPREAD Notes: 1. RL = 50 with CL = 2 pF and RR = 475 2. Single-ended waveform 3. Differential waveform 4. Measured at the crossing point 5. CLK pins are tri-stated when OE is LOW Thermal Characteristics Symbol JA JC Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Still air Min. Typ. Max. 90 24 Unit C/W C/W Recomended Crystal Specification Pericom recommends SRX7278 for optimium performance. Parameter Mode of Oscillation Frequency Frequency Tolerance Temperature and Aging Stability Load Cap Equivelent Series Resistance Drive Level Value Fundamental AT 25 20 30 20 35 100 Units MHz PPM pF mW 07-0274 7 PS8824C 12/14/07 PI6C557-03 PCI Express Clock Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AB Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 * www.pericom.com Ordering Information(1-3) Ordering Code PI6C557-03LE Package Code L PackageType Pb-free & Green, 16-Pin TSSOP Note: 1. Thermal characteristics and package top marking information can be found at http://www.pericom.com/packaging/ 2. E = lead-free and green packaging 3. Adding an X suffix = tape/reel Pericom Semiconductor Corporation * www.pericom.com 07-0274 8 PS8824C 12/14/07 |
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