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| DATA SHEET SKY72300-362: Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer Applications * General purpose RF systems * 2.5G and 3G wireless infrastructure * Broadband wireless access * Low bit rate wireless telemetry * Instrumentation * L-band receivers * Satellite communications * Direct digital modulation * 3 V operation * 5 V output to loop filter * QFN (24-pin, 4 x 4 mm) Pb-free (MSL3, 260 C per JEDEC JSTD-020) package Description Skyworks SKY72300-362 direct digital modulation fractional-N frequency synthesizer provides ultra-fine frequency resolution, fast switching speed, and low phase-noise performance. This synthesizer is a key building block for high-performance radio system designs that require low power and fine step size. The ultra-fine step size of less than 100 Hz allows this synthesizer to be used in very narrowband wireless applications. With proper temperature sensing or through control channels, the synthesizer's fine step size can compensate for crystal oscillator or Intermediate Frequency (IF) filter drift. As a result, crystal oscillators or crystals can replace temperature-compensated or ovenized crystal oscillators, reducing parts count and associated component cost. The device's fine step size can also be used for Doppler shift corrections. The SKY72300-362 has a phase noise floor of -90 dBc/Hz up to 2.1 GHz operation as measured inside the loop bandwidth. This is permitted by the on-chip low noise dividers and low divide ratios provided by the device's high fractionality. Reference crystals or oscillators up to 50 MHz can be used with the SKY72300-362. The crystal frequency is divided down by independent programmable dividers (1 to 32) for the main and auxiliary synthesizers. The phase detectors can operate at a maximum speed of 25 MHz, which allows better phase noise due to the lower division value. With a high reference frequency, the loop bandwidths can also be increased. Larger loop bandwidths improve the settling times and reduce in-band phase noise. Therefore, typical switching times of less than 100 s can be achieved. The lower in-band phase noise also permits the use of lower cost Voltage Controlled Oscillators (VCOs) in customer applications. The SKY72300-362 has a frequency power steering circuit that helps the loop filter to steer the VCO when the frequency is too fast or too slow, further enhancing acquisition time. Features * Spur-free operation * 2.1 GHz maximum operating frequency * 500 MHz maximum auxiliary synthesizer * Ultra-fine step size, 100 Hz or less * High internal reference frequency enables large loop bandwidth implementations * Very fast switching speed (e.g., below 100 s) * Phase noise to -91 dBc/Hz inside the loop filter bandwidth @ 1800 MHz * Software programmable power-down modes * High-speed serial interface up to 100 Mbps * Three-wire programming * Programmable division ratios on reference frequency * Phase detectors with programmable gain to provide a programmable loop bandwidth * Frequency power steering further enhances rapid acquisition time * On-chip crystal oscillator * Frequency adjust for temperature compensation Skyworks offers lead (Pb)-free RoHS (Restriction of Hazardous Substances) compliant packaging. Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 200731B * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * July 30, 2007 1 DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER The unit operates with a three-wire, high-speed serial interface. A combination of large bandwidth, fine resolution, and the threewire, high-speed serial interface allows for a direct frequency modulation of the VCO. This supports any continuous phase, constant envelope modulation scheme such as Frequency Modulation (FM), Frequency Shift Keying (FSK), Minimum Shift Keying (MSK), or Gaussian Minimum Shift Keying (GMSK). This capability can eliminate the need for In-phase and Quadrature (I/Q) Digital-to-Analog Converters (DACs), quadrature upconverters, and IF filters from the transmitter portion of the radio system. Figure 1 shows a functional block diagram for the SKY72300-362. The device package and pinout for the 24-pin Quad Flat No-Lead (QFN) package are shown in Figure 2. Data Clock CS Serial Interface Modulation Data Main MSB/LSB Dividend Main Divider Registers Modulation Control Ref Freq Dividers PD/Charge Pump Aux Aux Divider & Pwr-Dn/Mux Out Dividend Control Mod_in Modulation Unit Mux Mux_out 18-Bit 10-Bit Fractional Unit Fvco_main Fvco_main Main Divider Main Divider Fpd_main Main Phase/Freq. Detector and Charge Pump Reference Frequency Oscillator Fractional Unit Fvco_aux Auxiliary Divider Auxiliary Prescaler Fvco_aux Fref_main Fref_aux Auxiliary Phase/Freq. Detector and Charge Pump Fpd_aux Fref Reference Frequency Oscillator CPout_main Lock Detection or Power Steering LD/PSmain LD/PSaux CPout_aux Lock Detection or Power Steering C1447 Figure 1. SKY72300-362 Functional Block Diagram Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 2 July 30, 2007 * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * 200731B DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER 24 23 22 21 20 VCCcml_main Fvco_main Fvco_main LD/PS_main VCCcp_main CPout_main VCCdigital 19 18 17 16 15 14 13 Mux_out Mod_in Clock Data CS 1 2 3 4 5 6 VCCcml_aux Fvco_aux Fvco_aux CPout_aux VCCcp_aux LD/PS_aux 7 8 9 10 11 12 Xtalacgnd/OSC Xtalout/NC N/C VCCxtal Xtalin/OSC GNDXtal S1055 Figure 2. SKY72300-362 Pinout, 24-Pin QFN Technical Description The SKY72300-362 is a fractional-N frequency synthesizer using a modulation technique. The fractional-N implementation provides low in-band noise by having a low division ratio and fast frequency settling time. In addition, the SKY72300-362 provides arbitrarily fine frequency resolution with a digital word, so that the frequency synthesizer can be used to compensate for crystal frequency drift in the RF transceiver. Serial Interface The serial interface is a versatile three-wire interface consisting of three pins: Clock (serial clock), Data (serial input), and CS (chip select). It enables the SKY72300-362 to operate in a system where one or multiple masters and slaves are present. To perform a loopback test at startup and to check the integrity of the board and processor, the serial data is fed back to the master device (e.g., a microcontroller or microprocessor unit) through a programmable multiplexer. This facilitates hardware and software debugging. Registers There are ten 16-bit registers in the SKY72300-362. For more information, see the Register Descriptions section of this document. Main and Auxiliary Modulators The fractionality of the SKY72300-362 is accomplished by the use of a proprietary, configurable 10-bit or 18-bit modulator for the main synthesizer and 10-bit modulator for the auxiliary synthesizer. Main and Auxiliary Fractional Units The SKY72300-362 provides fractionality through the use of main and auxiliary modulators. The output from the modulators is combined with the main and auxiliary divider ratios through their respective fractional units. VCO Prescalers The VCO prescalers provide low-noise signal conditioning of the VCO signals. They translate from an off-chip, single-ended or differential signal to an on-chip differential Current Mode Logic (CML) signal. The SKY72300-362 has independent main and auxiliary VCO prescalers. Main and Auxiliary VCO Dividers The SKY72300-362 provides programmable dividers that control the CML prescalers and supply the required signals to the charge pump phase detectors. Programmable divide ratios ranging from 38 to 537 are possible in fractional-N mode and from 32 to 543 in integer-N mode. Reference Frequency Oscillator The SKY72300-362 has a self-contained, low-noise crystal oscillator. This crystal oscillator is followed by the clock generation circuitry that generates the required clock for the programmable reference frequency dividers. Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 200731B * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * July 30, 2007 3 DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER Reference Frequency Dividers The crystal oscillator signal can be divided by a ratio of 1 to 32 to create the reference frequencies for the phase detectors. The SKY72300-362 has both a main and an auxiliary frequency synthesizer, and provides independently configurable dividers of the crystal oscillator frequency for both the main and auxiliary phase detectors. The divide ratios are programmed by the Reference Frequency Dividers Register. NOTE: The divided crystal oscillator frequencies (which are the internal reference frequencies), Fref_main and Fref_aux, are referred to as reference frequencies throughout this document. Phase Detectors and Charge Pumps The SKY72300-362 uses a separate charge pump phase detector for each synthesizer which provides a programmable gain, Kd, from 31.25 to 1000 A/2 radians in 32 steps programmed using the Phase Detector/Charge Pump Control Register. Frequency Steering When programmed for frequency power steering, the SKY72300362 has a circuit that helps the loop filter steer the VCO, through the LD/PSmain signal (pin 4). In this configuration, the LD/PSmain signal can provide for more rapid acquisition. When programmed for lock detection, internal frequency steering is implemented and provides frequency acquisition times comparable to conventional phase/frequency detectors. Figure 3 depicts how a serial transfer takes place functionally. A serial transfer is initiated when a microcontroller or microprocessor forces the CS line to a low state. This is followed immediately by an address/data stream sent to the Data pin that coincides with the rising edges of the clock presented on the Clock line. Each rising edge of the Clock signal shifts in one bit of data on the Data line into a shift register. At the same time, one bit of data is shifted out of the Mux_out pin (if the serial bit stream is selected) at each falling edge of Clock. To load any of the registers, 16 bits of address or data must be presented to the Data line with the LSB last while the CS signal is low. If the CS signal is low for more than 16 clock cycles, only the last address or data bits are used to load the registers. If the CS signal is brought to a high state before the 13th Clock edge, the bit stream is assumed to be modulation data samples. In this case, it is assumed that no address bits are present and that all the bits in the stream should be loaded into the Modulation Data Register. Register Programming Register programming equations, described in this section, use the following variables and constants: Nfractional Desired VCO division ratio in fractional-N applications. This is a real number and can be interpreted as the reference frequency (Fref) multiplying factor such that the resulting frequency is equal to the desired VCO frequency. Desired VCO division ratio in integer-N applications. This number is an integer and can be interpreted as the reference frequency (Fref) multiplying factor so that the resulting frequency is equal to the desired VCO frequency. Nine-bit unsigned input value to the divider ranging from 0 to 511 (integer-N mode) and from 6 to 505 (fractional-N mode). This constant equals 262144 when the modulator is in 18-bit mode, and 1024 when the modulator is in 10-bit mode. Ninteger Lock Detection When programmed for lock detection, the SKY72300-362 provides an active low, pulsing open collector output using the LD/PSmain signal (pin 4) to indicate the out-of-lock condition. When locked, the LD/PSmain signal is tri-stated (high impedance). Power Down The SKY72300-362 supports a number of power-down modes through the serial interface. For more information, see the Register Descriptions section of this document. Nreg divider Serial Interface Operation The serial interface consists of three pins: Clock (pin 22), Data (pin 20), and CS (pin 21). The Clock signal controls data on the two serial data lines (Data and CS). The Data pin bits shift into a temporary register on the rising edge of Clock. The CS line allows individual selection transfers that synchronize and sample the information of slave devices on the same bus. dividend When in 18-bit mode, this is the 18-bit signed input value to the modulator, ranging from -131072 to +131071 and providing 262144 steps, each step equal to Fdiv_ref/218 Hz. When in 10-bit mode, this is the 10-bit signed input value to the modulator, ranging from -512 to +511 and providing 1024 steps, each step equal to Fdiv_ref/210 Hz. Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 4 July 30, 2007 * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * 200731B DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER Clock Data X A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX CS Last C1413 Figure 3. Serial Transfer Timing Diagram FVCO Fdiv_ref Desired VCO frequency (either Fvco_main or Fvco_aux). Divided reference frequency presented to the phase detector (either Fref_main or Fref_aux). N int eger = Fvco _ main Fdiv _ ref Fractional-N Applications. The desired division ratio for the main and auxiliary synthesizers is given by: where Ninteger is an integer number from 32 to 543. The value to be programmed by the Main or Auxiliary Divider Register is given by: N reg = N int eger - 32 N fractional = FVCO Fdiv _ ref where Nfractional must be between 37.5 and 537.5. The value to be programmed by the Main or Auxiliary Divider Register is given by: N reg = Round ( N fractional ) - 32 When in integer mode, allowed values for Nreg are from 0 to 511 for both the main and auxiliary synthesizers. NOTE: As with all integer-N synthesizers, the minimum step size is related to the crystal frequency and reference frequency division ratio. A sample calculation for an integer-N application is provided in Figure 5. Register Loading Order. In applications where the main synthesizer is in 18-bit mode, the Main Dividend MSB Register holds the 10 MSBs of the dividend and the Main Dividend LSB Register holds the 8 LSBs of the dividend. The registers that control the main synthesizer's divide ratio are to be loaded in the following order: NOTE: The Round function rounds the number to the nearest integer. When in fractional mode, allowed values for Nreg are from 6 to 505 inclusive. The value to be programmed by either of the MSB/LSB Dividend Registers or the Auxiliary Dividend Register is given by: dividend = Round [ divider x( N fractional - N reg - 32 )] where the divider is either 1024 in 10-bit mode or 262144 in 18-bit mode. Therefore, the dividend is a signed binary value either 10 or 18 bits long. NOTE: Because of the high fractionality of the SKY72300-362, there is no practical need for any integer relationship between the reference frequency and the channel spacing or desired VCO frequencies. Sample calculations for two fractional-N applications are provided in Figure 4. Integer-N Applications. The desired division ratio for the main or auxiliary synthesizer is given by: * Main Divider Register * Main Dividend LSB Register * Main Dividend MSB Register (at which point the new divide ratio takes effect) In applications where the main synthesizer is in 10-bit mode, the Main Dividend MSB Register holds the 10 bits of the dividend. The registers that control the main synthesizer's divide ratio are to be loaded in the following order: * Main Divider Register * Main Dividend MSB Register (at which point the new divide ratio takes effect) Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 200731B * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * July 30, 2007 5 DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER Case 1: To achieve a desired Fvco_main frequency of 902.4530 MHz using a crystal frequency of 40 MHz with operation of the synthesizer in 18-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal frequency is divided by 2 to obtain a Fdiv_ref of 20 MHz. Therefore: Nfractional = Fvco_main Fdiv_ref = 902.4530 20 = 45.12265 The value to be programmed in the Main Divider Register is: Nreg = Round[Nfractional] - 32 = Round[45.12265] - 32 = 45 - 32 = 13 (decimal) = 000001101 (binary) With the modulator in 18-bit mode, the value to be programmed in the Main Dividend Registers is: dividend = Round[divider x (Nfractional - Nreg - 32)] = Round[262144 x (45.12265 - 13 - 32)] = Round[262144 x (0.12265)] = Round[32151.9616] = 32152 (decimal) = 000111110110011000 (binary) where 00 0111 1101 is loaded in the MSB of the Main Dividend Register and 1001 1000 is loaded in the LSB of the Main Dividend Register. Summary: * * * * * Main Divider Register = 0 0000 1101 Main Dividend Register, LSB = 1001 1000 Main Dividend Register, MSB = 00 0111 1101 The resulting main VCO frequency is 902.453 MHz Step size is 76.3 Hz Note: The frequency step size for this case is 20 MHz divided by 218, giving 76.3 Hz. C1414 Figure 4. Fractional-N Applications: Sample Calculation (1 of 2) Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 6 July 30, 2007 * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * 200731B DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER Case 2: To achieve a desired Fvco_main frequency of 917.7786 MHz using a crystal frequency of 19.2 MHz with operation of the synthesizer in 10-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal frequency does not require the internal division to be greater than 1, which makes Fdiv_ref = 19.2 MHz. Therefore: Nfractional = Fvco_main Fdiv_ref = 917.7786 19.2 = 47.80097 The value to be programmed in the Main Divider Register is: Nreg = Round[Nfractional] - 32 = Round[47.80087] - 32 = 48 - 32 = 16 (decimal) = 000010000 (binary) With the modulator in 10-bit mode, the value to be programmed in the Main Dividend Registers is: dividend = Round[divider x (Nfractional - Nreg - 32)] = Round[1024 x (47.80087 - 16 - 32)] = Round[1024x (-0.1990312)] = Round[-203.808] = 204 (decimal) = 1100110100 (binary) where 11 0011 0100 is loaded in the MSB of the Main Dividend Register. Summary: * * * * Main Divider Register = 0 0001 0000 Main Dividend Register, MSB = 11 0011 0100 The resulting main VCO frequency is 917.775 MHz Step size is 18.75 kHz Note: The frequency step size for this case is 19.2 MHz divided by 210, giving 18.75 kHz. C1415 Figure 4. Fractional-N Applications: Sample Calculation (2 of 2) Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 200731B * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * July 30, 2007 7 DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER Case 1: To achieve a desired Fvco_aux frequency of 400 MHz using a crystal frequency of 16 MHz. Since the minimum divide ratio is 32, the reference frequency (Fdiv_ref) must be a maximum of 12.5 MHz. Choosing a reference frequency divide ratio of 2 provides a reference frequency of 8 MHz. Therefore: Ninteger = Fvco_aux Fdiv_ref 400 8 50 = = The value to be programmed in the Auxiliary Divider Register is: Nreg = Ninteger - 32 = 50 - 32 = 18 (decimal) = 000010010 (binary) Summary: * Auxiliary Divide Register = 0 0001 0010 C1416 Figure 5. Integer-N Applications: Sample Calculation For the auxiliary synthesizer, the Auxiliary Dividend Register holds the 10 bits of the dividend. The registers that control the auxiliary synthesizer's divide ratio are to be loaded in the following order: presented to the Data pin. The content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). Short CS Through Data Pin (No Address Bits Required). A shortened serial interface write occurs when the CS signal is from 2 to 12 clock cycles wide. The corresponding modulation data (2 to 12 bits) is simultaneously presented to the Data pin. The Data pin is the default pin used to enter modulation data directly in the Modulation Data Register with shortened CS strobes. This method of data entry eliminates the register address overhead on the serial interface. All serial interface bits are resynchronized internally at the reference oscillator frequency. The content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). Short CS Through Mod_in Pin (No Address Bits Required). A shortened serial interface write occurs when the CS signal is from 2 to 12 clock cycles wide. The corresponding modulation data (2 to 12 bits) is simultaneously presented on the Mod_in pin, an alternate pin used to enter modulation data directly into the Modulation Data Register with shortened CS strobes. This mode is selected through the Modulation Control Register. * Auxiliary Divider Register * Auxiliary Dividend Register (at which point the new divide ratio takes effect) NOTE: When in integer mode, the new divide ratios take effect as soon as the Main or Auxiliary Divider Register is loaded. Direct Digital Modulation The high fractionality and small step size of the SKY72300-362 allow the user to tune to practically any frequency in the VCO's operating range. This allows direct digital modulation by programming the different desired frequencies at precise instants. Typically, the channel frequency is programmed by the Main Divider and MSB/LSB Dividend Registers, and the instantaneous frequency offset from the carrier is programmed by the Modulation Data Register. The Modulation Data Register can be accessed in three ways as defined in the following subsections. Normal Register Write. A normal 16-bit serial interface write occurs when the CS signal is 16 clock cycles wide. The corresponding 16-bit modulation data is simultaneously Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 8 July 30, 2007 * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * 200731B DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER Table 1. SKY72300-362 Register Map Address (Hex) 0 1 2 3 4 5 6 7 8 9 -- Main Divider Register Main Dividend MSB Register Main Dividend LSB Register Auxiliary Divider Register Auxiliary Dividend Register Reference Frequency Dividers Register Phase Detector/Charge Pump Control Register Power Down/Multiplexer Output Select Control Register Modulation Control Register Modulation Data Register Modulation Data Register (Note 2) -- direct input Register (Note 1) Length (Bits) 12 12 12 12 12 12 12 12 12 12 2 length 12 bits Address (Bits) 4 4 4 4 4 4 4 4 4 4 0 Note 1: All registers are write only. Note 2: No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data. This method of data entry also eliminates the register address overhead on the serial interface and allows a different device than the one controlling the channel selection to enter the modulation data (e.g., a microcontroller for channel selection and a digital signal processor for modulation data). All serial interface bits are internally re-synchronized at the reference oscillator frequency and the content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). Modulation data samples in the Modulation Data Register can be from 2 to 12 bits long, and enable the user to select how many distinct frequency steps are to be used for the desired modulation scheme. The user can also control the frequency deviation through the modulation data magnitude offset in the Modulation Control Register. This allows shifting of the modulation data to accomplish a 2m multiplication of frequency deviation. NOTE: The programmable range of -0.5 to +0.5 of the main modulator can be exceeded up to the condition where the sum of the dividend and the modulation data conform to: -0.5625 ( N mod + dividend ) + 0.5625 Register Descriptions Table 1 lists the 10 16-bit registers that are used to program the SKY72300-362. All register writes are programmed address first, followed directly with data. MSBs are entered first. On power up, all registers are reset to 0x000 except registers at addresses 0x0 and 0x3, which are set to 0x006. Main Synthesizer Registers The Main Divider Register contains the integer portion closest to the desired fractional-N (or the integer-N) value minus 32 for the main synthesizer. This register, in conjunction with the Main Dividend MSB and LSB Registers (which control the fraction offset from -0.5 to +0.5), allows selection of a precise frequency. As shown in Figure 6, the value to be loaded is: * Main Synthesizer Divider Index = Nine-bit value for the integer portion of the main synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or 0 to 511 (integer-N). The Main Dividend MSB and LSB Registers control the fraction part of the desired fractional-N value and allow an offset of -0.5 to +0.5 to the main integer selected through the Main Divider Register. As shown in Figures 7 and 8, values to be loaded are: When the sum of the dividend and modulation data lie outside this range, the value of Ninteger must be changed. For a more detailed description of direct digital modulation functionality, refer to the Skyworks Application Note, Direct Digital Modulation Using the SKY72300, SKY72301, and SKY72302 Dual Synthesizers/PLLs (document number 101349). * Main Synthesizer Dividend (MSBs) = Ten-bit value for the MSBs of the 18-bit dividend for the main synthesizer. * Main Synthesizer Dividend (LSBs) = Eight-bit value for the LSBs of the 18-bit dividend for the main synthesizer. The Main Dividend Register MSB and LSB values are 2's complement format. NOTE: When in 10-bit mode, the Main Dividend LSB Register is not required. Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 200731B * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * July 30, 2007 9 DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER A3 0 A2 0 A1 0 A0 0 11 X 10 X 9 X 8 MSB 7 6 5 4 3 2 1 0 LSB Main Synthesizer Divider Index C1417 Figure 6. Main Divider Register (Write Only) A3 0 A2 0 A1 0 A0 1 11 X 10 X 9 MSB 8 7 6 5 4 3 2 1 0 LSB Main Synthesizer Dividend (MSBs) C1418 Figure 7. Main Dividend MSB Register (Write Only) A3 0 A2 0 A1 1 A0 0 11 X 10 X 9 X 8 X 7 MSB 6 5 4 3 2 1 0 LSB Main Synthesizer Dividend (LSBs) C1419 Figure 8. Main Dividend LSB Register (Write Only) Auxiliary Synthesizer Registers The Auxiliary Divider Register contains the integer portion closest to the desired fractional-N (or integer-N) value minus 32 for the auxiliary synthesizer. This register, in conjunction with the Auxiliary Dividend Register (which controls the fraction offset from -0.5 to +0.5), allows selection of a precise frequency. As shown in Figure 9, the value to be loaded is: Auxiliary Synthesizer Divider Index = Nine-bit value for the integer portion of the auxiliary synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or from 0 to 511 (integerN).The Auxiliary Dividend Register controls the fraction part of the desired fractional-N value and allows an offset of -0.5 to +0.5 to the auxiliary integer selected through the Auxiliary Divider Register. As shown Figure 10, the value to be loaded is: General Synthesizer Registers The dual-programmable reference frequency dividers provide the reference frequencies to the phase detectors by dividing the crystal oscillator frequency. The lower five bits hold the reference frequency divide index for the main phase detector. The next five bits hold the reference frequency divide index for the auxiliary phase detector. Divide ratios from 1 to 32 are possible for each reference frequency divider (see Tables 2 and 3). The Reference Frequency Dividers Register configures the dualprogrammable reference frequency dividers for the main and auxiliary synthesizers. As shown in Figure 11, the values to be loaded are: * Auxiliary Synthesizer Dividend = Ten-bit value for the auxiliary synthesizer dividend. * Main Reference Frequency Divider Index = Desired main oscillator frequency division ratio -1. Default value on power up is 0, signifying that the reference frequency is not divided for the main phase detector. * Auxiliary Reference Frequency Divider Index = Desired auxiliary oscillator frequency division ratio -1. Default value on power up is 0, signifying that the reference frequency is not divided for the auxiliary phase detector. Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 10 July 30, 2007 * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * 200731B DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER A3 0 A2 0 A1 1 A0 1 11 X 10 X 9 X 8 MSB 7 6 5 4 3 2 1 0 LSB Auxiliary Synthesizer Divider Index C1420 Figure 9. Auxiliary Divider Register (Write Only) A3 0 A2 1 A1 0 A0 0 11 X 10 X 9 MSB 8 7 6 5 4 3 2 1 0 LSB Auxiliary Synthesizer Dividend C1421 Figure 10. Auxiliary Dividend Register (Write Only) Table 2. Programming the Main Reference Frequency Divider Decimal 0 1 2 -- -- -- 31 Bit 4 (MSB) 0 0 0 -- -- -- 1 Bit 3 0 0 0 -- -- -- 1 Bit 2 0 0 0 -- -- -- 1 Bit 1 0 0 1 -- -- -- 1 Bit 0 (LSB) 0 1 0 -- -- -- 1 Reference Divider Ratio 1 2 3 -- -- -- 32 Table 3. Programming the Auxiliary Reference Frequency Divider Decimal 0 1 2 -- -- -- 31 Bit 9 (MSB) 0 0 0 -- -- -- 1 Bit 8 0 0 0 -- -- -- 1 Bit 7 0 0 0 -- -- -- 1 Bit 6 0 0 1 -- -- -- 1 Bit 5 (LSB) 0 1 0 -- -- -- 1 Reference Divider Ratio 1 2 3 -- -- -- 32 Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 200731B * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * July 30, 2007 11 DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER A3 0 A2 1 A1 0 A0 1 11 X 10 X 9 8 7 6 5 4 3 2 1 0 Main Reference Frequency Divider Index Auxiliary Reference Frequency Divider Index C1422 Figure 11. Reference Frequency Dividers Register (Write Only) A3 0 A2 1 A1 1 A0 0 11 10 9 8 7 6 5 4 3 2 1 0 Main Phase Detector Gain Main Power Steering/Lock Detect Enable Auxiliary Phase Detector Gain Auxiliary Power Steering/Lock Detect Enable C1423 Figure 12. Phase Detector/Charge Pump Control Register (Write Only) The Phase Detector/Charge Pump Control Register allows control of the gain for both phase detectors and configuration of the LD/PSmain and LD/PSaux signals for frequency power steering or lock detection. As shown in Figure 12, the values to be loaded are: frequency power steering pin and may be used to bypass the external auxiliary loop filter to provide faster frequency acquisition. The Power Down/Multiplexer Output Select Control Register allows control of the power-down modes, internal multiplexer output, and main synthesizer fractionality. As shown in Figure 13, the values to be loaded are: * Main Phase Detector Gain = Five-bit value for programmable main phase detector gain. Range is from 0 to 31 decimal for 31.25 to 1000 A/ 2 radian, respectively. * Main Power Steering Enable = One-bit flag to enable the frequency power steering circuitry of the main phase detector. When this bit is cleared, the LD/PSmain pin is configured to be a lock detect, active low, open collector pin. When this bit is set, the LD/PSmain pin is configured to be a frequency power steering pin and can be used to bypass the external main loop filter to provide faster frequency acquisition. * Auxiliary Phase Detector Gain = Five-bit value for programmable auxiliary phase detector gain. Range is from 0 to 31 decimal for 31.25 to 1000 A/2 radians, respectively. * Auxiliary Power Steering Enable = One-bit flag to enable the frequency power steering circuitry of the auxiliary phase detector. When this bit is cleared, the LD/PSaux pin is configured to be a lock detect, active low, open collector pin. When this bit is set, the LD/PSaux pin is configured to be a * Full Power Down = One-bit flag to power down the SKY72300362 except for the reference oscillator and the serial interface. When this bit is cleared, the SKY72300-362 is powered up. When this bit is set, the SKY72300-362 is in full power-down mode excluding the Mux_out signal (pin 24). * Main Synthesizer Power Down = One-bit flag to power down the main synthesizer. When this bit is cleared, the main synthesizer is powered up. When this bit is set, the main synthesizer is in power-down mode. * Main Synthesizer Mode = One-bit flag to power down the main synthesizer's modulator and fractional unit to operate as an integer-N synthesizer. When this bit is cleared, the main synthesizer is in fractional-N mode. When this bit is set, the main synthesizer is in integer-N mode. Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 12 July 30, 2007 * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * 200731B DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER A3 0 A2 1 A1 1 A0 1 11 X 10 X 9 8 MSB 7 6 LSB 5 4 3 2 1 0 Full Power Down Main Synthesizer Power Down Main Synthesizer Mode Main Synthesizer Fractionality Auxiliary Synthesizer Power Down Auxiliary Synthesizer Mode Multiplexer Output Selection Mux_out Pin Tri-State Enable C1424 Figure 13. Power Down and Multiplexer Output Register (Write Only) Table 4. Multiplexer Output Multiplexer Output Select (Bit 8) 0 0 0 0 1 1 1 1 Multiplexer Output Select (Bit 7) 0 0 1 1 0 0 1 1 Multiplexer Output Select (Bit 6) 0 1 0 1 0 1 0 1 Multiplexer Output (Mux_out) Reference Oscillator Auxiliary Reference Frequency (Fref_aux) Main Reference Frequency (Fref_main) Auxiliary Phase Detector Frequency (Fpd_aux) Main Phase Detector Frequency (Fpd_main) Serial data out Serial interface test output Unused * Main Synthesizer Fractionality = One-bit flag to configure the size of the main modulator. This has a direct effect on power consumption, and on the level of fractionality and step size. When this bit is cleared, the main modulator is 18-bit with a fractionality of 218 and a step size of Fref_main/262144. When this bit is set, the main modulator is 10-bit with a fractionality of 210 and a step size of Fref_main/1024. * Auxiliary Synthesizer Power Down = One-bit flag to power down the auxiliary synthesizer. When this bit is cleared, the auxiliary synthesizer is powered up. When this bit is set, the auxiliary synthesizer is in power-down mode. * Auxiliary Synthesizer Mode = One-bit flag to power down the auxiliary synthesizer's modulator and fractional unit to operate as an integer-N synthesizer. When this bit is cleared, the auxiliary synthesizer is in fractional-N mode. When this bit is set, the auxiliary synthesizer is in integer-N mode. NOTE: There are no special power-up sequences required for the SKY72300-362. * Multiplexer Output Selection = Three-bit value that selects which internal signal is output to the Mux_out pin. The following internal signals are available on this pin: - Reference oscillator: Fref - Main or auxiliary divided reference (post-reference frequency main or auxiliary dividers): Fref_main or Fref_aux - Main or auxiliary phase detector frequency (post-main or auxiliary frequency dividers): Fpd_main or Fpd_aux - Serial data out for loop-back and test purposes Refer to Table 4 for more information. * Mux_out Pin Tri-State Enable = One-bit flag to tri-state the Mux_out pin. When this bit is cleared, the Mux_out pin is enabled. When this bit is set, the Mux_out pin is tri-stated. Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 200731B * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * July 30, 2007 13 DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER A3 1 A2 0 A1 0 A0 0 11 X 10 X 9 8 7 6 5 4 3 0 2 0 1 0 0 0 Reserved Bits Modulation Data Magnitude Offset Modulation Data Input Select Modulation Address Disable C1425 Figure 14. Modulation Control Register (Write Only) A3 1 A2 0 A1 0 A0 1 11 MSB 10 9 8 7 6 5 4 3 2 1 0 LSB Modulation Data Bits C1426 Figure 15. Modulation Data Register (Write Only) The Modulation Control Register is used to configure the modulation unit of the main synthesizer. The modulation unit adds or subtracts a frequency offset to the selected center frequency at which the main synthesizer operates. The size of the modulation data sample, controlled by the duration of the CS signal, can be from 2 to 12 bits wide to provide from 4 to 4096 selectable frequency offset steps. The modulation data magnitude offset selects the magnitude multiplier for the modulation data and can be from 0 to 8. As shown in Figure 14, the values to be loaded are: no address is presented with the modulation data samples (i.e., all transfers are 2 to 12 bits long). The Modulation Data Register is used to load the modulation data samples to the modulation unit. These values are transferred to the modulation unit on the falling edge of Fpd_main where they are passed to the main modulator at the selected magnitude offset on the next falling edge of Fpd_main. Modulation Data Register values are 2's complement format. As shown in Figure 15, the value to be loaded is: * Modulation Data Magnitude Offset = Four-bit value that indicates the magnitude multiplier (m) for the modulation data samples. Valid values range from 0 to 13, effectively providing a 2m multiplication of the modulation data sample. * Modulation Data Input Select = One-bit flag to indicate the pin on which modulation data samples are serially input when the CS signal is between 2 and 12 bits long. When this bit is cleared, modulation data samples are to be presented on the Data pin. When this bit is set, modulation data samples are to be presented on the Mod_in pin. * Modulation Address Disable = One-bit flag to indicate the presence of the address as modulation data samples are presented on either the Mod_in or Data pins. When this bit is cleared, the address is presented with the modulation data samples (i.e., all transfers are 16 bits long). When this bit is set, * Modulation Data Bits = Modulation data samples that represent the instantaneous frequency offset to the selected main synthesizer frequency (selected channel) before being affected by the modulation data magnitude offset. Package and Handling Information Since the device package is sensitive to moisture absorption, it is baked and vacuum packed before shipping. Instructions on the shipping container label regarding exposure to moisture after the container seal is broken must be followed. Otherwise, problems related to moisture absorption may occur when the part is subjected to high temperature during solder assembly. The SKY72300-362 is rated to Moisture Sensitivity Level 3 (MSL3) at 260 C. It can be used for lead or lead-free soldering. Care must be taken when attaching this product, whether it is done manually or in a production solder reflow environment. Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 14 July 30, 2007 * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * 200731B DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER Production quantities of this product are shipped in a standard tape and reel format. For packaging details, refer to the Skyworks Application Note, Tape and Reel, document number 101568. operating conditions are specified in Table 7 and electrical specifications are provided in Table 8. Figure 16 provides a schematic diagram for the SKY72300-362. Figure 17 shows the package dimensions for the 24-pin QFN and Figure 18 provides the tape and reel dimensions. Electrical and Mechanical Specifications The SKY72300-362 is supplied as a 24-pin QFN. The exposed pad is located on the bottom side of the package and must be connected to ground for proper operation. The exposed pad should be soldered directly to the circuit board. Signal pin assignments and functional pin descriptions are described in Table 5. The absolute maximum ratings of the SKY72300-362 are provided in Table 6. The recommended Table 5. SKY72300-362 Signal Descriptions (1 of 2) Pin # 1 2 3 4 Pin Name VCCcml_main Fvco_main Fvco_main LD/PS_main Type Power and ground Input Input Analog output Electrostatic Discharge (ESD) Sensitivity The SKY72300-362 is a static-sensitive electronic device. Do not operate or store near strong electrostatic fields. Take proper ESD precautions. Description Emitter Coupled Logic/Current Mode Logic (ECL/CML), 3 V. Removing power safely powers down the associated divider chain and charge pump. Main VCO differential input. Main VCO complimentary differential input. Programmable output pin. Indicates phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or helps the loop filter steer the VCO. This pin is configured using the Phase Detector/Charge Pump Control Register. Charge pump supply, 3 to 5 V. Removing power safely powers down the associated divider chain and charge pump. Charge pump output. The gain of the charge pump phase detector is controlled by the Phase Detector/Charge Pump Control Register. No connection Reference crystal AC ground or external oscillator differential input. Reference crystal input or external oscillator differential input. Reference crystal output or no connect. Crystal oscillator ECL/CML, 3 V. Crystal oscillator ground. Programmable output pin. Indicates auxiliary phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or helps the loop filter steer the auxiliary VCO. This pin is configured using the Phase Detector/Charge Pump Control Register. Auxiliary charge pump supply, 3 to 5 V. Removing power safely powers down the associated divider chain and charge pump. Auxiliary charge pump output. The gain of the auxiliary charge pump phase detector is controlled by the Phase Detector/Charge Pump Control Register. Auxiliary VCO complimentary differential input. Auxiliary VCO differential input. ECL/CML, 3 V. Removing power safely powers down the associated divider chain and charge pump. Digital supply, 3 V. Serial address and data input pin. Address bits are followed by data bits. 5 6 7 8 9 10 11 12 13 VCCcp_main (Note 1) CPout_main N/C Xtalacgnd/OSC Xtalin/OSC Xtalout/NC VCCxtal GNDxtal LD/PS_aux Power and ground Analog output - Ground/input Input Input Power and ground Power and ground Analog output 14 15 16 17 18 19 20 VCCcp_aux (Note 1) CPout_aux Fvco_aux Fvco_aux VCCcml_aux (Note 1) VCCdigital (Note 1) Data Power and ground Analog output Input Input Power and ground Power and ground Digital input Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 200731B * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * July 30, 2007 15 DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER Table 5. SKY72300-362 Signal Descriptions (2 of 2) Pin # 21 CS Pin Name Type Digital input Description Active low enable pin. Enables loading of address and data on the Data pin on the rising edge of Clock. When CS goes high, data is transferred to the register indicated by the address. Subsequent clock edges are ignored. Clock signal pin. When CS is low, the register address and data are shifted in address bits first on the Data pin on the rising edge of Clock. Alternate serial modulation data input pin. Address bits are followed by data bits. Internal multiplexer output. Selects from oscillator frequency, reference frequency, divided VCO frequency, serial data out, or testability signals. This pin can be tri-stated from the synthesizer registers. 22 23 24 Clock Mod_in Mux_out Digital input Digital input Digital output Note 1: Associated pairs of power and ground pins must be decoupled using 0.1 F capacitors. Table 6. Absolute Maximum Ratings Parameter Maximum analog RF supply voltage Maximum digital supply voltage Maximum charge pump supply voltage Storage temperature Operating temperature Note: Min Max 3.6 3.6 5.25 Units VDC VDC VDC C C -65 -40 +150 +85 Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other parameters set at or below their nominal values. Table 7. Recommended Operating Conditions Parameter Analog RF supplies Digital supply Charge pump supplies Operating temperature (TA) Note 1: When power steering is enabled, the charge pump must be 4.5 V maximum. Min 2.7 2.7 2.7 -40 Max 3.3 3.3 5.0 (Note 1) +85 Units VDC VDC VDC C Table 8. Electrical Characteristics (1 of 2) (VDD = 3 V, TA = 25 C, Unless Otherwise Noted) Parameter Power Consumption Total power consumption PTOTAL Charge pump currents of 200 A. Both synthesizers fractional, FREF_MAIN = 20 MHz, FREF_AUX = 1 MHz Auxiliary synthesizer power down Power-down current Reference Oscillator Reference oscillator frequency Oscillator sensitivity (as a buffer) Frequency shift versus supply voltage FOSC VOSC FSHIFT_SUPPLY AC coupled, single-ended 2.7 V VXTAL 3.3 V 0.1 50 2.0 0.3 MHz Vpp ppm ICC_PWDN 37.5 mW Symbol Test Conditions Min Typ Max Units 27 10 (Note 1) mW A Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 16 July 30, 2007 * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * 200731B DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER Table 8. Electrical Characteristics (2 of 2) (VDD = 3 V, TA = 25 C, Unless Otherwise Noted) Parameter VCOs Main synthesizer operating frequency Auxiliary synthesizer operating frequency RF input sensitivity RF input impedance Main fractional-N tuning step size Auxiliary fractional-N tuning step size Noise Phase noise floor PNF Measured inside the loop bandwidth using 25 MHz reference frequency, -40 C to +85 C -128 + 20 Log (N) dBc/Hz FVCO_MAIN FVCO_AUX VVCO ZVCO_IN FSTEP_MAIN FSTEP_AUX Sinusoidal, -40 C to +85 C Sinusoidal, -40 C to +85 C AC coupled 100 (Note 2) 100 (Note 2) 50 94 - j140 @ 1200 MHz FREF_MAIN/218 or FREF_MAIN/210 FREF_AUX/2 10 Symbol Test Conditions Min Typ Max Units 2100 500 250 MHz MHz mVPEAK Hz Hz Phase Detectors and Charge Pumps Main phase detector frequency Auxiliary phase detector frequency Charge pump output source current Charge pump output sink current Charge pump accuracy Charge pump output voltage linearity range Charge pump current versus temperature Charge pump current versus voltage Digital Pins High level input voltage Low level input voltage High level output voltage Low level output voltage Timing - Serial Interface Clock frequency Data and CS set up time to Clock rising Data and CS hold time after Clock rising fCLOCK tSU tHOLD 3 0 100 MHz ns ns VIH FREF_MAIN FREF_AUX ICP-SOURCE ICP-SINK ICP-ACCURACY ICP vs VCP ICP vs T ICP vs VCP -40 C to +85 C -40 C to +85 C VCP = 0.5 VCCCP VCP = 0.5 VCCCP 0.5 V VCP (VCCCP - 0.5 V) VCP = 0.5 VCCCP -40 C < T < +85 C 0.5 V VCP (VCCCP - 0.5 V) 125 -125 20 GND + 400 25 25 1000 -1000 MHz MHz A A % VCCCP - 400 5 8 mV % % 0.7 VDIGITAL 0.3 VDIGITAL IOH = -2 mA IOL = +2 mA VDIGITAL -0.2 GND + 0.2 V V V V VIL VOH VOL Note 1: A 5 V charge pump power supply (on pin 5) results in higher power-down leakage current. Note 2: The minimum synthesizer frequency is 12 x FOSC, where FOSC is the frequency at the Xtalin/OSC pin. Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 200731B * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * July 30, 2007 17 DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER VCCMecl/cml 3V R4 DNI C1 DNI C2 DNI To Microprocessor J1 C5 68 pF 1 6 VCC GND GND VNA-25 DNI IN GND GND GND OUT 8 3 R74 18 R73 120 75 42 R75 120 R76 18 VCCMecl/cml 3V R22 DNI VNA-25 DNI 3 IN GND GND GND VCCMecl/cml 3V R16 10 R30 10 C15 1 F C16 100 pF C18 22 pF x C20 22 pF 1 24 23 22 21 20 19 Clock 1 VCC GND GND VCCdigital Mux_out Mod_in Data CS C14 DNI C13 DNI R24 18 VCCD_FNFS J2 Auxiliary RF Out 3V CD9 1 F CD10 100 pF VCCcml_main Fvco_main Fvco_main OUT 6 VCCEXT1 JP5 1 2 R36 120 R26 120 R32 18 R39 18 C30 39 pF OSC2 2 2 45 78 R33 18 R34 18 C22 DNI ETC1-1-13 5 4 T2 1 2 3 2 VCCcml_aux Fvco_aux Fvco_aux LD/PSmain VCCcp_main CPout_aux VCCcp_aux 18 17 C4 100 pF C6 100 pF C1 1 nF Auxiliary VCO GND 4 2 RFOUT VT 1 VCC 3 3 4 VCCMecl/cml 3V R80 10 R56 DNI 3 16 15 14 3V R52 DNI R48 2 k VCCCPM 3V 5 C8 470 pF C10 1 nF Xtalin/OSC VT JP1 1 2 VCCMecl/cml 3V R13 DNI R46 0 C45 100 pF C46 470 pF R58 0 C53 0.022 F N/C 1 V614ME01 R47 2 k VCCxtal GND GNDXtal 4 C47 330 pF R51 750 7 8 Xtalout/NC C48 68 pF C49 1 nF C50 1 F 6 Xtalacgnd/OCS VCC RFOUT R40 C25 10 1 F C26 100 pF CPout_main LD/PS_aux 13 3V R3 470 C12 27 nF R2 1.2 k C9 680 pF Auxiliary Synthesizer Loop Filter R44 10 9 10 11 12 x VCCXA 3V L1 DNI R83 0 R84 0 C36 1 F C42 22 pF C37 1 nF R21 0 C34 1 F C35 100 pF C41 22 pF Y1 24 MHz Power Supply C64 0.1 F VCCD_FNFS L6 BLM21A601S VCCCPM 3V 3V VCCMecl/cml 3V R49 DNI R6 100 Lock Detect Auxiliary Output R69 0 JP4 1 2 R68 0 C63 10 F + L7 BLM21A601S L2 DNI VCXA 3V C43 DNI C65 10 F + C44 DNI C66 0.1 F L8 BLM21A601S R71 0 A1 ERA-3SM DNI 1 IN 3 C74 DNI J6 DNI GND OUT 4 L3 BLM21A601S C60 0.1 F VCCMecl/cml 3V C51 DNI C52 DNI R57 DNI R61 DNI R59 DNI 2 C59 10 F + VCCMecl/cml 3V R72 DNI C55 DNI C56 DNI TTS05V-19.2MHz DNI 4 2 VDD GND OUT VCONT 3 1 GND C54 DNI R60 DNI J3 L11 BLM21A601S C71 10 F + L10 BLM21A601S C70 0.1 F + VCCMecl/cml 3V R62 R63 DNI DNI C72 0.1 F L12 BLM21A601S C68 10 F + C57 DNI C58 DNI S1058 Figure 16. SKY72300-362 Application Schematic Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 18 July 30, 2007 * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * 200731B DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER C 4 Pin 1 Indicator 2.70 +0.10/-0.15 Exposed Pad 0.02 +0.03/-0.023 See Detail A A B 0.20 Ref Seating Plane 4 2.500 -B- 2X 0.15 C 24X 3 0.08 C 2X 0.15 C Detail C 2.500 Detail B (4 Places) 0.90 0.10 0.10 C Top View Side View Bottom View 0.5 R0.20 0.25 0.35 0.10 0.25 +0.05/-0.07 0.100 M C A B 0.05 M C Detail A -A- All measurements are in millimeters. Dimensioning and tolerancing according to ASME Y14.5M-1994. Detail C Detail B (Even Terminal Side) S1054 Figure 17. SKY72300-362 24-Pin QFN Package Dimensions 8.00 0.10 1.13 0.10 Reference Pin Indicator 4.00 0.10 1.50 0.10 2.00 0.05 1.75 0.10 B 5.50 0.05 A 4.25 0.10 A 10o Max 0.229 0.02 B 1.50 0.25 B Notes: 1. Carrier tape material: black conductive polycarbonate or polysterene 2. Cover tape material: transparent conductive PSA 3. Cover tape size: 9.3 mm width 4. All measurements are in millimeters 4.25 0.10 10o Max A S1056 Figure 18. SKY72300-362 Tape and Reel Dimensions Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 200731B * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * July 30, 2007 12.00 +0.30/-0.10 2.70 +0.10/-0.15 19 DATA SHEET * SKY72300-362 FREQUENCY SYNTHESIZER Ordering Information Model Name SKY72300-362 2.1 GHz Frequency Synthesizer Manufacturing Part Number SKY72300-362 (Pb-free package) Evaluation Kit Part Number TW14-D790 Copyright (c) 2007 Skyworks Solutions, Inc. All Rights Reserved. Information in this document is provided in connection with Skyworks Solutions, Inc. ("Skyworks") products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes. No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks Terms and Conditions of Sale. THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale. Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of stated published specifications or parameters. Skyworks, the Skyworks symbol, and "Breakthrough Simplicity" are trademarks or registered trademarks of Skyworks Solutions, Inc., in the United States and other countries. Third-party brands and names are for identification purposes only, and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at www.skyworksinc.com, are incorporated by reference. Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com 20 July 30, 2007 * Skyworks Proprietary and Confidential information * Products and Product Information are Subject to Change Without Notice * 200731B |
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