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DATA SHEET
SKY72302: Spur-Free, 6.1 GHz Dual Fractional-N Frequency Synthesizer
Applications
* General purpose RF systems * 2.5G and 3G wireless infrastructures * Broadband wireless access * Low bit rate wireless telemetry * Wireless Local Loop (WLL) * Instrumentation * 3 V operation * 5 V output to loop filter * EP-TSSOP (28-pin, 9.7 x 6.4 x 1.1 mm) Pb-free (MSL3, 260 C per JEDEC J-STD-020) package
Description
Skyworks SKY72302 direct digital modulation fractional-N frequency synthesizer provides ultra-fine frequency resolution, fast switching speed, and low phase-noise performance. This synthesizer is a key building block for high-performance radio system designs that require low power and fine step size. The ultra-fine step size of less than 400 Hz allows this synthesizer to be used in very narrowband wireless applications. With proper temperature sensing or through control channels, the synthesizer's fine step size can compensate for crystal oscillator or Intermediate Frequency (IF) filter drift. As a result, crystal oscillators or crystals can replace temperature-compensated or ovenized crystal oscillators, reducing parts count and associated component cost. The device's fine step size can also be used for Doppler shift corrections. The SKY72302 has a phase noise floor of -80 dBc/Hz up to 6.1 GHz operation as measured inside the loop bandwidth. This is permitted by the on-chip low noise dividers and low divide ratios provided by the device's high fractionality. Reference crystals or oscillators up to 50 MHz can be used with the SKY72302. The crystal frequency is divided down by independent programmable dividers (1 to 32) for the main and auxiliary synthesizers. The phase detectors can operate at a maximum speed of 25 MHz, which allows better phase noise due to the lower division value. With a high reference frequency, the loop bandwidths can also be increased. Larger loop bandwidths improve the settling times and reduce in-band phase noise. Therefore, typical switching times of less than 100 s can be achieved. The lower in-band phase noise also permits the use of lower cost Voltage Controlled Oscillators (VCOs) in customer applications. The SKY72302 has a frequency power steering circuit that helps the loop filter to steer the VCO when the frequency is too fast or too slow, further enhancing acquisition time.
Features
* Spur-free operation * 6.1 GHz maximum operating frequency * 1000 MHz maximum auxiliary synthesizer * Ultra-fine step size, 400 Hz or less * High internal reference frequency enables large loop bandwidth implementations * Very fast switching speed (e.g., below 100 s) * Phase noise to -80 dBc/Hz inside loop filter bandwidth @ 6100 MHz * Software programmable power-down modes * High speed serial interface up to 100 Mbps * Three-wire programming * Programmable division ratios on reference frequency * Phase detectors with programmable gains to provide a programmable loop bandwidth * Frequency power steering further enhances rapid acquisition time * On-chip crystal oscillator * Frequency adjust for temperature compensation * Direct digital modulation Skyworks offers lead (Pb)-free, RoHS (Restriction of Hazardous Substances) compliant packaging.
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1
DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
The unit operates with a three-wire, high-speed serial interface. A combination of a large bandwidth, fine resolution, and the threewire, high-speed serial interface allows for a direct frequency modulation of the VCO. This supports any continuous phase, constant envelope modulation scheme such as Frequency Modulation (FM), Frequency Shift Keying (FSK), Minimum Shift Keying (MSK), or Gaussian Minimum Shift Keying (GMSK).
This capability can eliminate the need for In-Phase and Quadrature (I/Q) Digital-to-Analog Converters (DACs), quadrature upconverters, and IF filters from the transmitter portion of the radio system. Figure 1 shows a functional block diagram for the SKY72302. The device package and pinout for the 28-pin Exposed Pad Thin Shrink Small Outline Package (EP-TSSOP) are shown in Figure 2.
Data Clock CS Serial Interface Modulation Data Main MSB/LSB Dividend Main Divider
Registers
Modulation Control Ref Freq Dividers PD/Charge Pump Aux Aux Divider & Pwr-Dn/Mux Out Dividend Control
Mod_in
Modulation Unit
Mux
Mux_out
18-Bit
10-Bit
Fractional Unit Fvco_main Fvco_main Main Divider Main Divider Fpd_main Main Phase/Freq. Detector and Charge Pump
Reference Frequency Oscillator
Fractional Unit Fvco_aux Auxiliary Divider Auxiliary Prescaler Fvco_aux
Fref_main
Fref_aux Auxiliary Phase/Freq. Detector and Charge Pump
Fpd_aux
Fref Reference Frequency Oscillator
CPout_main Lock Detection or Power Steering LD/PSmain LD/PSaux
CPout_aux Lock Detection or Power Steering C1447
Figure 1. SKY72302 Functional Block Diagram
Clock Mod_in Mux_out VSUBdigital GNDcml VCCcml_main Fvco_main Fvco_main LD/PSmain VCCcp_main CPout_main GNDcp_main Xtalacgnd/OSC Xtalin/OSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
CS Data VCCdigital GNDdigital VCCcml_aux VCCvco_aux Fvco_aux GNDcp_aux CPout_aux VCCcp_aux LD/PSaux GNDxtal VCCxtal Xtalout/NC
C1412
Figure 2. SKY72302 Pinout, 28-Pin EP-TSSOP (Top View)
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
Technical Description
The SKY72302 is a fractional-N frequency synthesizer using a modulation technique. The fractional-N implementation provides low in-band noise by having a low division ratio and fast frequency settling time. In addition, the SKY72302 provides arbitrarily fine frequency resolution with a digital word, so that the frequency synthesizer can be used to compensate for crystal frequency drift in the RF transceiver. Serial Interface The serial interface is a versatile three-wire interface consisting of three pins: Clock (serial clock), Data (serial input), and CS (chip select). It enables the SKY72302 to operate in a system where one or multiple masters and slaves are present. To perform a loopback test at start-up and to check the integrity of the board and processor, the serial data is fed back to the master device (e.g., a microcontroller or microprocessor unit) through a programmable multiplexer. This facilitates hardware and software debugging. Registers There are ten 16-bit registers in the SKY72302. For more information, see the Register Descriptions section of this document. Main and Auxiliary Modulators The fractionality of the SKY72302 is accomplished by the use of a proprietary, configurable 10-bit or 18-bit modulator for the main synthesizer and 10-bit modulator for the auxiliary synthesizer. Main and Auxiliary Fractional Units The SKY72302 provides fractionality through the use of main and auxiliary modulators. The output from the modulators is combined with the main and auxiliary divider ratios through their respective fractional units. VCO Prescalers The VCO prescalers provide low-noise signal conditioning of the VCO signals. They translate from an off-chip, single-ended or differential signal to an on-chip differential Current Mode Logic (CML) signal. The SKY72302 has independent main and auxiliary VCO prescalers. Main and Auxiliary VCO Dividers The SKY72302 provides programmable dividers that control the CML prescalers and supply the required signals to the charge pump phase detectors. Programmable divide ratios ranging from 152 to 2148 are possible in fractional-N mode, and from 128 to
2172 in integer-N mode. Note that due to the fixed divide-by-four divider on the main synthesizer, the divide ratios are multiples of four. Programmable divide ratios ranging from 38 to 537 are possible in fractional-N mode, and from 32 to 543 in integer-N mode for the auxiliary synthesizer. Reference Frequency Oscillator The SKY72302 has a self-contained, low-noise crystal oscillator. This crystal oscillator is followed by the clock generation circuitry that generates the required clock for the programmable reference frequency dividers. Reference Frequency Dividers The crystal oscillator signal can be divided by a ratio of 1 to 32 to create the reference frequencies for the phase detectors. The SKY72302 has both a main and auxiliary frequency synthesizer, and provides independently configurable dividers of the crystal oscillator frequency for both the main and auxiliary phase detectors. The divide ratios are programmed by the Reference Frequency Dividers Register. NOTE: The divided crystal oscillator frequencies (which are the internal reference frequencies), Fref_main and Fref_aux, are referred to as reference frequencies throughout this document. Phase Detectors and Charge Pumps The SKY72302 uses a separate charge pump phase detector for each synthesizer which provides a programmable gain, Kd, from 31.25 to 1000 A/2 radians in 32 steps programmed using the Phase Detector/Charge Pump Control Register. Frequency Steering When programmed for frequency power steering, the SKY72302 has a circuit that helps the loop filter steer the VCO, through the LD/PSmain signal (pin 9). In this configuration, the LD/PSmain signal can provide for more rapid acquisition. When programmed for lock detection, internal frequency steering is implemented and provides frequency acquisition times comparable to conventional phase/frequency detectors. Lock Detection When programmed for lock detection, the SKY72302 provides an active low, pulsing open collector output using the LD/PSmain signal (pin 9) to indicate the out-of-lock condition. When locked, the LD/PSmain signal is tri-stated (high impedance).
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
Power Down The SKY72302 supports a number of power-down modes through the serial interface. For more information, see the Register Descriptions section of this document.
Register Programming Register programming equations, described in this section, use the following variables and constants: Nfractional Desired VCO division ratio in fractional-N applications. This is a real number and can be interpreted as the reference frequency (Fref) multiplying factor such that the resulting frequency is equal to the desired VCO frequency. Desired VCO division ratio in integer-N applications. This number is an integer and can be interpreted as the reference frequency (Fref) multiplying factor so that the resulting frequency is equal to the desired VCO frequency. Nine-bit unsigned input value to the divider ranging from 0 to 511 (integer-N mode) and from 6 to 505 (fractional-N mode). This constant equals 262144 when the modulator is in 18-bit mode, and 1024 when the modulator is in 10-bit mode.
Serial Interface Operation
The serial interface consists of three pins: Clock (pin 1), Data (pin 27), and CS (pin 28). The Clock signal controls data on the two serial data lines (Data and CS). The Data pin bits shift into a temporary register on the rising edge of Clock. The CS line allows individual selection transfers that synchronize and sample the information of slave devices on the same bus. Figure 3 functionally depicts how a serial transfer takes place. A serial transfer is initiated when a microcontroller or microprocessor forces the CS line to a low state. This is followed immediately by an address/data stream sent to the Data pin that coincides with the rising edges of the clock presented on the Clock line. Each rising edge of the Clock signal shifts in one bit of data on the Data line into a shift register. At the same time, one bit of data is shifted out of the Mux_out pin (if the serial bit stream is selected) at each falling edge of Clock. To load any of the registers, 16 bits of address or data must be presented to the Data line with the LSB last while the CS signal is low. If the CS signal is low for more than 16 clock cycles, only the last address or data bits are used to load the registers. If the CS signal is brought to a high state before the 13th Clock edge, the bit stream is assumed to be modulation data samples. In this case, it is assumed that no address bits are present and that all the bits in the stream should be loaded into the Modulation Data Register. Ninteger
Nreg
divider
dividend When in 18-bit mode, this is the 18-bit signed input value to the modulator, ranging from -131072 to +131071 and providing 262144 steps, each step equal to Fdiv_ref/218 Hz. When in 10-bit mode, this is the 10-bit signed input value to the modulator, ranging from -512 to +511 and providing 1024 steps, each step equal to Fdiv_ref/210 Hz. FVCO Fdiv_ref Desired VCO frequency (either Fvco_main or Fvco_aux). Divided reference frequency presented to the phase detector (either Fref_main or Fref_aux).
Clock
Data
X
A3
A2
A1
A0 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XXX
CS
Last
C1413
Figure 3. Serial Transfer Timing Diagram
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
Fractional-N Applications. The desired division ratio for the main synthesizer is given by:
F VCO_main Nfrac tion al = --------------------------------( 4 x Fdiv_r ef )
NOTE: As with all integer-N synthesizers, the minimum step size is related to the crystal frequency and reference frequency division ratio. A sample calculation for an integer-N application is provided in Figure 5. Register Loading Order. In applications where the main synthesizer is in 18-bit mode, the Main Dividend MSB Register holds the 10 MSBs of the dividend and the Main Dividend LSB Register holds the 8 LSBs of the dividend. The registers that control the main synthesizer's divide ratio are to be loaded in the following order: * Main Divider Register * Main Dividend LSB Register * Main Dividend MSB Register (at which point the new divide ratio takes effect) In applications where the main synthesizer is in 10-bit mode, the Main Dividend MSB Register holds the 10 bits of the dividend. The registers that control the main synthesizer's divide ratio are to be loaded in the following order: * Main Divider Register * Main Dividend MSB Register (at which point the new divide ratio takes effect) For the auxiliary synthesizer, the Auxiliary Dividend Register holds the 10 bits of the dividend. The registers that control the auxiliary synthesizer's divide ratio are to be loaded in the following order: * Auxiliary Divider Register * Auxiliary Dividend Register (at which point the new divide ratio takes effect) NOTE: When in integer mode, the new divide ratios take effect as soon as the Main or Auxiliary Divider Register is loaded. Direct Digital Modulation The high fractionality and small step size of the SKY72302 allow the user to tune to practically any frequency in the VCO's operating range. This allows direct digital modulation by programming the different desired frequencies at precise instants. Typically, the channel frequency is programmed by the Main Divider and MSB/LSB Dividend Registers, and the instantaneous frequency offset from the carrier is programmed by the Modulation Data Register. The Modulation Data Register can be accessed in three ways as defined in the following subsections.
The desired division ratio for the auxiliary synthesizer is given by:
F VCO_aux Nfrac tion al = -----------------------F div_r ef
where Nfractional must be between 150 and 2150 for the main synthesizer or between 37.5 and 537.5 for the auxiliary synthesizer. The value to be programmed by the Main or Auxiliary Divider Register is given by:
N reg = Round ( N fractional ) - 32
NOTE: The Round function rounds the number to the nearest integer. When in fractional mode, allowed values for Nreg are from 6 to 505 inclusive. The value to be programmed by either of the MSB/LSB Dividend Registers or the Auxiliary Dividend Register is given by:
dividend = Round [ divider x( N fractional - N reg - 32 )]
where the divider is either 1024 in 10-bit mode or 262144 in 18-bit mode. Therefore, the dividend is a signed binary value either 10 or 18 bits long. NOTE: Because of the high fractionality of the SKY72302, there is no practical need for any integer relationship between the reference frequency and the channel spacing or desired VCO frequencies. Sample calculations for two fractional-N applications are provided in Figure 4. Integer-N Applications. The desired division ratio for the main or auxiliary synthesizer is given by:
N int eger = Fvco _ main Fdiv _ ref
where Ninteger is an integer number from 32 to 543. The value to be programmed by the Main or Auxiliary Divider Register is given by:
N reg = N int eger - 32
When in integer mode, allowed values for Nreg are from 0 to 511 for both the main and auxiliary synthesizers.
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
Case 1: To achieve a desired Fvco_main frequency of 5900.4530 MHz using a crystal frequency of 40 MHz with operation of the synthesizer in 18-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal frequency is divided by 2 to obtain a Fdiv_ref of 20 MHz. Therefore: Nfractional = Fvco_main 4 x Fdiv_ref
= 5900.4530 80 = 73.755663 The value to be programmed in the Main Divider Register is: Nreg = Round[Nfractional] - 32 = Round[73.755663] - 32 = 74 - 32 = 42 (decimal) = 000101010 (binary) With the modulator in 18-bit mode, the value to be programmed in the Main Dividend Registers is: dividend = Round[divider x (Nfractional - Nreg - 32)] = Round[262144 x (73.755663 - 42 - 32)] = Round[262144 x (-0.2443375)] = Round[-64051.6096] = -64052 (decimal) = 110000010111001100 (binary) where 11 0000 0101 is loaded in the MSB of the Main Dividend Register and 1100 1100 is loaded in the LSB of the Main Dividend Register. Summary: * * * * Main Divider Register = 0 0010 1010 Main Dividend Register, LSB = 1100 1100 Main Dividend Register, MSB = 11 0000 0101 The resulting main VCO frequency is 5900.4529 MHz
Note: The frequency step size for this case is 4 x 20 MHz divided by 218, giving 305.2 Hz.
C1449
Figure 4. Fractional-N Applications: Sample Calculation (1 of 2)
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
Case 1: To achieve a desired Fvco_main frequency of 5217.1776 MHz using a crystal frequency of 19.2 MHz with operation of the synthesizer in 10-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal frequency does not require the internal division to be greater than 1, which makes Fdiv_ref = 19.2 MHz. Therefore: Nfractional = Fvco_main 4 x Fdiv_ref
= 5217.1776 4 x 19.2 = 67.9320
The value to be programmed in the Main Divider Register is: Nreg = Round[Nfractional] - 32 = Round[67.9320] - 32 = 68 - 32 = 36 (decimal) = 000100100 (binary) With the modulator in 18-bit mode, the value to be programmed in the Main Dividend Registers is: dividend = Round[divider x (Nfractional - Nreg - 32)] = Round[1024 x (67.9320 - 36 - 32)] = Round[1024 x (-0.068)] = Round[-69.632] = -70 (decimal) = 1110111010 (binary) where 11 1011 1010 is loaded in the MSB of the Main Dividend Register. Summary: * Main Divider Register = 0 0010 0100 * Main Dividend Register, MSB = 11 1011 1010 * The resulting main VCO frequency is 5217.15 MHz Note: The frequency step size for this case is 4 x 19.2 MHz divided by 210, giving 75 kHz.
C1450
Figure 4. Fractional-N Applications: Sample Calculation (2 of 2)
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
Case 1: To achieve a desired Fvco_aux frequency of 400 MHz using a crystal frequency of 16 MHz. Since the minimum divide ratio is 32, the reference frequency (Fdiv_ref) must be a maximum of 12.5 MHz. Choosing a reference frequency divide ratio of 2 provides a reference frequency of 8 MHz. Therefore: Ninteger = Fvco_aux Fdiv_ref 400 8 50
= =
The value to be programmed in the Auxiliary Divider Register is: Nreg = Ninteger - 32 = 50 - 32 = 18 (decimal) = 000010010 (binary) Summary: * Auxiliary Divide Register = 0 0001 0010
C1416
Figure 5. Integer-N Applications: Sample Calculation
Normal Register Write. A normal 16-bit serial interface write occurs when the CS signal is 16 clock cycles wide. The corresponding 16-bit modulation data is simultaneously presented to the Data pin. The content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). Short CS Through Data Pin (No Address Bits Required). A shortened serial interface write occurs when the CS signal is from 2 to 12 clock cycles wide. The corresponding modulation data (2 to 12 bits) is simultaneously presented to the Data pin. The Data pin is the default pin used to enter modulation data directly in the Modulation Data Register with shortened CS strobes. This method of data entry eliminates the register address overhead on the serial interface. All serial interface bits are resynchronized internally at the reference oscillator frequency. The content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). Short CS Through Mod_in Pin (No Address Bits Required). A shortened serial interface write occurs when the CS signal is from 2 to 12 clock cycles wide. The corresponding modulation data (2 to 12 bits) is simultaneously presented to the Mod_in pin, an alternate pin used to enter modulation data directly into the Modulation Data Register with shortened CS strobes.
This mode is selected through the Modulation Control Register. This method of data entry also eliminates the register address overhead on the serial interface and allows a different device than the one controlling the channel selection to enter the modulation data (e.g., a microcontroller for channel selection and a digital signal processor for modulation data). All serial interface bits are internally re-synchronized at the reference oscillator frequency and the content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). Modulation data samples in the Modulation Data Register can be from 2 to 12 bits long, and enable the user to select how many distinct frequency steps are to be used for the desired modulation scheme. The user can also control the frequency deviation through the modulation data magnitude offset in the Modulation Control Register. This allows shifting of the modulation data to accomplish a 2m multiplication of frequency deviation. NOTE: The programmable range of -0.5 to +0.5 of the main modulator can be exceeded up to the condition where the sum of the dividend and the modulation data conform to:
-0.5625 ( N mod + dividend ) + 0.5625
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
Table 1. SKY72302 Register Map
Address (Hex) 0 1 2 3 4 5 6 7 8 9 -- Main Divider Register Main Dividend MSB Register Main Dividend LSB Register Auxiliary Divider Register Auxiliary Dividend Register Reference Frequency Dividers Register Phase Detector/Charge Pump Control Register Power Down/Multiplexer Output Select Control Register Modulation Control Register Modulation Data Register Modulation Data Register (Note 2) -- direct input Register (Note 1) Length (Bits) 12 12 12 12 12 12 12 12 12 12 2 length 12 bits Address (Bits) 4 4 4 4 4 4 4 4 4 4 0
Note 1: All registers are write only. Note 2: No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data.
When the sum of the dividend and modulation data lie outside this range, the value of Ninteger must be changed. For a more detailed description of direct digital modulation functionality, refer to the Skyworks Application Note, Direct Digital Modulation Using the SKY72300, SKY72301, and SKY72302 Dual Synthesizers/PLLs (document number 101349).
The Main Dividend MSB and LSB Registers control the fraction part of the desired fractional-N value and allow an offset of -0.5 to + 0.5 to the main integer selected through the Main Divider Register. As shown in Figures 7 and 8, the values to be loaded are: * Main Synthesizer Dividend (MSBs) = Ten-bit value for the MSBs of the 18-bit dividend for the main synthesizer. * Main Synthesizer Dividend (LSBs) = Eight-bit value for the LSBs of the 18-bit dividend for the main synthesizer. The Main Dividend MSB and LSB Register values are 2's complement format. NOTE: When in 10-bit mode, the Main Dividend LSB Register is not required. Auxiliary Synthesizer Registers The Auxiliary Divider Register contains the integer portion closest to the desired fractional-N (or integer-N) value minus 32 for the auxiliary synthesizer. This register, in conjunction with the Auxiliary Dividend Register (which controls the fraction offset from -0.5 to +0.5), allows selection of a precise frequency. As shown in Figure 9, the value to be loaded is: * Auxiliary Synthesizer Divider Index = nine-bit value for the integer portion of the auxiliary synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or from 0 to 511 (integer-N).
Register Descriptions
Table 1 lists the 10 16-bit registers that are used to program the SKY72302. All register writes are programmed address first, followed directly with data. MSBs are entered first. On power-up, all registers are reset to 0x000 except registers at address 0x0 and 0x3, which are set to 0x006. Main Synthesizer Registers The Main Divider Register contains the integer portion closest to the desired fractional-N (or the integer-N) value minus 32 for the main synthesizer. This register, in conjunction with the Main Dividend and MSB/LSB Registers (which control the fraction offset from -0.5 to +0.5), allows selection of a precise frequency. NOTE: The fixed divide-by-four divider upstream from the programmable main divider must be taken into consideration to determine the value to be programmed in this register. For more information, refer to the Register Programming section in this document. As shown in Figure 6, the value to be loaded is: * Main Synthesizer Divider Index = Nine-bit value for the integer portion of the main synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or 0 to 511 (integer-N).
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
A3 0
A2 0
A1 0
A0 0
11 X
10 X
9 X
8 MSB
7
6
5
4
3
2
1
0 LSB
Main Synthesizer Divider Index
C1417
Figure 6. Main Divider Register (Write Only)
A3 0
A2 0
A1 0
A0 1
11 X
10 X
9 MSB
8
7
6
5
4
3
2
1
0 LSB
Main Synthesizer Dividend (MSBs)
C1418
Figure 7. Main Dividend MSB Register (Write Only)
A3 0
A2 0
A1 1
A0 0
11 X
10 X
9 X
8 X
7 MSB
6
5
4
3
2
1
0 LSB
Main Synthesizer Dividend (LSBs)
C1419
Figure 8. Main Dividend LSB Register (Write Only)
A3 0
A2 0
A1 1
A0 1
11 X
10 X
9 X
8 MSB
7
6
5
4
3
2
1
0 LSB
Auxiliary Synthesizer Divider Index
C1420
Figure 9. Auxiliary Divider Register (Write Only)
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
The Auxiliary Dividend Register controls the fraction part of the desired fractional-N value and allows an offset of -0.5 to +0.5 to the auxiliary integer selected through the Auxiliary Divider Register. As shown in Figure 10, the value to be loaded is: * Auxiliary Synthesizer Dividend = Ten-bit value for the auxiliary synthesizer dividend. General Synthesizer Registers The dual-programmable reference frequency dividers provide the reference frequencies to the phase detectors by dividing the crystal oscillator frequency. The lower five bits hold the reference frequency divide index for the main phase detector. The next five bits hold the reference frequency divide index for the auxiliary phase detector. Divide ratios from 1 to 32 are possible for each reference frequency divider (see Tables 2 and 3).
A3 0 A2 1 A1 0 A0 0 11 X 10 X 9 MSB 8 7 6 5 4
The Reference Frequency Dividers Register configures the dualprogrammable reference frequency dividers for the main and auxiliary synthesizers. As shown in Figure 11, the values to be loaded are: * Main Reference Frequency Divider Index = Desired main oscillator frequency division ratio -1. Default value on power-up is 0, signifying that the reference frequency is not divided for the main phase detector. * Auxiliary Reference Frequency Divider Index = Desired auxiliary oscillator frequency division ratio -1. Default value on power-up is 0, signifying that the reference frequency is not divided for the auxiliary phase detector.
3
2
1
0 LSB
Auxiliary Synthesizer Dividend
C1421
Figure 10. Auxiliary Dividend Register (Write Only) Table 2. Programming the Main Reference Frequency Divider
Decimal 0 1 2 -- -- -- 31 Bit 4 (MSB) 0 0 0 -- -- -- 1 Bit 3 0 0 0 -- -- -- 1 Bit 2 0 0 0 -- -- -- 1 Bit 1 0 0 1 -- -- -- 1 Bit 0 (LSB) 0 1 0 -- -- -- 1 Reference Divider Ratio 1 2 3 -- -- -- 32
Table 3. Programming the Auxiliary Reference Frequency Divider
Decimal 0 1 2 -- -- -- 31 Bit 9 (MSB) 0 0 0 -- -- -- 1 Bit 8 0 0 0 -- -- -- 1 Bit 7 0 0 0 -- -- -- 1 Bit 6 0 0 1 -- -- -- 1 Bit 5 (LSB) 0 1 0 -- -- -- 1 Reference Divider Ratio 1 2 3 -- -- -- 32
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
A3 0
A2 1
A1 0
A0 1
11 X
10 X
9
8
7
6
5
4
3
2
1
0
Main Reference Frequency Divider Index Auxiliary Reference Frequency Divider Index
C1422
Figure 11. Reference Frequency Dividers Register (Write Only)
A3 0
A2 1
A1 1
A0 0
11
10
9
8
7
6
5
4
3
2
1
0
Main Phase Detector Gain Main Power Steering/Lock Detect Enable Auxiliary Phase Detector Gain Auxiliary Power Steering/Lock Detect Enable
C1423
Figure 12. Phase Detector/Charge Pump Control Register (Write Only)
The Phase Detector/Charge Pump Control Register allows control of the gain for both phase detectors and configuration of the LD/PSmain and LD/PSaux signals for frequency power steering or lock detection. As shown in Figure 12, the values to be loaded are: * Main Phase Detector Gain = Five-bit value for programmable main phase detector gain. Range is from 0 to 31 decimal for 31.25 to 1000 A/2 radian, respectively. * Main Power Steering Enable = One-bit flag to enable the frequency power steering circuitry of the main phase detector. When this bit is cleared, the LD/PSmain pin is configured to be a lock detect, active-low, open collector pin. When this bit is set, the LD/PSmain pin is configured to be a frequency power steering pin and can be used to bypass the external main loop filter to provide faster frequency acquisition. * Auxiliary Phase Detector Gain = Five-bit value for programmable auxiliary phase detector gain. Range is from 0 to 31 decimal for 31.25 to 1000 A/2 radian, respectively. * Auxiliary Power Steering Enable = One-bit flag to enable the frequency power steering circuitry of the auxiliary phase detector. When this bit is cleared, the LD/PSaux pin is configured to be a lock detect, active-low, open collector pin. When this bit is set, the LD/PSaux pin is configured to be a
frequency power steering pin and may be used to bypass the external auxiliary loop filter to provide faster frequency acquisition. The Power Down/Multiplexer Output Select Control Register allows control of the power-down modes, internal multiplexer output, and main synthesizer fractionality. As shown in Figure 13, the values to be loaded are: * Full Power Down = One-bit flag that powers down the SKY72302 except for the reference oscillator and the serial interface. When this bit is cleared, the SKY72302 is powered up. When this bit is set, the SKY72302 is in full power-down mode excluding the Mux_out signal (pin 3). * Main Synthesizer Power Down = One-bit flag to power down the main synthesizer. When this bit is cleared, the main synthesizer is powered up. When this bit is set, the main synthesizer is in power-down mode. * Main Synthesizer Mode = One-bit flag to power down the main synthesizer's modulator and fractional unit to operate as an integer-N synthesizer. When this bit is cleared, the main synthesizer is in fractional-N mode. When this bit is set, the main synthesizer is in integer-N mode.
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
A3 0
A2 1
A1 1
A0 1
11 X
10 X
9
8 MSB
7
6 LSB
5
4
3
2
1
0
Full Power Down Main Synthesizer Power Down Main Synthesizer Mode Main Synthesizer Fractionality Auxiliary Synthesizer Power Down Auxiliary Synthesizer Mode Multiplexer Output Selection Mux_out Pin Tri-State Enable
C1424
Figure 13. Power Down and Multiplexer Output Register (Write Only)
* Main Synthesizer Fractionality = One-bit flag to configure the size of the main modulator. This has a direct effect on power consumption and on the level of fractionality and step size. When this bit is cleared, the main modulator is 18-bit with a fractionality of 218 and a step size of Fref_main/262144. When this bit is set, the main modulator is 10-bit with a fractionality of 210 and a step size of Fref_main/1024. * Auxiliary Synthesizer Power Down = One-bit flag to power down the auxiliary synthesizer. When this bit is cleared, the auxiliary synthesizer is powered up. When this bit is set, the auxiliary synthesizer is in power-down mode. * Auxiliary Synthesizer Mode = One-bit flag to power down the auxiliary synthesizer's modulator and fractional unit to operate as an integer-N synthesizer. When this bit is cleared, the auxiliary synthesizer is in fractional-N mode. When this bit is set, the auxiliary synthesizer is in integer-N mode. NOTE: There are no special power-up sequences required for the SKY72302. * Multiplexer Output Selection = Three-bit value that selects which internal signal is output to the Mux_out pin. The following internal signals are available on this pin: - Reference oscillator, Fref - Main or auxiliary divided reference (post-reference frequency main or auxiliary dividers), Fref_main or Fref_aux - Main or auxiliary phase detector frequency (post-main or auxiliary frequency dividers), Fpd_main or Fpd_aux - Serial data out, for loop-back and test purposes Refer to Table 4 for more information.
* Mux_out Pin Tri-State Enable = One-bit flag to tri-state the Mux_out pin. When this bit is cleared, the Mux_out pin is enabled. When this bit is set, the Mux_out pin is tri-stated. The Modulation Control Register is used to configure the modulation unit of the main synthesizer The modulation unit adds or subtracts a frequency offset to the selected center frequency at which the main synthesizer operates. The size of the modulation data sample, controlled by the duration of the CS signal, can be from 2 to 12 bits wide, to provide from 4 to 4096 selectable frequency offset steps. The modulation data magnitude offset selects the magnitude multiplier for the modulation data and can be from 0 to 8. As shown in Figure14, the values to be loaded are: * Modulation Data Magnitude Offset = Four-bit value that indicates the magnitude multiplier (m) for the modulation data samples. Valid values range from 0 to 13, effectively providing a 2m multiplication of the modulation data sample. * Modulation Data Input Select = One-bit flag to indicate the pin on which modulation data samples are serially input when the CS signal is between 2 and 12 bits long. When this bit is cleared, modulation data samples are to be presented on the Data pin. When this bit is set, modulation data samples are to be presented on the Mod_in pin. * Modulation Address Disable = One-bit flag to indicate the presence of the address as modulation data samples are presented on either the Mod_in or Data pins. When this bit is cleared, the address is presented with the modulation data samples (i.e., all transfers are 16 bits long). When this bit is set, no address is presented with the modulation data samples (i.e., all transfers are 2 to 12 bits long).
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
Table 4. Multiplexer Output
Multiplexer Output Select (Bit 8) 0 0 0 0 1 1 1 1 Multiplexer Output Select (Bit 7) 0 0 1 1 0 0 1 1 Multiplexer Output Select (Bit 6) 0 1 0 1 0 1 0 1 Multiplexer Output (Mux_out) Reference Oscillator Auxiliary Reference Frequency (Fref_aux) Main Reference Frequency (Fref_main) Auxiliary Phase Detector Frequency (Fpd_aux) Main Phase Detector Frequency (Fpd_main) Serial data out Serial interface test output Unused
A3 1
A2 0
A1 0
A0 0
11 X
10 X
9
8
7
6
5
4
3 0
2 0
1 0
0 0
Reserved Bits Modulation Data Magnitude Offset Modulation Data Input Select Modulation Address Disable
C1425
Figure 14. Modulation Control Register (Write Only)
A3 1
A2 0
A1 0
A0 1
11 MSB
10
9
8
7
6
5
4
3
2
1
0 LSB
Modulation Data Bits
C1426
Figure 15. Modulation Data Register (Write Only)
The Modulation Data Register is used to load the modulation data samples to the modulation unit. These values are transferred to the modulation unit on the falling edge of Fpd_main where they are passed to the main modulator at the selected magnitude offset on the next falling edge of Fpd_main. Modulation Data Register values are 2's complement format. As shown in Figure 15, the value to be loaded is: * Modulation Data Bits = Modulation data samples that represent the desired instantaneous frequency offset to the selected main synthesizer frequency (selected channel) before being affected by the modulation data magnitude offset.
Package and Handling Information
Since the device package is sensitive to moisture absorption, it is baked and vacuum packed before shipping. Instructions on the shipping container label regarding exposure to moisture after the container seal is broken must be followed. Otherwise, problems related to moisture absorption may occur when the part is subjected to high temperature during solder assembly. The SKY72302 is rated to Moisture Sensitivity Level 3 (MSL3) at 260 C. It can be used for lead or lead-free soldering. Care must be taken when attaching this product, whether it is done manually or in a production solder reflow environment. Production quantities of this product are shipped in a standard
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tape and reel format. For packaging details, refer to the Skyworks Application Note, Tape and Reel, document number 101568.
Figure 16 provides a schematic diagram for the SKY72302. Figure 17 shows the package dimensions for the 28-pin EP-TSSOP and Figure 18 provides the tape and reel dimensions.
Electrical and Mechanical Specifications
The SKY72302 is supplied as a 28-pin EP-TSSOP. The exposed pad is located on the bottom side of the package and must be connected to ground for proper operation. The exposed pad should be soldered directly to the circuit board. Signal pin assignments and functional pin descriptions are specified in Table 5. The absolute maximum ratings of the SKY72302 are provided in Table 6. The recommended operating conditions are specified in Table 7 and electrical specifications are provided in Table 8.
Table 5. SKY72302 Signal Descriptions (1 of 2)
Pin # 1 2 3 Pin Name Clock Mod_in Mux_out Type Digital input Digital input Digital output Description Clock signal pin. When CS is low, the register address and data are shifted in address bits first on the Data pin on the rising edge of Clock. Alternate serial modulation data input pin. Address bits are followed by data bits. Internal multiplexer output. Selects from oscillator frequency, main or auxiliary reference frequency, main or auxiliary divided VCO frequency, serial data out, or testability signals. This pin can be tri-stated from the general synthesizer registers. Substrate isolation. Connect to ground. Emitter Coupled Logic (ECL)/Current Mode Logic (CML) ground. ECL/CML, 3 V. Removing power safely powers down the associated divider chain and charge pump. Main VCO differential input. Main VCO complimentary differential input. Programmable output pin. Indicates main phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or helps the loop filter steer the main VCO. This pin is configured using the Phase Detector/Charge Pump Control Register. Main charge pump supply, 3 to 5 V. Removing power safely powers down the associated divider chain and charge pump. Main charge pump output. The gain of the main charge pump phase detector is controlled by the Phase Detector/Charge Pump Control Register. Main charge pump ground. Reference crystal AC ground or external oscillator differential input. Reference crystal input or external oscillator differential input. Reference crystal output or no connect. Crystal oscillator ECL/CML, 3 V. Crystal oscillator ground. Programmable output pin. Indicates auxiliary phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or helps the loop filter steer the auxiliary VCO. This pin is configured using the Phase Detector/Charge Pump Control Register. Auxiliary charge pump supply, 3 to 5 V. Removing power safely powers down the associated divider chain and charge pump.
Electrostatic Discharge (ESD) Sensitivity
The SKY72302 is a static-sensitive electronic device. Do not operate or store near strong electrostatic fields. Take proper ESD precautions.
4 5 6 7 8 9
VSUBdigital GNDecl/cml (Note 1) VCCcml_main (Note 1) Fvco_main Fvco_main LD/PSmain
- Power and ground Power and ground Input Input Analog output
10 11 12 13 14 15 16 17 18
VCCcp_main (Note 1) CPout_main GNDcp_main (Note 1) Xtalacgnd/OSC Xtalin/OSC Xtalout/NC VCCxtal GNDxtal LD/PSaux
Power and ground Analog output Power and ground Ground/input Input Input Power and ground Power and ground Analog output
19
VCCcp_aux (Note 1)
Power and ground
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
Table 5. SKY72302 Signal Descriptions (2 of 2)
Pin # 20 21 22 23 24 25 26 27 28 Pin Name CPout_aux GNDcp_aux (Note 1) Fvco_aux Fvco_aux VCCcml_aux (Note 1) GNDdigital (Note 1) VCCdigital (Note 1) Data CS Type Analog output Power and ground Input Input Power and ground Power and ground Power and ground Digital input Digital input Description Auxiliary charge pump output. The gain of the auxiliary charge pump phase detector is controlled by the Phase Detector/Charge Pump Control Register. Auxiliary charge pump ground. Auxiliary VCO complimentary differential input. Auxiliary VCO differential input. ECL/CML, 3 V. Removing power safely powers down the associated divider chain and charge pump. Digital ground. Digital 3 V. Serial address and data input pin. Address bits are followed by data bits. Active low enable pin. Enables loading of address and data on the Data pin on the rising edge of Clock. When CS goes high, data is transferred to the register indicated by the address. Subsequent clock edges are ignored.
Note 1: Associated pairs of power and ground pins must be decoupled using 0.1 F capacitors.
Table 6. Absolute Maximum Ratings
Parameter Maximum analog RF supply voltage Maximum digital supply voltage Maximum charge pump supply voltage Storage temperature Operating temperature
Note:
Min
Max 3.6 3.6 5.25
Units VDC VDC VDC C C
-65 -40
+150 +85
Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other parameters set at or below their nominal values.
Table 7. Recommended Operating Conditions
Parameter Analog RF supplies Digital supply Charge pump supplies Operating temperature (TA)
Note 1: When power steering is enabled, the charge pump supply must be 4.5 V maximum.
Min 2.7 2.7 2.7 -40
Max 3.3 3.3 5.0 (Note 1) +85
Units VDC VDC VDC C
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
Table 8. Electrical Characteristics (1 of 2)
(VDD = 3 V, TA = 25 C, Unless Otherwise Noted) Parameter Power Consumption Total power consumption PTOTAL Charge pump currents of 200 A. Both synthesizers fractional, FREF_MAIN = 20 MHz, FREF_AUX = 1 MHz Auxiliary synthesizer power down Power-down current Reference Oscillator Reference oscillator frequency Oscillator sensitivity (as a buffer) Frequency shift versus supply voltage VCOs Main synthesizer operating frequency Auxiliary synthesizer operating frequency RF input sensitivity Main fractional-N tuning step size Auxiliary fractional-N tuning step size Noise Phase noise floor Pnf Measured inside the loop bandwidth using 25 MHz reference frequency, -40 C to +85 C -128 + 20 Log (N) dBc/Hz FVCO_MAIN
FVCO_AUX
Symbol
Test Conditions
Min
Typ
Max
Units
54
mW
39 10 (Note 1)
mW A
ICC-PWDN
FOSC VOSC FSHIFT_SUPPLY AC coupled, single-ended 2.7 V VXTAL 3.3 V 0.1
50 2.0 0.3
MHz Vpp ppm
Sinusoidal, -40 C to +85 C Sinusoidal, -40 C to +85 C AC coupled
400 (Note 2) 100 (Note 3) 50 4 x FREF_MAIN/2 or FREF_MAIN/2
18 10
6100 1000 250
MHz MHz mVpeak Hz Hz
VVCO FSTEP_MAIN FSTEP_AUX
FREF_AUX/210
Phase Detectors and Charge Pumps Main phase detector frequency Auxiliary phase detector frequency Charge pump output source current Charge pump output sink current Charge pump accuracy Charge pump output voltage linearity range Charge pump current versus temperature Charge pump current versus voltage FREF_MAIN FREF_AUX ICP-SOURCE ICP-SINK ICP-ACCURACY ICP vs VCP ICP vs T ICP vs VCP 0.5 V VCP (VCCCP - 0.5 V) VCP = 0.5 VCCCP -40 C < T < +85 C 0.5 V VCP (VCCCP - 0.5 V) GND + 400 -40 C to +85 C -40 C to +85 C VCP = 0.5 VCCCP VCP = 0.5 VCCCP 125 -125 20 VCCCP - 400 5 8 25 25 1000 -1000 MHz MHz A A % mV % %
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
Table 8. Electrical Characteristics (2 of 2)
(VDD = 3 V, TA = 25 C, Unless Otherwise Noted) Parameter Digital Pins High level input voltage Low level input voltage High level output voltage Low level output voltage Timing - Serial Interface Clock frequency Data and CS set up time to Clock rising Data and CS hold time after Clock rising fCLOCK tSU tHOLD 3 0 100 MHz ns ns VIH VIL VOH VOL IOH = -2 mA IOL = +2 mA VDIGITAL -0.2 GND + 0.2 0.7 VDIGITAL 0.3 VDIGITAL V V V V Symbol Test Conditions Min Typ Max Units
Note 1: A 5 V charge pump power supply (on pin 10 and/or pin 19) results in higher power-down leakage current. Note 2: The minimum synthesizer frequency is 48 x FOSC, where FOSC is the frequency at the Xtalin/OSC pin. Note 3: The minimum synthesizer frequency is 12 x FOSC, where FOSC is the frequency at the Xtalin/OSC pin.
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DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
To Microprocessor
3V
RF Out Auxiliary J1 1
1 2 3 3V 4 5 C3 1 nF RF Out Main J1 1 5 4 3 2 3V R1 100 k Lock Detect Main Output < VCC 3 VCC 3V 10 2
RFOUT
Clock Mod_in Mux_out VSUBdigital GNDecl/cml VCCcml_main Fvco_main Fvco_main LD/PSmain VCCcp_main CPout_main GNDcp_main Xtalacgnd/OSC Xtalin/OSC
CS Data VCCdigital GNDdigital VCCcml_aux Fvco_aux Fvco_aux GNDcp_aux CPout_aux VCCcp_aux LD/PSaux GNDxtal VCCxtal Xtalout/NC
28 27 26 25 24 23 22 21 20 3V 19 18 17 16 15 C17 1 nF Auxiliary Synthesizer Loop Filter 3V C10 1 nF C8 R3 C12 R2 C9 C4 C6 Auxiliary VCO 4 2
RFOUT
3V
C1 1 nF
2
3
4
A C2 1 nF
6 C5 C7 7 8 9
VCC VCC 3
1
C11 1 nF
11 12
1
VT
GND Main VCO
4
13 14 R4
GND
C14
C15 R5 C16 100 pF
External Pad Connection to Ground
C17 C19 Main Synthesizer Loop Filter 3V R6 100 k Y1 C18
Lock Detect > Auxiliary Output C1427
Figure 16. SKY72302 Application Schematic
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VT
GND
5
19
DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
0.25 +0.5/-0.6
0.65 BSC
Pin 1
4.4 0.10
6.40 BSC
9.70 BSC
3.50
Top View
1.10 0.90 0.05
Exposed Pad Bottom View
0.10 0.05 0.60 0.10
Side View
All measurements are in millimeters
C1428
Figure 17. SKY72302 28-Pin EP-TSSOP Package Dimensions
4.00 0.10 8.00 0.10 Pin #1 1.50 0.10
2.00 0.05
1.75 0.10
B A A
7.50 0.10
B
1.50 0.25 3.96 1.10 0.318 0.013
8o Max
7o Max
6.75 0.10 1.60 0.10 Notes: 1. 2. 3. 4.
9.95 0.10
A
B
Carrier tape material: black conductive polystyrene Cover tape material: transparent conductive PSA Cover tape size: 13.3 mm width All measurements are in millimeters
C1430
Figure 18. SKY72302 Tape and Reel Dimensions
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16.00 +0.30/-0.10
3.00
DATA SHEET * SKY72302 FREQUENCY SYNTHESIZER
Ordering Information
Model Name SKY72302 6.1 GHz Frequency Synthesizer Manufacturing Part Number SKY72302-21 (Pb-free package) Evaluation Kit Part Number PH00-D122
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