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VN920SP-E
HIGH SIDE DRIVER
Table 1. General Features
Type VN920SP-E
s s
Figure 1. Package
IOUT 30 A VCC 36 V
RDS(on) 15m
CMOS COMPATIBLE INPUT PROPORTIONAL LOAD CURRENT SENSE s SHORTED LOAD PROTECTION s UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN s OVERVOLTAGE CLAMP s THERMAL SHUTDOWN s CURRENT LIMITATION PROTECTION AGAINST LOSS OF GROUND AND LOSS VCC s VERY LOW STAND-BY POWER DISSIPATION
s
10
1
PowerSO-10TM
REVERSE BATTERY PROTECTION (*) s IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE
s
DESCRIPTION The VN920SP-E is a monolithic device designed in STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table).
Active current limitation combined with thermal shutdown and automatic restart protect the device against overload. The device integrates an analog current sense output which delivers a current proportional to the load current. Device automatically turns off in case of ground pin disconnection.
Table 2. Order Codes
Package Tube VN920SP-E Tape and Reel VN920SPTR-E
PowerSO-10
Note: (*) See application schematic at page 9.
Rev. 1 October 2004 1/18
VN920SP-E
Figure 2. Block Diagram
VCC
VCC CLAMP
OVERVOLTAGE DETECTION UNDERVOLTAGE DETECTION
GND
Power CLAMP
DRIVER INPUT LOGIC CURRENT LIMITER VDS LIMITER IOUT K OVERTEMPERATURE DETECTION CURRENT SENSE OUTPUT
Table 3. Absolute Maximum Ratings
Symbol VCC - VCC - IGND IOUT - IOUT IIN VCSENSE Parameter DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current Current Sense Maximum Voltage Electrostatic Discharge (Human Body Model: R=1.5K; C=100pF) VESD - INPUT - CURRENT SENSE - OUTPUT - VCC Maximum Switching Energy (L=0.25mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=45A) Power Dissipation TC25C Junction Operating Temperature Case Operating Temperature Storage Temperature 4000 2000 5000 5000 362 96.1 Internally limited - 40 to 150 - 55 to 150 V V V V mJ W C C C Value 41 - 0.3 - 200 Internally Limited - 40 +/- 10 -3 +15 Unit V V mA A A mA V V
EMAX Ptot Tj Tc TSTG
2/18
VN920SP-E
Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
GROUND INPUT C.SENSE N.C. N.C.
6 7 8 9 10 11 VCC
5 4 3 2 1
OUTPUT OUTPUT N.C. OUTPUT OUTPUT
Connection / Pin Current Sense Floating To Ground Through 1K resistor
N.C. X X
Output X
Input X Through 10K resistor
Figure 4. Current and Voltage Conventions
IS VCC VF
VCC
IOUT OUTPUT IIN INPUT VIN CURRENT SENSE VSENSE GND IGND ISENSE VOUT
Table 4. Thermal Data
Symbol Rthj-case Rthj-amb
(1) (2)
Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient
Max Max
Value 1.3 51.3 (1) 37 (2)
Unit C/W C/W
When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35m thick). When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35m thick).
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VN920SP-E
ELECTRICAL CHARACTERISTICS (8VSymbol VCC VUSD VOV RON Vclamp Parameter Operating Supply Voltage Undervoltage Shut-down Overvoltage Shut-down On State Resistance IOUT=10A IOUT=3A; VCC=6V ICC=20mA (See note 1) Off State; VCC=13V; VIN=VOUT=0V Off State; VCC=13V; Tj=25C; VIN=VOUT=0V On State; VCC=13V; VIN=5V; IOUT=0; RSENSE=3.9K VIN=VOUT=0V VIN=0V; VOUT=3.5V VIN=VOUT=0V; VCC=13V; Tj =125C VIN=VOUT=0V; VCC=13V; Tj =25C 41 48 10 10 Test Conditions Min 5.5 3 36 Typ 13 4 Max 36 5.5 15 30 50 55 25 20 5 Unit V V V m m m V A A mA A A A A
IOUT=10A; Tj =25C
Clamp Voltage
IS
Supply Current
IL(off1) IL(off2) IL(off3) IL(off4)
Off Off Off Off
State State State State
Output Current Output Current Output Current Output Current
0 -75
50 0 5 3
Note: 1. Vclamp and VOV are correlated. Typical difference is 5V.
Table 6. Switching (VCC =13V)
Symbol td(on) td(off) dVOUT/ dt(on) dVOUT/ dt(off) Parameter Turn-on Delay Time Turn-off Delay Time Turn-on Voltage Slope Test Conditions RL=1.3 (see figure 2) RL=1.3 (see figure 2) RL=1.3 (see figure 2) Min Typ 50 50 See relative diagram See relative diagram Max Unit s s V/s
Turn-off Voltage Slope
RL=1.3 (see figure 2)
V/s
Table 7. Logic Input
Symbol VIL IIL VIH IIH VI(hyst) VICL Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage IIN=1mA IIN=-1mA VIN=3.25V 0.5 6 6.8 -0.7 8 VIN=1.25V 1 3.25 10 Test Conditions Min Typ Max 1.25 Unit V A V A V V V
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VN920SP-E
ELECTRICAL CHARACTERISTICS (continued) Table 8. VCC - Output Diode
Symbol VF Parameter Forward on Voltage Test Conditions -IOUT=5.3A; Tj=150C Min. Typ. Max. 0.6 Unit V
Table 9. Protections (see note 2)
Symbol TTSD TR Thyst Ilim Vdemag VON Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis DC Short Circuit Current Turn-off Output Clamp Voltage Output Voltage Drop Limitation VCC=13V 5V75 75 VCC-55
Note: 2. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
Table 10. Current Sense (9VVCC16V) (See Fig. 5)
Symbol K1 dK1/K1 K2 dK2/K2 K3 dK3/K3 Parameter IOUT/ISENSE Current Sense Ratio Drift IOUT/ISENSE Current Sense Ratio Drift IOUT/ISENSE Current Sense Ratio Drift Analog Sense Leakage Current Test Conditions IOUT=1A; VSENSE=0.5V; Tj= -40C...150C IOUT=1A; VSENSE=0.5V; Tj= -40C...+150C IOUT=10A; VSENSE=4V; Tj=-40C Tj=25C...150C IOUT=10A; VSENSE=4V; Tj=-40C...+150C IOUT=30A; VSENSE=4V; Tj=-40C Tj=25C...150C IOUT=30A; VSENSE=4V; Tj=-40C...+150C VCC=6...16V; IOUT=0A;VSENSE=0V; Tj=-40C...+150C Min 3300 -10 4200 4400 -8 4200 4400 -6 4900 4900 4900 4900 Typ 4400 Max 6000 +10 6000 5750 +8 5500 5250 +6 % % % Unit
ISENSEO
0 2 4 5.5
10
A V V V
VSENSE VSENSEH
RVSENSEH tDSENSE
Max Analog Sense Output VCC=5.5V; IOUT=5A; RSENSE=10K Voltage VCC>8V; IOUT=10A; RSENSE=10K Sense Voltage in Overtemperature VCC=13V; RSENSE=3.9K conditions Analog sense output impedance in VCC=13V; Tj>TTSD; Output Open overtemperature condition Current sense delay to 90% ISENSE (see note 3) response
400 500
s
Note: 3. Current sense signal delay after positive input slope
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VN920SP-E
Figure 5. IOUT/ISENSE versus IOUT
IOUT/ISENSE
6500
6000
max.Tj=-40C
5500
max.Tj=25...150C
5000
min.Tj=25...150C
4500
typical value
4000
min.Tj=-40C
3500
3000 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
IOUT (A)
Figure 6. Switching Characteristics (Resistive load RL=1.3)
VOUT
80% dVOUT/dt(on) tr ISENSE 90% 10%
90% dVOUT/dt(off) tf t
INPUT
tDSENSE
t td(off)
td(on)
t
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VN920SP-E
Table 11. Truth Table
CONDITIONS Normal operation Overtemperature Undervoltage Overvoltage INPUT L H L H L H L H L H H L H L OUTPUT L H L L L L L L L L L H H L SENSE 0 Nominal 0 VSENSEH 0 0 0 0 0 (TjTTSD) VSENSEH 0 < Nominal 0
Short circuit to GND
Short circuit to VCC Negative output voltage clamp
Table 12. Electrical Transient Requirements On VCC Pin
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I C C C C C C I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C E C C C C C E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2
IV C C C C C E
CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
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VN920SP-E
Figure 7. Waveforms
NORMAL OPERATION INPUT LOAD CURRENT SENSE
UNDERVOLTAGE VCC INPUT LOAD CURRENT SENSE
VUSD VUSDhyst
OVERVOLTAGE
VOV
VCC INPUT LOAD CURRENT SENSE
VCC > VUSD
VOVhyst
SHORT TO GROUND INPUT LOAD CURRENT LOAD VOLTAGE SENSE
SHORT TO VCC INPUT LOAD VOLTAGE LOAD CURRENT SENSE
OVERTEMPERATURE Tj INPUT LOAD CURRENT SENSE
ISENSE= VSENSEH RSENSE TTSD TR
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VN920SP-E
Figure 8. Application Schematic
+5V
Rprot INPUT
VCC
Dld C Rprot CURRENT SENSE RSENSE GND OUTPUT
VGND
RGND DGND
GND PROTECTION REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / (IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load.
This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT line is also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT pin is to leave it unconnected, while unused SENSE pin has to be connected to Ground pin.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table.
C I/Os PROTECTION:
If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k.
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VN920SP-E
Figure 9. Off State Output Current
IL(off1) (uA)
9 8 7 6 5 2.5 4 2 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Figure 10. High Level Input Current
Iih (uA)
5 4.5
Vin=3.25V
4 3.5 3
Tc (C)
Tc (C)
Figure 11. Input Clamp Voltage
Vicl (V)
8 7.8
Figure 13. On State Resistance Vs VCC
Ron (mOhm)
30 27.5
Tc= 150C
Iin=1mA
7.6 7.4 7.2 7 6.8 6.6
25 22.5 20 17.5 15 12.5 10 7.5
Tc= 25C
Tc= - 40C
6.4 6.2 6 -50 -25 0 25 50 75 100 125 150 175
5 2.5 0 5 10 15 20 25 30 35 40
IOUT=10A
Tc (C)
Vcc (V)
Figure 12. On State Resistance Vs Tcase
Ron (mOhm)
30 27.5
Figure 14. Input High Level
Vih (V)
3.6 3.4 3.2 3 2.8 2.6 2.4
Iout=10A
25
Vcc=8V; 36V
22.5 20 17.5 15 12.5 10 7.5 5 -25 0 25 50 75 100 125 150 175
2.2 2 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VN920SP-E
Figure 15. Input Low Level
Vil (V)
2.6 2.4 2.2 1.2 2 1.8 1.6 1.4 0.7 1.2 1 -50 -25 0 25 50 75 100 125 150 175 0.6 0.5 -50 -25 0 25 50 75 100 125 150 175 1.1 1 0.9 0.8
Figure 18. Input Hysteresis Voltage
Vhyst (V)
1.5 1.4 1.3
Tc (C)
Tc (C)
Figure 16. Turn-on Voltage Slope
dVout/dt(on) (V/ms)
700 650 600 550 500 450 400 350
Figure 19. Turn-off Voltage Slope
dVout/dt(off) (V/ms)
550 500
Vcc=13V Rl=1.3Ohm
450 400 350 300 250 200 150 100
Vcc=13V Rl=1.3Ohm
300 250 -50 -25 0 25 50 75 100 125 150 175
50 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 17. Overvoltage Shutdown
Vov (V)
50 48 46 44 42 40 38 36 34 32 30 -50 -25 0 25 50 75 100 125 150 175
Figure 20. ILIM Vs Tcase
Ilim (A)
100 90
Vcc=13V
80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VN920SP-E
Figure 21. Maximum turn off current versus load inductance
ILMAX (A) 100
A B
10
C
1 0.01 0.1 1 L(mH ) 10 100
A = Single Pulse at TJstart=150C B= Repetitive pulse at TJstart=100C C= Repetitive Pulse at TJstart=125C Conditions: VCC=13.5V VIN, IL Demagnetization
Values are generated with RL=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C.
Demagnetization
Demagnetization
t
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VN920SP-E
PowerSO-10TM Thermal Data Figure 22. PowerSO-10TM PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: from minimum pad lay-out to 8cm2).
Figure 23. Rthj-amb Vs PCB copper area in open box free air condition
RTHj_amb (C/W)
55
Tj-Tamb=50C
50 45 40 35 30
0 2 4 6 8 10
PCB Cu heatsink area (cm^2)
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VN920SP-E
Figure 24. PowerSO-10 Thermal Impedance Junction Ambient Single Pulse
ZTH (C/W) 100
0.5 cm2 6 cm2
10
1
0.1
0.01 0.0001
0.001
0.01
0.1
1
10
100
1000
Time (s)
Figure 25. Thermal fitting model of a single channel HSD in PowerSO-10 Pulse calculation formula
TH
= R TH + Z THtp ( 1 - ) = tp T
where
Table 13. Thermal Parameter
Tj
Area/island (cm2) R1 (C/W) R2 (C/W) R3( C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C) Footprint 0.02 0.1 0.2 0.8 12 37 0.0015 7.00E-03 0.015 0.3 0.75 3 6
C1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
Pd
T_amb
22
5
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VN920SP-E
PACKAGE MECHANICAL Table 14. PowerSO-10TM Mechanical Data
Symbol A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) a (*)
Note: (*) Muar only POA P013P
millimeters Min 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 1.27 1.25 1.20 13.80 13.85 0.50 1.20 0.80 0 2 1.80 1.10 8 8 1.35 1.40 14.40 14.35 Typ Max 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30
Figure 26. PowerSO-10TM Package Dimensions
B
0.10 A B
10
H
E
E2
E4
1
SEATING PLANE e
0.25
B
DETAIL "A"
A
C D = D1 = = = SEATING PLANE
h
A F A1
A1
L DETAIL "A"
P095A
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VN920SP-E
Figure 27. PowerSO-10TM Suggested Pad Layout And Tube Shipment (No Suffix)
14.6 - 14.9 10.8 - 11 6.30
A A C C
CASABLANCA
B
MUAR
0.67 - 0.73 1 2 3 4 5 10 9 8 7 6 0.54 - 0.6
B
9.5
All dimensions are in mm.
1.27
Base Q.ty Bulk Q.ty Tube length ( 0.5) Casablanca Muar 50 50 1000 1000 532 532
A
B
C ( 0.1) 0.8 0.8
10.4 16.4 4.9 17.2
Figure 28. Tape And Reel Shipment (suffix "TR") REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 24 4 24 1.5 1.5 11.5 6.5 2
End
All dimensions are in mm.
Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components
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VN920SP-E
REVISION HISTORY Table 15. Revision History
Date Oct. 2004 Revision 1 - First Issue. Description of Changes
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VN920SP-E
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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