View CAT93HC46JA-18TE13_4192990.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CAT93HC46
1-kb High Speed Microwire Serial EEPROM FEATURES
s High speed operation: 4 MHz @ 5.0 V s 1.8 to 5.5 volt operation s Selectable x8 or x16 word organization s Sequential Read s Software write protection s Power-up inadvertent write protection s Low power CMOS technology s 1,000,000 program/erase cycles s 100 year data retention
H
GEN FR ALO
EE
LE
A D F R E ETM
s Industrial and extended temperature ranges s 8-Lead PDIP, SOIC, MSOP and TSSOP
packages
DESCRIPTION
The CAT93HC46 is a 1-kb Serial EEPROM memory device which is configured as registers of either 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93HC46 is manufactured using Catalyst's advanced CMOS EEPROM floating gate
PIN CONFIGURATION
DIP Package (P, L)
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND
SOIC Package (J, W)
NC VCC CS SK
SOIC Package (S, V) MSOP Package (R, Z)
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND
CS SK DI DO
D
1 2 3 4
TSSOP Package (U, Y)
8 7 6 5 VCC NC ORG GND
is
o c
1 2 3 4
8 7 6 5
ORG GND DO DI
i t n
u n
CS SK DI DO VCC
technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The CAT93HC46 is available in 8-pin DIP, SOIC, MSOP or TSSOP packages.
FUNCTIONAL SYMBOL
VCC
d e
a P
t r
ORG DI CAT93HC46 SK CS DO
VSS
PIN FUNCTIONS
Pin Name Function Chip Select Clock Input Serial Data Input Serial Data Output 1.8 to 5.5 V Power Supply Ground Memory Organization No Connection
Note: When the ORG pin is connected to VCC, the X16 organization is selected. When it is connected to ground, the X8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the X16 organization.
GND ORG NC
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
1
Doc. No. 1008,Rev. H
CAT93HC46 ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55C to +125C Storage Temperature ........................ -65C to +150C Pin with Respect to Ground(1) .... -2.0 V to VCC + 2.0 V VCC with Respect to Ground ................ -2.0 V to 7.0 V Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS
Symbol NEND(3) TDR(3) VZAP(3) ILTH(3)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 Typ
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
D.C. OPERATING CHARACTERISTICS Industrial Temperature Range (-40C to 85C)
Symbol ICC1 ICC2 ISB1 ISB2(5) ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Standby Supply Current (x8) Standby Supply Current (x16) Input Leakage Current
Output Leakage Current
Note: (1) The minimum DC input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. (2) Output shorted for no more than one second. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1 V to VCC + 1 V. (5) Standby Current (ISB2) = 0 A (<900 nA).
is D
Input Low Voltage
Input High Voltage Input Low Voltage
Input High Voltage
Output Low Voltage
o c
i t n
Min -0.1 2 0 2.4
Limits Typ
0
u n
Max 2 200 10 10 1 1 0.8 VCC + 1 VCC x 0.2 VCC + 1 0.4 0.2
d e
100
Units mA A A A A A V
2000
a P
Max
Test Conditions 4.5 V VCC < 5.5 V 4.5 V VCC < 5.5 V 1.8 V VCC < 4.5 V 1.8V VCC < 4.5 V
Units
Cycles/Byte Years Volts mA
t r
fSK = 4 MHz, VCC = 5.0 V
fSK = 4 MHz, VCC = 5.0 V CS = GND, ORG=GND CS = GND, ORG = Float or VCC VIN = 0 V to VCC, CS = GND VOUT = 0 V to VCC, CS = GND
VCC x 0.7
4.5 V VCC < 5.5 V, IOL = 2.1 mA 4.5 V VCC < 5.5 V, IOH = -400 A
1.8 V VCC < 4.5 V, IOL = 1 mA
Output High Voltage Output Low Voltage
Output High Voltage
VCC - 0.2
1.8 V VCC < 4.5 V, IOH = -100 A
Doc. No. 1008, Rev. H
2
CAT93HC46
POWER-UP TIMING (1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Min Typ Max 1 1 Units ms ms
A.C. CHARACTERISTICS Industrial Temperature Range (-40C to 85C) 1.8 V - 5.5 V Symbol SKMAX tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tCSMIN tSKHI tSKLOW tSV tEW Parameter Maximum Clock Frequency CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Min DC 240 0 240 240 480 480 Max 1 2.5 V - 5.5 V Min DC 120 0 120 120 Max 2 4.5 V - 5.5 V Min DC 60 Max 4
Output Delay to Status Valid Program/Erase Pulse Width
NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) The input levels and timing reference points are shown in the "AC Test Conditions" table.
A.C. TEST CONDITIONS Input Pulse Voltages
Input Rise and Fall Times
Timing Reference Voltages Input Pulse Voltages
Timing Reference Voltages
is D
o c
i t n
240 480 240
240
480 5
u n
120 240 120
240 240
120
d e
60 60 60 120 60
0
120 120 60
a P
Units MHz ns ns ns ns ns ns ns ns ns ns ns ms
Conditions
t r
Test (3)
CL = 100 pF
240 5
120 5
10 ns 4.5 V VCC 5.5 V 4.5 V VCC 5.5 V 1.8 V VCC 4.5 V 1.8 V VCC 4.5 V
0.4 V to 2.4 V 0.8 V, 2.0 V VCC x 0.2 to VCC x 0.8 VCC x 0.5
3
Doc. No. 1008, Rev. H
CAT93HC46 DEVICE OPERATION
The CAT93HC46 is a 1024-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93HC46 can be organized as registers of either 16 bits or 8 bits. When organized as X16, seven 9-bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 10-bit instructions control the operation of the device. The CAT93HC46 operates on a single power supply and will generate on chip the high voltage required during write operation. Instructions, addresses, and data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state, except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state by shifting a dummy "1" into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/ word address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organization).
INSTRUCTION SET
Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL
Start Bit Opcode 1 1 1 1 1 1 1 10 11 01 00 00 00
Address x8 x16 A6-A0 A6-A0 A6-A0
11XXXXX 00XXXXX 10XXXXX 01XXXXX
x8
00
Figure 1. Sychronous Data Timing
SK
DI
is D
tCSS
o c
tDIS VALID
i t n
A5-A0 A5-A0 A5-A0
11XXXX 00XXXX 10XXXX 01XXXX
D7-D0
u n
Data x16
Comments
Read Address AN-A0 Clear Address AN-A0
d e
a P
t r
D15-D0 Write Address AN-A0 Write Enable Write Disable Clear All Addresses D15-D0 Write All Addresses
D7-D0
tSKHI
tSKLOW
tCSH
tDIH VALID
CS tDIS DO tPD0,tPD1 DATA VALID tCSMIN
Doc. No. 1008, Rev. H
4
CAT93HC46
Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93HC46 will come out of the high impedance state; after an initial dummy zero bit, data will be shifted out, MSB first. The output will toggle on the rising edge of the SK clock and will be stable after the specified time delay (tPD0 or tPD1) After the 1st data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the CAT93HC46 will automatically increment to the next address and shift out the next data word. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit; all subsequent data words will follow without a dummy zero bit.
Write After receiving a WRITE command, address and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self-timed clear and data store cycle into the specified memory location. The clocking of the SK pin is not necessary after the device has entered the self-timed mode. (Note 1.) The ready/busy status of the CAT93HC46 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Erase
Figure 2a. Read Instruction Timing
SK
CS
DI
1
1
DO
Figure 2b. Sequential Read Instruction Timing
SK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
is D
CS DI DO
o c
AN 0 HIGH-Z
AN 1 0 HIGH-Z
AN--1
i t n
tPD0
AN-1
u n
0 DN DN-- 1
A0
Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self-timed clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self-timed mode. (Note 1.) The ready/busy status of the CAT93HC46 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical "1" state.
d e
D1
a P
STANDBY
t r
tCS MIN
A0
tHZ HIGH-Z D0
Don't Care
1
Dummy 0
D15 . . . D0 or D7 . . . D0
Address + 1 D15 . . . D0 or D7 . . . D0
Address + 2 D15 . . . D0 or D7 . . . D0
Address + n D15 . . . or D7 . . .
5
Doc. No. 1008, Rev. H
CAT93HC46
Erase/Write Enable and Disable The CAT93HC46 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once write is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93HC46 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self-timed clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self-timed mode. (Note 1.) The ready/busy status of the CAT93HC46 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory locations will return to a logical "1" state. Figure 3. Write Instruction Timing
SK
Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self-timed data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self-timed mode. The ready/busy status of the CAT93HC46 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Once written, the contents of all memory locations will return to a logical "0" state.
Note 1: After the last data bit has been sampled, Chip Select (CS) must be brought Low before the next rising edge of the clock (SK) in order to start the self-timed high voltage cycle. This is important because if the CS is brought low before or after this specific frame window, the addressed location will not be programmed or erased.
CS
DI
1
0
Figure 4. Erase Instruction Timing
SK
CS
is D
1 1 1
DO
o c
1
AN
AN-1
i t n
A0 HIGH-Z
u n
DN D0
d e
tCS MIN STATUS VERIFY tSV BUSY tEW
a P
STANDBY tHZ HIGH-Z
t r
READY
STATUS VERIFY AN AN-1 A0 tCS MIN
STANDBY
DI
tSV HIGH-Z DO tEW BUSY READY
tHZ HIGH-Z
Doc. No. 1008, Rev. H
6
CAT93HC46
Figure 5. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
* * ENABLE=11 DISABLE=00
Figure 6. ERAL Instruction Timing
SK
CS
DI
1
0
0
1
0
DO
HIGH-Z
Figure 7. WRAL Instruction Timing
SK
CS
DI
is D
1 0 0
o c
0 1
i t n
u n
tSV
DN
d e
tCS MIN BUSY tEW
a P
tHZ READY
t r
STATUS VERIFY
STANDBY
HIGH-Z
STATUS VERIFY tCS MIN D0 tSV
STANDBY
tHZ BUSY tEW READY HIGH-Z
DO
7
Doc. No. 1008, Rev. H
CAT93HC46 ORDERING INFORMATION
Prefix CAT Device # 93HC46 Suffix S I -1.8 TE13 Rev H(2)
Optional Company ID
Product Number 93HC46: 1K
Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) A = Automotive (-40C to +105C) E = Extended (-40C to +125C) Package P = PDIP S = SOIC (JEDEC) J = SOIC (JEDEC) U = TSSOP
Tape & Reel
Operating Voltage Blank (Vcc=2.5 to 6.0V) 1.8 (Vcc=1.8 to 6.0V)
* available upon request
Notes: (1) The device used in the above example is a 93HC46SI-TE13 (SOIC, Industrial Temperature,Tape & Reel). (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWH.) For additional information, please contact your Catalyst sales office.
is D
Doc. No. 1008, Rev. H
o c
i t n
u n
d e
a P
Die Revision
t r
8
REVISION HISTORY
Date 11/11/2003 Rev. E Reason Updated Features Eliminated Commercial temperature range Updated DC Operating Characteristics Updated AC Characteristics Updated Ordering Information 11/14/2003 7/27/2004 03/11/2005 F G H Updated DC Operating Characteristics Add die revision to Ordering Information Updated Ordering Information
Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP TM AE2 TM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
is D
o c
i t n
u n
d e
a P
t r
Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com
Publication #: Revison: Issue date: Type:
1008 H 03/11/05 Final

▲Up To Search▲

Price & Availability of CAT93HC46JA-18TE13

	To Download CAT93HC46JA-18TE13 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .