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LOW SKEW, 1:6 CRYSTAL-TOLVCMOS/LVTTL FANOUT BUFFER
ICS83905
GENERAL DESCRIPTION
The ICS83905 is a low skew, 1-to-6 LVCMOS / LVTTL IC S Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from IDT. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines. The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V, mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply mode. Guaranteed output and part-to-part skew characteristics along with the 1.8V output capabilities makes the ICS83905 ideal for high performance, single ended applications that also require a limited output voltage.
FEATURES
* Six LVCMOS / LVTTL outputs * Outputs able to drive 12 series terminated lines * Crystal oscillator interface * Crystal input frequency range: 10MHz to 40MHz * Output skew: 80ps (maximum) * RMS phase jitter @ 25MHz, (100Hz - 1MHz): 0.26ps (typical) (VDD = VDDO = 2.5V) Phase noise: Offset Noise Power 100Hz ............. -129.7 dBc/Hz 1kHz ............. -144.4 dBc/Hz 10kHz ............. -147.3 dBc/Hz 100kHz ............. -157.3 dBc/Hz * 5V tolerant enable inputs * Synchronous output enables * Operating power supply modes: Full 3.3V, 2.5V and 1.8V, mixed 3.3V core/2.5V output operating supply, mixed 3.3V core/1.8V output operating supply, mixed 2.5V core/1.8V output operating supply
15 14 13 12 11 BCLK5 VDDO BCLK4 GND GND
PIN ASSIGNMENTS
XTAL_OUT ENABLE 2 ENABLE 1 XTAL_IN nc
20 19 18 17 16
ICS83905
20-Lead VFQFN
4mm x 4mm x 0.9mm body package
GND GND BCLK0 VDDO BCLK1
1 2 3 4 5 6
GND
* 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
K Package Top View
7
GND
8
BCLK2
9 10
BCLK3 VDD
BLOCK DIAGRAM
BCLK0
XTAL_OUT ENABLE 2 GND BCLK0 VDDo BCLK1 GND BCLK2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
XTAL_IN ENABLE 1 BCLK5 VDDO BCLK4 GND BCLK3 VDD
BCLK1 XTAL_IN BCLK2
XTAL_OUT
ICS83905
16-Lead SOIC 3.9mm x 9.9mm x 1.38mm body package M Pacakge Top View 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm body package G Pacakge Top View
BCLK3
BCLK4 ENABLE 1
SYNCHRONIZE
BCLK5
ENABLE 2
SYNCHRONIZE
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TABLE 1. PIN DESCRIPTIONS
Name XTAL_OUT XTAL_IN ENABLE 1, ENABLE 2 BCLK0, BCLK1, BCLK2, BCLK3, BCLK4, BCLK5 GND VDD VDDO n/c Input Input Output Power Power Power Unused Type Output Description Cr ystal oscillator interface. XTAL_OUT is the output. Cr ystal oscillator interface. XTAL_IN is the input. Clock enable. LVCMOS / LVTTL interface levels. See Table 3. Clock outputs. LVCMOS / LVTTL interface levels. Power supply ground. Core supply pin. Output supply pin. No connect.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance (per output) VDDO = 3.465V VDDO = 2.625V VDDO = 2V VDDO = 3.3V 5% ROUT Output Impedance VDDO = 2.5V 5% VDDO = 1.8V 0.2V 7 7 10 Test Conditions Minimum Typical 4 19 18 16 Maximum Units pF pF pF pF
TABLE 3. CLOCK ENABLE FUNCTION TABLE
Control Inputs ENABLE 1 0 0 1 1 ENABLE 2 0 1 0 1 LOW LOW Toggling Toggling Outputs BCLK0:BCLK4 BCLK5 LOW Toggling LOW Toggling
BCLK5
BCLK0:4 ENABLE2
ENABLE1
FIGURE 1. ENABLE TIMING DIAGRAM
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 16 Lead SOIC package 78.8C/W (0 mps) 16 Lead TSSOP package 89C/W (0 lfpm) 20 Lead VFQFN package 60.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current ENABLE 1:2 = 00 ENABLE 1:2 = 00 Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 10 5 Units V V mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current ENABLE 1:2 = 00 ENABLE 1:2 = 00 Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 Maximum 2.625 2.625 8 4 Units V V mA mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current ENABLE 1:2 = 00 ENABLE 1:2 = 00 Test Conditions Minimum 1.6 1.6 Typical 1.8 1.8 Maximum 2.0 2.0 5 3 Units V V mA mA
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current ENABLE 1:2 = 00 ENABLE 1:2 = 00 Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 10 4 Units V V mA mA
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TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current ENABLE 1:2 = 00 ENABLE 1:2 = 00 Test Conditions Minimum 3.135 1.6 Typical 3.3 1.8 Maximum 3.465 2.0 10 3 Units V V mA mA
TABLE 4F. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current ENABLE 1:2 = 00 ENABLE 1:2 = 00 Test Conditions Minimum 2.375 1.6 Typical 2.5 1.8 Maximum 2.625 2.0 8 3 Units V V mA mA
TABLE 4G. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0C TO 70C
Symbol VIH Parameter Input High Voltage ENABLE 1, ENABLE 2 Test Conditions VDD = 3.3V 5% VDD = 2.5V 5% VDD = 1.8V 0.2V VIL Input Low Voltage ENABLE 1, ENABLE 2 VDD = 3.3V 5% VDD = 2.5V 5% VDD = 1.8V 0.2V VDDO = 3.3V 5%; NOTE 1 VOH Output High Voltage VDDO = 2.5V 5%; IOH = -1mA VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 0.2V; NOTE 1 VDDO = 3.3V 5%; NOTE 1 VOL Output Low Voltage VDDO = 2.5V 5%; IOL = 1mA VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 0.2V; NOTE 1 Minimum 2 1.7 0.65*VDD -0.3 -0.3 -0.3 2.6 2 1.8 VDDO - 0.3 0.5 0.4 0.45 0.35 Typical Maximum VDD + 0.3 VDD + 0.3 VDD + 0.3 0.8 0.7 0.35*VDD Units V V V V V V V V V V V V V V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 10 Test Conditions Minimum Typical Fundamental 40 50 7 1 MHz pF mW Maximum Units
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TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter Using External Crystal fMAX o dc tsk(o) tjit(O) tR/tF tEN tDIS Output Frequency Output Duty Cycle Output Skew; NOTE 2, 4 RMS Phase Jitter (Random) Output Rise/Fall Time Output Enable Time; NOTE 3 ENABLE 1 ENABLE 2 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 200 0.13 800 4 4 4 4 Using External Clock Source; NOTE 1 Test Conditions Minimum Typical Maximum Units 10 DC 48 40 100 52 80 MHz MHz % ps ps ps cycles cycles cycles cycles
Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2
All parameters measured at fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Using External Crystal fMAX o dc tsk(o) tjit(O) tR/tF tEN tDIS Output Frequency Output Duty Cycle Output Skew; NOTE 2, 5 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Output Enable Time; NOTE 4 ENABLE 1 ENABLE 2 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 200 0.26 800 4 4 4 4 Using External Clock Source; NOTE 1 Test Conditions Minimum Typical Maximum Units 10 DC 47 40 100 53 80 MHz MHz % ps ps ps cycles cycles cycles cycles
Output Disable Time; ENABLE 1 NOTE 4 ENABLE 2
All parameters measured at fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Please refer to phase noise plot. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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TABLE 6C. AC CHARACTERISTICS, VDD = VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter Using External Crystal fMAX o dc tsk(o) tjit(O) tR/tF tEN tDIS Output Frequency Output Duty Cycle Output Skew; NOTE 2, 4 RMS Phase Jitter (Random) Output Rise/Fall Time Output Enable Time; NOTE 3 ENABLE 1 ENABLE 2 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 200 0.27 900 4 4 4 4 Using External Clock Source; NOTE 1 Test Conditions Minimum Typical Maximum Units 10 DC 47 40 100 53 80 MHz MHz % ps ps ps cycles cycles cycles cycles
Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2
All parameters measured at fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6D. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Using External Crystal fMAX o dc tsk(o) tjit(O) tR/tF tEN tDIS Output Frequency Output Duty Cycle Output Skew; NOTE 2, 4 RMS Phase Jitter (Random) Output Rise/Fall Time Output Enable Time; NOTE 3 ENABLE 1 ENABLE 2 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 200 0.14 800 4 4 4 4 Using External Clock Source; NOTE 1 Test Conditions Minimum Typical Maximum Units 10 DC 48 40 100 52 80 MHz MHz % ps ps ps cycles cycles cycles cycles
Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2
All parameters measured at fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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TABLE 6E. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter Using External Crystal fMAX o dc tsk(o) tjit(O) tR/tF tEN tDIS Output Frequency Output Duty Cycle Output Skew; NOTE 2, 4 RMS Phase Jitter (Random) Output Rise/Fall Time Output Enable Time; NOTE 3 ENABLE 1 ENABLE 2 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 200 0.18 900 4 4 4 4 Using External Clock Source; NOTE 1 Test Conditions Minimum Typical Maximum Units 10 DC 48 40 100 52 80 MHz MHz % ps ps ps cycles cycles cycles cycles
Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2
All parameters measured at fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6F. AC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter Using External Crystal fMAX o dc tsk(o) tjit(O) tR/tF tEN tDIS Output Frequency Output Duty Cycle Output Skew; NOTE 2, 4 RMS Phase Jitter (Random) Output Rise/Fall Time Output Enable Time; NOTE 3 ENABLE 1 ENABLE 2 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 200 0.19 900 4 4 4 4 Using External Clock Source; NOTE 1 Test Conditions Minimum Typical Maximum Units 10 DC 47 40 100 53 80 MHz MHz % ps ps ps cycles cycles cycles cycles
Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2
All parameters measured at fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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TYPICAL PHASE NOISE AT 25MHZ (2.5V CORE/ 2.5V OUTPUT)
0 -10 -20 -30 -40 -50
25MHz
RMS Phase Jitter (Random) 100Hz to 1MHz = 0.26ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M
Raw Phase Noise Data
TYPICAL PHASE NOISE AT 25MHZ (3.3V CORE/ 3.3V OUTPUT)
0 -10 -20 -30 -40 -50
OFFSET FREQUENCY (HZ) 25MHz
RMS Phase Jitter (Random) 100Hz to 1MHz = 0.13ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M
Raw Phase Noise Data
OFFSET FREQUENCY (HZ)
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PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, VDDO
Qx
SCOPE
VDD, VDDO
Qx
SCOPE
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
0.9V0.1V
2.05V5% 1.25V5%
VDD, VDDO
Qx
SCOPE
VDD VDDO
GND Qx
SCOPE
LVCMOS
LVCMOS
GND
-0.9V 0.1V
-1.25V5%
1.8V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.40.9V 0.9V0.1V
1.6V0.025% 0.9V0.1V
VDD VDDO
GND Qx
SCOPE
VDD VDDO
GND Qx
SCOPE
LVCMOS
LVCMOS
-0.9V0.1V
-0.9V0.1V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
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V
V
DD
DDO
Qx
2
BCLKx t PW
t
2
V
PERIOD
DDO
Qy
2 tsk(o)
odc =
t PW t PERIOD
x 100%
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80% 20% tR
80% 20% tF
Clock Outputs
OUTPUT RISE/FALL TIME
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APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
Figure 2 shows an example of ICS83905 crystal interface with a parallel resonant crystal. The frequency accuracy can be fine tuned by adjusting the C1 and C2 values. For a parallel crystal with loading capacitance CL = 18pF, we suggest C1 = 15pF and C2 = 15pF to start with. These values may be slightly fine tuned further to optimize the frequency accuracy for different board layouts. Slightly increasing the C1 and C2 values will slightly reduce the frequency. Slightly decreasing the C1 and C2 values will slightly increase the frequency. For the oscillator circuit below, R1 can be used, but is not required. For new designs, it is recommended that R1 not be used.
XTAL_IN C1 15p X1 18pF Parallel Cry stal 0 XTAL_OUT C2 15p R1 (optional)
FIGURE 2. CRYSTAL OSCILLATOR INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver
VDD VCC
(Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD VCC
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER
TO
XTAL INPUT INTERFACE
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached.
THERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to the P.C. board. The expose metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is contacted through solder as shown in Figure 4. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor's Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology.
EXPOSED PAD SOLDER
SOLDER M ASK SIGNAL TRACE
SIGNAL TRACE
GROUND PLANE THERM AL VIA
Expose Metal Pad (GROUND PAD)
FIGURE 4. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
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LAYOUT GUIDELINE
Figure 5 shows an example of ICS83905 application schematic. In this example, the device is operated at VDD = 3.3V and VDDO = 3.3V. The decoupling capacitors should be located as close as possible to the power pins. The input is driven by an 18pF load resonant quartz crystal. The tuning capacitors (C1, C2) are fairly accurate, but minor adjustments might be required. For the LVCMOS output drivers, two termination examples are shown in the schematic. For additional termination, examples are shown in the LVCMOS Termination Application Note.
VDDO = 3.3V VDD = 3.3V CL = 18 pf C2 15pf U1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C1 15pF R2 31 Zo = 50 Ohm
LVCMOS
ENABLE 2 VDDO
XTAL_OUT ENABLE 2 GND BCLK0 VDDO BCLK1 GND BCLK2
XTAL_IN ENABLE 1 BCLK5 VDDO BCLK4 GND BCLK3 VDD
ENABLE 1 VDD R3 100 Zo = 50 Ohm R4 100 LVCMOS
ICS83905
VDD C3 10uF C4 .1uF
VDDO C5 .1uF C6 .1uF
Optional Termination
Unused outputs can be left floating. There should be no trace attached to unused outputs. Device characterized and specification limits set with all outputs terminated.
FIGURE 5. SCHEMATIC OF RECOMMENDED LAYOUT
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RELIABILITY INFORMATION
TABLE 7A. JAVS. AIR FLOW TABLE
FOR
16 LEAD SOIC
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 78.8C/W
1
71.1C/W
2
66.2C/W
TABLE 7B. JAVS. AIR FLOW TABLE
FOR
16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7C. JAVS. AIR FLOW TABLE
FOR
20 LEAD VFQFN
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 60.4C/W
1
52.8C/W
3
46.0C/W
TRANSISTOR COUNT
The transistor count for ICS83905 is: 339 Pin compatible to MPC905
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PACKAGE OUTLINE - M SUFFIX FOR 16 LEAD SOIC
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 9.80 3.80 MINIMUM
FOR
16 LEAD SOIC
MAXIMUM
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N Minimum
FOR TSSOP
Millimeters
Millimeters Maximum 16 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.30 0.65 BASIC 0.45 0 -0.75 8 0.10 4.50 1.20 0.15 1.05 0.30 0.20 5.10
16 1.75 0.25 0.51 0.25 10.00 4.00 1.27 BASIC 6.20 0.50 1.27 8
A A1 A2 b c D E E1 e L aaa
Reference Document: JEDEC Publication 95, MS-012
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PACKAGE OUTLINE - K SUFFIX FOR 20 LEAD VFQFN
TABLE 8C. PACKAGE DIMENSIONS FOR 20 LEAD VFQFN
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.75 0.35 0.75 4.0 2.80 0.75 0.18 0.50 BASIC 5 5 4.0 2.80 0.80 0 0.25 Reference 0.30 MINIMUM 20 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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ICS83905AM REV. B JULY 9, 2007
ICS83905 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS83905AM ICS83905AMT ICS83905AMLF ICS83905AMLFT ICS83905AG ICS83905AGT ICS83905AGLF ICS83905AGLFT ICS83905AK ICS83905AKT ICS83905AKLF ICS83905AKLFT Marking 83905AM 83905AM 83905AML 83905AML 83905AG 83905AG 83905AGL 83905AGL 83905A 83905A 3905AL 3905AL Package 16 Lead SOIC 16 Lead SOIC 16 Lead "Lead-Free" SOIC 16 Lead "Lead-Free" SOIC 16 Lead TSSOP 16 Lead TSSOP 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP 20 Lead VFQFN 20 Lead VFQFN 20 Lead "Lead-Free" VFQFN 20 Lead "Lead-Free" VFQFN Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER
17
ICS83905AM REV. B JULY 9, 2007
ICS83905 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
REVISION HISTORY SHEET Rev A B B B 6A - 6F T9 Table Page 2 1 5-7 8 14 11 12 3 11 13 11 12 17 Description of Change Added Enable Timing Diagram. Features Section - added RMS Phase Jitter bullet. AC Characteristics Tables - added RMS Phase Jitter spec. Added Phase Noise Plot. Ordering Information Table - add TSSOP, non-LF par t number. Added Cr ystal Input Interface in Application Section. Added schematic layout. Absolute Maximum Ratings - correct 20 lead VFQFN Package Thermal Impedance. Added Recommendations for Unused Input and Output Pins. Corrected Theta JA Air Flow Table for 20 lead VFQFN. Added LVCMOS to XTAL Interface section. Added Thermal Release Path section. AC Characteristics Table - added lead-free marking for 20 VFQFN package. Date 3/28/05 4/8/05 4/25/05 5/16/05
B T7C B T9
10/2/06
7/9/07
IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER
18
ICS83905AM REV. B JULY 9, 2007
ICS83905 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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