View ICS9FG1904B-1_4183858.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS9FG1904B-1
Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD
Recommended Application:
DB1900GS/GSO with 15:4 output grouping
Functionality at Power Up (PLL Mode) CLK_IN (CPU FSB) 1 FS_A_410 MHz 1 100 <= CLK_IN < 200 0 200<= CLK_IN <= 400
Features:
* * * * * * * Power up default is all outputs in 1:1 mode DIF_(14:0) can be "gear-shifted" from the input CPU Host Clock DIF_(18:15) can be "gear-shifted" from the input CPU Host Clock Spread spectrum compatible Supports output clock frequencies up to 400 MHz 8 Selectable SMBus addresses SMBus address determines PLL or Bypass mode
DIF_(18:0) MHz CLK_IN CLK_IN
1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Power Down Functionality
INPUTS CKPWRGD/ CLK_IN/ PD# CLK_IN# 1 Running 0 X OUTPUTS PLL State DIF/DIF# Running Hi-Z ON OFF
Key Specifications:
* * DIF output cycle-to-cycle jitter < 50ps DIF output-to-output skew < 100ps within a group
SMB_A2_PLLBYP#
Pin Configuration
CKPWRGD/PD#
OE_17_18#
OE_15_16#
CLK_IN#
DIF_18#
DIF_17#
DIF_16#
DIF_15#
DIF_14#
DIF_ 16
CLK_IN
DIF_18
DIF_17
DIF_15
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 IREF GNDA VDDA HIGH_BW# FS_A_410 DIF_0 DIF_0# DIF_1 DIF_1# GND VDD DIF_2 DIF_2# DIF_3 DIF_3# DIF_4 DIF_4# OE_01234# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SMBCLK SMBDAT OE5# DIF_5 DIF_5# OE6# 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 DIF_7# OE8# DIF_8 DIF_8# SMB_A0 SMB_A1 OE14# DIF_13# DIF_13 OE13# DIF_12# DIF_12 OE12# VDD GND DIF_11# DIF_11 OE11# DIF_10# DIF_10 OE10# DIF_9# DIF_9 OE9#
ICS9FG1904-1
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 DIF_6 DIF_6# VDD GND OE7# DIF_7
72-pin MLF
1255B--08/03/07
Other names and brands may be claimed as the property of others.
DIF_14
GND
VDD
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PIN NAME IREF GNDA VDDA HIGH_BW# FS_A_410 DIF_0 DIF_0# DIF_1 DIF_1# GND VDD DIF_2 DIF_2# DIF_3 DIF_3# DIF_4 DIF_4# OE_01234# SMBCLK SMBDAT OE5# DIF_5 DIF_5# OE6# DIF_6 DIF_6# VDD GND OE7# DIF_7 DIF_7# OE8# DIF_8 DIF_8# SMB_A0 SMB_A1 PIN TYPE OUT PWR PWR IN IN OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT OUT OUT IN IN I/O IN OUT OUT IN OUT OUT PWR PWR IN OUT OUT IN OUT OUT IN IN DESCRIPTION This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. 3.3V input for selecting PLL Band Width 0 = High, 1= Low 3.3V tolerant low threshold input for CPU frequency selection. This pin requires CK410 FSA. Refer to input electrical characteristics for Vil_FS and Vih_FS threshold values. 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output Ground pin. Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pairs 0, 1, 2, 3 and 4. 1 = tri-state outputs, 0 = enable outputs Clock pin of SMBUS circuitry, 5V tolerant Data pin of SMBUS circuitry, 5V tolerant Active low input for enabling DIF pair 5. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 6. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Ground pin. Active low input for enabling DIF pair 7. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 8. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output SMBus address bit 0 (LSB) SMBus address bit 1
1255B--08/03/07
2
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
Pin Description (Continued)
PIN # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PIN NAME OE9# DIF_9 DIF_9# OE10# DIF_10 DIF_10# OE11# DIF_11 DIF_11# GND VDD OE12# DIF_12 DIF_12# OE13# DIF_13 DIF_13# OE14# DIF_14 DIF_14# CKPWRGD/PD# DIF_15 DIF_15# OE_15_16# DIF_ 16 DIF_16# VDD GND DIF_17 DIF_17# DIF_18 DIF_18# OE_17_18# CLK_IN CLK_IN# SMB_A2_PLLBYP# PIN TYPE IN OUT OUT IN OUT OUT IN OUT OUT PWR PWR IN OUT OUT IN OUT OUT IN OUT OUT IN OUT OUT IN OUT OUT PWR PWR OUT OUT OUT OUT IN IN IN IN DESCRIPTION Active low input for enabling DIF pair 9. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 10. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 11. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Ground pin. Power supply, nominal 3.3V Active low input for enabling DIF pair 12. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 13. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 14. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output A rising edge samples latched inputs and release Power Down Mode, a low puts the part into power down mode and tristates all outputs. 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 15 and 16. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 17, 18. 1 = tri-state outputs, 0 = enable outputs Input for reference clock. "Complementary" reference clock input. SMBus address bit 2. When Low, the part operates as a fanout buffer with the PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with the PLL operating. 0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
1255B--08/03/07
3
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
General Description
ThThe ICS9FG1904-1 follows the Intel DB1900GS Differential Buffer Specification, except for the output groupings and gear table. The gear table is a blend of the GS and GSO gearing. This buffer provides 19 output clocks for CPU Host Bus, PCIExpress, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups, DIF_(14:0) and DIF_(18:15) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410B+ main clock generator, such as the ICS932S421, drives the ICS9FG1904-1. The ICS9FG1904-1 can provide outputs up to 400MHz.
Block Diagram
OE_17_18# OE_15_16#
2
SPREAD COMPATIBLE 1:1 PLL
4 DIF(18:15)
OE(14:5)#, OE_01234#
11
CLK_IN CLK_IN#
SPREAD COMPATIBLE GEARING PLL
15 DIF(14:0)
HIGH_BW# FS_A_410 CKPWRGD/PD# SMB_A0 SMB_A1 SMB_A2_PLLBYP# SMBDAT SMBCLK
CONTROL LOGIC
IREF
Power Groups Pin Number VDD GND 3 2 11,27,47,63 10,28,46,64
Description Main PLLs, Analog DIF clocks
1255B--08/03/07
4
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
ICS 9FG1904B-1 Programmable Gear Ratios
CLK_IN (CPU FSB) MHz 100.00 100.00 100.00 100.00 100.00 100.00 133.33 133.33 133.33 133.33 133.33 166.67 166.67 166.67 160/ 166.67 166.67 200.00 200.00 200.00 200.00 200.00 266.67 266.667/ 320.00 266.67 333.33 320/ 333.33 333.33 400.00 400.00 400.00 400.00 400.00 Geared DIF Outputs MHz 133.33 166.67 200.00 266.67 333.33 400.00 166.67 200.00 266.67 333.33 100.00 133.33 200.00 266.67 320/ 333.33 400.00 133.33 166.67 266.67 333.33 400.00 133.33 166.67/ 200.00 200.00 133.33 160/ 166.67 200.00 133.33 160.00 166.67 320.00 333.33 M 3 3 1 3 3 1 4 2 1 2 4 5 5 5 1 5 3 6 3 3 1 2 8 4 5 2 5 3 5 12 5 6 Gear n Ratio n/M 4 5 2 8 10 4 5 3 2 5 3 4 6 8 2 12 2 5 4 5 2 1 5 3 2 1 3 1 2 5 4 5 1.333 1.667 2.000 2.667 3.333 4.000 1.250 1.500 1.250 1.500 0.750 0.800 1.200 1.600 2.000 2.400 0.667 0.833 1.333 1.667 2.000 0.500 0.625 0.750 0.400 0.500 0.600 0.333 0.400 0.417 0.800 0.833 (FS_A_410#) Byte 0, bit 4 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Byte 0, Byte 0, Byte 0, Byte 0, bit 3 bit 2 bit 1 bit 0 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes
1 1
1,3 1 1,2
1 1 1 1 1 1 1, 6 1 1 1,5 1 1,4 1 1 1 1
Notes: 1. Targetted input/output frequency pairs 2. This Gear is also used for 160MHz/320 MHz. 3. Gear Ratio 5/4 is power up default for FS_A_410 = 1 4. Gear Ratio 3/1 is power up default for FS_A_410 = 0 5. This Gear is also used for 400MHz/200MHz 6. This Gear is also used for 320MHz/200MHz
1255B--08/03/07
5
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
ICS 9FG1904B-1 1:1 PLL Programming
Byte 9, bit 2 FSC
1 0 0 0 0 1 1 1
Byte9, bit 1 FSB
0 0 1 1 0 0 1 1
Byte 9, bit 0 FS_A_410
1 1 1 0 0 0 0 1
CLK_IN 1:1 DIF (CPU FSB) Outputs MHz MHz 100.00 100.00 133.33 133.33 166.67 166.67 200.00 200.00 266.67 266.67 333.33 333.33 400.00 400.00 Reserved
Notes 3 3 1 3 3 3 2
Notes:FS_A_410 = 1 1. Powerup Default for FS_A_410 = 1 2. Powerup Default for FS_A_410 = 0 3. Setting the exact FSB frequency after Power is required for best phase noise performance.
Output Divider Ratios Binary Desired Value to Decimal write to Value Register 2 0000 3 0001 5 0010 7 0011 4 0100 6 0101 10 0110 14 0111 8 1000 12 1001 20 1010 28 1011 16 1100 24 1101 40 1110 56 1111
1255B--08/03/07
6
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
Absolute Max
PARAMETER 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection SYMBOL VDD_A VDD_In Ts Tambient Tcase ESD prot CONDITIONS MIN GND - 0.5 GND - 0.5 -65 0 Human Body Model 2000 TYP MAX UNITS VDD + 0.5V V V VDD + 0.5V 150 70 115
C C C V
Notes 1 1 1 1 1 1
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Input High Voltage VIH Input Low Voltage Input High Current Input Low Current Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Current Powerdown Current Input Frequency Pin Inductance Input Capacitance Clk Stabilization Modulation Frequency Tdrive_PD# Tfall_Pd# Trise_Pd# SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time VIL IIH I IL1 VIH_FS VIL_FS IDD3.3OP IDD3.3PD Fi Lpin CIN COUT TSTAB CONDITIONS 3.3 V +/-5% MIN 2 VSS - 0.3 -5 -5 0.7 VDD + 0.3 0.35 500 30 400 7 5 2.5 1.8 30 33 300 5 5 5.5 0.4 4 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 1000 300 TYP MAX VDD + 0.3 0.8 5 UNITS V V uA uA V V mA mA MHz nH pF pF ms kHz us ns ns V V mA ns ns 1 1 1 1 3 1 1 1 1 1 1 1 2 1 1 1 1 1 Notes 1 1
3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors 3.3 V +/-5%, Applies to FS_A_410 pin
3.3 V +/-5%, Applies to FS_A_410 VSS - 0.3 pin all outputs driven all differential pairs tri-stated VDD = 3.3 V 100 Logic Inputs Output pin capacitance From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation DIF output enable after PD# de-assertion PD# fall time of PD# rise time of Maximum input voltage @ I PULLUP
VMAX VOL IPULLUP TRI2C TFI2C
1255B--08/03/07
7
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo
1
CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value.
MIN 3000 660 -150 -300 250
TYP
MAX
UNITS NOTES 1 1,3 mV 1,3 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps 1 1 1 1 1,2,7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1,4,5 1,4
VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm
850 150 1150 550 140
Variation of crossing over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V 0 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175
Average period
Tperiod
0 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533
Absolute min period
Tabsmin
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Jitter, Cycle to cycle Notes:
tr tf d-tr d-tf dt3 tJCYC-CYC tJBYP
700 700 125 125 55 50 50
Measurement from differential wavefrom PLL mode, from differential wavefrom Bypass mode as additive jitter
45
1.Guaranteed by design and characterization, not 100% tested in production. 2. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that the input frequency meets CK410 accuracy requirements 3.IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. 4. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 5. Measured from differential cross-point to differential cross-point 6. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 7. This device does not introduce any ppm errors to the input clock.
1255B--08/03/07
8
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
Electrical Characteristics - Skew and Differential Jitter Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% Group Parameter Description Input-to-Output Skew in PLL mode (1:1 only), tSPO_PLL CLK_IN, DIF[x:0] nominal value @ 25C, 3.3V Input-to-Output Skew in Bypass mode (1:1 only), tPD_BYP CLK_IN, DIF[x:0] nominal value @ 25C, 3.3V Input-to-Output Skew Variation in PLL mode CLK_IN, DIF [x:0] tSPO_PLL (over specified voltage / temperature operating ranges) CLK_IN, DIF [x:0] DIF[14:0] DIF[18:15] DIF[18:0] DIF[18:0] DIF[18:0] NOTES: tPD_BYP tSKEW_G15
tSKEW_G4
Min -500 2.5
Max Units Notes 500 4.5 |350| |500| 100 50 150 10 80 ps ns ps ps ps ps ps ps ps
1,2,4,5,8 1,2,3,5 1,2,4,5,6, 10 1,2,3,4,5, 6,10 1,2 1.2 1,2,3 1,4,7 1,4,9
Input-to-Output Skew Variation in Bypass mode (over specified voltage / temperature operating ranges) Output-to-Output Skew Group of 15 (Common to Bypass and PLL mode) Output-to-Output Skew Group of 4 (Common to Bypass and PLL mode) Output-to-Output Skew across all 19 outputs (Common to Bypass and PLL mode - all outputs at same gear) Differential Phase Jitter (RMS Value) Differential Spread Spectrum Tracking Error (peak to peak)
tSKEW_A19 tJPH tSSTERROR
1. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 2. Measured from differential cross-point to differential cross-point 3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 4. This parameter is deterministic for a given device 5. Measured with scope averaging on to find mean value. 6. Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device. 7. This parameter is measured at the outputs of two separate ICS9FG1900 devices driven by a single CK410B. The ICS9FG1900's must be set to high bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the affects of spread spectrum). Target ranges of consideration are agents with BW of 1-22Mhz and 11-33Mhz. 8. t is the period of the input clock 9. Differential spread spectrum tracking error is the difference in spread spectrum tracking between two ICS9FG1900 devices This parameter is measured at the outputs of two separate ICS9FG1900 devices driven by a single CK410B in Spread Spectrum mode. The ICS9FG1900's must be set to high bandwidth. The spread spectrum characteristics are: maximum of 0.5%, 30-33KHz modulation frequency, linear profile. 10. This parameter is an absolute value. It is not a double-sided figure.
Electrical Characteristics - Phase Jitter Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, when driven by 932S421B or equivalent PARAMETER Symbol Conditions Min Typ t jphPCIe1 PCIe Gen 1 PCIe Gen 2 t jphPCIe2Lo 10kHz < f < 1.5MHz Jitter, Phase t jphPCIe2Hi t jphFBD1_3.2G t jphFBD1_4.0G
1
Max 108 3 3.1 3 2.5
Units ps (p-p) ps (RMS) ps (RMS) ps (RMS) ps (RMS)
Notes 1,2 1,2 1,2 1,2 1,2
PCIe Gen 2 1.5MHz < f < Nyquist (50MHz) FBD1 3.2/4G 11MHz to 33MHz FBD1 4.8G 11MHz to 33MHz
Notes: Guaranteed by design and characterization, not 100% tested in production. 2 See http://www.pcisig.com for complete specs
1255B--08/03/07
9
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
Programming the 9FG1904B-1
The 9FG1904B-1 uses advanced power saving features to detect when only geared outputs or only 1:1 outputs are needed. It then shuts down the unused PLL. At power up all outputs are coming from the 1:1 PLL and the Gear PLL is shut down. This power saving feature requires a little care when configuring the gear outputs in the device.
Configuring Gear Outputs of the 9FG1904B-1
Selecting Pre-configured Gear Ratios Byte 0 contains both the bits that enable the gear ratio outputs (Bits 7 and 6), and the bits that select the actual gear ratio (bits (4:0)). It is tempting to enable the gearing outputs and select the gear ratio at the same time. However, this can result in the inability to obtain the proper output frequency. Due to the power saving feature, it is necessary to perform this operation as two steps: 1. First, enable outputs to the gear ratio PLL, which actually powers up the gear ratio PLL (Set Byte 0, bits 7 and 6) 2. Then select the desired gear ratio in a separate write to byte 0 (Set Byte 0, bits (4:0) The actual order of the two operations is unimportant, so steps 1 and 2 could be reversed if desired. Programming Gear Ratios that are not Pre-Configured Most applications using the 9FG1904B-1 can obtain the desired output frequencies from the selections built into the gear table. There are two gear tables defined for these devices. There is the original GS gear set indicated by the DBxxxxGS yellow cover designation and the newer optimized GSO gear set indicated by DBxxxxGSO yellow cover designation. The 9FG1904B-1 contains a gear set that is a combination of the GS and GSO gear sets. The differences between the GS and GSO gear sets are highlighted in Figure 1 GS versus GSO versus 9FG1904B-1 Gear Ratios. Any gear in the GS or the GSO table that is not pre-configured in the 9FG1904B-1, and virtually any other input/output combination can be obtained by use of M/N programming. Note that care must be used or the jitter/bandwidth characteristics of the PLL can be compromised. The values provided later in this document have been verified to preserve the PLL performance of the device. Refer to the section Using M/N Programming to Obtain Other Gear Ratios for additional details.
1255B--08/03/07
10
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
GS Gear Ratios
CLK_IN (CPU FSB) MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 100.00 100.00 100.00 100.00 100.00 100.00 133.33 133.33 133.33 133.33 133.33 166.67 166.67 166.67 160/ 166.67 166.67 200.00 200.00 200.00 200.00 200.00 266.67 266.667/ 320 266.67 333.33 320/ 333.33 333.33 400.00 400.00 400.00 400.00 400.00 Geared DIF Outputs MHz 133.33 166.67 200.00 266.67 333.33 400.00 166.67 200.00 266.67 333.33 400.00 133.33 200.00 266.67 320/ 333.33 400.00 133.33 166.67 266.67 333.33 400.00 133.33 166.67/ 200 200.00 133.33 160/ 166.67 200.00 133.33 160.00 166.67 320.00 333.33 Gear Ratio n/M Mn 3 4 1.33 3 5 1.67 1 2 2.00 3 8 2.67 3 10 3.33 1 4 4.00 4 5 1.25 2 3 1.50 1 2 1.25 2 5 1.50 1 3 3.00 5 4 0.80 5 6 1.20 5 8 1.60 1 2 2.00 2.40 0.67 0.83 1.33 1.67 2.00 0.50 0.63 0.75 0.40 0.50 0.60 0.33 0.40 0.42 0.80 0.83
GSO Gear Ratios
CLK_IN (CPU FSB) MHz 100.00 100.00 100.00 100.00 100.00 133.33 133.33 133.33 133.33 133.33 133.33 166.67 166.67 166.67 166.67 166.67 200.00 200.00 200.00 200.00 200.00 266.67 266.67 266.67 333.33 333.33 333.33 400.00 400.00 400.00 400.00 400.00 Geared DIF Outputs MHz 133.33 166.67 200.00 266.67 333.33 100.00 166.67 200.00 266.67 333.33 400.00 133.33 200.00 266.67 333.33 400.00 133.33 166.67 266.67 333.33 400.00 133.33 166.67 200.00 133.33 166.67 200.00 133.33 166.67 200.00 266.67 333.33
9FG1904-1 Gear Ratios
CLK_IN Gear (CPU FSB) Ratio MHz n/M 1.33 100.00 1.67 100.00 2.00 100.00 2.67 100.00 3.33 100.00 0.75 100.00 1.25 133.33 1.50 133.33 2.00 133.33 2.50 133.33 3.00 133.33 0.80 166.67 1.20 166.67 1.60 166.67 160/ 2.00 166.67 2.40 166.67 0.67 200.00 0.83 200.00 1.33 200.00 1.67 200.00 2.00 200.00 0.50 266.67 266.667/ 0.63 320.00 0.75 266.67 0.40 333.33 320/ 0.50 333.33 0.60 333.33 0.33 400.00 0.42 400.00 0.50 400.00 0.67 400.00 0.83 400.00 Geared DIF Outputs M MHz 133.33 3 166.67 3 200.00 1 266.67 3 333.33 3 400.00 1 166.67 4 200.00 2 266.67 1 333.33 2 100.00 4 133.33 5 200.00 5 266.67 5 320/ 1 333.33 400.00 5 133.33 3 166.67 6 266.67 3 333.33 3 400.00 1 133.33 2 166.67/ 8 200.00 200.00 4 133.33 5 160/ 2 166.67 200.00 5 133.33 3 160.00 5 166.67 12 320.00 5 333.33 6 Gear Ratio n/M 1.33 1.67 2.00 2.67 3.33 4.00 1.25 1.50 1.25 1.50 0.75 0.80 1.20 1.60 2.00 2.40 0.67 0.83 1.33 1.67 2.00 0.50 0.63 0.75 0.40 0.50 0.60 0.33 0.40 0.42 0.80 0.83
M 3 3 1 3 3 4 4 2 1 2 1 5 5 5 1 5 3 6 3 3 1 2 8 4 5 2 5 3 12 2 6 6
n 4 5 2 8 10 3 5 3 2 5 3 4 6 8 2 12 2 5 4 5 2 1 5 3 2 1 3 1 5 1 4 5
n 4 5 2 8 10 4 5 3 2 5 3 4 6 8 2 12 2 5 4 5 2 1 5 3 2 1 3 1 2 5 4 5
5 12 32 65 34 35 12 21 8 4 5 2 5 3 5 12 5 6 5 3 2 1 3 1 2 5 4 5
Figure 1 GS versus GSO versus 9FG1904B-1 Gear Ratios
1255B--08/03/07
11
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
Using M/N Programming to Obtain Other Gear Ratios
M/N programming can be used to obtain input output frequency combinations that are not preconfigured in the 9FG1904B-1. Refer to Figure 2 PLL Block Diagram. The internal architecture of the 9FG1904B-1 is standard pseudo-ZDB architecture with internal feedback. This means that the REF divider, the Output divider and the Feedback divider all play a role in determining the output frequency. The output frequency is given by the equation: Output Frequency = (Input Frequency x N x Output Div)/M
Input Clock
REF (M) DIV FBK (N) DIV
vco
OUTPUT DIV
BUFFERS
Output Clocks
Figure 2 PLL Block Diagram
The DBxxxxGSO input/output combinations that are not in the 9FG1904B-1 gear table are shown in Table 1 DBxxxxGSO Gears Not Present in the 9FG1904B-1. This table also gives the values needed to program the gearing PLL to provide the desired input/output combination.
Byte 17 Byte 11 REF M Div (Hex) Byte 18 Byte 12 VCO N Div (Hex) A 4 6 Byte 19 Byte 13 Output Div (Hex) 0 4 1
1:1 PLL Bytes Gear PLL Bytes Decimal Post Divider FS_A_410# Input Frequency (Fref) Output Frequency Decimal M Value Decimal N Value
Line
1 0 133.33 400.00 4 12 2 3.000 2 1 400.00 200.00 12 6 4 0.500 3 1 400.00 266.67 12 8 3 0.667 Table 1 DBxxxxGSO Gears Not Present in the 9FG1904B-1
Gear
2 A A
Note before the M/N programming can be accomplished, Byte 10, bit 7 (the M/N_Enable bit) must be set to a `1'. The values provided in the table above have been verified to meet the specified performance of the 9FG1901B-1. Performance is not guaranteed for any other values that have not been pre-approved by IDT. Contact your local IDT representative for other values not mentioned here.
Setting the 1:1 PLL Operating Point
After configuring the Gearing outputs, it is also necessary to set the 1:1 PLL operating point by writing the input frequency value to Byte 9 bits (2:0). The input frequency is usually the CPU HCLK frequency.
1255B--08/03/07
12
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
9FG1904-1 SMBus Address Mapping when using CK410/CK410B, 9FG1200, and 9DB401/801 SMB_A(2:0) = 000 SMB Adr: D0 9FG1904-1 (DB1900GS) SMB_A(2:0) = 000 SMB Adr: D0 9FG1200-1 (DB1200GS)
OR
PLL B YPAS S M ODE S MB _A 2_PLLB YP# = 0
SMB_A(2:0) = 001 SMB Adr: D2 9FG1904-1 (DB1900GS)
OR
SMB_A(2:0) = 001 SMB Adr: D2 9FG1200-1 (DB1200GS)
OR
SMB Adr: D2 954101 932S401 (CK410/410B)
SMB_A(2:0) = 010 SMB Adr: D4 9FG1904-1 (DB1900GS)
OR
SMB_A(2:0) = 010 SMB Adr: D4 9FG1200-1 (DB1200GS)
SMB_A(2:0) = 011 SMB Adr: D6 9FG1904-1 (DB1900GS)
OR
SMB_A(2:0) = 011 SMB Adr: D6 9FG1200-1 (DB1200GS)
SMB_A(2:0) = 100 SMB Adr: D8 9FG1904-1 (DB1900GS)
OR
SMB_A(2:0) = 100 SMB Adr: D8 9FG1200-1 (DB1200GS)
P LL ZD B M ODE SM B_A2_PLLBYP# = 1
SMB_A(2:0) = 101 SMB Adr: DA 9FG1904-1 (DB1900GS)
OR
SMB_A(2:0) = 101 SMB Adr: DA 9FG1200-1 (DB1200GS)
SMB_A(2:0) = 110 SMB Adr: DC 9FG1904-1 (DB1900GS)
OR
SMB_A(2:0) = 110 SMB Adr: DC 9FG1200-1 (DB1200GS)
OR
SMB Adr: DC 9DB401/801 (DB400/800)
SMB_A(2:0) = 111 SMB Adr: DE 9FG1904-1 (DB1900GS)
OR
SMB_A(2:0) = 111 SMB Adr: DE 9FG1200-1 (DB1200GS)
1255B--08/03/07
13
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
General SMBus serial interface information for the ICS9FG1904B-1 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address *D0 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address *D0 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address *D1 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address *D0(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address *D0(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address *D1(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
* The SMBus Address of this device is programmable. See the preceding page for details on how to set the SMBus address.
X Byte Byte N + X - 1 N P Not acknowledge stoP bit
1255B--08/03/07
14
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
SMBusTable: Gear Ratio Select Register Pin # Name Control Function Byte 0 Group of 15 gear ratio enable Bit 7 DIF(14:0) Group of 4 gear ratio enable Bit 6 DIF(18:15) Reserved Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Gear Ratio FS4 (Inverse of FS_A_410 input!) Gear Ratio FS3 Gear Ratio FS2 Gear Ratio FS1 Gear Ratio FS0
0 Type RW Gear Ratio RW Gear Ratio RW RW RW RW RW RW
1 1:1 1:1
PWD 1 1 1 Latch 1 0 1 1
See ICS9FG1904-1 Programmable Gear Ratios Table
SMBusTable: Output Control Register Pin # Name Byte 1 DIF_7 Bit 7 DIF_6 Bit 6 DIF_5 Bit 5 DIF_4 Bit 4 DIF_3 Bit 3 DIF_2 Bit 2 DIF_1 Bit 1 DIF_0 Bit 0
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
SMBusTable: Output and PLL BW Control Register Byte 2 0 1 Pin # Name Control Function Type RW High BW Low BW see note PLL_BW# adjust Bit 7 RW Bypass PLL see note BYPASS# test mode / PLL Bit 6 DIF_13 Output Control RW Hi-Z Enable Bit 5 DIF_12 Output Control RW Hi-Z Enable Bit 4 DIF_11 Output Control RW Hi-Z Enable Bit 3 DIF_10 Output Control RW Hi-Z Enable Bit 2 DIF_9 Output Control RW Hi-Z Enable Bit 1 DIF_8 Output Control RW Hi-Z Enable Bit 0 Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode SMBusTable: Output Enable Readback Register Byte 3 Pin # Name Control Function Readback - OE9# Input Bit 7 Readback - OE8# Input Bit 6 Readback - OE7# Input Bit 5 Readback - OE6# Input Bit 4 Readback - OE5# Input Bit 3 Readback - OE_01234# Input Bit 2 Readback - HIGH_BW# In 8 Bit 1 Readback - SMB_A2_PLLBYP# In 72 Bit 0
1255B--08/03/07
PWD 1 1 1 1 1 1 1 1
Type R R R R R R R R
0 Readback Readback Readback Readback Readback Readback Readback Readback
1
PWD X X X X X X X X
15
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
SMBusTable: Output Enable Readback Register Byte 4 Pin # Name Control Function 69 Readback - OE17_18# Input Bit 7 60 Readback - OE15_16# Input Bit 6 Reserved Bit 5 54 Readback - OE14# Input Bit 4 51 Readback - OE13# Input Bit 3 48 Readback - OE12# Input Bit 2 43 Readback - OE11# Input Bit 1 40 Readback - OE10# Input Bit 0 SMBusTable: Vendor & Revision ID Register Pin # Name Control Function Byte 5 RID3 Bit 7 RID2 Bit 6 REVISION ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 SMBusTable: DEVICE ID Pin # Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type R R R R R R R
0 Readback Readback Readback Readback Readback Readback Readback
1
PWD X X X X X X X X
Type R R R R R R R R
0 -
1 -
PWD 0 0 0 1 0 0 0 1
Name
Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0
Type RW RW RW RW RW RW RW RW
0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
1
PWD 1 0 0 1 0 1 0 0
SMBusTable: Byte Count Register Byte 7 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0
Type RW RW RW Writing to this register RW configures how many RW bytes will be read back. RW RW RW
Control Function
0 -
1 -
PWD 0 0 0 0 0 1 1 1
1255B--08/03/07
16
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
SMBusTable: Control Pin Readback Register Name Control Function Pin # Byte 8 5 Readback - FS_A_410 Bit 7 RESERVED Bit 6 RESERVED Bit 5 DIF_18 Output Control Bit 4 DIF_17 Output Control Bit 3 DIF_16 Output Control Bit 2 DIF_15 Output Control Bit 1 DIF_14 Output Control Bit 0 SMBusTable: 1:1 PLL Operating Set Point Register Pin # Name Control Function Byte 9 RESERVED Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 Frequency Select C Bit 2 Frequency Select B Bit 1 Bit 0 FS_A_410
Type R
0 Readback
1
RW RW RW RW RW
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Enable Enable Enable Enable Enable
PWD X X X 1 1 1 1 1
Type
0
1
RW RW RW
See ICS9FG1904 1:1 PLL Programming Table
PWD 0 0 0 0 0 x 1 Latch
SMBus Table: M/N Programming & Watchdog Safe Register Pin # Name Control Function Byte 10 Gear and 1:1 PLL M/N M/N_EN Bit 7 Programming Enable RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit 0 SMBus Table: Gear PLL Frequency Control Register Byte 11 Pin # Name Control Function RESERVED Bit 7 RESERVED Bit 6 Gear PLL M Div5 Bit 5 Gear PLL M Div4 Bit 4 Gear PLL M Div3 Bit 3 M Divider Gear PLL M Div2 Bit 2 Gear PLL M Div1 Bit 1 Gear PLL M Div0 Bit 0
1255B--08/03/07
Type RW
0 Disable
1 Enable
PWD 0 X X X X X X X
Type
RW RW RW RW RW RW
PWD X X X X See M/N Programming Section X of the Data Sheet X X X
0
1
17
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
SMBus Table: Gear PLL Frequency Control Register Byte 12 Pin # Name Control Function Gear PLL N Div7 Bit 7 Gear PLL N Div6 Bit 6 Gear PLL N Div5 Bit 5 Gear PLL N Div4 Bit 4 N Divider Gear PLL N Div3 Bit 3 Gear PLL N Div2 Bit 2 Gear PLL N Div1 Bit 1 Gear PLL N Div0 Bit 0 SMBusTable: Reserved Register Byte 13 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Gear PLL Out Bit 3 Gear PLL Out Bit 2 Gear PLL Out Bit 1 Gear PLL Out Bit 0 SMBusTable: Reserved Register Byte 14 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBusTable: Reserved Register Byte 15 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 1 PWD Type RW X RW X RW X RW See M/N Programming Section X of the Data Sheet RW X RW X RW X RW X
Div Div Div Div
3 2 1 0
Control Function RESERVED RESERVED RESERVED RESERVED Gear PLL Output Divider Gear PLL Output Divider Gear PLL Output Divider Gear PLL Output Divider
Type
RW RW RW RW
PWD 0 0 0 0 x See Output Divider Ratios x Table x x
0
1
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
0
1
PWD 0 0 0 0 0 0 0 0
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
0
1
PWD 0 0 0 0 0 0 0 0
1255B--08/03/07
18
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
SMBusTable: Reserved Register Byte 16 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: 1:1 PLL Pin # Byte 17 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: 1:1 PLL Byte 18 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
0
1
PWD 0 0 0 0 0 0 0 0
Frequency Control Register Name Control Function Type 0 1 PWD X RESERVED X RESERVED 1:1 PLL M Div5 RW X 1:1 PLL M Div4 RW X M Divider Programming RW See M/N Programming Section X 1:1 PLL M Div3 of the Data Sheet bits 1:1 PLL M Div2 RW X 1:1 PLL M Div1 RW X 1:1 PLL M Div0 RW X Frequency Control Register 0 1 PWD Name Control Function Type 1:1 PLL N Div7 RW X 1:1 PLL N Div6 RW X 1:1 PLL N Div5 RW X N Divider Programming RW See M/N Programming Section X 1:1 PLL N Div4 of the Data Sheet b(7:0) 1:1 PLL N Div3 RW X 1:1 PLL N Div2 RW X 1:1 PLL N Div1 RW X 1:1 PLL N Div0 RW X
SMBusTable: Reserved Register Pin # Name Byte 19 Bit 7 Bit 6 Bit 5 Bit 4 1:1 PLL Out Bit 3 1:1 PLL Out Bit 2 1:1 PLL Out Bit 1 1:1 PLL Out Bit 0
Div Div Div Div
3 2 1 0
Control Function RESERVED RESERVED RESERVED RESERVED 1:1 PLL Output Divider 1:1 PLL Output Divider 1:1 PLL Output Divider 1:1 PLL Output Divider
Type
RW RW RW RW
PWD 0 0 0 0 x See Output Divider Ratios x Table x x
0
1
1255B--08/03/07
19
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
SMBusTable: Reserved Register Byte 20 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
0
1
PWD 0 0 0 0 0 0 0 0
SMBusTable: Test Byte Register Byte 21 Test Test Function ICS ONLY TEST Bit 7 ICS ONLY TEST Bit 6 ICS ONLY TEST Bit 5 ICS ONLY TEST Bit 4 ICS ONLY TEST Bit 3 ICS ONLY TEST Bit 2 ICS ONLY TEST Bit 1 ICS ONLY TEST Bit 0 Note: Do NOT write to Bit 21. Erratic device operation will result!
Type RW RW RW RW RW RW RW RW
Test Result Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PWD 0 0 0 0 0 0 0 0
1255B--08/03/07
20
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
Seating Plane Index Area N 1 E Top View Anvil Singulation OR Sawn Singulation E2 E2 2 A1 A3 L
(Ref. )
(N D - 1)x e
(Ref. )
ND & NE Even N e (Typ.) 2 If N D & N E are Even 1 2 (N E - 1)x e
(Ref. )
b A
(Ref.)
e D2 2 D2
D
ND & NE Odd C
Thermal Base
Chamfer 4x 0.6 x 0.6 max OPTIONAL
0.08
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS SYMBOL A A1 A3 b e MIN. MAX. 0.8 1.0 0 0.05 0.25 Reference 0.18 0.3 0.50 BASIC
DIMENSIONS SYMBOL N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. ICS 72L TOLERANCE 72 18 18 10.00 x 10.00 5.75 / 6.15 5.75 / 6.15 0.30/ 0.50
Ordering Information
ICS 9FG1904BK-1LFT
Example:
ICS XXXX B K - V LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Variation Number Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers)
1255B--08/03/07
21
Integrated Circuit Systems, Inc.
ICS9FG1904B-1
Revision History
Rev. A B Issue Date Description 1. Added Output Divider Table. 2. Added Phase Jitter Table to electrical characteristics. 05/04/07 3. Added M/N programming information. 4. Changed part number to reference 9FG1904B-1. 08/03/07 Release to Final. Page # Various -
1255B--08/03/07
22

▲Up To Search▲

Price & Availability of ICS9FG1904B-1

	To Download ICS9FG1904B-1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .