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PD - 97323
IRFP4004PBF
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits
G
HEXFET(R) Power MOSFET
D
VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited)
Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability
S
40V 1.35m 1.70m 350Ac 195A
D
D G
S
TO-247AC
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Wire Bond Limited) Pulsed Drain Current d Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery f Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
350c 250c 195 1390 380 2.5 20 2.0 -55 to + 175 300 10lbxin (1.1Nxm)
Units
A
W W/C V V/ns C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy e Avalanche Current d Repetitive Avalanche Energy g 290 See Fig. 14, 15, 22a, 22b mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA
Parameter
Junction-to-Case k Case-to-Sink, Flat Greased Surface Junction-to-Ambient jk
Typ.
--- 0.24 ---
Max.
0.40 --- 40
Units
C/W
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1
06/05/08
IRFP4004PBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage
Min. Typ. Max. Units
40 --- --- 2.0 --- --- --- --- --- --- 0.035 --- 1.35 1.70 --- 4.0 --- 20 --- 250 --- 200 --- -200
Conditions
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAd m VGS = 10V, ID = 195A g V VDS = VGS, ID = 250A A VDS = 40V, VGS = 0V VDS = 40V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync RG(int) td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Internal Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
290 --- --- --- ---
---
Conditions
VDS = 10V, ID = 195A ID = 195A VDS = 20V VGS = 10V g ID = 195A, VDS =0V, VGS = 10V
--- 220 59 75 145 6.8 59 370 160 190 8920 2360 930 2860 3110
--- 330 --- --- --- --- --- --- --- --- --- --- --- --- ---
S nC
---
ns
VDD = 20V ID = 195A RG = 2.7 VGS = 10V g VGS = 0V VDS = 25V = 1.0MHz VGS = 0V, VDS = 0V to 32V i VGS = 0V, VDS = 0V to 32V h
--- --- --- --- --- --- Effective Output Capacitance (Energy Related)i --- --- Effective Output Capacitance (Time Related)h
pF
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) di Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- 350c 1390 A
Conditions
MOSFET symbol showing the integral reverse
G S D
--- --- 1.3 V --- 83 130 ns --- 78 120 --- 190 290 nC TJ = 125C --- 210 320 --- 4.0 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode. TJ = 25C, IS = 195A, VGS = 0V g TJ = 25C VR = 20V, TJ = 125C IF = 195A di/dt = 100A/s g TJ = 25C
Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 195A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. Refer to App Notes (AN-1140). Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.015mH RG = 25, IAS = 195A, VGS =10V. Part not recommended for use above this value.
ISD 195A, di/dt 690A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994. Coss while VDS is rising from 0 to 80% VDSS.
R is measured at TJ approximately 90C.
2
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IRFP4004PBF
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
BOTTOM
BOTTOM
100
100
4.5V
4.5V
60s PULSE WIDTH
Tj = 25C 10 0.1 1 V DS, Drain-to-Source Voltage (V) 10 10 0.1
60s PULSE WIDTH
Tj = 175C 1 V DS, Drain-to-Source Voltage (V) 10
Fig 1. Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance
Fig 2. Typical Output Characteristics
2.0 ID = 195A VGS = 10V
ID, Drain-to-Source Current (A)
100
T J = 175C
1.5
(Normalized)
T J = 25C 10
1.0
VDS = 10V 60s PULSE WIDTH 1.0 3 4 5 6 7 8
0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C)
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd Coss = Cds + Cgd
Fig 4. Normalized On-Resistance vs. Temperature
12.0 ID= 195A
VGS , Gate-to-Source Voltage (V)
10.0
C, Capacitance (pF)
VDS= 32V VDS= 24V
10000
Ciss Coss Crss
8.0
6.0
1000
4.0
2.0
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0.0 0 50 100 150 200 250 Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFP4004PBF
1000 10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 100sec
ISD, Reverse Drain Current (A)
T J = 175C 100
ID, Drain-to-Source Current (A)
1000
10
T J = 25C
100
1msec
10msec 10 Tc = 25C Tj = 175C Single Pulse 1 1 DC
1 VGS = 0V 0.1 0.0 0.4 0.8 1.2 1.6 2.0 VSD, Source-to-Drain Voltage (V)
10 VDS, Drain-to-Source Voltage (V)
100
Fig 7. Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
350 300
ID, Drain Current (A)
Fig 8. Maximum Safe Operating Area
52 Id = 5.0mA 50
Limited By Package
250 200 150 100 50 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
48
46
44
42
40 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C )
Fig 9. Maximum Drain Current vs. Case Temperature
2.5
Fig 10. Drain-to-Source Breakdown Voltage
1200
EAS , Single Pulse Avalanche Energy (mJ)
2.0
1000
ID 36A 73A BOTTOM 195A TOP
800
Energy (J)
1.5
600
1.0
400
0.5
200
0.0 -5 0 5 10 15 20 25 30 35 40
0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C)
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRFP4004PBF
1
Thermal Response ( Z thJC ) C/W
D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) 1E-005 0.0001 0.001
J J 1 R1 R1 2 R2 R2 R3 R3 3 R4 R4 C 2 3 4 4
Ri (C/W)
0.0123 0.0585 0.1693 0.1601
i (sec)
0.000011 0.000055 0.000917 0.008784
1
Ci= i/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.01 0.1
0.001 1E-006
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100 0.05 0.10 10
0.01
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
300 TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 195A
EAR , Avalanche Energy (mJ)
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
0 25 50 75 100 125 150 Starting T J , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFP4004PBF
5.0
VGS(th) , Gate threshold Voltage (V)
12 IF = 78A V R = 34V TJ = 25C TJ = 125C
4.5 10 4.0 3.5 3.0 2.5 2.0 4 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( C ) 2 0 ID = 250A ID = 1.0mA ID = 1.0A
IRR (A)
8
6
200
400
600
800
1000
diF /dt (A/s)
Fig 16. Threshold Voltage vs. Temperature
14 IF = 117A V R = 34V TJ = 25C TJ = 125C
Q RR (A)
Fig. 17 - Typical Recovery Current vs. dif/dt
350 IF = 78A V R = 34V TJ = 25C TJ = 125C
12
300
10
IRR (A)
250
8
200
6
150
4
100
2 0 100 200 300 400 500 600 diF /dt (A/s)
50 0 200 400 600 800 1000 diF /dt (A/s)
Fig. 18 - Typical Recovery Current vs. dif/dt
400 IF = 117A V R = 34V TJ = 25C TJ = 125C
Fig. 19 - Typical Stored Charge vs. dif/dt
350
300
Q RR (A)
250
200
150
100 0 100 200 300 400 500 600 diF /dt (A/s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFP4004PBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 21a. Unclamped Inductive Test Circuit
LD VDS
Fig 21b. Unclamped Inductive Waveforms
VDS
90%
+
VDD -
D.U.T VGS Pulse Width < 1s Duty Factor < 0.1%
10%
VGS
td(on) tr td(off) tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id Vds Vgs
L VCC
0
DUT 1K
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 23a. Gate Charge Test Circuit
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Fig 23b. Gate Charge Waveform
7
IRFP4004PBF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
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TO-247AC package is not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 06/08
8
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