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Ordering number : ENA0569A
LC74736PT
Overview
CMOS IC
On-Screen Display Controller
The LC74736PT is an on-screen display CMOS IC that displays characters and patterns on a TV screen under the control of a microcontroller. For QVGA display, the LC74736PT supports the use of both a 16 x 16 dot character font and a 16 x 16 dot graphic font with 16 colors. For WVGA display, the LC74736PT supports the use of both a 24 x 32 dot character font and a 24 x 32 dot graphic font with 16 colors. The LC74736PT can also implement extremely varied displays by the use of an external ROM. The LC74736PT supports both QVGA (480x234) and WVGA (800x480).
Features
(1) Screen structure Main: 2 screens (1 screen for WVGA display) 30 charactersx15 lines (up to 450 characters) on a QVGA panel 33 charactersx15 lines (up to 495 characters) on a WVGA panel (Up to 34 charactersx18 lines) Wallpaper display screen: QVGA mode: maximum Permanent repetition of a 4x4 (horizontalxvertical) character pattern WVGA mode: maximum Permanent repetition of a 2x2 (horizontalxvertical) character pattern
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
60607HKIM 20061221-S00013 No.A0569-1/106
LC74736PT
(2) Character structure QVGA mode: About 9MHz 16 dots (horizontal) x16 dots (vertical): Character display 16 dots (horizontal) x16 dots (vertical): Graphic glyph display WVGA mode: About 33.2MHz 24 dots (horizontal) x32 dots (vertical): Character display 24 dots (horizontal) x32 dots (vertical): Graphic glyph display Character display clock: LC oscillator (about 10MHz) External clock signal input (up to 40MHz) Built-in PLL (VCO) (7 to 40MHz) (3) Number of characters QVGA mode Up to 16384 characters when an external 16-bit 16M ROM is used. WVGA mode Up to 4096 characters when an external 16-bit 16M ROM is used. No internal ROM Internal character RAM QVGA: 4 characters, WVGA: 1 character (4) Character sizes: Four horizontal sizes (1x, 2x, 3x, and 4x) Four vertical sizes (1x, 2x, 3x, and 4x) (The character size is specified in line units.) (5) Display start positions: 1024 positions in the horizontal direction and 512 positions in the vertical direction. Setting units: Horizontal: 1 dot (in screen units) Vertical: 1 dot (in screen units) (6) Display functions * Blinking specification (in character units) Period: 1/64, 1/32, and 1/16 of the vertical sync signal (in screen units) Duty: Fixed at 50% * Box (raised or recessed) display Raised/recessed specification (in character units) Left: Off/on specification (in character units) Right: Off/on specification (in character units) Top: Off/on specification (in character units) Bottom: Off/on specification (in character units) * Border specification (in line units): Only valid with glyphs from the character font. (7) Color specification Character * Character color (in character units): 1 of 16 colors can be specified. * Character background color (in character units): 1 of 16 colors can be specified. * Border color (in line units): 1 of 16 colors can be specified. Graphic * 16 types can be specified by ROM data Graphic 2 * 16 types can be specified by ROM data 1 color type can be changed. Graphic 3 * 16 types can be specified by ROM data 1 color table type can be changed. * Box (raised or recessed) color (line units): 1 of 16 colors can be specified. * Background color (screen units): 1 of 16 colors can be specified.
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(8) Color table (palette) * Sixteen colors can be selected from a set of 4096 colors (One of which is specified to be transparent.) * Number of color tables: 4. This allows up to 64 colors to be displayed at the same time. (9) Wallpaper screen (Graphics glyphs only) Wallpaper display: Repeated display under the main screen (up to 4 characters horizontally by 4 characters vertically). Sprite character display: Displayed above the main screen (up to 4 characters horizontally by 4 characters vertically). (10) Line spacing control 0-15 scan lines (in line units) (11) Output Analog RGB output( to 20MHz) Digital RGB output (4 bits per color) BLK (OSD display period signal) Package: TQFP100 Voltage: 3.3V
Package Dimensions
unit : mm (typ) 3274
16.0 14.0 75 76 51 50
100 1 (1.0)
(1.0)
26 0.5 0.2 25 0.125
1.2max
0.1
SANYO : TQFP100(14X14)
14.0 16.0
0.5
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Pin Assignment
VDD3 VDD3 VDD3 VSS3 VSS3 VSS3
A16
A17 CCOMP
A10
A11
A12
A13
A14
A0
A1
A2
A3
A4
A5
A6
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VSS1 1 VDD1 2 OSCin 3 OSCout 4 EXTclk 5 CTRL1 6 SCLK 7 SIN 8 CS 9 VSYNC 10 HSYNC 11 TEST1 12 TEST2 13 RST 14 CLKOUT 15 VSS1 16 NC 17 NC 18 NC 19 NC 20 NC 21 VSS4 22 PD0 23 VCOR 24 VDD4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 HFTOT GOUT ROUT BOUT RREF BFin BFout VDD1 GD3 GD2 GD1 GD0 VSS1 VDD2 VSS2 Top view No.A0569-4/106 BD3 BD2 BD1 RD3 RD2 RD1 RD0 BD0 BLK 75 A19 74 CE 73 OE 72 VDD3 71 VSS3 70 VDD1 69 VSS1 68 D0 67 D1 66 D2 65 D3 64 D4 63 D5 62 D6 61 D7 60 VDD1 59 VSS1 58 D8 57 D9 56 D10 55 D11 54 D12 53 D13 52 D14 51 D15
A7
LC74736PT
A15
A8
A9
A18
LC74736PT
Pin Functions
Pin No. 1 2 3 4 5 6 Symbol VSS1 VDD1 OSCin OSCout EXTclk CTRL1 External clock signal input OSCin oscillator input control Ground Power supply (+3.3V) LC oscillator Type Functional description Connect a ground to this pin. (Digital system ground) Digital system power supply: +3.3V Connect to the character output dot clock generator oscillator coil and capacitor. Receives an external clock signal. Capacitor coupling, 50% duty cycle, 0.5Vp-p or higher Switches between external clock input mode and LC oscillator mode. Low: LC oscillator, high: external clock input MORE+ OR control with MORE+ command 7 8 9 SCLK SIN CS Clock input Data input Enable input Clock input for the serial data input system MORE+ (This input has hysteresis characteristics.) Serial data input MORE+ (This input has hysteresis characteristics.) Enable input for the serial data input system. Serial data input is enabled when this pin is set low. MORE+ (This input has hysteresis characteristics.) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 VSYNC HSYNC TEST1 TEST2 RST CLKOUT VSS1 NC NC NC NC NC VSS4 PD0 Ground PLL charge pump output PLL VCO control voltage input 24 25 26 27 28 29 30 31 32 33 34 35 36 VCOR VDD4 BFin BFout RD3 RD2 RD1 RD0 GD3 GD2 GD1 GD0 VDD1 VCO variable range adjustment Power supply (+3.3V) Amplifier input Amplifier output Rout output: bit 3 Rout output: bit 2 Rout output: bit 1 Rout output: bit 0 Gout output: bit 3 Gout output: bit 2 Gout output: bit 1 Gout output: bit 0 Power supply (+3.3V) Digital system power supply: +3.3V Gout output This is a 4-bit digital output with values from 0000 to 1111. Connect a ground tro this pin. (PLL system power supply) Charge pump output Connect a LPF (lug lead filter) to this pin. Voltage input for internal VCO control Used to adjust variable voltage range of internal VCO. Connect a resistor to this pin. PLL system power supply: +3.3V Oscillation input for external VCO Oscillation output for external VCO Rout output This is a 4-bit digital output with values from 0000 to 1111. Vertical sync signal input Horizontal sync signal input Test mode control 1 Test mode control 2 Reset input Clock output Ground Vertical sync signal input MORE+ (This input has hysteresis characteristics.) Horizontal sync signal input MORE+ (This input has hysteresis characteristics.) Test mode control 1 Low: normal operation, high: test mode MORE+ Test mode control 2 Low: normal operation, high: test mode (scan mode) MORE+ System reset input MORE+ (This input has hysteresis characteristics.) Clock output Connect a ground to this pin. (Digital system ground)
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Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Symbol BD3 BD2 BD1 BD0 BLK HFTOT VSS1 Rout Gout Bout RREF VDD2 CCOMP VSS2 D15 D14 D13 D12 D11 D10 D9 D8 VSS1 VDD1 D7 D6 D5 D4 D3 D2 D1 D0 VSS1 VDD1 VSS3 VDD3 OE CE A19 A18 A17 A16 VSS3 VDD3 A15 A14 A13 A12 A11 Type Bout output: bit 3 Bout output: bit 2 Bout output: bit 1 Bout output: bit 0 Blanking signal output Halftone control signal output Ground Rout output: analog Gout output: analog Bout output: analog Reference resistor connection Power supply (+3.3V) Phase correction capacitor connection Ground Data input 15 Data input 14 Data input 13 Data input 12 Data input 11 Data input 10 Data input 9 Data input 8 Ground Power supply (+3.3V) Data input 7 Data input 6 Data input 5 Data input 4 Data input 3 Data input 2 Data input 1 Data input 0 Ground Power supply (+3.3V) Ground Power supply (+3.3 or +5.5V) Output enable Chip enable Address output 19 Address output 18 Address output 17 Address output 16 Ground Power supply (+3.3 or +5.5V) Address output 15 Address output 14 Address output 13 Address output 12 Address output 11 This signal indicates the OSD display period. OSD halftone period control signal Synthesized in the next stage IC. Connect a ground to this pin. (Digital system ground) D/A converter (4 bits) output. Connect a resistor Ro to this pin. D/A converter (4 bits) output. Connect a resistor Ro to this pin. D/A converter (4 bits) output. Connect a resistor Ro to this pin. Connect a reference register to this pin. D/A converter power supply: +3.3V Capacitor connection: 1.5F Connect a ground to this pin. (D/A converter ground) ROM data input 15. MORE+ [MSB] ROM data input 14. MORE+ ROM data input 13. MORE+ ROM data input 12. MORE+ ROM data input 11. MORE+ [MSB] ROM data input 10. MORE+ ROM data input 9. MORE+ ROM data input 8. MORE+ Connect a ground to this pin. (Digital system ground) Digital system power supply: +3.3V ROM data input 7. MORE+ ROM data input 6. MORE+ ROM data input 5. MORE+ ROM data input 4. MORE+ ROM data input 3. MORE+ ROM data input 2. MORE+ ROM data input 1. MORE+ ROM data input 0. MORE+ [LSB][LSB] Connect a ground to this pin. (Digital system ground) Power supply: (+3.3V: Digital system) Connect a ground to this pin. (External ROM output system ground) Power supply (External ROM output system power supply) ROM output enable output. This is an active low output. ROM chip enable output. This is an active low output. ROM address output 19 ROM address output 18 ROM address output 17 ROM address output 16 Connect a ground to this pin. (External ROM output system ground) Power supply (External ROM output system power supply) ROM address output 15 ROM address output 14 ROM address output 13 ROM address output 12 ROM address output 11 Bout output This is a 4-bit digital output with values from 0000 to 1111. Functional description
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Pin No. 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol A10 A9 A8 VSS3 VDD3 A7 A6 A5 A4 A3 A2 A1 A0 VSS3 VDD3 Type Address output 10 Address output 9 Address output 8 Ground Power supply (+3.3 or +5.5V) Address output 7 Address output 6 Address output 5 Address output 4 Address output 3 Address output 2 Address output 1 Address output 0 Ground Power supply (+3.3 or +5.5V) ROM address output 10 ROM address output 9 ROM address output 8 Connect a ground to this pin. (External ROM output system ground) Power supply (External ROM output system power supply) ROM address output 7 ROM address output 6 ROM address output 5 ROM address output 4 ROM address output 3 ROM address output 2 ROM address output 1 ROM address output 0 Connect a ground to this pin. (External ROM output system ground) Power supply (External ROM output system power supply) Functional description
Specifications
Absolute Maximum Ratings at Ta=25C
Parameter Supply voltage Symbol VDD1 VDD3 Input voltage Output voltage VIN VOUT1 VOUT2 Maximum power dissipation Operating temperature Storage temperature Pd max Topr Tstg Conditions VDD1,VDD2, and VDD4 VDD3 All input pins RD3 to RD0, GD3 to GD0, BD3 to BD0, BLK, HFTOT outputs A0 to 19, CE, OE outputs Ratings VSS-0.3 to VSS+4.6 VSS-0.3 to VSS+6.0 VSS-0.3 to VDD1+0.3 VSS-0.3 to VDD1+0.3 VSS-0.3 to VDD3+0.3 275 -40 to +85 -40 to +125 Unit V V V V V mW C C
Recommended Operating Conditions
Parameter Supply voltage Symbol VDD1 VDD3 Input high-level voltage VIH1 VIH2 VIH3 Input low-level voltage VIL1 VIL2 VIH3 Oscillator frequency (LC) External clock input FOSC1 FOSC2 VIN1 Oscillator frequency (VCO) D/A converter (4-bit, 3 ch) When maximum output voltage = 0.7V FOSC3 Vrefda Rfda Rref Conditions min VDD1, 2, and VDD4 VDD3 CTRL1, TEST1, TEST2 SCLK, SIN, CS, VSYNC, HSYNC, RST D0 to D15 CTRL1, TEST1, TEST2 SCLK, SIN, CS, VSYNC, HSYNC, RST D0 to D11 OSCin and OSCout oscillator pins (LC oscillator) OSCin, VDD1 = 3.3V VDD1 = 3.3V CTRL1 = high VCO oscillator (internal) Reference voltage Output load resistance ROUT, GOUT, BOUT Reference load resistance, RREF 120 1100 0.5 7 1.1 225 3.0 3.0 0.7VDD1 0.8VDD1 0.7VDD1 VSS-0.3 VSS-0.3 VSS-0.3 10 33 40 3.3 40 Ratings typ 3.3 3.3 max 3.6 5.5 5.5 5.5 5.5 0.3VDD1 0.2VDD1 0.3VDD1 V V V V V V V V MHz MHz Vp-p MHz V Unit
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Electrical Characteristics at Ta = -40 to +85C, VDD = 3.3V unless otherwise specified
Parameter Output high-level voltage VOH2 VOH3 Symbol VOH1 Pin RD3 to RD0, GD3 to GD0, BD3 to BD0, BLK, and HFTOT outputs A0 to A19, CE, and OE A0 to A19, CE, and OE Conditions min VDD1 = 3.0V IOH1 = -8mA VDD3 = 3.0V IOH2 = -8mA VDD3 = 4.5V IOH3 = -8mA VDD1 = 3.0V IOL1 = 8mA VDD3 = 3.0V IOL2 = 8mA VDD3 = 4.5V IOL3 = 8mA VIN = VDD1 10 VIN = VDD3 VIN = VSS VIN = VSS All outputs open OSCin: 20MHz IDD2 IDD3 IDD4 D/A converter CLK V max V min0 VDD2 VDD3 VDD4 Clock frequency Maximum output voltage Minimum output voltage VDD2 = 3.3V VDD2 = 3.3V 0.25 0 VCO on D/A on -10 -10 25 22 10 22 20 1.5 10 A A A A mA mA mA mA MHz V V VDD1 -0.8 VDD3 -0.8 VDD3 -0.8 0.4 Ratings typ max V Unit
V V
Output low-level voltage
VOL1 VOL2 VOL3
RD3 to RD0, GD3 to GD0, BD3 to BD0, BLK, and HFTOT outputs A0 to A19, CE, and OE A0 to A19, CE, and OE CTRL1, TEST1, TEST2 SCLK, SIN, CS, VSYNC, HSYNC, RST D0 to D15 CTRL1, TEST1, TEST2 SCLK, SIN, CS, VSYNC, HSYNC D0 to D15 VDD1
V
0.4
V
0.4
V
Input current
IIH1
IIH2 IIL1 IIL2 Operating current drain IDD1
Timing Characteristics
OSD Write (See figure 1.) at Ta = -40 to +85C, VDD1 = 3.3V 0.3V
Parameter Minimum input pulse width Symbol tw(sclk) tw(cs) Data setup time tsu(cs) tsu(sin) Data hold time th(cs) th(sin) One word write time tword twt SCLK CS (The period CS is high) CS SIN CS SIN The time to write 8 bits of data RAM data write time Conditions min 200 1 200 200 2 200 4.2 1 Ratings typ max ns s ns ns s ns s s Unit
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Supplementary Materials
tw(cs)
CS
tsu(cs)
tw(sclk)
tw(sclk)
th(cs)
SCLK
tsu(sin)
th(sin)
SIN
CS tword twt SCLK 0 1 5 6 7 0 1 4 5 6 7
Figure 1 OSD Serial Data Input Timing
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System Block Diagram
VDD1 to 4 CS SIN SCLK Serial-toparallel converter 16-bits latch + command decoder VSS1 to 4
RST
Horizontal direction control register
Address control circuit
HSYNC HBLK
Horizontal direction counter Vertical direction control register
VRAM
VSYNC VBLK
Vertical direction counter RAM and ROM read and write control
Address control circuit
External ROM control circuit
OE,CE A0 to 19
D0 to 15 FRAM
RD3 to 0 Character size control OSCin OSCout CTRL1 EXTCLK D/A VCO PD CP Timing generator GD3 to 0 Output control circuit BD3 to 0 BLK HFTOT
OUTR ROUT GOUT BOUT CCOMP CVREF RREF
CPout FC BFin BFout
VCOR
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Display Control Commands
The display control commands have serial input format that consists of 8-bit units transmitted LSB first. A commands consists of a command identification code in the first byte and data in the second and following bytes. Both a first byte and a second byte (16 bits) must be transmitted for each command. Commands 10, 11, 12, 6C1, and 701 set the IC to continuous write mode. (Continuous write mode is cleared by setting the CS pin high.) Display Control Command Table
First byte Command 7 COMMAND00 (Write address) Main 1: V COMMAND01 (Write address) Main 1: H COMMAND02 (Write address) Main 2: V COMMAND03 (Write address) Main 2: H COMMAND04 (Write address) Sub COMMAND10 (Character write) Main 1 1 0 0 1 0 0 RM2 RM1[1] [2] [3] [4] [5] COMMAND11 (Character write) Main 2 1 0 0 1 0 1 RM2 RM1[1] [2] [3] [4] [5] COMMAND12 (Character write) Sub 1 0 0 1 1 0 RM2 RM1[1] [2] [3] [4] [5] COMMAND20 (System control) COMMAND21 (Display control) COMMAND22 (I/O polarity control 1) COMMAND23 (Screen background color) COMMAND24 (I/O polarity control 2) 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 1 DPM DPM HC1 HC0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 HF1 CB3 0 0 C7 HF1 CB3 0 0 C7 0 0 0 0 C7 TST MD2 BK 12 0 HF0 CB2 at CB1 BXS CB0 I/E C12 C4 BXS CB0 I/E C12 C4 0 0 I/E C12 C4 FRM ERS BK 01 BLO 1 BGC T0 SBG SL BXL CC3 MG1 C11 C3 BXL CC3 MG1 C11 C3 0 0 MG1 C11 C3 CT ERS DSP BG BLO 0 BGC 3 GD 2 BGC 2 GD 1 BGC 1 BGC 0 BXR CC2 MG0 C10 C2 BXR CC2 MG0 C10 C2 0 0 MG0 C10 C2 SRM ERS DSP GS CKP BXU CC1 RO1 C9 C1 BXU CC1 RO1 C9 C1 0 0 RO1 C9 C1 BXD CC0 RO0 C8 C0 BXD CC0 RO0 C8 C0 0 0 RO0 C8 C0 1 0 0 0 1 0 0 0 SV1 SV0 0 0 0 0 SH1 SH0 1 0 0 0 0 1 1 0 0 0 H25 H24 H23 H22 H21 H20 1 0 0 0 0 1 0 0 0 0 0 V24 V23 V22 V21 V20 1 0 0 0 0 0 1 0 0 0 H15 H14 H13 H12 H11 H10 1 6 0 Command identification code data 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 V14 Second byte Data 3 V13 2 V12 1 V11 0 V10
CTB1 CTB0 0 C6 HF0 CB2 C13 C5 at CB1
CTB1 CTB0 0 C6 0 0 C13 C5 0 0
CTB1 CTB0 0 C6 TST MD1 BK 02 C13 C5 SYS RST BK 11
MRM MRM ER2 ERS1 DSP GM2 VIP DSP GM1 HIP
BLOP BLO 2 BGC T1 DA SEL
DPM DPM MD VC
GD CKOP 0
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First byte Command 7 COMMAND25 (Output control 1) COMMAND26 (Output control 2) COMMAND27 (Output control 3) COMMAND28 (Output control 4) COMMAND29 (Output control 5) COMMAND2A (Display area control 1) COMMAND30 (Vertical display start position: main 1) COMMAND31 (Horizontal display start position: main 1) COMMAND32 (Vertical display start position: main 2) COMMAND33 (Horizontal display start position: main 2) COMMAND34 (Vertical display start positions: sub) COMMAND35 (Horizontal display start position: sub) COMMAND36 (Vertical display start positions: screen) COMMAND37 (Horizontal display start position: screen) 1 0 1 1 1 1 1 HPG 8 1 0 1 1 1 1 0 1 0 1 1 1 0 1 HPS 8 0 1 0 1 1 1 0 0 1 0 1 1 0 1 1 HPM 28 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 HPM 18 0 1 0 1 1 0 0 0 0 VPM 17 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 0 HPG 9 0 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 6 0 Command identification code data 5 1 4 0 3 0 2 1 1 0 0 1 7 CEH SL HF OFF 0 6 TOK SL TBL OFF HFT 2 HPS 9 SVH 1 HIN DIN VPM 16 5 VI PSL KBL 2 HFT 1 HPM 29 SVH 0 HI D1 VPM 15 HPM 15 VPM 25 HPM 25 VPS 5 HPS 5 VPG 5 HPG 5 4 LCS SP2 BL 1 HFT 0 HPM 19 SHH 1 HI D0 VPM 14 HPM 14 VPM 24 HPM 24 VPS 4 HPS 4 VPG 4 HPG 4 Second byte Data 3 2 1 LCS STP ROT OFF TOK CB2 VPM 28 0 0 LCS OFF DOT OFF TOK CB1 VPM 18 ML CH VI D0 VPM 12 VPM 11 VPM 10 0 0
OTM OTM 1 BL 0 TOK CB4 VPG 8 SHH 0 VI D1 VPM 1 0 OTM 2 TOK CB3 VPS 8 0
HPM HPM 17 VPM 27 16 VPM 26
HPM HPM 13 VPM 23 12 VPM 22
HPM HPM 11 VPM 21 10 VPM 20
HPM HPM 27 VPS 7 HPS 7 VPG 7 HPG 7 26 VPS 6 HPS 6 VPG 6 HPG 6
HPM HPM 23 VPS 3 HPS 3 VPG 3 HPG 3 22 VPS 2 HPS 2 VPG 2 HPG 2
HPM HPM 21 VPS 1 HPS 1 VPG 1 HPG 1 20 VPS 0 HPS 0 VPG 0 HPG 0
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First byte Command 7 COMMAND40 (Character size control) COMMAND41 main 1 (Character size control: line setting U) COMMAND42 main 1 (Character size control: line setting D) COMMAND43 main 1 (Character size control: line setting D2) COMMAND44 main 2 (Character size control: line setting U) COMMAND45 main 2 (Character size control: line setting D) COMMAND46 main 2 (Character size control: line setting D2) COMMAND50 (BOX control U) COMMAND51 (BOX control D) COMMAND52 main 1 (BOX control: line setting U) COMMAND53 main 1 (BOX control: line setting D) COMMAND54 main 1 (BOX control: line setting D2) COMMAND55 main 2 (BOX control: line setting U) COMMAND56 main 2 (BOX control: line setting D) COMMAND57 main 2 (BOX control: line setting D2) 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 LBX 7 LBX 15 0 LBX 6 LBX 14 0 LBX 5 LBX 13 0 LBX 4 LBX 12 0 LBX 3 LBX 11 0 LBX 2 LBX 10 0 1 1 0 1 0 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 0 BXL W1 BXR W1 LBX 7 LBX 15 0 BXL W0 BXR W0 LBX 6 LBX 14 0 BXU CT1 BXD CT1 LBX 5 LBX 13 0 BXU CT0 BXD CT0 LBX 4 LBX 12 0 BXU C3 BXD C3 LBX 3 LBX 11 0 BXU C2 BXD C2 LBX 2 LBX 10 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 LSZ 7 LSZ 15 0 LSZ 6 LSZ 14 0 LSZ 5 LSZ 13 0 LSZ 4 LSZ 12 0 LSZ 3 LSZ 11 0 LSZ 2 LSZ 10 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 1 LSZ 7 LSZ 15 0 LSZ 6 LSZ 14 0 LSZ 5 LSZ 13 0 LSZ 4 LSZ 12 0 LSZ 3 LSZ 11 0 LSZ 2 LSZ 10 0 LSZ 1 LSZ 9 LSZ 17 LSZ 1 LSZ 9 LSZ 17 BXU C1 BXD C1 LBX 1 LBX 9 LBX 17 LBX 1 LBX 9 LBX 17 LSZ 0 LSZ 8 LSZ 16 LSZ 0 LSZ 8 LSZ 16 BXU C0 BXD C0 LBX 0 LBX 8 LBX 16 LBX 0 LBX 8 LBX 16 1 6 1 Command identification code data 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 Second byte Data 3 2 1 0
SZV1 SZV0 SZH1 SZH0
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LC74736PT
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First byte Command 7 COMMAND58 (Line spacing control 1) COMMAND59 (Line spacing control 2) COMMAND5A main 1 (Line spacing control: line setting U) COMMAND5B main 1 (Line spacing control: line setting U) COMMAND5C main 1 (Line spacing control: line setting D2) COMMAND5D main 2 (Line spacing control: line setting U) COMMAND5E main 2 (Line spacing control: line setting D) COMMAND5F main 2 (Line spacing control: line setting D2) COMMAND60 (Border control) COMMAND61 main 1 (Border control: line setting U) COMMAND62 main 1 (Border control: line setting D) COMMAND63 main 1 (Border control: line setting D2) COMMAND64 main 2 (Border control: line setting U) COMMAND65 main 2 (Border control: line setting D) COMMAND66 main 2 (Border control: line setting D2) COMMAND67 (PLL control 1) COMMAND68 (PLL control 2) COMMAND69 (PLL control 3) COMMAND6A (PLL control 5) COMMAND6C0 (Write address) Color table COMMAND6C1 (Data write) Color table 1 1 1 0 1 1 1 RM3[1] [2] 0 TG3 0 TG2 HFT TG1 TOK TG0 TB3 TR3 TB2 TR2 TB1 TR1 TB0 TR0 1 1 1 0 1 1 0 0 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 0 1 DIV 7 0 DIV 6 HD SL 0 DIV 5 DZ 1 CTN 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 1 1 EVO OFF 0 LC OFF 0 ECK OFF 0 VCO OFF DIV 12 DIV 4 DZ 0 CTN 0 VCS 1 DIV 11 DIV 3 HR SL CTA 3 VCS 0 DIV 10 DIV 2 DID 2 CTA 2 1 1 1 0 0 1 1 0 1 1 1 0 0 1 0 1 1 1 1 0 0 1 0 0 LFC 7 LFC 15 0 LFC 6 LFC 14 0 LFC 5 LFC 13 0 LFC 4 LFC 12 0 LFC 3 LFC 11 0 LFC 2 LFC 10 0 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 0 1 1 1 0 0 0 0 1 LFC 7 LFC 15 0 LFC 6 LFC 14 0 1 1 1 0 0 0 0 0 BLK BLK EGC T1 LFC 5 LFC 13 0 EGC T0 LFC 4 LFC 12 0 EGC 3 LFC 3 LFC 11 0 EGC 2 LFC 2 LFC 10 0 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 0 1 1 1 0 1 LGY 7 LGY 15 0 LGY 6 LGY 14 0 LGY 5 LGY 13 0 LGY 4 LGY 12 0 LGY 3 LGY 11 0 LGY 2 LGY 10 0 1 1 0 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 BXD W LGY 7 LGY 15 0 1 6 1 Command identification code data 5 0 4 1 3 1 2 0 1 0 0 0 7 0 6 GYB CK BXU W LGY 6 LGY 14 0 5 GS 1 GYH SL LGY 5 LGY 13 0 4 GS 0 BXH SL LGY 4 LGY 12 0 Second byte Data 3 GY 3 FCH SL LGY 3 LGY 11 0 2 GY 2 BXC 3 LGY 2 LGY 10 0 1 GY 1 BXC 2 LGY 1 LGY 9 LGY 17 LGY 1 LGY 9 LGY 17 EGC 1 LFC 1 LFC 9 LFC 17 LFC 1 LFC 9 LFC 17 0 GY 0 BXC 1 LGY 0 LGY 8 LGY 16 LGY 0 LGY 8 LGY 16 EGC 0 LFC 0 LFC 8 LFC 16 LFC 0 LFC 8 LFC 16
CKSL CKSL 1 DIV 9 DIV 1 DID 1 CTA 1 0 DIV 8 DIV 0 DID 0 CTA 0
Continued on next page.
No.A0569-14/106
LC74736PT
Continued from preceding page.
First byte Command 7 COMMAND700 (character ram1) writeaddress COMMAND701 (character ram2) write COMMAND710 (WVGA ROM) COMMAND711 (PLL control 6) COMMAND712 (PLL control 7) 1 1 1 1 0 1 1 0 0 STB CP RES CP 1 1 1 1 0 1 0 1 RSTB 0 1 1 1 1 0 1 0 0 1 1 1 1 0 0 1 RM3[1] [2] 1 6 1 Command identification code data 5 1 4 1 3 0 2 0 1 0 0 0 7 FAD 1 D15 D7 0 6 FAD 0 D14 D6 0 5 FRN 1 D13 D5 CKO S1 4 FRN 0 D12 D4 CKO S0 Second byte Data 3 FVA 3 D11 D3 2 FVA 2 D10 D2 1 FVA 1 D9 D1 0 FVA 0 D8 D0
WFC WRA MD CP 0 DIV ECP M2 0 X2 GAN 2
WRA WRA M1 CP I11 GAN 1 M0 CP I0 GAN 0
VCRS VCRS 1 SCP CP
1 COMMAND00 (Main screen 1: horizontal write address setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 0 0 0 0 0 0 Sub-identification code: 0 Content Function Command 0 identification code Main screen 1 memory horizontal write address setting Notes
(2) Second byte
DA0 to 7 7 6 5 4 Register State V14 [MSB] 3 V13 0 0 0 0 1 0 1 2 V12 0 1 1 V11 0 1 0 V10 [LSB] 0 1 Main screen 1 memory line address (0 to 11, hexadecimal) 15 lines: 0E (hexadecimal) 18 lines: 11 (hexadecimal) COM24-2: Line number specification Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-15/106
LC74736PT
2 COMMAND01 (Main screen 1: vertical write address setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 0 0 0 0 1 0 Sub-identification code: 1 Content Function Command 0 identification code Main screen 1 memory vertical write address setting Notes
(2) Second byte
DA0 to 7 7 6 5 4 Register State H15 [MSB] 4 H14 0 0 0 0 1 0 1 3 H13 0 1 2 H12 0 1 1 H11 0 1 0 H10 [LSB] 0 1 Main screen 1 memory character position address (0 to 21, hexadecimal) 30 characters: 1D (hexadecimal) 33 characters: 20 (hexadecimal) 34 characters: 21 (hexadecimal) COM23-2: Character number specification Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-16/106
LC74736PT
3 COMMAND02 (Main screen 2: horizontal write address setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 0 0 0 1 0 0 Sub-identification code: 2 Content Function Command 0 identification code Main screen 2 memory horizontal write address setting Notes
(2) Second byte
DA0 to 7 7 6 5 4 Register State V24 [MSB] 3 V23 0 0 0 0 1 0 1 2 V22 0 1 1 V21 0 1 0 V20 [LSB] 0 1 Main screen 2 memory line address (0 to 0E, hexadecimal) 15 lines: 0E (hexadecimal) 18 lines: 11 (hexadecimal) COM24-2: Line number specification Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-17/106
LC74736PT
4 COMMAND03 (Main screen 2: vertical write address setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 0 0 0 1 1 0 Sub-identification code: 3 Content Function Command 0 identification code Main screen 2 memory vertical write address setting Notes
(2) Second byte
DA0 to 7 7 6 5 4 Register State H25 [MSB] 4 H24 0 0 0 0 1 0 1 3 H23 0 1 2 H22 0 1 1 H21 0 1 0 H20 [LSB] 0 1 Main screen 2 memory character position address (0 to 21, hexadecimal) 30 characters: 1D (hexadecimal) 33 characters: 20 (hexadecimal) 34 characters: 21 (hexadecimal) COM23-3: Character number specification Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-18/106
LC74736PT
5 COMMAND04 (Subscreen write address setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 0 0 1 0 0 0 Sub-identification code: 4 Content Function Command 0 identification code Subscreen write address setting Notes
(2) Second byte
DA0 to 7 7 Register State SV1 0 1 6 SV0 0 1 5 4 3 2 1 SH1 0 0 0 0 0 1 0 SH0 0 1 Subscreen memory character position address 0 to 3 (hexadecimal) 4 characters (maximum) COM29-2: Character number specification 0 to 3 (hexadecimal) 4 lines (maximum) Content Function Subscreen memory line address COM29-2: Line number specification Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-19/106
LC74736PT
6 COMMAND10 (Main screen 1 display character data write setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 Register State RM2 1 0 0 1 0 0 0 1 0 RM1 0 1 RM2 RM1 0 0 1 1 0 1 0 1 Mode [1][2][3][4][5] [1][2][3][4][5] [3][4][5] [2][3][4][5] End Continuous Continuous Continuous Continuous write mode selection Sub-identification code: 0 Content Function Command 1 identification code Display character data write setting When this command has been issued, the IC remains in display character data write mode until the CS pin is set high. Notes
(2) Second byte-[1]
DA0 to 7 7 Register State HFT1 0 1 6 HFT0 0 1 5 at 0 1 4 BXS 0 1 3 BXL 0 1 2 BXR 0 1 1 BXU 0 1 0 BXD 0 1 HFT1 HFT0 0 0 1 1 0 1 0 1 None Character only Character background only Character+Character background Blinking specification Content Function Halftone specification Graphic is processed as a character. COM59-2 Notes
Blinking off Blinking on Raised Recessed None Box displayed None Box displayed None Box displayed None Box displayed
Box specification: raised/recessed
Box specification: left side
Box specification: right side
Box specification: upper
Box specification: down
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-20/106
LC74736PT
(3) Second byte-[2]
DA0 to 7 7 Register State CB3 [MSB] 6 CB2 0 1 0 1 5 CB1 0 1 4 CB0 [LSB] 3 CC3 [MSB] 2 CC2 0 1 0 1 0 1 1 CC1 0 1 0 CC0 [LSB] 0 1 Character color specification 0000 to 1111, or 0 to F (hexadecimal) Character color specification When a character glyph is specified, 1 of 16 colors may be selected. Content Function Character background color specification 0000 to 1111, or 0 to F (hexadecimal) Character background color specification When a character glyph is specified, 1 of 16 colors may be selected. Notes
(4) Second byte-[3]
DA0 to 7 7 6 Register State CTB1 0 0 1 5 CTB0 0 1 4 I/E 0 1 3 M/G1 0 1 2 M/G0 0 1 1 1 1 CTB1 CTB0 0 0 1 1 0 1 0 1 Color table number 1 Color table number 2 Color table number 3 Color table number 4 ROM selection Color table selection Content Function Notes
Character RAM (internal) External ROM MG1 0 0 1 MG0 0 1 0 Character Graphic 1(CB, CC invalid) Graphic 2 CTB address shown with CB Chantged to CTB address shown with CC Graphic 3 CTBNo of address shown with CB Changed to CTBNo shown with CC1, CC0
Character/graphic specification
1
ROM1
0 1
ROM1 ROM0 0 0 1 1 0 1 0 1 ROM area number 1 ROM area number 2 ROM area number 3 ROM area number 4
ROM area selection
0
ROM0
0 1
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-21/106
LC74736PT
(5) Second byte-[4]
DA0 to 7 7 6 5 Register State C13 [MSB] 4 C12 0 0 0 1 0 1 3 C11 0 1 2 C10 0 1 1 C9 0 1 0 C8 0 1 Character code specification Content Function Notes
(6) Second byte-[5]
DA0 to 7 7 Register State C7 0 1 6 C6 0 1 5 C5 0 1 4 C4 0 1 3 C3 0 1 2 C2 0 1 1 C1 0 1 0 C0 [LSB] 0 1 Character code External ROM: 16384 characters 0000 to 3FFF (hexadecimal) 0 to 16383 Character RAM (internal): QVGA mode: 0 to 3, hexadecimal, 4 characters WVGA mode: 0 hexadecimal, 1 character * Transparent character specification I/E = 0 (Internal character RAM) M/G10 = 00 (Character) Code = FF (hexadecimal) Content Function Character code specification Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-22/106
LC74736PT
7 COMMAND11 (Main screen 2 display character data write setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 Register State RM2 1 0 0 1 0 0 0 1 0 RM1 0 1 RM2 RM1 0 0 1 1 0 1 0 1 Mode [1][2][3][4][5] [1][2][3][4][5] [3][4][5] [2][3][4][5] End Continuous Continuous Continuous Continuous write mode selection Sub-identification code: 1 Content Function Command 1 identification code Display character data write setting When this command has been issued, the IC remains in display character data write mode until the CS pin is set high. Notes
(2) Second byte-[1]
DA0 to 7 7 Register State HFT1 0 1 6 HFT0 0 1 5 at 0 1 4 BXS 0 1 3 BXL 0 1 2 BXR 0 1 1 BXU 0 1 0 BXD 0 1 HFT1 HFT0 0 0 1 1 0 1 0 1 None Character only Character background only Character+Character background Blinking specification Content Function Halftone specification Graphic is processed as a character. COM59-2 Notes
Blinking off Blinking on Raised Recessed None Box displayed None Box displayed None Box displayed None Box displayed
Box specification: raised/recessed
Box specification: left side
Box specification: right side
Box specification: upper
Box specification: down
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-23/106
LC74736PT
(3) Second byte-[2]
DA0 to 7 7 Register State CB3 [MSB] 6 CB2 0 1 0 1 5 CB1 0 1 4 CB0 [LSB] 3 CC3 [MSB] 2 CC2 0 1 0 1 0 1 1 CC1 0 1 0 CC0 [LSB] 0 1 Character color specification 0000 to 1111, or 0 to F (hexadecimal) Character color specification When a character glyph is specified, 1 of 16 colors may be selected. Content Function Character background color specification 0000 to 1111, or 0 to F (hexadecimal) Character background color specification When a character glyph is specified, 1 of 16 colors may be selected. Notes
(4) Second byte-[3]
DA0 to 7 7 6 Register State CTB1 0 0 1 5 CTB0 0 1 4 I/E 0 1 3 M/G1 0 1 2 M/G0 0 1 1 1 1 CTB1 CTB0 0 0 1 1 0 1 0 1 Color table number 1 Color table number 2 Color table number 3 Color table number 4 ROM selection Color table selection Content Function Notes
Character RAM (internal) External ROM MG1 0 0 1 MG0 0 1 0 Character Graphic 1 (CB, CC invalid) Graphic 2 CTB address shown with CB Changed to CTB address shown with CC. Graphic 3 CTBNo of address shown with CB. Changed to CTBNo shown with CC1, CC0.
Character/graphic specification
1
ROM1
0 1
ROM1 ROM0 0 0 1 1 0 1 0 1 ROM area number 1 ROM area number 2 ROM area number 3 ROM area number 4
ROM area selection
0
ROM0
0 1
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-24/106
LC74736PT
(5) Second byte-[4]
DA0 to 7 7 6 5 Register State C13 [MSB] 4 C12 0 0 0 1 0 1 3 C11 0 1 2 C10 0 1 1 C9 0 1 0 C8 0 1 Character code specification Content Function Notes
(6) Second byte-[5]
DA0 to 7 7 Register State C7 0 1 6 C6 0 1 5 C5 0 1 4 C4 0 1 3 C3 0 1 2 C2 0 1 1 C1 0 1 0 C0 [LSB] 0 1 Character code External ROM: 16384 characters 0000 to 3FFF (hexadecimal) 0 to 16383 Character RAM (internal): QVGA mode: 0 to 3, hexadecimal, 4 characters WVGA mode: 0 hexadecimal, 1 character * Transparent character specification I/E = 0 (Internal character RAM) M/G10 = 00 (Character) Code = FF (hexadecimal) Content Function Character code specification Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-25/106
LC74736PT
12 COMMAND12 (Subscreen display character data write setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 Register State RM2 1 0 0 1 1 0 0 1 0 RM1 0 1 RM2 RM1 0 0 1 1 0 1 0 1 Mode [1][2][3][4][5] [1][2][3][4][5] [3][4][5] [2][3][4][5] End Continuous Continuous Continuous Continuous write mode selection Sub-identification code 2 Content Function Command 1 identification code Display character data write setting When this command has been issued, the IC remains in display character data write mode until the CS pin is set high. Notes
(2) Second byte-[1]
DA0 to 7 7 6 5 4 3 2 1 0 Register State 0 0 0 0 0 0 0 0 Content Function Notes
(3) Second byte-[2]
DA0 to 7 7 6 5 4 3 2 1 0 Register State 0 0 0 0 0 0 0 0 Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-26/106
LC74736PT
(4) Second byte-[3]
DA0 to 7 7 6 Register State CTB1 0 0 1 5 CTB0 0 1 4 I/E 0 1 3 M/G1 0 1 2 M/G0 0 1 1 1 0 0 0 CTB1 CTB0 0 0 1 1 0 1 0 1 Color table number 1 Color table number 2 Color table number 3 Color table number 4 ROM selection Color table selection Content Function Notes
Character RAM (internal) External ROM MG1 MG0 0 0 0 1 Character (only when transparent character is specified.) Graphic 1 only
Graphic only
(5) Second byte-[4]
DA0 to 7 7 6 5 Register State C13 [MSB] 4 C12 0 0 0 1 0 1 3 C11 0 1 2 C10 0 1 1 C9 0 1 0 C8 0 1 Character code specification Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-27/106
LC74736PT
(6) Second byte-[5]
DA0 to 7 7 Register State C7 0 1 6 C6 0 1 5 C5 0 1 4 C4 0 1 3 C3 0 1 2 C2 0 1 1 C1 0 1 0 C0 [LSB] 0 1 Character code External ROM: 16384 characters 0000 to 3FFF (hexadecimal) 0 to 16383 Character RAM (internal): QVGA mode: 0 to 3, hexadecimal, 4 characters WVGA mode: 0 hexadecimal, 1 character * Transparent character specification I/E = 0 (Internal character RAM) M/G10 = 00 (Character) Code = FF (hexadecimal) Content Function Character code specification Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-28/106
LC74736PT
9 COMMAND20 (System control setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 0 0 0 0 0 Sub-identification code 0 Content Function Command 2 identification code System control settings Notes
(2) Second byte
DA0 to 7 7 Register State TST MD2 6 TST MD1 5 SYS RST 0 1 0 1 0 1 Reset all registers (All bits set to 0.) Normal operation Test mode 2 Normal operation Test mode 1 Content Function Do not use test mode. This bit must always be set to 0. Do not use test mode. This bit must always be set to 0. The registers are reset when the CS pin is low. The reset state is cleared when the CS pin goes high. 4 FRM ERS 0 1 0 1 0 1 0 1 0 1 Erase main RAM. (Sets all values to 00.) Main screen Erase main RAM. (Sets all values to 00.) Main screen 0 MRM ER1 Erase sub-RAM. (Sets all values to 00.) Wallpaper 1 MRM ER2 Erase the color table. (Sets all values to 00.) Erase FontRAM (Sets all values to 00.) Applications must provide a wait time of about 1ms. Use DSPOFF to execute this operation. 3 CT ERS 2 SRM ERS Applications must provide a wait time of about 1ms. Use DSPOFF to execute this operation. Applications must provide a wait time of about 1ms. Use DSPOFF to execute this operation. Applications must provide a wait time of about 1ms. Use DSPOFF to execute this operation. Applications must provide a wait time of about 1ms. Use DSPOFF to execute this operation. Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-29/106
LC74736PT
10 COMMAND21 (Display control setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 0 0 0 0 1 Extended command 1 identification code Display control Content Function Command 2 identification code Notes
(2) Second byte
DA0 to 7 7 Register State BK12 0 1 6 BK02 0 1 5 BK11 0 1 4 BK01 0 1 3 DSP BG 2 DSP GS 1 DSP GM2 0 DSP GM1 0 1 0 1 0 1 0 1 Display off Display on Display off Display on Display off Display on Display off Display on Main screen 1 Main screen 2 Subscreen (wallpaper) Screen background color BK11 0 0 1 BK01 0 1 0 Blinking period 1/16 1/32 1/64 Blinking period main 1 Specified for screen units. BK12 0 0 1 BK02 0 1 0 Content Function Blinking period 1/16 1/32 1/64 Blinking period main 2 Specified for screen units. Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-30/106
LC74736PT
11 COMMAND22 (I/O polarity control 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 0 0 0 1 0 Extended command 2 identification code I/O polarity control 1 Content Function Command 2 identification code Notes
(2) Second byte
DA0 to 7 7 6 Register State BLOP 0 0 1 5 4 BLO2 BLO1 0 0 1 3 BLO0 0 1 BLK output: positive polarity BLK output: negative polarity BLO210 000 001 010 011 100 101 110 2 CKP 0 1 1 VIP 0 1 0 HIP 0 1 BLK output Normal character.+charcter background+graphic Character only Character background only Graphic only Character+character background only Character+graphic only Character background+graphic only Clock input polarity selection BLK output control Character, character background, and graphic output control. Border specification is enabled when character background output is selected. BLK output polarity selection Content Function Notes
Clock input: positive polarity Clock input: negative polarity VSYNC input: negative polarity VSYNC input: positive polarity HSYNC input: negative polarity HSYNC input: positive polarity
VSYNC input polarity selection
HSYNC input polarity selection
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-31/106
LC74736PT
12 COMMAND23 (Screen background color setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 0 0 0 1 1 Extended command 3 identification code Content Function Command 2 identification code Screen background color Notes
(2) Second byte
DA0 to 7 7 Register State DPM HC1 6 DPM HC0 5 BGC T1 4 BGC T0 3 BGC3 0 1 0 1 0 1 0 1 0 1 2 BGC2 0 1 1 BGC1 0 1 0 BGC0 0 1 T1 0 0 1 1 T0 0 1 0 1 Color table setting Color table number 1 Color table number 2 Color table number 3 Color table number 4 Screen background color setting 1 of 16 colors may be selected. Screen background color Color table setting HC1 0 0 1 0 0 1 0 Content Function Characters 30 characters (1D, hexadecimal) 33 characters (20, hexadecimal) 34 characters (21, hexadecimal) Main screen display area specification Horizontal direction Notes
Screen background color 0000 to 1111 0 to F (hexadecimal)
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-32/106
LC74736PT
13 COMMAND24 (I/O polarity control 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 0 0 1 0 0 Extended command 4 identification code I/O polarity control 2 Content Function Command 2 identification code Notes
(2) Second byte
DA0 to 7 7 Register State DPM MD 6 DPM VC 5 D/A SEL 4 SBG SL 0 1 0 1 0 1 0 1 Content Function QVGA mode (16x16 dots) WVGA mode (24x32 dots) 15 lines 18 lines D/A on D/A off Repeated display (wallpaper) Cursor display (sprite display) QVGA: Horizontal 4 charactersxVertical 4 lines (maximum) WVGA: Horizontal 2 charactersxVertical 2 lines (maximum) 3 GD2 0 1 2 GD1 0 1 1 GD0 0 1 0 CKOP 0 1 GD2 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 Screen display [upperlower] Main 1, Main 2, Wallpaper Main 2, Main 1, Wallpaper Wallpaper, Main 1, Main 2 Wallpaper, Main 2, Main 1 Main 1, Wallpaper, Main 2 Main 2, Wallpaper, Main 1 Clock output polarity selection Screen display order selection Subscreen display selection COM29-2: Display area specification Mmain screen display area specification Vertical D/A converter use/no-use selection Display mode selection Notes
Clock output: positive polarity Clock output: negative polarity
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-33/106
LC74736PT
14 COMMAND25 (Output control 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 0 0 1 0 1 Extended command 5 identification code Output control 1 Content Function Command 2 identification code Notes
(2) Second byte
DA0 to 7 7 Register State CEHSL 0 1 6 TOKSL 0 1 Normal operation CE pin held fixed at the high level Normal mode Transmissive mode The color specified at address 0 in color table No. 1 is displayed in the transmissive state. 5 VIPSL 0 1 4 LCS OF2 0 1 0 1 2 OTMD0 0 1 1 LCS STP 0 LCS OFF 0 1 0 1 Falling edge detection Rising edge detection LC oscillator: Normal operation (H sync) LC oscillator: STOP state (OFF) RSTLC also 3 OTMD1 OTMD1 OTMD0 0 0 1 1 0 1 0 1 Output Normal Disabled Disabled High-impedance state LC oscillator STOP control Enabled when display is off LC oscillator STOP control When external clock is input. A0 to A19, CE, OE output selection Selects the detection polarity for the VSYNC signal. LC oscillator STOP control When external clock is input. Transparent mode specification Specifis effective color table with COMN27-2. Content Function CE pin Notes
LC oscillator: Normal operation (H sync.) LC oscillator: Always STOP state LC oscillator: Normal operation (H sync.) LC oscillator: STOP state (OFF) LCSTOP only
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-34/106
LC74736PT
15 COMMAND26 (Output control 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 0 0 1 1 0 Extended command 6 identification code Output control 1 Content Function Command 2 identification code Notes
(2) Second byte
DA0 to 7 7 Register State HFT OFF 6 BLK OFF 5 BLD2 0 1 0 1 0 1 4 BLD1 0 1 3 BLD0 0 1 2 OTM2 0 1 1 ROT OFF 1 0 DOT OFF 0 1 0 Output off=Low Normal output External ROM address, OE, CE output on External ROM address, OE, CE output off=low Digital RGB output on Digital RGB output off=low Digital RGB output setting External ROM address output setting CLKout output output control HFTOT output on HFTOT output off=low BLK output on BLK output off=low BLD2 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 BLK output delay 0 (analog) +1 +2 -1 (digital) -2 BLK output delay BLK output setting Content Function HFTOT output setting Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-35/106
LC74736PT
16 COMMAND27 (Output control 3 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 0 0 1 1 1 Extended command 7 identification code Output control 1 Content Function Command 2 identification code Notes
(2) Second byte
DA0 to 7 7 6 Register State HFT OD2 5 HFT OD1 4 HFT OD0 3 TOK CB4 0 1 0 1 0 1 Address 0000: Normal color Address 0000: Transparent color Transparent color specification or specifiable color table No. 4 COM25-2 Enabled by setting TOKSL to 1. 2 TOK CB3 0 1 Address 0000: Normal color Address 0000: Transparent color Transparent color specification or specifiable color table No. 3 COM25-2 Enabled by setting TOKSL to 1. 1 TOK CB2 0 1 Address 0000: Norrmal color Address 0000: Transparent color Transparent color specification or specifiable color table No. 2 COM25-2 Enabled by setting TOKSL to 1. 0 TOK CB1 0 1 Address 0000: Normal color Address 0000: Transparent color Transparent color specification or specifiable color table No. 1 COM25-2 Enabled by setting TOKSL to 1. 0 0 HFTOD2 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 (analog) +1 +2 -1 (digital) -2 HFTOT output delay Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-36/106
LC74736PT
17 COMMAND28 (Output control 4 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 0 1 0 0 0 Extended command 8 identification code Output control 1 Content Function Command 2 identification code Notes
(2) Second byte
DA0 to 7 7 Register State HPG 9 6 HPS 9 5 HPM2 29 4 HPM1 19 3 VPG 8 2 VPS 8 1 VPM2 28 0 VPM1 18 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Content Function Screen background color H position msb 0 Screen background color H position msb 1 Subscreen H position msb 0 Subscreen H position msb 1 Main screen 2 H position msb 0 Main screen 2 H position msb 1 Main screen 1 H position msb 0 Main screen 1 H position msb 1 Screen background V position msb 0 Screen background V position msb 1 Subscreen V position msb 0 Subscreen V position msb 1 Main screen 2 V position msb 0 Main screen 2 V position msb 1 Main screen 1 V position msb 0 Main screen 1 V position msb 1 V position main screen 1 msb V position main screen 2 msb V position subscreen msb V position screen background color msb H position main screen 1 msb H position main screen 2 msb H position subscreen msb H position screen background color msb Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-37/106
LC74736PT
18 COMMAND29 (Output control 5 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 0 1 0 0 1 Extended command 9 identification code Output control 1 Content Function Command 2 identification code Notes
(2) Second byte
DA0 to 7 7 6 Register State SVH1 0 0 1 5 SVH0 0 1 0 0 1 1 4 SHH1 0 1 3 SHH0 0 1 0 0 1 1 2 1 0 ML CHG 0 0 0 1 LSB first MSB first 3-wire control transfer direction selection 0 1 0 1 0 1 0 1 SVH1 SVH0 Display area QVGA 1 line 2 line 3 line 4 line QVGA 1 character 2 characters 3 characters 4 characters WVGA 1 line 2 line Subscreen horizontal direction display range WVGA 1 character 2 characters selection QVGA: 4 characters (maximum) WVGA: 2 characters (maximum) Subscreen vertical direction display range selection QVGA: 4 lines (maximum) WVGA: 2 lines (maximum) Content Function Notes
SHH1 SHH0
Display area
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-38/106
LC74736PT
18 COMMAND2A (Display area control 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 0 1 0 1 0 Extended command A identification code Output control 1 Content Function Command 2 identification code Notes
(2) Second byte
DA0 to 7 7 6 Register State HIN DIN 5 HI D1 4 HI D0 3 VI D1 2 VI D0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 Normal (LC oscillator control route) Direct taking in HID1 0 0 1 1 VID1 0 0 1 1 HID0 0 1 0 1 VID0 0 1 0 1 delay 0 (initial) +1 +2 +3 delay 0 (initial) +1 +2 +3 VSYNC taking in HSYNC input selection Direct taking-in specification (1) must be used in modes other than LC oscillator. HSYNC taking in Enabled when HINDIN is set to 1. Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-39/106
LC74736PT
25 COMMAND30 (Main screen 1: vertical display start position setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 1 0 0 0 0 Extended command 0 identification code Content Function Command 3 identification code Main screen 1 vertical display start position setting Notes
(2) Second byte
DA0 to 7 7 Register State VPM17 0 1 6 VPM16 0 1 5 VPM15 0 1 4 VPM14 0 1 3 VPM13 0 1 2 VPM12 0 1 1 VPM11 0 1 0 VPM10 (LSB) 0 1
8 n=0
Content Function The vertical display start position, VSM 1, is given by: VSM1=1Hx(2 VPM1n)
n
Notes Main screen 1 The vertical display start position is specified by the 9 bits VPM18 to VPM10. The weight of the LSB is 1H. This setting applies in screen units.
HSYNC
VSM1 VSYNC
HSM1
Main screen display area
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-40/106
LC74736PT
26 COMMAND31 (Main screen 1: horizontal display start position setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State HPM18 1 0 1 1 0 0 1 0 1 Extended command 1 identification code Content Function Command 3 identification code Main screen: horizontal display start position setting Notes
(2) Second byte
DA0 to 7 7 Register State HPM17 0 1 6 HPM16 0 1 5 HPM15 0 1 4 HPM14 0 1 3 HPM13 0 1 2 HPM12 0 1 1 HPM11 0 1 0 HPM10 (LSB) 0 1 Sub H 2 characters 00 to 0DHEX Sub H 3 characters 00 to 15HEX Sub H 4 characters 00 to 1DHEX The values in parentheses apply when ROM access No. 2 and No. 3 are set. Sub H 0 character Sub H 1 character =45Tc(QVGA) 41Tc(WVGA) Tc: The input clock frequency in operating mode. Setting disable range QVGA 00HEX 00 to 05HEX WVGA 00HEX 00 to 15HEX (00 to 0CHEX) 00 to 2CHEX (00 to 1CHEX)
9
Content Function The horizontal display start position, HSM1, is given by: HSM1=1Tcx(2 HPM1n)+
n=0
Notes Main screen 1 The horizontal display start position is specified by the 10 bits HPM19 to HPM10. The weight of the LSB is 1TC. This setting applies in screen units.
n
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-41/106
LC74736PT
27 COMMAND32 (Main screen 2: vertical display start position setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 1 0 1 0 0 Extended command 2 identification code Content Function Command 3 identification code Main screen 2 vertical display start position setting Notes
(2) Second byte
DA0 to 7 7 Register State VPM27 0 1 6 VPM26 0 1 5 VPM25 0 1 4 VPM24 0 1 3 VPM23 0 1 2 VPM22 0 1 1 VPM21 0 1 0 VPM20 (LSB) 0 1
8 n=0
Content Function The vertical display start position, VSM2, is given by: VSM2=1Hx(2 VPM2n)
n
Notes Main screen 2 The vertical display start position is specified by the 9 bits VPM28 to VPM20. The weight of the LSB is 1H. This setting applies in screen units.
HSYNC
VSM2 VSYNC
HSM2
Main screen display area
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-42/106
LC74736PT
28 COMMAND33 (Main screen 2: horizontal display start position setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State HPM28 1 0 1 1 0 1 1 0 1 Extended command 3 identification code Content Function Command 3 identification code Main screen: horizontal display start position setting Notes
(2) Second byte
DA0 to 7 7 Register State HPM27 0 1 6 HPM26 0 1 5 HPM25 0 1 4 HPM24 0 1 3 HPM23 0 1 2 HPM22 0 1 1 HPM21 0 1 0 HPM20 (LSB) 0 1 Sub H 2 characters 00 to 0DHEX Sub H 3 characters 00 to 15HEX Sub H 4 characters 00 to 1DHEX The values in parentheses apply when ROM access No. 2 and No. 3 are set. Setting disable range QVGA Sub H 0 character Sub H 1 character 00HEX 00 to 05HEX WVGA 00HEX 00 to 15HEX (00 to 0CHEX) 00 to 2CHEX (00 to 1CHEX)
9
Content Function The horizontal display start position, HSM2, is given by: HSM2=1Tcx(2 HPM2n)+
n=0
Notes Main screen 2 The horizontal display start position is specified by the 10 bits HPM29 to HPM20. The weight of the LSB is 1TC. This setting applies in screen units.
n
=45Tc(QVGA) 41Tc(WVGA) Tc: The input clock frequency in operating mode.
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-43/106
LC74736PT
29 COMMAND34 (Subscreen: vertical display start position setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 1 1 0 0 0 Extended command 4 identification code Content Function Command 3 identification code Subscreen: vertical display start position setting Notes
(2) Second byte
DA0 to 7 7 Register State VPS7 0 1 6 VPS6 0 1 5 VPS5 0 1
8 n=0
Content Function The vertical display start position, VSS, is given by: VSS=1Hx(2 VPSn)
n
Notes Subscreen (wallpaper) The vertical display start position is specified by the 9 bits VPS8 to VPS0. The weight of the LSB is 1H.
HSYNC
This setting applies in screen units.
VSYNC
4
VPS4
0 1
VSS Subscreen (wallpaper) display area
3
VPS3
0 1
HSS
2
VPS2
0 1
1
VPS1
0 1
0
VPS0 (LSB)
0 1
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-44/106
LC74736PT
30 COMMAND35 (Subscreen: horizontal display start position setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State HPS8 1 0 1 1 1 0 1 0 1 Extended command 5 identification code Content Function Command 3 identification code Subscreen: horizontal display start position setting Notes
(2) Second byte
DA0 to 7 7 Register State HPS7 0 1 6 HPS6 0 1 5 HPS5 0 1 4 HPS4 0 1 3 HPS3 0 1 2 HPS2 0 1 1 HPS1 0 1 0 HPS0 (LSB) 0 1 Sub H 3 characters 00 to 23HEX Sub H 4 characters 00 to 2BHEX The values in parentheses apply when ROM access No. 2 and No. 3 are set. Sub H 2 characters 00 to 1BHEX Setting disable range QVGA Sub H 1 character 00 to 13HEX WVGA 00 to 22HEX (00 to 1AHEX) 00 to 3AHEX (00 to 2AHEX)
9
Content Function The horizontal display start position, HSS, is given by: HSS=1Tcx(2 HPSn)+
n=0
Notes Subscreen (wallpaper) The horizontal display start position is specified by the 9 bits HPS9 to HPS0. The weight of the LSB is 1TC. This setting applies in screen units.
n
=15Tc Tc: The input clock frequency in operating mode.
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-45/106
LC74736PT
31 COMMAND36 (Screen background color: vertical display start position setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 0 1 1 1 1 0 0 Extended command 6 identification code Content Function Command 3 identification code Screen background color: vertical display start position setting Notes
(2) Second byte
DA0 to 7 7 Register State VPG7 0 1 6 VPG6 0 1 5 VPG5 0 1
8 n=0
Content Function The vertical display start position, VSG, is given by: VSG=1Hx(2 VPGn)
n
Notes Screen background color The vertical display start position is specified by the 8 bits VPG8 to VPG0. The weight of the LSB is 1H.
HSYNC
This setting applies in screen units.
1 3 VPG3 0 1 2 VPG2 0 1 1 VPG1 0 1 0 VPG0 (LSB) 0 1
VSYNC
4
VPG4
0
VSG
HSG
Screen background color display area
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-46/106
LC74736PT
32 COMMAND37 (Screen background color: horizontal display start position setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State HPG8 1 0 1 1 1 1 1 0 1 Extended command 7 identification code Content Function Command 3 identification code Screen background color: horizontal display start position setting Notes
(2) Second byte
DA0 to 7 7 Register State HPG7 0 1 6 HPG6 0 1 5 HPG5 0 1 4 HPG4 0 1 3 HPG3 0 1 2 HPG2 0 1 1 HPG1 0 1 0 HPG0 (LSB) 0 1 This setting applies in screen units.
9 n=0
Content Function The horizontal display start position, HSG, is given by: HSG=1Tcx(2 HPGn) Tc: The input clock frequency in operating mode.
n
Notes Screen background color The horizontal display start position is specified by the 10 bits HPG9 to HPG0. The weight of the LSB is 1TC.
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-47/106
LC74736PT
33 COMMAND40 (Character size control setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 0 0 0 0 0 Extended command 0 identification code Content Function Command 4 identification code Character size control settings Notes
(2) Second byte
DA0 to 7 7 6 5 4 3 Register State SZV1 0 0 0 0 0 1 2 SZV0 0 1 1 SZH1 0 1 0 SZH0 0 1 SZV1 SZV0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Character size 1x 2x 3x 4x Character size 1x 2x 3x 4x Specifies the character size in the horizontal direction. This setting applies in line units. Specifies the character size in the vertical direction. This setting applies in line units. Content Function Notes
SZH1 SZH0
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-48/106
LC74736PT
34 COMMAND41 (Character size line U control main 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 0 0 0 0 1 Extended command 1 identification code Content Function Command 4 identification code Character size line U control main 1 Notes
(2) Second byte
DA0 to 7 7 Register State LSZ7 0 1 6 LSZ6 0 1 5 LSZ5 0 1 4 LSZ4 0 1 3 LSZ3 0 1 2 LSZ2 0 1 1 LSZ1 0 1 0 LSZ0 0 1 Do not set for line 8. Set for line 8. Do not set for line 7. Set for line 7. Do not set for line 6. Set for line 6. Do not set for line 5. Set for line 5. Do not set for line 4. Set for line 4. Do not set for line 3. Set for line 3. Do not set for line 2. Set for line 2. Do not set for line 1. Set for line 1. Content Function Character size line setting control Upper lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-49/106
LC74736PT
35 COMMAND42 (Character size line D control main 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 0 0 0 1 0 Extended command 2 identification code Content Function Command 4 identification code Character size line D control main 1 Notes
(2) Second byte
DA0 to 7 7 Register State LSZ15 0 1 6 LSZ14 0 1 5 LSZ13 0 1 4 LSZ12 0 1 3 LSZ11 0 1 2 LSZ10 0 1 1 LSZ9 0 1 0 LSZ8 0 1 Do not set for line 16. Set for line 16. Do not set for line 15. Set for line 15. Do not set for line 14. Set for line 14. Do not set for line 13. Set for line 13. Do not set for line 12. Set for line 12. Do not set for line 11. Set for line 11. Do not set for line 10. Set for line 10. Do not set for line 9. Set for line 9. Content Function Character size line setting control Lower lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-50/106
LC74736PT
36 COMMAND43 (Character size line D2 control main 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register Content State 1 1 0 0 0 0 1 1 Extended command 3 identification code Function Command 4 identification code Character size line D2 control main 1 Notes
(2) Second byte
DA0 to 7 7 6 5 4 3 2 1 Register LSZ17 Content State 0 0 0 0 0 0 0 1 0 LSZ16 0 1 Do not set for line 18. Set for line 18. Do not set for line 17. Set for line 17. Character size line setting control Lower lines 2 Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-51/106
LC74736PT
37 COMMAND44 (Character size line U control main 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register Content State 1 1 0 0 0 1 0 0 Extended command 4 identification code Function Command 4 identification code Character size line U control main 2 Notes
(2) Second byte
DA0 to 7 7 Register LSZ7 Content State 0 1 6 LSZ6 0 1 5 LSZ5 0 1 4 LSZ4 0 1 3 LSZ3 0 1 2 LSZ2 0 1 1 LSZ1 0 1 0 LSZ0 0 1 Do not set for line 8. Set for line 8. Do not set for line 7. Set for line 7. Do not set for line 6. Set for line 6. Do not set for line 5. Set for line 5. Do not set for line 4. Set for line 4. Do not set for line 3. Set for line 3. Do not set for line 2. Set for line 2. Do not set for line 1. Set for line 1. Function Character size line setting control Upper lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-52/106
LC74736PT
38 COMMAND45 (Character size line D control main 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register Content State 1 1 0 0 0 1 0 1 Extended command 5 identification code Function Command 4 identification code Character size line D control main 2 Notes
(2) Second byte
DA0 to 7 7 Register State LSZ15 0 1 6 LSZ14 0 1 5 LSZ13 0 1 4 LSZ12 0 1 3 LSZ11 0 1 2 LSZ10 0 1 1 LSZ9 0 1 0 LSZ8 0 1 Do not set for line 16. Set for line 16. Do not set for line 15. Set for line 15. Do not set for line 14. Set for line 14. Do not set for line 13. Set for line 13. Do not set for line 12. Set for line 12. Do not set for line 11. Set for line 11. Do not set for line 10. Set for line 10. Do not set for line 9. Set for line 9. Content Function Character size line setting control Lower lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-53/106
LC74736PT
39 COMMAND46 (Character size line D control main 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 0 0 1 1 0 Extended command 6 identification code Content Function Command 4 identification code Character size line D control main 2 Notes
(2) Second byte
DA0 to 7 7 6 5 4 3 2 1 Register State LSZ17 0 0 0 0 0 0 0 1 0 LSZ16 0 1 Do not set for line 18. Set for line 18. Do not set for line 17. Set for line 17. Character size line setting control Lower lines 2 Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-54/106
LC74736PT
46 COMMAND50 (Box control: U setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 0 0 0 0 Extended command 0 identification code Box control U settings Content Function Command 5 identification code Notes
(2) Second byte
DA0 to 7 7 Register State BXL W1 6 BXL W0 5 BXU CT1 4 BXU CT0 3 BXU C3 2 BXU C2 1 BXU C1 0 BXU C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 W1 0 0 1 1 0 0 1 1 W0 0 1 0 1 0 1 0 1 1 dot 2 dots 3 dots 4 dots Box display: upper side Color table number 1 Color table number 2 Color table number 3 Color table number 4 Box display: upper side Color specification This setting applies in line units. Color table specification This setting applies in line units. Content Function Box display: left side Dot width. This setting applies in line units. It does not depend on the character size. Notes
BXUCT1 0
Box display: upper side color specification 0000 to 1111 0 to F (hexadecimal)
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-55/106
LC74736PT
47 COMMAND51 (Box control: D setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 0 0 0 1 Extended command 1 identification code Box control D settings Content Function Command 5 identification code Notes
(2) Second byte
DA0 to 7 7 Register State BXR W1 6 BXR W0 5 BXD CT1 4 BXD CT0 3 BXD C3 2 BXD C2 1 BXD C1 0 BXD C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 W1 0 0 1 1 0 0 1 1 W0 0 1 0 1 0 1 0 1 1 dot 2 dots 3 dots 4 dots Box display: lower side Color table number 1 Color table number 1 Color table number 3 Color table number 4 Box display: lower side Color specification This setting applies in line units. Color table specification This setting applies in line units. Content Function Box display: right side Dot width. This setting applies in line units. It does not depend on the character size. Notes
BXDCT1 0
Box display: lower side color specification 0000 to 1111 0 to F (hexadecimal)
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-56/106
LC74736PT
48 COMMAND52 (Box control: U line main 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 0 0 1 0 Extended command 2 identification code Content Function Command 5 identification code Box control U line main 1 setting Notes
(2) Second byte
DA0 to 7 7 Register State LBX7 0 1 6 LBX6 0 1 5 LBX5 0 1 4 LBX4 0 1 3 LBX3 0 1 2 LBX2 0 1 1 LBX1 0 1 0 LBX0 0 1 Do not set for line 8. Set for line 8. Do not set for line 7. Set for line 7. Do not set for line 6. Set for line 6. Do not set for line 5. Set for line 5. Do not set for line 4. Set for line 4. Do not set for line 3. Set for line 3. Do not set for line 2. Set for line 2. Do not set for line 1. Set for line 1. Content Function Box control line setting control Upper lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-57/106
LC74736PT
49 COMMAND53 (Box control: D line main 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 0 0 1 1 Extended command 3 identification code Content Function Command 5 identification code Box control D line main 1 setting Notes
(2) Second byte
DA0 to 7 7 Register State LBX15 0 1 6 LBX14 0 1 5 LBX13 0 1 4 LBX12 0 1 3 LBX11 0 1 2 LBX10 0 1 1 LBX9 0 1 0 LBX8 0 1 Do not set for line 16. Set for line 16. Do not set for line 15. Set for line 15. Do not set for line 14. Set for line 14. Do not set for line 13. Set for line 13. Do not set for line 12. Set for line 12. Do not set for line 11. Set for line 11. Do not set for line 10. Set for line 10. Do not set for line 9. Set for line 9. Content Function Box control line setting control Lower lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-58/106
LC74736PT
50 COMMAND54 (Box control: D2 line main 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 0 1 0 0 Extended command 4 identification code Content Function Command 5 identification code Box control D2 line main 1 setting Notes
(2) Second byte
DA0 to 7 7 6 5 4 3 2 1 Register State LBX17 0 0 0 0 0 0 0 1 0 LBX16 0 1 Do not set for line 18. Set for line 18. Do not set for line 17. Set for line 17. Box control line setting control Lower lines Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-59/106
LC74736PT
51 COMMAND55 (Box control: U line main 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 0 1 0 1 Extended command 5 identification code Content Function Command 5 identification code Box control U line main 2 setting Notes
(2) Second byte
DA0 to 7 7 Register State LBX7 0 1 6 LBX6 0 1 5 LBX5 0 1 4 LBX4 0 1 3 LBX3 0 1 2 LBX2 0 1 1 LBX1 0 1 0 LBX0 0 1 Do not set for line 8. Set for line 8. Do not set for line 7. Set for line 7. Do not set for line 6. Set for line 6. Do not set for line 5. Set for line 5. Do not set for line 4. Set for line 4. Do not set for line 3. Set for line 3. Do not set for line 2. Set for line 2. Do not set for line 1. Set for line 1. Content Function Box control line setting control Upper lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-60/106
LC74736PT
52 COMMAND56 (Box control: D line main 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 0 1 1 0 Extended command 6 identification code Content Function Command 5 identification code Box control D line main 2 setting Notes
(2) Second byte
DA0 to 7 7 Register State LBX15 0 1 6 LBX14 0 1 5 LBX13 0 1 4 LBX12 0 1 3 LBX11 0 1 2 LBX10 0 1 1 LBX9 0 1 0 LBX8 0 1 Do not set for line 16. Set for line 16. Do not set for line 15. Set for line 15. Do not set for line 14. Set for line 14. Do not set for line 13. Set for line 13. Do not set for line 12. Set for line 12. Do not set for line 11. Set for line 11. Do not set for line 10. Set for line 10. Do not set for line 9. Set for line 9. Content Function Box control line setting control Lower lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-61/106
LC74736PT
53 COMMAND57 (Box control: D line main 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 0 1 1 1 Extended command 7 identification code Content Function Command 5 identification code Box control D2 line main 2 setting Notes
(2) Second byte
DA0 to 7 7 6 5 4 3 2 1 Register State LBX17 0 0 0 0 0 0 0 1 0 LBX16 0 1 Do not set for line 18. Set for line 18. Do not set for line 17. Set for line 17. Box control line setting control Lower lines 2 Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-62/106
LC74736PT
54 COMMAND58 (Line spacing control 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 1 0 0 0 Extended command 8 identification code Content Function Command 5 identification code Line spacing control 1 setting Notes
(2) Second byte
DA0 to 7 7 6 Register State 0 GYB CK 0 0 1 0 1 4 GS0 0 1 Line spacing basic clock: 1V Line spacing basic clock: Depending on the character size 5 GS1 GS1 GS0 0 0 1 1 3 GY3 0 1 2 GY2 0 1 1 GY1 0 1 0 GY0 0 1 GY3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Character Transparent Transparent Char. bkg. color Transparent (Border enabled) 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Line spacing (xH) 0 -1 (upper) +1 (lower) -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 Line spacing dot number setting This setting applies in line units of 1H Graphic Transparent Transparent CB specified color Transparent Line spacing mode setting This setting applies in line units Line spacing basic unit (clock) setting Content Function Notes
1 (char. bkg color) 1 (CB specified color)
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-63/106
LC74736PT
55 COMMAND59 (Line spacing control 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 1 0 0 1 Extended command 9 identification code Content Function Command 5 identification code Line spacing control 2 setting Notes
(2) Second byte
DA0 to 7 7 Register State BXW D 6 BXW U 0 1 0 1 0 1 4 BXHSL 0 1 3 FCHSL 0 1 2 BXC3 0 1 1 BXC2 0 1 0 BXC1 0 1 Content Function Box display: lower side is 1 dot Box display: lower side is 2 dots Box display: upper side is 1 dot Box display: upper side is 2 dots (Invalid when line spacing is specified.) 5 GYHSL Normal display Line spacing area: halftone Normal display Box area: halftone Depending on the character Depending on the character background Displayed in upper part of character lower line spacing Displayed in lower part of character lower line spacing Inside the character range (V1&V16 dots) Outside the character range (line spacing area): Valid only when line spacing is specified. Inside the character range Outside the character range Box left and ight display control This setting applies in line units Box display Lower side. This setting applies in line units. Depending on the character size Box display Upper side. This setting applies in line units. Depending on the character size Line spacing area when halftone is specified This setting applies in line units. Transparent is supported except for 00. Box area when halftone is specified This setting applies in line units Border area when halftone is specified This setting applies in line units Box upper and lower display control 2 Valid when line spacing is specified. This setting applies in line units Box upper and lower display control 1 This setting applies in line units Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-64/106
LC74736PT
56 COMMAND5A (Line spacing control: U line main 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 1 0 1 0 Extended command A identification code Content Function Command 5 identification code Control the line spacing control line setting U main 1 Notes
(2) Second byte
DA0 to 7 7 Register State LGY7 0 1 6 LGY6 0 1 5 LGY5 0 1 4 LGY4 0 1 3 LGY3 0 1 2 LGY2 0 1 1 LGY1 0 1 0 LGY0 0 1 Do not set for line 8. Set for line 8. Do not set for line 7. Set for line 7. Do not set for line 6. Set for line 6. Do not set for line 5. Set for line 5. Do not set for line 4. Set for line 4. Do not set for line 3. Set for line 3. Do not set for line 2. Set for line 2. Do not set for line 1. Set for line 1. Content Function Control the line spacing control line setting Upper lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-65/106
LC74736PT
57 COMMAND5B (Line spacing control: D line main 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 1 0 1 1 Extended command B identification code Content Function Command 5 identification code Control the line spacing control line setting D main 1 Notes
(2) Second byte
DA0 to 7 7 Register State LGY15 0 1 6 LGY14 0 1 5 LGY13 0 1 4 LGY12 0 1 3 LGY11 0 1 2 LGY10 0 1 1 LGY9 0 1 0 LGY8 0 1 Do not set for line 16. Set for line 16. Do not set for line 15. Set for line 15. Do not set for line 14. Set for line 14. Do not set for line 13. Set for line 13. Do not set for line 12. Set for line 12. Do not set for line 11. Set for line 11. Do not set for line 10. Set for line 10. Do not set for line 9. Set for line 9. Content Function Control the line spacing control line setting Lower lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-66/106
LC74736PT
58 COMMAND5C (Line spacing control: D line main 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 1 1 0 0 Extended command C identification code Content Function Command 5 identification code Control the line spacing control line setting D main 1 Notes
(2) Second byte
DA0 to 7 7 6 5 4 3 2 1 Register State LGY17 0 0 0 0 0 0 0 1 0 LGY16 0 1 Do not set for line 18. Set for line 18. Do not set for line 17. Set for line 17. Control the line spacing control line setting Lower lines 2 Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-67/106
LC74736PT
59 COMMAND5D (Line spacing control: U line main 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 1 1 0 1 Extended command D identification code Content Function Command 5 identification code Control the line spacing control line setting U main 2 Notes
(2) Second byte
DA0 to 7 7 Register State LGY7 0 1 6 LGY6 0 1 5 LGY5 0 1 4 LGY4 0 1 3 LGY3 0 1 2 LGY2 0 1 1 LGY1 0 1 0 LGY0 0 1 Do not set for line 8. Set for line 8. Do not set for line 7. Set for line 7. Do not set for line 6. Set for line 6. Do not set for line 5. Set for line 5. Do not set for line 4. Set for line 4. Do not set for line 3. Set for line 3. Do not set for line 2. Set for line 2. Do not set for line 1. Set for line 1. Content Function Control the line spacing control line setting Upper lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-68/106
LC74736PT
60 COMMAND5E (Line spacing control: D line main 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 1 1 1 0 Extended command E identification code Content Function Command 5 identification code Control the line spacing control line setting D main 2. Notes
(2) Second byte
DA0 to 7 7 Register State LGY15 0 1 6 LGY14 0 1 5 LGY13 0 1 4 LGY12 0 1 3 LGY11 0 1 2 LGY10 0 1 1 LGY9 0 1 0 LGY8 0 1 Do not set for line 16. Set for line 16. Do not set for line 15. Set for line 15. Do not set for line 14. Set for line 14. Do not set for line 13. Set for line 13. Do not set for line 12. Set for line 12. Do not set for line 11. Set for line 11. Do not set for line 10. Set for line 10. Do not set for line 9. Set for line 9. Content Function Control the line spacing control line setting Lower lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-69/106
LC74736PT
61 COMMAND5F (Line spacing control: D line main 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 0 1 1 1 1 1 Extended command F identification code Content Function Command 5 identification code Control the line spacing control line setting D main 2. Notes
(2) Second byte
DA0 to 7 7 6 5 4 3 2 1 Register State LGY17 0 0 0 0 0 0 0 1 0 LGY16 0 1 Do not set for line 18. Set for line 18. Do not set for line 17. Set for line 17. Control the line spacing control line setting Lower lines Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-70/106
LC74736PT
62 COMMAND60 (Border control setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 0 0 0 0 0 Extended command 0 identification code Border control setting Content Function Command 6 identification code Notes
(2) Second byte
DA0 to 7 7 Register State BLK1 0 1 6 BLK0 0 1 5 EG CT1 4 EG CT0 3 EG C3 2 EG C2 1 EG C1 0 EG C0 0 1 0 1 0 1 0 1 0 1 0 1 BLK1 BLK0 0 0 1 1 EGCT1 0 0 1 1 0 1 0 1 0 0 1 0 1 Color table number 1 Color table number 2 Color table number 3 Color table number 4 Border display color specification This setting applies in line units. Content Function Border mode specification Normal display Border Shadow 1 (lower side) Shadow 2 (lower and right sides) Border display Color table specification This setting applies in line units. Border mode specification This setting applies in line units. Notes
Border display: color specification 0000 to 1111 0 to F (hexadecimal)
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-71/106
LC74736PT
63 COMMAND61 (Border control U line main 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 0 0 0 0 1 Extended command 1 identification code Content Function Command 6 identification code Border line setting U main 1 control Notes
(2) Second byte
DA0 to 7 7 Register State LFC7 0 1 6 LFC6 0 1 5 LFC5 0 1 4 LFC4 0 1 3 LFC3 0 1 2 LFC2 0 1 1 LFC1 0 1 0 LFC0 0 1 Do not set for line 8. Set for line 8. Do not set for line 7. Set for line 7. Do not set for line 6. Set for line 6. Do not set for line 5. Set for line 5. Do not set for line 4. Set for line 4. Do not set for line 3. Set for line 3. Do not set for line 2. Set for line 2. Do not set for line 1. Set for line 1. Content Function Border control line settings control main 1 Upper lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-72/106
LC74736PT
64 COMMAND62 (Border control D line main 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 0 0 0 1 0 Extended command 2 identification code Content Function Command 6 identification code Border line setting D main 1 control Notes
(2) Second byte
DA0 to 7 7 Register State LFC15 0 1 6 LFC14 0 1 5 LFC13 0 1 4 LFC12 0 1 3 LFC11 0 1 2 LFC10 0 1 1 LFC9 0 1 0 LFC8 0 1 Do not set for line 16. Set for line 16. Do not set for line 15. Set for line 15. Do not set for line 14. Set for line 14. Do not set for line 13. Set for line 13. Do not set for line 12. Set for line 12. Do not set for line 11. Set for line 11. Do not set for line 10. Set for line 10. Do not set for line 9. Set for line 9. Content Function Border control line settings control main 1 Lower lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-73/106
LC74736PT
65 COMMAND63 (Border control D line main 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 0 0 0 1 1 Extended command 3 identification code Content Function Command 6 identification code Border line setting D main 1 control Notes
(2) Second byte
DA0 to 7 7 6 5 4 3 2 1 Register State LFC17 0 0 0 0 0 0 0 1 0 LFC16 0 1 Do not set for line 18. Set for line 18. Do not set for line 17. Set for line 17. Border control line settings control main 1 Lower lines Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-74/106
LC74736PT
66 COMMAND64 (Border control U line main 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 0 0 1 0 0 Extended command 4 identification code Content Function Command 6 identification code Border line setting U main 2 control Notes
(2) Second byte
DA0 to 7 7 Register State LFC7 0 1 6 LFC6 0 1 5 LFC5 0 1 4 LFC4 0 1 3 LFC3 0 1 2 LFC2 0 1 1 LFC1 0 1 0 LFC0 0 1 Do not set for line 8. Set for line 8. Do not set for line 7. Set for line 7. Do not set for line 6. Set for line 6. Do not set for line 5. Set for line 5. Do not set for line 4. Set for line 4. Do not set for line 3. Set for line 3. Do not set for line 2. Set for line 2. Do not set for line 1. Set for line 1. Content Function Border control line settings control main 2 Upper lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-75/106
LC74736PT
67 COMMAND65 (Border control D line main 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 0 0 1 0 1 Extended command 5 identification code Content Function Command 6 identification code Border line setting D main 2 control Notes
(2) Second byte
DA0 to 7 7 Register State LFC15 0 1 6 LFC14 0 1 5 LFC13 0 1 4 LFC12 0 1 3 LFC11 0 1 2 LFC10 0 1 1 LFC9 0 1 0 LFC8 0 1 Do not set for line 16. Set for line 16. Do not set for line 15. Set for line 15. Do not set for line 14. Set for line 14. Do not set for line 13. Set for line 13. Do not set for line 12. Set for line 12. Do not set for line 11. Set for line 11. Do not set for line 10. Set for line 10. Do not set for line 9. Set for line 9. Content Function Border control line settings control main 2 Lower lines Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-76/106
LC74736PT
68 COMMAND66 (Border control D line main 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 0 0 1 1 0 Extended command 6 identification code Content Function Command 6 identification code Border line setting D main 2 control Notes
(2) Second byte
DA0 to 7 7 6 5 4 3 2 1 Register State LFC17 0 0 0 0 0 0 0 1 0 LFC16 0 1 Do not set for line 18. Set for line 18. Do not set for line 17. Set for line 17. Border control line settings control main 2 Lower lines Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-77/106
LC74736PT
69 COMMAND67 (PLL control 1 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 0 0 1 1 1 Extended command 7 identification code PLL control 1 Content Function Command 6 identification code Notes
(2) Second byte
DA0 to 7 7 Register State EVO OFF 6 LC OFF 5 ECK OFF 4 VCO OFF 3 VCO SL1 2 VCO SL0 1 CKSL 1 0 CKSL 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 External VCO on External VCO off LC oscillator on LC oscillatior off External clock on External clock off VCO oscillator on VCO oscillator off VCOSL1 0 0 0 1 1 CKSL1 0 0 1 0 1 0 1 0 0 1 0 LC External clock Internal VCO (PLL) or external VCO Internal VCO 1/1 Internal VCO 1/2 Internal VCO 1/4 External VCO Clock selection VCO selection Clock selection required CKSL = 10 Content Function Oscillator-related control Initial LC oscillation Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-78/106
LC74736PT
70 COMMAND68 (PLL control 2 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 0 1 0 0 0 Extended command 8 identification code PLL control 2 Content Function Command 6 identification code Notes
(2) Second byte
DA0 to 7 7 6 5 4 Register State DIV 12 3 DIV 11 2 DIV 10 1 DIV 9 0 0 0 0 1 0 1 0 1 0 1 1 0 DIV 8 0 1 PLL-circuit frequency division ratio setting Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-79/106
LC74736PT
71 COMMAND69 (PLL control 3 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 0 1 0 0 1 Extended command 9 identification code PLL control 3 Content Function Command 6 identification code Notes
(2) Second byte
DA0 to 7 7 Register DIV 7 6 DIV 6 5 DIV 5 4 DIV 4 3 DIV 3 2 DIV 2 1 DIV 1 0 DIV 0 Content State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function N2=2nDIVn
n=0 12
Notes PLL-circuit frequency division ratio setting Initial values: 27BHEX fH = 15.734kHz FVCO = 10MHz
N2: 48 to 8196 30 to 1FFF (hexadecimal) FVCO = fHxN2 VCO oscillation frequency Horizontal frequency input
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-80/106
LC74736PT
72 COMMAND6A (PLL control 5 setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 0 1 0 1 0 Extended command A identification code PLL control 5 Content Function Command 6 identification code Notes
(2) Second byte
DA0 to 7 7 6 Register State HD SEL 5 DZ1 0 0 1 0 1 4 DZ0 0 1 3 HREF SL 2 DID 2 1 DID 1 0 DID 0 0 1 0 1 0 1 0 1 HREF (sync) HREF (directly) DID2 0 0 0 0 1 Dot clock 1 0 0 1 1 0 0 0 1 0 1 0 Frequency division ratio (N1) 1/1 1/2 1/3 1/4 1/6 Dot clock frequency division ratio specification HREF selection HD (AFC) HIN (input) DZ1 0 0 1 DZ0 0 1 0 DZA DZB DZC 0.0ns 0.5ns 2.5ns H sync signal switch at AFC Enabled when Com67-2 CKSL is set to 10. Dead zone specification Content Function Notes
FDOT = FVCOxN1 VCO oscillation frequency
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-81/106
LC74736PT
73 COMMAND6C0 (Color table write address setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 0 1 1 0 0 Sub-identifier code CO Content Function Command 6 identification code Color table write address setting Notes
(2) Second byte
DA0 to 7 7 6 5 Register State CTN1 0 1 4 CTN0 0 1 3 CTA3 (MSB) 2 CTA2 0 1 0 1 1 CTA1 0 1 0 CTA0 (LSB) 0 1 CTN1 CTN0 0 0 1 1 0 to 15 0 to F (hexadecimal) 16 values 0 1 0 1 Color table number 1 Color table number 2 Color table number 3 Color table number 4 Address of the color tables Color table selection Content Function Notes
Color table address
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-82/106
LC74736PT
74 COMMAND6C1 (Color table data write setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State RM3 1 1 1 0 1 1 1 0 1 RM3 0 1 [1][2] [1][2] Mode End Continuous Continuous write mode selection Sub-identifier code C1 Content Function Command 6 identification code Color table write setting When this command has been issued, the IC remains in display character data write mode until the CS pin is set high. Notes
(2) Second byte-[1]
DA0 to 7 7 6 5 Register State HFT 0 0 0 1 4 TOK 0 1 3 TB3 0 1 2 TB2 0 1 1 TB1 0 1 0 TB0 0 1 Halftone: off Halftone: on (HFTOT output is high.) Color Transparent (BLK output: low) Color table B output 0000 to 1111 0 to F (hexadecimal) Color table setting B Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-83/106
LC74736PT
(3) Second byte-[2]
DA0 to 7 7 Register State TG3 0 1 6 TG2 0 1 5 TG1 0 1 4 TG0 0 1 3 TR3 0 1 2 TR2 0 1 1 TR1 0 1 0 TR0 0 1 Color table R output 0000 to 1111 0 to F (hexadecimal) Color table setting R Color table G output 0000 to 1111 0 to F (hexadecimal) Content Function Color table setting G Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin. When transparent is selected, the BLK output is set to the low level. (Transparent state) The RGB outputs are values from the color table. The transparent specification is best for color table 1, address 0000. Since the data is set to all zeros by a RAM clear operation, the RGB output will be 000 (black) and the BLK output will be 1. Transparent is specified by setting the TOK bit to 1. (The BLK output will go to the low level.)
No.A0569-84/106
LC74736PT
75 COMMAND700 (Character RAM write address setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 1 0 0 0 0 Sub-identifier code 000 Content Function Command 7 identification code Character RAM write address setting Notes
(2) Second byte
DA0 to 7 7 Register State FAD1 0 1 6 FAD0 0 1 QVGA mode Character RAM address 0 to 3 0 to 3 (hexadecimal) WVGA mode PNo. 0 to 3 P1 to P4 5 FRN1 0 1 4 FRN0 0 1 3 FVA3 (MSB) 2 FVA2 0 1 0 1 1 FVA1 0 1 0 FVA0 (LSB) 0 1 Character RAM V dot addresses 0 to 15 0 to F (hexadecimal) Character RAM V dot address ROM No.1 to 4 0 to 3 0 to 3 (hexadecimal) No.1 to No.4 Character RAM ROM No. Content Function Character RAM QVGA: address WVGA: PNo. Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-85/106
LC74736PT
76 COMMAND701 (Character RAM data write setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State RM3 1 1 1 1 0 0 1 0 1 RM3 0 1 [1][2] [1][2] Mode End Continuous Continuous write mode selection Sub-identifier code 001 Content Function Command 7 identification code Character RAM data write address setting When this command has been issued, the IC remains in display character data write mode until the CS pin is set high. Notes
(2) Second byte-[1]
DA0 to 7 7 Register State D15 0 1 6 D14 0 1 5 D13 0 1 4 D12 0 1 3 D11 0 1 2 D10 0 1 1 D9 0 1 0 D8 0 1 D15 to D0 Content Function Character RAM write data Character RAM write data Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-86/106
LC74736PT
(3) Second byte-[2]
DA0 to 7 7 Register State D7 0 1 6 D6 0 1 5 D5 0 1 4 D4 0 1 3 D3 0 1 2 D2 0 1 1 D1 0 1 0 D0 0 1 Content Function Character RAM write data Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-87/106
LC74736PT
77 COMMAND710 (WVGA: ROM access setting command) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 1 0 1 0 0 Sub-identifier code 0100 Content Function Command 7 identification code WVGA ROM access setting Notes
(2) Second byte
DA0 to 7 7 6 5 CKOS1 Register State 0 0 0 1 4 CKOS0 0 1 3 WFCMD 0 1 2 WRAM2 0 1 1 WRAM1 0 1 0 WRAM0 0 1 CKOS1 0 0 1 1 No border Border (displayed for each upper and lower 1V) When WRAM210 DCLK=33.3MHz * No.1 3CLK = 90ns 000 001 Main 1 only (Main 2 display off) Main 2 only (Main 1 display off) because box is displayed * No.2 2CLK 60ns Main 1 010 011 Character Graphic Main 2 Character Character 0 0 1 0 1 CLK PHASECP(HD1BFQ) NCHCP PCHCP WVGA mode Specifies border display when ROM access mode is set to 011 or 100. WVGA mode ROM access specification CLKout output selection Content Function Notes
HPM1HPM2 * The character has no border. 100 Character Graphic HPM1HPM2 * The character has no border. * No.3 1CLK = 30ns 101 Equivalent to QVGA (external ROM only)
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-88/106
LC74736PT
78 COMMAND711 (PLL setting command 6) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 1 0 1 0 1 Sub-identifier code 0101 Content Function Command 7 identification code PLL setting command 6 Notes
(2) Second byte
DA0 to 7 7 Register State RSETB 0 1 6 5 VCR S1 4 VCR S0 3 CPI X2 2 1 CPI S1 0 CPI S0 0 0 1 0 1 0 1 0 0 1 0 1 CPIS1 0 0 1 1 CPIS0 0 1 0 1 40A 44A 52A 60A CPIS0 0 1 0 0 1 0 0 1 0 2 0 0 0 1 CP current value setting 1 VCRS1 VCRS0 0 0 1 1 0 1 0 1 5.6K 6.6K 7.6K 4.6K RSET0 1 1 0 1 1 1 0 0 1 2 0 0 0 1 CP current value setting 2 Internal VCOR value setting Large resistance low gain VCOR: Internal VCOR: External Content Function RSETB"H" "L" VCOR selection Notes
The following set current x1 The following set current x3
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-89/106
LC74736PT
79 COMMAND712 (PLL setting command 7) (1) First byte
DA0 to 7 7 6 5 4 3 2 1 0 Register State 1 1 1 1 0 1 1 0 Sub-identifier code 0110 Content Function Command 7 identification code Display character data write setting Notes
(2) Second byte
DA0 to 7 7 6 Register State STYB CP 5 RESETBCP 0 0 1 0 1 4 SCP1 CP 3 DIV ENB 2 GAIN 2 1 GAIN 1 0 GAIN 0 0 1 0 1 0 1 0 1 0 1 2 0 0 0 0 1 1 1 1 Normal operation: STYB"H" CP, VCO standby: PD0 = "Z" Normal operation: RESETB"H" PD reset: PD0 = "Z" CP enable: SCP1"H" CP disable Normal operation: DIVENB"H" Frequency divider reset GAIN 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 7 7 -20% -20% +20% +20% 7 7 40 -20% 40 -20% +10% -10% +10% -10% 20/V -22.5% +2.5% -20% +8.75% -13.75% +11.25% +11.25% Fmin Fmax Gain[MHz] VCO adjustment Frequency divider control CP control PD reset setting CP, VCO standby setting Content Function Notes
*: This resistor is set to the all bits zero state when the IC is reset by the RST pin.
No.A0569-90/106
LC74736PT
Display Structure
The display screen consists of a 34-characterx18-line grid (maximum). * QVGA mode (16x16 dot characters) QVGA panel (480x234) 30-characterx15-line * WVGA mode (24x32 dot characters) WVGA panel (800x480) 33-characterx15-line Up to a maximum of 612 characters can be displayed. If the character size is increased, the number of characters that can be displayed will decrease to be fewer than 612 characters. Display memory is addressed by specifying a line address (00 to 17 (hexadecimal) and a character position address (00 to 32 (hexadecimal)). Display memory is addressed by specifying a line address (00 to 11 (hexadecimal) and a character position address (00 to 21 (hexadecimal)). Display structure (Display memory address): 34 charactersx18 lines (maximum) 00 00 33 21
No.A0569-91/106
LC74736PT
Operational Description
1. Command transfer method 1.1 Overview (1) Commands are transferred in 8-bit units, LSB first. Always send a first byte and a second byte (16 bits). (2) COMMAND10 (Main screen 1 RAM write) COMMAND11 (Main screen 2 RAM write) COMMAND12 (Subscreen write) COMMNAD6C1 (Color table write) COMMAND701 (Character RAM write) is locked in continuous write mode when a continuous mode is specified (RM2, 1 RM3). (Continuous mode is cleared by setting the CS pin high.) 1.2 Writing Data to VRAM (1) Write start address specification Write start address is set using: COMMAND00, COMMAND01 (Main screen 1) COMMAND02, COMMAND03 (Main screen 2) COMMAND04 (Subscreen) V4 to V0: Vertical direction; H5 to H0: Horizontal direction (2) Data write Continuous write mode differs depending on the write mode specification. (RM1, RM2) 1. Normal (RM2 = 0, RM1 = 0: initial state) *Continuous mode not used* -- COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-5 command wait state -2. Write continuous (RM2 = 0, RM1 = 1): Mode 2 COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-5
3. Write continuous (RM2 = 1, RM1 = 0): Mode 3 COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-5 10-2-3 10-2-4 10-2-5
4. Write continuous (RM2 = 1, RM1 = 1): Mode 4 COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-5 10-2-2 10-2-3 10-2-4 10-2-5
*: In modes 2, 3, and 4, the IC remains locked in continuous write mode until the CS pin is set high. * The write address is automatically incremented. * The write address is retained unless the IC is reset or a new write address is issued.
No.A0569-92/106
LC74736PT
1.3 Color Table write (1) Write start address specification Use command 6C0 to set the color table write start address. CTN1 to CTN0: Color table specification (No.1 to No.4), CTA3 to CTA0: Address specification
No.1 B 0000 0001 0010 XX XXXX G XXXX R XXXX
Address
1110 1111
(2) Data write Continuous write mode differs depending on the write mode specification. (RM3) 1. Normal (RM3 = 0: initial state) *Continuous mode not used* ---COM6C1-1 6C1-2-1 6C1-2-2 command wait state --2. Write continuous (RM3 = 1) mode COM6C1-1 6C1-2-1 6C1-2-2
*: In mode 2, the IC remains locked in continuous write mode until the CS pin is set high. * The write address is automatically incremented. * The write address is retained unless the IC is reset or a new write address is issued.
No.A0569-93/106
LC74736PT
1.4 Character RAM write (1) Write start address specification Use COMMAND700 to specify the character RAM write start address. FAD1to FAD0: Character RAM address P-No specification QVGA: 0 to 3, hexadecimal, (4 characters) WVGA: 1 character only 0 to 3 (hexadecimal) P1 to P4 FVA3 to FVA0: Character RAM V dot address specificatrion 0 to F (hexadecimal) FRN1 to FRN0: ROM No. specification 0 to 3 (hexadecimal) No.1 to No.4
D15 to 0000 0001 0010 V dot Address D0
1110 1111
(2) Data write Continuous write mode differs depending on the write mode specification. (RM3) 1. Normal (RM3 = 0: initial state) *Continuous mode not used* ---COM701-1 701-2-1 701-2-2 command wait state --2. Write continuous (RM3 = 1) mode COM701-1 701-2-1 701-2-2
*: In mode 2, the IC remains locked in continuous write mode until the CS pin is set high. * The write address is automatically incremented. * The write address is retained unless the IC is reset or a new write address is issued.
No.A0569-94/106
LC74736PT
2. Display format 2.1 Color Specification Related Items (1) When a character is specified Specify color with the character color (character area) and character background color (outside the character area) Character color: 1 of 16 colors Character background color: 1 of 16 colors Color tables: Table No. 1 to No. 4 specified by CT1 to CT0. (COM10-2-3: VRAM) 1 of 64 types Character color Specified by CC0 to CC3: 1of 16 colors (COM10-2-2: VRAM) Character background color Specified by CB0 to CB3: 1 of 16 colors (COM10-2-2: VRAM)
(2) When a graphic 1 is specified Specify color is in dot units (16x16) 1 of 16 colors (FROM) Color tables: Table No. 1 to No. 4 specified by CT1 to CT0. (COM10-2-3: VRAM) 1 of 64 types Specified by FROM: 1 of 16 types
No.A0569-95/106
LC74736PT
(3) When a graphic 2 is specified Specify color is in dot units (16x16) 1 of 16 colors (FROM) Color tables: Table No. 1 to No. 4 specified by CT1 to CT0. (COM10-2-3: VRAM) 1 of 64 types
The CTB address display color shown with CB3 to CB0 is changed to the CTB address display color shown with CC3 to CC0. One color in the graphic character display can be changed by setting CB and CC. Specified by FROM: 1 of 16 types
(4) When a graphic 3 is specified Specify color is in dot units (16x16) 1 of 16 colors (FROM) Color tables: Table No. 1 to No. 4 specified by CT1 to CT0. (COM10-2-3: VRAM) 1 of 64 types CTB No. in the address shown with CB3 to CB0 is changed to CTB No. shown with CC1 to CC0 and display it. CTB No. of one color in the graphic character display can be changed by setting CB and CC. Specified by FROM: 1 of 16 types
No.A0569-96/106
LC74736PT
2.2 Display Control Related Items (1) Blinking: In character units 1. Normal at1 = 0 (COM10-2-1: VRAM)
2. Blinking at1 = 1 Display alternates between normal and transparent with the blinking period. (COM21-2: BK1, BK0) (2) Border display: Only valid for font specified characters 1. Border color: 1 of 16 colors (COM60-2 EGC3 to EGC0) Color table specification (COM60-2 EGCT1 to EGCT0) 1 of 64 types specified in line units 2. Border mode control (COM60-2 BLK1, BLK0) specified in line units i. Border ii. Shadow 1: lower
iii. Shadow 2: lower + right
No.A0569-97/106
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(3) Character size: Specified in line units The character size is specified as 1x to 4x independently for the vertical and horizontal directions. (COM40-2) 2.3 Box Display (raised/recessed)
raised 16 dots recessed
16 dots
(1) Raised/recessed specification: In character units (COM10-2-1 BXS) (2) Left side-displayed/undisplayed specification: in character units (COM10-2-1 BXL) (3) Right side-displayed/undisplayed specification: in character units (COM10-2-1 BXR) (4) Upper side-displayed/undisplayed specification: in character units (COM10-2-1 BXU) (5) Lower side-displayed/undisplayed specification: in character units (COM10-2-1 BXD) (6) Color specification: In line units COM50 (Upper side) COM51 (Lower side) BXUC3 to BXDC0: 1 of 16 colors BXDC3 to BXDC0: 1 of 16 colors Color table specification BXUCT1 to BXUCT0 BXDCT1 to BXUCT0 1 of 64 types Box dot width specification Each of left, right, upper, and lower can be specified independently. Left: BXLW1 to BXLW0 1 to 4 dots Right: BXRW1 to BXRW0 1 to 4 dots Upper and lower (COM59-2) Upper BXWU 1 to 2 dots (It depends on the character size.) Lower BXWD 1 to 2 dots (It depends on the character size.)
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2.4 Line spacing control (Command 58-2: GY3, GY2, GY1, GY0)
-1
16 dots
16 dots
+1 to +15 Line spacing
16 dots
-1
16 dots
16 dots
Line spacing
+1 to +15
-1
16 dots
+1 to +15
* Line spacing display control COM58-2: GS1, GS0 Character (1) Transparent (2) Transparent 1(character background color) (3) Character background color (4) Transparent (Border enabled)
Graphic Transparent Transparent 1(CB specified color) CB setting color Transparent
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* Basic line spacing unit GYBCK "0": 1V "1": It depends on the character size. * Box display (COM59-2) Character display range
16
16
Box display
Inside the character
Outside the character 1 (Valid only when line spacing is set.)
BXC1 = "0" BXC2 = "0"
BXC1 = "1" BXC2 = "1" BXC3 = "0"
Outside the character 2 (Valid only when line spacing is set.) BXC1 = "1" BXC2 = "1" BXC3 = "1"
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2.5 Screen Structure
Screen background color
Wallpaper display screen
Main screen 2 16x16 dot characters 30-characterx15-line QVGA panel
Main screen 1 16x16 dot characters 30-characterx15-line
* For each screen: Display on/off (transparent) can be specified independently. * For each screen: The display start position can be specified independently. The wallpaper display screen and the main screen require xxxx clocks before the horizontal start position is reached.
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* Display Format
1) QVGA Character specification 16 dots Graphic 16 dots
16H
2) WVGA Character specification 24 dots Graphic 24 dots
32H
* ROM structure (1) No internal ROM (2) Internal character RAM QVGA: 4 characters, WVGA: 1 character 1) Character font QVGA: 16x16-dot structure WVGA: 24x32-dot structure 2) Graphics QVGA: 16x16-dot structure WVGA: 24x32-dot structure
No.A0569-102/106
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(3) External ROM (QVGA: 16384 characters, WVGA: 4096 characters) x16 types, 16M 1) Conditions * QVGA mode Access time = 2x dot clock frequency or shorter Example: DCLK = 10MHz = 100nsx2 = 200ns or shorter * WVGA mode 1) Access time =3x dot clock frequency or shorter, with display limitations Example: DCLK = 33MHz = 30nsx3 = 90ns or shorter 2) Access time =2x dot clock frequency or shorter, with display limitations Example: DCLK = 33MHz = 30nsx2 = 60ns or shorter 3) Access time =1x dot clock frequency or shorter Example: DCLK = 33MHz = 30nsx1 = 30ns or shorter
2) ROM map * QVGA * Address A19 to A0
A1 to A0 00 16 dots A5 to A2 16 dots N1 N2 N3 N4 01 10 11
* Data D15 to D0 Used
Color information
A19 to A6 (14 bits) = 16384 characters = character codes
No.A0569-103/106
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* WVGA * Address A19 to A0 * Data D15 to D12, D11 to D0 Unused Used
A3 to A2 Location information 12 dots 12 dots
16 dots
P1 00
P2 01
16 dots
P3 10
P4 11
On each of P1 to P4
A1 to A0 00 12 dots A7 to A4 16 dots N1 N2 N3 N4 01 10 11 Color information
A19 to A8 (12 bits) = 4096 characters = character codes
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3) Display appearance * QVGA: 1 character = 16x16 dots Character N1 or N2 or N3 or N4, VRAM selectable Graphic N1+N2+N3+N4 Character
16 N1 or N2 or N3 or N4 16 16
Graphic
16 N1+N2 +N3+N4
* WVGA: 1 character = 24x32 dots Character P1+P2+P3+P4 (12x16x4) N1 or N2 or N3 or N4, VRAM selectable Graphic P1+P2+P3+P4 (12x16x4) N1+N2+N3+N4 Character
24 N1 or N2 or N3 or N4 32 32
Graphic
24 N1+N2 +N3+N4
12
12
16
P1
P2
16
16
P3 12
P4 12
16
No.A0569-105/106
LC74736PT
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of June, 2007. Specifications and information herein are subject to change without notice.
PS No.A0569-106/106

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