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PRELIMINARY
CY2XP306
High-frequency Programmable PECL Clock Generation Module
Features
* 60 ps typical Cycle-to-Cycle Jitter * 30 ps typical Output-Output Skew * Phase-locked loop (PLL) multiplier select * LVTTL or XO Input; Six LVPECL Outputs * Selectable Output Divider (/2) * 1-133 MHz Input Frequency Range * 62.5-500 MHz Output Frequency Range * 36-pin VFBGA, 6 x 8 x 1 mm * 3.3V operation * Serially Configurable Multiply Ratios
Block Diagram
QA1 FSELA QA1#
PLL_MULT
0 1
QA2 QA2# QA3 QA3# QB1
XIN/REF XOUT SER CLK SER DATA MR
XTAL OSCILLATOR
PLL xM
/1 /2 0 1
QB1# QB2 QB2# QB3
FSELB
QB3#
Pin Configuration (Top View)
C Y 2 X P 3 0 6 3 6 V F B G A P IN C O N F IG U R A T IO N T O P V IE W
QA1
Q A1#
Q A2
6
Q A2#
Q A3
Q A3#
Q B1
Q B1#
5
VDDA
GND
GND
VDDA
4
GND
SER_ DATA
Q B2
QB3
VDDB
VDDA
3
XO UT
SER_ C LK
Q B2#
Q B3#
VDDB
NC
2
X IN
GND
GND
VDDA
1
VDDB
VDDB
GND
PLL_ M ULT
MR
FSELA
FSELB
VDDA
A
B
C
D
E
F
G
H
Cypress Semiconductor Corporation Document #: 38-07725 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised April 8, 2005
PRELIMINARY
Pin Definitions
Pin # A2 A3 B2,B5,C1,G2,G5,A4 A5,H1,H2,H4,H5 A1,B1,G3,G4 A6 B6 C6 D6 E6 F6 G6 H6 C4 C3 F4 F3 D1 E1 F1 G1 H3 B4 B3 Table 1. Frequency Table PLL_Mult 0 1 M (PLL Multiplier) x16 x8 Example Input Frequency 19.44 MHz 19.53 MHz 19.44 MHz 19.53 MHz 38.88 MHz Pin Name XIN/REF XOUT GND VDDA VDDB QA1 QA1# QA2 QA2# QA3 QA3# QB1 QB1# QB2 QB2# QB3 QB3# MR FSELA FSELB NC Reference Crystal Input or LVTTL Reference Crystal Feedback Ground 3.3V Power Supply 3.3V Power Supply LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Reset; Internal Pull-Down, see Function Table Pin Description
CY2XP306
PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table No Connect
SER_DATA Serial Interface Data SER_CLK Serial Interface Clock
Example PLL Output Frequency 311.04 MHz 312.5 MHz 155.52 MHz 156.25 MHz 311.04 MHz
Table 2. Output Frequency Table Control Pin FSELA FSELB Table 3. Function Table Control Pin MR (Asynchronous) 0 Active 1 Reset (QX = Low, QX# = High) 0 QAx = PLL Output Frequency QBx = PLL Output Frequency 1 QAx = PLL Output Frequency/2 QBx = PLL Output Frequency/2
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PRELIMINARY
Two-Wire Serial Interface
Introduction The CY2XP306 has a two-wire serial interface designed for data transfer operations, and is used for programming the P and Q values for frequency generation. Sclk is the serial clock line controlled by the master device. Sdata is a serial bidirectional data line. The CY2XP306 is a slave device and can either read or write information on the dataline upon request from the master device. Figure 1 shows the basic bus connections between master and slave device. The buses are shared by a number of devices and are pulled high by a pull-up resistor.
CY2XP306
Data is allowed to change only at LOW period of clock, and must be stable at the HIGH period of clock. To acknowledge, drive the Sdata LOW before the Sclk rising edge and hold it LOW until the Sclk falling edge. Serial Interface Format Each slave carries an address. The data transfer is initiated by a start signal (S). Each transfer segment is one byte in length. The slave address and the read/write bit are first sent from the master device after the start signal. The addressed slave device must acknowledge (Ack) the master device. Depending on the Read/Write bit, the master device will either write data into (logic 0) or read data (logic 1) from the slave device. Each time a byte of data is successfully transferred, the receiving device must acknowledge. At the end of the transfer, the master device will generate a stop signal (P). Serial Interface Transfer Format Figure 2 shows the serial interface transfer format used with the CY2XP306. Two dummy bytes must be transferred before the first data byte. The CY2XP306 has only three bytes of latches to store information, and the third byte of data is reserved. Extra data will be ignored.
Serial Interface Specifications
Figure 2 shows the basic transmission specification. To begin and end a transmission, the master device generates a start signal (S) and a stop signal (P). Start (S) is defined as switching the Sdata from HIGH to LOW while the Sclk is at HIGH. Similarly, stop (P) is defined as switching the Sdata from LOW to HIGH while holding the Sclk HIGH. Between these two signals, data on Sdata is synchronous with the clock on the Sclk.
S d a ta S clk
S c lk _ C S d ata _ C
Rp
Rp
V DD
S d ata _ C
S clk _ in
S d ata _ in
S clk _ in
S d ata _ in
M a s te r D e vic e
S lav e D ev ice
Figure 1. Device Connections
S clk
S data
Start (S) valid data Acknowledge Stop (P)
Figure 2. Serial Interface Specifications
1 bit 7 bits Slave Address 1 bit R/W 1 bit 8 bits Dummy Byte 0 1 bit 8 bits 1 bit 8 bits 1 bit
S
Ack
Ack Dummy Byte 1 Ack
Data 0
Ack
Data 1
8 bits
Ack
1 bit
P
Figure 3. CY2XP306 Transfer Format
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PRELIMINARY
Serial Interface Address for the CY2XP306
A6 1 A5 1 A4 0 A3 0 A2 1 A1 0 A0 1
CY2XP306
R/W 0
Serial Interface Programming for the CY2XP306
b7 Data0 Data1 Data2 QCNTBYP P<7> Reserved b6 SELPQ P<6> Reserved b5 Q<5> P<5> Reserved b4 Q<4> P<4> Reserved b3 Q<3> P<3> Reserved b2 Q<2> P<2> Reserved b1 Q<1> P<1> Reserved b0 Q<0> P<0> Reserved
To program the CY2XP306 using the two-wire serial interface, set the SELPQ bit HIGH. The default setting of this bit is LOW. The P and Q values are determined by the following formulas: Pfinal = (P7..0 + 3) * 2 Qfinal = Q5..0 + 2. If the QCNTBYP bit is set HIGH, then Qfinal defaults to a value of 1. The default setting of this bit is LOW.
Reference Q
If the SELPQ bit is set LOW, the PLL multipliers will be set using the values in the Select Function Table. CyberClocksTM has been developed to generate P and Q values for stable PLL operation. This software is downloadable from www.cypress.com. PLL Frequency = Reference x P/Q = Output
Output VCO P
PLL
Figure 4. PLL Block Diagram
Functional Specifications
Crystal Input The CY2XP306 receives its reference from an external reference input or external crystal. Pin XIN is the reference crystal input, and pin XOUT is the reference crystal feedback. The oscillator circuit requires external capacitors. Please refer to the application note entitled Crystal Oscillator Topics for details. Select Input There are four select input pins, the PLL_MULT, MR, FSELA and FSELB. PLL_MULT pin selects the frequency multiplier in Table 4. State Transition Characteristics Table From VDD On To QA/QB Outputs Normal Transition Latency 3 ms
the PLL. The PLL_MULT pin has an internal pull-up resistor. The multiplier selection is given on Table 1, Frequency Table. The MR pin is a reset control pin. It has an internal pull-down resistor. Please see Table 3 for detailed function. The FSELA and FSELB pins are output dividers select pins, see Table 2 for Output Frequency Table. All of these four select pins are standard LVCMOS inputs. State Transition Characteristics Specifies the maximum settling time of the QA and QB bank outputs from device power-up. For VDD, any sequences are allowed to power-up and power-down the CY2XP306.
Description Time from VDD is applied and settled to outputs settled.
Table 5. Operating Ambient Temperature Parameter TA Industrial Temperature Description Commercial Temperature Min. 0 -40 Max. 70 85 Unit C C
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PRELIMINARY
Absolute Maximum Conditions
Parameter VDD VDD VTT VIN VOUT LUI TS TA TJ OJc OJa ESDh MSL Description Supply Voltage Operating Voltage Output Termination Voltage Input Voltage Output Voltage Latch Up Immunity Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Moisture Sensitivity Level Condition Non-functional Functional Relative to VDD[1] Relative to VDD[1] Relative to VDD[1] Functional Non-functional Functional Non-functional Functional Functional -65 -40 - 11.48 85.8 2000 3 -0.3 -0.3 100 Min. -0.3 3.135 VDD - 2
CY2XP306
Max. 4.6 3.465 VDD + 0.3 VDD + 0.3 +150 +85 150 Unit V V V V V mA C C C C/W C/W V N.A.
Crystal Requirements
Requirements to use parallel mode fundamental xtal. External capacitors are required in the crystal oscillator circuit. Please
refer to the application note entitled Crystal Oscillator Topics for details.
Crystal Requirements
Parameter XF Frequency Description Min. 10 Max. 31.25 Unit MHz
DC Specifications (VDD = 3.3 V 5%, Commercial and Industrial Temperature)
Parameter VDD VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 RPUP tPU IEE VOL VOH Supply voltage Input signal low voltage at pin PLL_MULT Input signal high voltage at pin PLL_MULT Input signal low voltage at pins REF Input signal high voltage at pins REF LVPECL input signal low voltage at pins MR, FSELA, FSELB Internal pull-up resistance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Maximum Quiescent Supply Current without Output Termination Current LVPECL Output Low Voltage VDD = 3.3V 5% LVPECL Output High Voltage IOL = -5 mA[2] IOH = -30 mA[2] Description Min. 3.135 - 0.65 - 2.0 Max. 3.465 0.35 - 0.8 - Unit V VDD VDD V V V V k ms mA V V
VDD - 1.945 VDD - 1.625[3] LVPECL input signal high voltage at pins MR, FSELA, FSELB VDD - 1.165[3] VDD - 0.88 10 0.05 - VDD - 1.995 VDD - 1.25 100 500 150 VDD - 1.5 VDD - 0.7
Note: 1. Where VDD is 3.3V5% 2. Equivalent to a termination of 50 to VTT. 3. VIL3 will operate down to GND; VIH3 will operate up to VDD.
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PRELIMINARY
AC Specifications (VDD = 3.3 V 5%, Commercial and Industrial Temperature)
Parameter fIN fXTALIN CIN,CMOS fO Vo(P-P) VCMRO tsk(O) tsk(PP) TR,TF DC JC2C Description Input frequency Crystal Input frequency Input capacitance at PLL_MULT pin[4] Output Frequency Differential output voltage (peak-to-peak) Output Common Voltage Range Typical Output-to-output skew Part-to-part output skew Output Rise / Fall time Long-term average output duty cycle Cycle-to-cycle Jitter (Peak) peak; 311 MHz; Jitter Defined by JESD65B 311 MHz 50% duty cycle Standard load Differential Operation 311 MHz 50% duty cycle Standard load Differential Operation 311 MHz 50% duty cycle Differential (20% to 80%) - - - 45 - Conditions Limited by Max PLL Frequency Min. 1 10 - 125 0.5
CY2XP306
Typ. - - - - -
Max. 133 10 500 -
Unit MHz pF MHz V V ps ps ns % ps
31.25 MHz
VDD - 1.425 30 - - - 60 TBD 150 0.3 55 TBD
tr, tf, 2 0 -8 0 %
VO
Figure 5. LVPECL Output
Notes: 4. Capacitance measured at freq. = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV.
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PRELIMINARY
Test Configurations
Standard test load using a differential pulse generator and differential measurement instrument.
CY2XP306
DUT
Pulse Generator Z = 50 ohm
VTT
RT = 50 ohm 5" Zo = 50 ohm 5" RT = 50 ohm
VTT
PLL
Figure 6. CY2XP306 AC Test Reference. One output LVPECL pair is shown for clarity.
Applications Information
Termination Example
Vdd - 2V Vdd R T = 50 ohm
REF
Zo = 50 ohm
R T = 50 ohm Vdd - 2 V GND
Figure 7. Standard LVPECL-PECL Output Termination. One output is shown for clarity.
Ordering Information
Ordering Code Lead Free CY2XP306BVXI CY2XP306BVXIT 36-lead VFBGA 36-lead VFBGA - Tape and Reel Industrial Temp Industrial Temp 3.3V 3.3V Package Type Operating Range Operating Voltage
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PRELIMINARY
Package Drawing and Dimensions
36-Lead VFBGA (6 x 8 x 1 mm) BV36A
BOTTOM VIEW
CY2XP306
A1 CORNER TOP VIEW A1 CORNER 1 2 3 4 5 6 O0.05 M C O0.25 M C A B O0.300.05(36X) 6 5 4 3 2 1
A B 8.000.10 0.75 C 8.000.10 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.15 C
SEATING PLANE 0.26 MAX. C 1.00 MAX
51-85149-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
Document History Page
Document Title: CY2XP306 High-frequency Programmable PECL Clock Generation Module Document Number: 38-07725 REV. ECN NO. Issue Date ** *A 312633 349137 See ECN See ECN Orig. of Change RGL RGL New Data Sheet Data sheet re-write Description of Change
CY2XP306
Document #: 38-07725 Rev. *A
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