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Ordering number : EN8927A
Bi-CMOS LSI
LV4141W
Overview
For LCD Panel Drive
Single Chip IC
The LV4141W is single chip IC for LCD panel drive.
Functions
* Analog block RGB Decoder/Driver * Digital block Timing Generator
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Symbol VCC1 max VCC2 max VDD max Allowable power dissipation Operating temperature Storage temperature Input pin voltage Pd max Topr Tstg VINA VINA VIND VIND Analog input pin (other than pin 33) Analog input pin (33PIN) Digital input pin (other than pins 6, 7, and 8) Digital input pin (6, 7, 8PIN) Conditions Analog LOW type Analog HIGH type Digital type Ta 75C * Mounted on a board. Ratings 6 12 4.5 350 -15 to +75 -40 to +125 -0.3 to VCC1 -0.3 to 10 -0.3 to VDD+0.3 -0.3 to +4.5 Unit V V V mW C C V V V V
* : Mounted on a board : 30x30x1.6mm3, glass epoxy board
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
41107 TI PC B8-6227, 6576 No.8927-1/27
LV4141W
Operating Ratings at Ta = 25C
Parameter Maximum supply voltage Symbol VCC1 VCC2 VDD Operating voltage range VCC1op VCC2op VDDop Analog LOW type Analog HIGH type Digital type Analog LOW type Analog HIGH type Digital type Conditions Ratings 3.0 7.0 4.5 2.7 to 3.6 6 to 9.5 2.7 to 3.6 Unit V V V V V V
Input Signal Voltage
Parameter Recommended input amplitude Conditions R, G, B input pin (RGB input mode) Ratings min typ 0.35 max 0.42 Unit Vp-p
Electrical DC Characteristics Unless otherwise specified, the setting 2 must be made. Unless otherwise specified, VCC1 = 3V, VCC2 = VCCCOM = 7V, GND1 = GND2 = GNDCON = 0, VDD1 = VDD2 = VDD0 = 3V, VSS1 = VSS2 = VSS0 = 0, Ta = 25C [Current Characteristics]
Parameter Current dissipation VCC1 Current dissipation VCC2 Current dissipation VDD, logic Symbol ICC11 ICC2 IDD1 IDD2 IDD3 Conditions Enter SIG4 (VL = 0mV) to (A). Measure the current value of ICC1. Enter SIG4 (VL = 0mV) to (A). Measure the current value of ICC2. Enter SIG4 (VL = 0mV) to (A). Measure the current value of IDD11 and IDD22. IDD1, IDD2, IDD3 = IDD11+IDD22 Normal Standby Normal Standby Normal Standby Sleep Ratings min 9.5 1 1.5 0 3.5 3 1 typ 14 1.5 2.8 0.1 6.5 6 1.6 max 18.5 2 3.5 0.2 8.5 8 2.5 Unit mA mA mA mA mA mA mA
[Digital block input/output characteristics]
Parameter L-level input voltage H-level input voltage H-level output voltage L-level output voltage Output transition time Symbol VIH VIL VOHT VOL tTLH tTHL Cross point time difference CHK duty T DTYHC Load 30pF Measure CKH1 and CKH2.(see Fig. 3) Load 30pF Measure the duty of CKH1 and CKH2. (Note 1) Digital block input pins : LOAD, DATA, SCLK, VDIN, HDIN, CLPIN (Note 2) Digital block output pin (pins 17 to 30) 47 50 53 % Conditions Digital block input pin (Note 1) Digital block input pin (Note 1) VDD = 3.0V IOH = -1.0mA (Note 2) IOL = 1.0mA (Note 2) Load 30pF (see Fig. 2) 0.7VDD 2.8 0.3 30 30 10 Ratings min typ max 0.3VDD Unit V V V V ns ns ns
No.8927-2/27
LV4141W
Electrical AC Characteristics (1) Unless otherwise specified, the setting 1 and 2 must be made. Unless otherwise specified, VCC1 = 3V, VCC2 = VCCCOM = 7V, GND1 = GND2 = GNDCON = 0, VDD1 = VDD2 = VDD0 = 3V, VSS1 = VSS2 = VSS0 = 0, Ta = 25C Unless otherwise specified, measure non-inverted output for P TP40, TP43, TP45 outputs. [RGB signal system]
Parameter Input-output gain TYP Symbol GTP Conditions Enter SIG3 to (A) and measure the ratio between the output amplitude (white to black) and input amplitude of TP43. Input-output gain MIN GMN Enter SIG3 to (A) and measure the ratio between the output amplitude (white to black) and input amplitude of TP43. Input-output maximum gain, MAX Frequency characteristics FCH FCL GMX Enter SIG3 to (A) and measure the ratio between the output amplitude (white to black) and input amplitude of TP43. Assume that the output amplitude of TP43 when SIG1 (0dB, 100kHz) is entered to (A) is 0dB. Change the input signal frequency to change and determine the frequency at which the output amplitude becomes -3dB. FCH when the serial bus LPF = HIGH and FCL when LPF = LOW Input/output delay rate TD Enter SIG8 to (A). Measure the delay time from the input signal 2T pulse peak to the peak of TP43 non-inverted output. Antipole output DC voltage change amount Output DC voltage VCC2 = 8.5V Output DC voltage VCC2 = 7V RGB signal output DC voltage VCC2 = 8.5V VOUTH VDSD COMBMX COMBMN VDSDH Measure TP38 output. DC IO = 1m ACOMBMX when COMB = 63 and COMBMN when COMB = 0 Measure the TP50 voltage by setting VCC2 = 8,5V and SIG center level changeover = low voltage mode. Measure the TP50 voltage by setting VCC2 = 7V and SIG center level changeover = high voltage mode. Set VCC2 = 8.5V and SIG center level changeover = low voltage mode and enter SIG4 (VL = 0mV) into (A). Adjust the serial bus BRIGHT to set TP43 output to 3Vp-p and measure the DC voltage of TP40, TP43, and TP45. RGB signal output DC voltage VCC2 = 7V VOUT Set VCC2 = 7V and SIG center level changeover = high voltage mode, and enter SIG4 (VL = 0mV) to (A). Adjust the serial bus BRIGHT to set the TP43 output to 3Vp-p and measure the DC voltage of TP40, TP43, and TP45. RGB signal output DC voltage difference Brightness change rate BRTMX VOUT Determine the maximum of differences among measurements of TP40, TP43, and TP45 of VOUT of previous item. Measure the change rate of the black level of TP40, TP43, and TP45 outputs when SIG2 is entered to (A) and BRT is changed from 128 to 255. BRTMN Measure the change rate of the white level of TP40, TP43, and TP45 outputs when SIG2 is entered to (A) and BRT is changed from 128 to 0. Antipole output change amount COMWMN COMWMX Measure the difference between non-inverted and inverted levels of TP38 output when (A) = SIG2 is entered and COMW is set to 255. Measure the difference between non-inverted and inverted levels of TP38 output when (A) = SIG2 is entered and COMW is set to 0. Continued on next page. 0.1 V 4.6 V -2.5 -2 V 2 2.5 V 0 120 mV 3.3 3.5 3.7 V 3.3 3.5 3.7 V 3.4 3.5 3.6 V 3.4 3.5 3.6 V 3.55 2.6 V V 0 100 200 ns 3.5 2.5 MHz MHz 19.5 21.5 23.5 dB -2 1 4.5 dB Ratings min 14 typ 16 max 18 Unit dB
No.8927-3/27
LV4141W
Continued from preceding page. Parameter Sub-brightness R change rates Symbol SBBRTR Conditions Measure the change amount of TP45 output black level when SIG2 is entered in (A) and COMW is changed from 128 to 255 and that of TP45 output white level change amount when COMW is changed from 128 to 0. Sub-brightness B change rates SBBRTR Measure the change amount of TP40 output black level when SIG2 is entered in (A) and COMW is changed from 128 to 255 and that of TP45 output white level when COMW is changed from 128 to 0. Gain difference between RGB signals Sub-contrast R change rate SBCNTR GRGB Determine the level difference of non-inverted output amplitude (white to black) of TP40, TP43, and TP45 when SIG3 is entered to (A). Measure the non-inverted output (white to black) of TP45 for the non-inverted output (white to black) of TP43 when SIG3 is entered to (A) and when R-CNT = 0 and R-CNT = 255. Sub-contrast B change rate SBCNTB Measure the non-inverted output (white to black) of TP40 for the non-inverted output (white to black) of TP43 when SIG3 is entered to (A) and when B-CNT = 0 and B-CNT = 255. RGB inverted/non-inverted gain difference GINV Determine the difference of inverted output amplitude for the non-inverted output amplitude (white to black) of TP40, TP43, and TP45 when SIG3 is entered to (A). -0.5 0 0.5 dB 2.0 dB 2.0 dB -0.6 0 0.6 dB 1.3 1.7 V Ratings min 1.3 typ 1.7 max Unit V
[RGB signal system]
Parameter Black level potential difference between RGB signals Symbol VBL Conditions Determine the difference between highest and lowest black levels for inverted and non-inverted outputs of TP40, TP43, and TP45 when SIG3 is entered to (A). Gamma gain GL GM GH Enter SIG7 into (A) and set the non-inverted output amplitude (black and white) of TP43 at 1 = 120, 2 = 0 to 2.7Vp-p with CONT. Adjust the amplitude (black and white) to 3.5Vp-p with 2 and the black level to 1.5V with BRT. Measure VG1, VG2 and VG3 and calculate as follows : GL = 20log (VG1/0.0357) GM = 20log (VG2/0.0357) GH = 20log (VG3/0.0357) (See Fig. 4.) 1 adjustment variable range V1MN V1MX Enter SIG7 to (A) and set the TP43 output (black to black) to 3Vp-p through BRIGHT adjustment. Read the gain change point at 2 = 0, 2 = 255 by referring to the IRE level of input signal : V1MN for1 = 0 V1MX for 1 = 255 2 adjustment variable range V2MN V2MX Enter SIG7 to (A) and set the TP43 output (black to black) to 3Vp-p through BRIGHT adjustment. Read the gain change point at1 = 0, 1 = 255 by referring to the IRE level of input signal : V2MN for2 = 0 V2MX for 2 = 255 Antipole transition time tCOMH tCOML RGB output black limiter variablerange RGB output white limiter variablerange VBLIMN VBLIMX VWLIMN VWLIMX Enter SIG3 to (A) and set the output amplitude of TP38 to 3Vp-p. Measure tCOMH for rise and tCOML for fall. Load : 1000pF Enter SIG2 to (A) and measure the amplitude of the black side limiter of inverted/non-inverted TP38, 40, 43 and 45 output. Enter SIG2 to (A) and measure the amplitude of the white side limiter of inverted/non-inverted TP38, 40, 43 and 45 output. Continued on next page. 4 2.2 Vp-p Vp-p 4.5 2 1 1 1.5 1.5 s s Vp-p Vp-p 100 0 IRE IRE 100 0 IRE IRE 23 12 23 26 15 26 29 18 29 dB dB dB Ratings min typ max 300 Unit mV
No.8927-4/27
LV4141W
Continued from preceding page. Parameter Black limiter Dcvoltage Symbol DVBLIM Conditions Enter SIG4 (VL = 0 mV) to (A) and adjust BLIM to set the TP43 output to 3Vp-p. Measure the DC voltage of TP40, Tp43, and TP45. White limiter Dcvoltage DVWLIM Enter SIG4 (VL = 350mV) into (A), measure the DC voltage of TP40, TP43, and TP45, and determine the difference from the above VOUT. 3.3 3.5 3.7 V Ratings min 3.3 typ 3.5 max 3.7 Unit V
[Sync. separation, TG]
Parameter Input sync signal width sensitivity Symbol WSSEP Conditions Enter SIG4 (VL = 0mV, VS = 143mV, WS variable) to (A) and confirm synchronization with the TP15HD output. Narrow WS of SIG4 from 4.7s and determine WS at which synchronization between the input and TP15HD output is lost. Sync separation input sensitivity VSSEP Enter SIG4 (VL = 0mV, WS = 4.7s, VS variable) to (A) and confirm synchronization with the TP15HD output. Reduce VS of SIG4 from 143mV and determine VS at which synchronization between the input and TP15HD output is lost. Sync separation output delay rate TDSY1 TDSY2 Enter SIG4 (VL = 0mV, WS = 4.7s, VS = 143mV) into (A) and measure the delay amount from the TP2RPD output. Assume that the period from fall of input HSYNC to a front edge of RPD output is TDSY1 and the period from rise of input HSYNC to the rear edge of RPD output is TDSY2. Horizontal pull-in range HPLLN HPLLP Enter SIG4 (VL = 0mV, WS = 4.7s, and VS = 143mV, horizontal frequency variable) to (A) and confirm synchronization with TP15HD output. Determine the horizontal frequency fH of SIG4 and calculate HPLLN = fH-15734 HPLLP = fH-15625. 500 500 Hz Hz 300 150 500 300 700 550 ns ns 40 60 mV Ratings min 2.0 typ max Unit s
Package Dimensions
unit : mm (typ) 3190A
12.0 48 49 33 32
0.5
10.0
64 1 0.5 (1.25)
(1.5)
17 16 0.18 0.15
1.7max
0.1
SANYO : SQFP64(10X10)
10.0
12.0
No.8927-5/27
LV4141W
Conditions of setting to measure the electric characteristic Following settings must be made before measurement of electric characteristics. Setting 1. System reset Turn ON SW56 and start V56 from GND in order to perform system reset for MOS block. (See fig. 1-1.) The default value is set for the serial bus. Setting 2. Horizontal AFC adjustment Enter SIG4 (VL = 0mV) to (A) and adjust VR1 so that the width of WL and WH becomes equal in the TP2 output waveform.(See fig 1-2.) (Note) In order to measure the 2MHz or more band for measurement items, such as the RGB signal frequency characteristics, etc., it is necessary to pass through the sample hold circuit via serial bus.
VDD1,VDD2
V56 (RESET)
Tr
Tr > 10s
Fig.1-1 System reset
SIG4
V-sync
TP2
TP2
Approx.1/2VDD
Fig.1-2 Horizontal AFC adjustment
No.8927-6/27
LV4141W
Electric characteristics measurement method
tTLH
tTHL 90%
10%
Fig.2 Output transition time measurement conditions
T
50%
T
Fig.3 Cross point time difference measurement conditions
White VG3 Non-inverted output
VG2 3.5V
VG1 1.5V Input
Black
Fig.4 characteristics measurement conditions
No.8927-7/27
LV4141W
Block Diagram
No.8927-8/27
LV4141W
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 VDD1 RPD VSS1 TEST4 TEST5 LOAD DATA SCLK TEST8 TEST3 VDD2 VDDO BLSW BLHD HD VSSO XSTH STH CKH2 CKH1 TEST6 TEST7 XDSG DSG XSTV STV CKV2 CKV1 XENB ENB VD VSS2 SHIN CSVO CSHO FBCOM GNDCOM COMOUT VCCCOM BOUT FBB GND2 GOUT FBG ROUT FBR VCC2 SIGCENT VCC1 DSDOUT NC VREG RIN GIN BIN Pin Name I/O O I O I I I I I O O O O O O O O O O O O O O O O O O I O O O O O O O O O O I O I I I Phase comparison output GND for oscillation cell Oscillator cell input (also used for test) Oscillator cell output Load input for serial bus Data input for serial bus Clock input for serial bus Test pin 8 Test pin 3 Digital system power supply (3V) Digital output system power supply (3V) Backlight control pulse output Backlight drive pulse output H-drive output Digital output system ground H-start pulse output (inverted) H-start pulse output H-clock 2 pulse output H-clock 1 pulse output Test pin 6 Test pin 7 Drain hold timing pulse output (inverted) Drain hold timing pulse output V-start pulse output (inverted) V-start pulse output V-clock 2 pulse output V-clock 1 pulse output Enable pulse output (inverted) Enable pulse output V-drive pulse output(positive polarity) Digital system ground Input pin for test Open collector output for vertical scan changeover Open collector output for lateral scan changeover Time constant pin for antipole output DC return Antipole output ground Antipole output Power supply for antipole output (7V) B output Time constant pin for B-output DC return 7V ground G output Time constant pin for G-output DC return R output Time constant pin for R-output DC return 7V power supply Time constant pin for R, G, B, COM, and DSD output DC voltage Analog 3V power supply Drain hold data output NC Reference power supply R signal input G signal input B signal input Continued on next page. Pin Description Oscillation cell power supply (3V)
No.8927-9/27
LV4141W
Continued from preceding page. Pin No. 56 57 58 59 60 61 62 63 64 RESET SYNC IN VSEP TC VDIN HDIN TEST1 TEST2 CLPIN GND1 Pin Name I/O I I O I I I I I System reset Sync signal input (composite) Time constant pin for separation of vertical sync VSYNC input CSYNC/HSYNC input Test pin 1 Test pin 2 External clamp input Analog 3V power supply Pin Description
Analog pin function description
Pin No. 33 Pin Name SHIN Pin Voltage Pin Description Input pin for test Normally, connect to the ground for use. Equivqlent Circuit
VDD2 10k 33 1k 40k 100k 10k
VSS2
34 35 CSVO CSHO Vertical and horizontal inversion control output pin. Output is made from the open collector. Connect a resistor to CSVO and CSHO pins of the panel power supply. The resistance must comply with the panel specification.
VCC2
34 35 GND2
36 41 44 46
FBCOM FBR FBG FBB
1.5V
Feedback circuit smoothing capacitor pin for control of antipole output DC level and RGB output DC level. Because of high impedance, a capacitor with small leakage is used.
VCC1 1k 36 41 44 46 GND1 1k 1k 100k
37 38
GNDCOM COMOUT
0V 2.6 to 3.55V
Ground pin of antipole output Antipole AC output pin that can adjust the output DC voltage with variable resistor of serial bus. When the signal output DC voltage has been changed to VCC2/2 and VCC2*21/51 with the serial bus and the voltage has been applied to SIC.C from the outside, the DC voltage of antipole output follows.
VCCCOM 150 38 20 GNDCOM
39
VCCCOM
7V
Power pin of antipole output Continued on next page.
No.8927-10/27
LV4141W
Continued from preceding page. Pin No. 40 43 45 Pin Name ROUT GOUT BOUT Pin Voltage VCC2/2 VCC2*21/51 Pin Description RGB elementary color signal output pin. Can be changed to VCC2/2 and VCC2*21/51 with the serial bus. Equivqlent Circuit
VCC2 40 43 45 20 20 40A 150k 300 150k 1k
GND2
42 47 48 GND2 VCC2 SIGCENT 0V 7V VCC2/2 VCC2 ground. 7V power supply. Pin to set the DC voltage of R/G/B/COM/DSD output. Connect a capacitor of 0.01F between this pin and GND2. When the signal output DC voltage is to be used with the setting other than VCC2/2 and VCC2*21/51, set to the SIG center level changeover: high voltage mode with the serial bus and apply the voltage (3.3 - 3.7V) from the outside.
VCC2
150k
48
GND2
49 50 VCC1 DSDOUT 3.0V VCC2/2 VCC2*21/51 Analog 3V power supply. Drain hold data power output pin. The output DC voltage can be set to VCC2/2 and VCC2*21/51 with the serial bus. Connect a capacitor of 1F between this pin and GND2.
105k
1k 1k 10 20 1k
VCC2
50
10k
51 52 NC VREG 2.0V Pin not used Regulator output pin. Connect an external capacitor of 1F or more.
GND2
VCC1
52 18.5k GND1
53 54 55 RIN GIN BIN 1.45V Analog RGB signal input pin.The standard input signal level is 0.5Vp-p (from sink chip to white 100%). Pedestal clamp is made with an external coupling capacitor.
30k
VCC1 53 54 55 GND1
Continued on next page.
1k
20A
No.8927-11/27
LV4141W
Continued from preceding page. Pin No. 56 Pin Name RESET Pin Voltage Pin Description C-MOS circuit reset pin. Normally, this is used with the capacity connected to the ground. (Threshold value = 2.0V) Equivqlent Circuit
VDD1
2A 300
56
1k
GND1
57 SYNCIN 1.6V Input pin for sync separation. Input is made via the external capacitor.
VDD1
1k
57
1k 500 GND1 0.6A 12A
58
VSEPTC
1.7V
Time constant connection pin for vertical sync separation.
VDD1
500
58
1k 1k 20A
GND1
64 GND1 Analog 3V power supply.
20A
Digital pin function description
Pin No. 1 2 Pin Name VDD1 RPD Pin Voltage Pin Description Power supply dedicated for VCO Phase comparator output pin Equivqlent Circuit
VDD1 2 1k 100k 100k VSS1
3 4 5 VSS1 TEST4 TEST5 0 Groud pin for VCO TEST4 is an input pin for test. TEST5 is an output pin for test. Use while fixing TEST4 to the ground potential and keeping TEST5 open.
6k
1.5V
VDD1 4 5 VSS1
Continued on next page.
600
No.8927-12/27
LV4141W
Continued from preceding page. Pin No. 6 7 8 Pin Name LOAD DATA SCLK Pin Voltage Pin Description Serial bus input pin. Input possible up to 4.5V regardless of the VDD2 power voltage. Equivqlent Circuit
VDD2
6 7 8 VSS2
9 10 61 62 63 TEST8 TEST3 TEST1 TEST2 CLPIN TEST8, TEST3, TEST1, and TEST2 are input pins for test. Normally, this is used at the ground potential or in the open state. CLPIN is an input pin for external clamp. Use after setting to the external clamp input with the serial bus. Connect the CLPIN pin to the ground in cases other than external clamp input.
2k
VDD2 9 10 61 62 63
2k
50k VSS2
11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 32 59 60
VDD2 VDD0 BLSW BLHD HD XSTH STH CKH2 CKH1 TEST6 TEST7 XDSG DSG XSTV STV CKV2 CKV1 XENB ENB VD VSSO VSS2 VDIN HDIN
-
Power pin for digital block Power pin for digital system output Digital output pin.
VDD0
VSS0
0 -
Power pin for digital system output. Ground Digital ground pin. External VD and HD input pins. When using, set them to the external synchronous signal input with the serial bus. Connect VDIN and HDIN pins to the ground in cases other than the external synchronous signal input.
VDD2 50k 59 60 VSS2 2k
No.8927-13/27
No. 38 (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG4(VL=0mV) (A)=SIG3 (A)=SIG3 (A)=SIG3 (A)=SIG6 (A)=SIG6 (A)=SIG8 (A)=SIG2 (A)=SIG2 (A)=SIG4 (A)=SIG4 (A)=SIG4 (A)=SIG4 (Calculate) (A)=SIG2 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF B B B B B B OFF OFF OFF OFF B B B B B B B B OFF OFF OFF OFF B B B B B B B B B B OFF OFF OFF OFF B B B OFF OFF OFF OFF B B B ON ON ON ON ON ON ON ON ON ON OFF ON ON ON A B A ON OFF ON ON ON A B A ON OFF OFF OFF OFF B B B ON 1 ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL OFF OFF OFF OFF B B B ON 1 OFF OFF OFF OFF B B B ON 1 128 128 128 128 128 128 128 128 ADJ ADJ ADJ ADJ ADJ 255 0 OFF OFF OFF OFF B B B ON 1 128 OFF OFF OFF OFF B B B ON 1 128 128 128 128 0 255 128 128 128 128 128 128 128 128 128 128 128 128 OFF OFF OFF OFF B B B ON 1 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 OFF OFF 128 OFF OFF B B B ON 1 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 OFF OFF OFF OFF B B B ON 1 128 128 128 128 OFF OFF OFF OFF B B B ON 1 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFF OFF 128 0 OFF OFF B B B ON 1 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFF OFF 128 0 0 OFF OFF B B B ON 1 128 128 128 OFF OFF OFF OFF B B B ON 1 128 128 128 128 0 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 ADJ ADJ ADJ ADJ ADJ 128 128 OFF OFF 128 0 0 OFF OFF B B B ON 1 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 OFF 0 0 OFF OFF OFF B B B ON 1 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 OFF OFF OFF OFF B B B ON 1 128 128 128 128 0 0 128 128 128 OFF OFF OFF OFF B B B ON 1 128 128 128 128 0 0 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFF OFF OFF OFF B B B ON 1 128 128 128 128 0 0 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFF OFF OFF OFF A B A ON 1 128 128 128 128 0 0 128 128 128 0 0 OFF OFF OFF OFF B B B ON 1 128 128 128 128 0 0 128 128 128 0 0 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ 40 43 45 53 54 55 56 Panel System S/H BRT CNT R-B B-B 1 COMW RCNT BCNT BLM WLM 2
Parameter
Symbol
Test
Input signal, Conditions, etc. VCO COMB 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 63 0 51 51 51 51 51 51 51
SW set
Mode set
DAC set
Pin
0
(Setting 2, horizontal AFC
1
Current dissipation, VCC1(Normal)
ICC11
ICC1
Current dissipation, VCC1(Standby)
ICC1
2
Current dissipation, VCC2(Normal)
ICC2
ICC2
Current dissipation, VCC2(Standby)
3
Current dissipation, VDD(Normal)
IDD1
IDD
Current dissipation, VDD(Standby)
IDD2
IDD
Current dissipation, VDD(Sleep)
IDD3
IDD
4
L-level input voltage
VIL
5
H-level input voltage
VIH
6
H-level output voltage
VOH
7
L-level output voltage
VOL
8
Output transition time
tTLH
TP12
tTHL
TP12
9
Cross point time difference
T
TP12
LV4141W
10
HCK duty
DTYHC
TP12
11
Input-output gain TYP
GTP
TP43
12
Input-output gain MIN
GMN
TP43
13
Input-output gain MAX
GMX
TP43
14
Frequency characteristics
FCH
TP43
FCL
TP43
15
Input/output delay rate
TD
TP43
16
Antipole output DC current change amount
COMBMX
P38
COMBMN
P38
17
DSD output DC voltage VCC2=8.5V VDSDH
P50
18
DSD output DC voltage VCC2=7V
VDSD
P50
19
RGB output DC voltage VCC2=8.5V VOUTH
20
RGB output DC voltage VCC2=7V
VOUT
21
RGB output DC voltage difference
VOUT
No.8927-14/27
22
Brightness change rate
BRTMX
P43
OFF OFF OFF OFF BRTMN P43 (A)=SIG2 (Note) PLL resetting necessary after change of the panel mode (- : arbitrary, ADJ : adjustment, SET : setting)
No. Conditions, etc. 38 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON B B B OFF OFF OFF OFF OFF OFF OFF B B B B B B B B B B B B B B B ON ON ON ON ON ON ON NT PAL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF B OFF OFF OFF B B OFF OFF OFF B B B OFF OFF OFF B B B ON OFF OFF OFF B B B ON OFF OFF OFF B B B ON OFF OFF OFF B B B ON OFF OFF OFF B B B ON OFF OFF OFF B B B ON ALL 128 128 0 0 255 255 0 255 128 128 128 128 128 128 OFF OFF OFF B B B ON ALL ADJ OFF OFF OFF B B B ON ALL ADJ 60 60 128 128 128 128 128 128 128 128 128 128 128 128 128 128 OFF OFF OFF B B B ON ALL ADJ 60 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 OFF OFF OFF B B B ON ALL ADJ 60 128 OFF ADJ OFF OFF B B B ON ALL ADJ 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 OFF OFF OFF B B B ON ALL ADJ ADJ 128 128 120 120 0 255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFF OFF OFF B B B ON ALL ADJ ADJ 128 128 120 ADJ ADJ 180 0 0 0 255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFF OFF OFF B B B ON ALL 128 128 128 128 0 0 OFF OFF OFF B B B ON ALL 128 128 128 128 0 0 128 128 128 128 128 128 128 128 128 ADJ ADJ 128 128 128 128 128 128 128 128 128 128 128 128 OFF OFF OFF B B B ON ALL 128 70 128 128 0 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 OFF OFF OFF B B B ON ALL 128 70 128 128 0 0 128 SET 128 SET 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 OFF OFF OFF B B B ON ALL 128 128 128 128 0 0 128 128 128 OFF OFF OFF B B B ON ALL 160 128 128 SET 0 0 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 255 0 0 ADJ 0 0 0 0 0 0 0 OFF OFF OFF B B B ON ALL 160 128 SET 128 0 0 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 8 0 0 0 0 0 0 OFF OFF OFF B B B ON ALL 128 128 128 128 0 0 0 128 128 0 0 OFF OFF OFF B B B ON ALL 128 128 128 128 0 0 255 128 128 0 0 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ 40 43 45 53 54 55 56 Panel System S/H BRT CNT R-B B-B COMW RCNT BCNT BLM WLM (A)=SIG2 (A)=SIG2 (A)=SIG4 (A)=SIG4 (A)=SIG3 (A)=SIG3 (A)=SIG3 (A)=SIG3 (A)=SIG3 (A)=SIG7 (A)=SIG7 (A)=SIG7 (A)=SIG7 (A)=SIG7 (A)=SIG7 (A)=SIG7 (A)=SIG3 (A)=SIG3 (A)=SIG2 (A)=SIG2 (A)=SIG2 (A)=SIG2 (A)=SIG4 (A)=SIG4 (A)=SIG4 (A)=SIG4 (A)=SIG4 (A)=SIG4 (A)=SIG4 (A)=SIG4 1 2 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
Parameter
Symbol
Test
Input signal, VCO COMB
SW set
Mode set
DAC set
Pin
23
Antipole output change amount
COMWMX
P38
COMWMN
P38
24
Sub-brightness R change rate
SBBRTR
P41
25
Sub-brightness B change rate
SBBRTB
P45
26
Gain difference between RGB
GRGB
27
Sub-contrast R change rate
SBCNTR
28
Sub-contrast B change rate
SBCNTB
29
RGB inverted/non-inverted gain
GINV
30
Black level potential difference between RGB signals
VBL
31
Gamma gain
GL
P43
GM
P43
GH
P43
32
1 adjustment variable range
V1MN
P43
V1MX
P43
33
2 adjustment variable range
V2MN
P43
LV4141W
V2MX
P43
34
Antipole transition time
tCOM
P38
tCOM
P38
35
RGB output black limiter operating
VBLIMN
voltage
VBLIMX
36
RGB output white limiter operating
VWLIMN
voltage
VWLIMX
37
Black limiter DC voltage difference
VBLIM
38
White limiter DC voltage difference
VWLIM
39
Input sync signal amplitude sensitivity
WSSEP
40
Sync separation input sensitivity
VSSEP
41
HD output delay rate
TDSY1
P15
TDSY2
P15
42
Horizontal pull-in range
HPLLN
P15
No.8927-15/27
HPLLP
P15
(Note) PLL resetting necessary after change of the panel mode (- : arbitrary, ADJ : adjustment, SET : setting)
LV4141W
Input sine wave (1)
SG No. SIG1 Sine wave With/without sine wave video signal (Amplitude and frequency variable)
150m 143m
Value shown in the left 0dB
SIG2
357mV
143mV
SIG3
150 143
5-step staircase wave
SIG4
VL amplitude variable VS variable:
VL VS WS fH
143mV, unless otherwise specified. WS variable: 4.7s, unless otherwise specified. fH variable : NTSC 15.734kHz PAL 15.625kHz unless otherwise specified.
Input sine wave (2)
SG No. SIG5 Sine wave
30s GND
5s VL
VL amplitude variable
SYNC Timing
SIG6
75mV 175mV 143mV
Frequency variable
SIG7
357mV 143mV
SIG8
10-step staircase wave
357mV 143mV
2T pulse
No.8927-16/27
LV4141W
Serial bus communication specifications (1) Conditions for serial transfer
DATA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
ts1
th1
SCLK
50%
tw1L
tw1H
LOAD
50%
ts0
th0
tw2
Parameter Serial transfer Data setup time
Symbol
Conditions
min
typ
max
unit
ts0 ts1
LOAD setup time to start SCLK. DATA setup time to start SCLK. Hold time of LOAD for fall of SCLK. Data hold time to start SCLK. SCLK pulse width. SCLK pulse width. LOAD pulse width.
150 150 150 150 160 160 1.0
ns ns ns ns ns ns s
Data hold time
th0 th1
Pulse width
tw1L tw1H tw2
No.8927-17/27
LV4141W
(2) 3-wave serial format
DATA
SCLK
LOAD
Data length : 16bit Clock frequency : 3MHz or less DATA loaded at start of "LOAD" only when 16-clock of "SCLK" is entered in the "LOAD" "L" period. (Note) Data not loaded in case of 15 or less clocks or 17 or more clocks in "LOAD" "L" period
(3) Data output timing 1. Various mode settings Some items (with a circle in the V latch column of data specification) have data set at fall of the vertical synchronous signal and some (without a mark in the V latch column) do not. When data immediately before the vertical synchronous signal is transferred for multiple times, data immediately before vertical synchronous signal becomes effective for items to be set with the vertical synchronous signal. For items for whcih no setting is made, data becomes effective each time "DATA" is loaded. 2. Setting of the electric volume D/A output data is changed at the same time with loading of "DATA."
No.8927-18/27
LV4141W
(4) Data specifications (4-1) Various mode settings 1
D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 D6 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 D3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 D2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 D1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 D0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Not used Not used LPF characteristic changeover : High LPF characteristic changeover : Low Not used Not used System changeover NTSC System changeover PAL External VD input changeover OFF (used to separate IC sync) External VD input changeover ON (with external VD input) Normal mode For test. Do not set. For test. Do not set. For test. Do not set. HD output polarity, positive HD output polarity, negative VD output polarity, positive VD output polarity, negative Panel selection, 521x218 :L1 Panel selection, 557x234 :L2 Not used Not used Field overlap method, odd number on even number Field overlap method, even number on odd number Horizontal inversion, normal scan Horizontal inversion, reverse scan Vertical inversion, from top to bottom Vertical inversion, from bottom to top Not used Not used Normal mode For test. Do not set. For test. Do not set. For test. Do not set. For test. Do not set. For test. Do not set. External SYNC input polarity change, negative polarity External SYNC input polarity, positive polarity External clamp input changeover OFF (IC internal pulse used) External clamp input changeover ON (external pulse input) HSYNC/CSYNC input changeover. SYNC IN valid HSYNC input changeover. HD IN valid Description V latch Default
No.8927-19/27
LV4141W
(4-1) Various mode settings 2
D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 D8 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 D7 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 1 0 x x x x 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 1 0 0 x x x x 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 1 0 0 0 0 D3 0 0 0 0 0 0 1 0 0 0 0 0 0 D2 0 0 0 0 0 1 0 0 0 0 0 0 0 D1 0 0 0 1 0 0 0 0 0 0 0 0 0 D0 0 1 0 0 0 0 0 0 0 0 0 0 0 Normal mode For test. Do not set. VGATE function ON VGATE function OFF Normal mode For test. Do not set. For test. Do not set. SIG center level changeover Low voltage SIG center level changeover High voltage Normal mode For test. Do not set. For test. Do not set. For test. Do not set. H-position setting, 2fhx31Step (Note 1) V-position setting, 1Hx4Step (Note 2) HD phase setting, 4fhx31Step (Note 3) BLHD pulse setting, 2fhx31Step (Note 4) Not used Normal mode For test. Do not set. For test. Do not set. For test. Do not set. For test. Do not set. V blanking period CKH?STH stop OFF V blanking period CKH/STH stop ON H blanking period CKH stop OFF H blanking period STH stop ON Normal mode For test. Do not set. For test. Do not set. HD/VD output ON HD/VD output OFF (HD generation counter stop) BLHD output ON BLHD output OFF (BLHD generation counter stop) 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Backlight OFF (BLSW = 3V) Backlight ON (BLSW = 0V) Normal mode For test. Do not set. For test. Do not set. For test. Do not set. For test. Do not set. Horizontal system counter operation Horizontal system counter stop (effective at standby only) Not used Not used Not used Not used Not used 10000 010 00000 10000 Description V latch Default
HC5 HC4 HC3 HC2 HC1 x x VP2 VP1 VP0
HD6 HD5 HD4 HD3 HD2 HW5 HW4 HW3 HW2 HW1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0
No.8927-20/27
LV4141W
(4-1) Various mode settings 3
D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 D7 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 D6 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 D5 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 D4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 D3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 D2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 D1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 D0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 x 0 0 0 0 0 0 Description Standby mode (Note 6) Sleep mode (Note 6) Normal mode (Note 6) Not used Blanking at transfer to normal ON Blanking at transfer to normal OFF Blanking period at transfer to normal changed to 0.25 sec Blanking period at transfer to normal changed to 0.5 sec Normal mode For test. Do not set. For test. Do not set. For test. Do not set. For test. Do not set. Sample hold phase SHS1 (Note 5) Sample hold phase SHS2 (Note 5) Sample hold phase SHS3 (Note 5) Sample hold phase SHS4 (Note 5) Sample hold phase SHS5 (Note 5) Sample hold phase SHS6 (Note 5) Sample hold phase, ALL through (Note 5) Normal mode For test. Do not set. For test. Do not set. For test. Do not set. For test. Do not set. For test. Do not set. V latch Note 6 Note 6 Note 6 Default
(4-2) Electronic volume setting
D15 D14 D13 D12 D11 D10 D9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 D8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Not used Not used BRIGHT adjustment CONTRAST adjustment R-BRIGHT adjustment B-BRIGHT adjustment -1 adjustment -2 adjustment Not used R-CONT adjustment B-CONT adjustment BLKLIMT adjustment Not used Not used Not used VCO adjustment WHTLIMT adjustment COM amplitude adjustment COM level adjustment For test. Do not set. 10000000 0000 10000000 100000 10000000 10000000 10101100 10010101 10001100 10000000 10000000 01100100 00000000 Description Default DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 x x x x DA3 DA2 DA1 DA0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 x x DA5 DA4 DA3 DA2 DA1 DA0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
No.8927-21/27
LV4141W
(Note 1) H-Position set (1Step = 2x1/fh) : 1/fh = 90ns
CLK(fh)
10001(+1) STH 10000(Default) 01111(-1)
Step 1 Step 15
Step 1 Step 16
Center
(Note 2) V-Position set
-2H -1H
(VD) (VD) 2H
STV(Default) +1H +2H
(VD) (VD) (VD)
(Note 3) HD phase set (1Step = 4x1/fh)
HSYNC Approx.6.5s HD Approx.2s 00000 (Default) HD Step 31 11111
No.8927-22/27
LV4141W
(Note 4) BLHD phase set (1Step = 2x1/fh)
00000 Step 16 Approx.7s BLHD Step 15 10000 (Default) 11111
(Note 5) Sample hold phase S/H pulse timing
CKH B A B C D E SH3 F SH2 SH1 SH4 G S/H1 S/H4 S/H3 S/H4
R
S/H2
S/H4
CSH = H (Normal)
SHS1 SH1 SH2 SH3 SH4 B F D C SHS2 C A E D SHS3 D B F E SHS4 E C A F SHS5 F D B A SHS6 A E C B
CSH = L (Inverted)
SHS1 SH1 SH2 SH3 SH4 D F B C SHS2 E A C D SHS3 F B D E SHS4 A C E F SHS5 B D F A SHS6 C E A B
SH1 : SH pulse for G signal SH3 : SH pulse for B signal
SH2 : SH pulse for R signal SH4 : SH pulse for RGB signal
No.8927-23/27
LV4141W
(Note 6) Powr save function a) Signal output in each mode
Output Pin RGBout DSD COM CKH1 CKH2 STH XSTH DSG XDSG ENB XENB CKV1 CKV2 STV XSTV HD VD BLHD BLSW Normal output Normal output Normal output CKH1 = H CKH2 = L STH = H XSTH = L PCG1 = H PCG2 = L ENB = H XENB = L CKV1 = H * CKV2 = L * STV = H * XSTV = L * all "L" Normal output all OFF Normal Standb Sleep
* After transfer from normal to standby, the respective state becomes effective after normal output for the 1V period.
b) Transfer/return to each mode * Transfer/return between normal and standby modes is acknowledged with the vertical synchronous signal. * Transfer/return between standby and sleep modes is changed over each time the serial data is transmitted. * Transfer/return between normal and sleep modes cannot be made directly. Be sure to carry out changeover via the standby mode.
No.8927-24/27
LV4141W
Sampl Application Circuit (at input of internal synchronous separate signal)
To LCD Panel
+7V
0.01F
+ 47F
10k
0.47F
0.47F
0.47F
+3V 48 47 46
45
44
43
42
41
0.47F
40
39
38
37
36
0.47F
35
34
10k
33
GOUT
FBG
FBB
BOUT
COMOUT
FBCOM
ROUT
SIGCENT
VCCCOM
GNDCOM
CSHO
CSVO
VCC2
FBR
GND2
0.01F
+ 47F To LCD Panel
49 VCC1 50 DSDOUT 51 NC
VSS2 32 VD 31 ENB 30 XENB 29 CKV1 28 CKV2 27 STV 26 To LCD Panel
+ 1F + 1F + 1F + 1F + 1F
52 VREG 53 RIN 54 GIN 55 BIN 56 RESET
R G B
22000pF
0.01F 57 SYNC IN 58 VSEP TC 59 VDIN 60 HDIN 61 TEST1 62 TEST2 63 CLPIN 64 GND1
LV4141W
XSTV 25 DSG 24 XDSG 23 TEST7 22 TEST6 21 CKH1 20 CKH2 19 STH 18 To LCD Panel
0.33F
TEST4
TEST5
TEST8
TEST3
XSTH 17
BLSW
LOAD
VDD1
VDD2
VDD0
DATA
BLHD
SCLK
VSS1
+3V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0.01F
47F
+
To Serial Controller +
+3V
10k + 1F
6800pF
47F
0.01F
VSS0
RPD
HD
SHIN
No.8927-25/27
LV4141W
Sampl Application Circuit (at input of external synchronous separate signal)
To LCD Panel
+7V
0.01F
+ 47F
10k
0.47F 0.47F 0.47F 0.47F
0.47F
+3V 48 47 46
45
44
43
42
41
40
39
38
37
36
35
34
10k
33
GOUT
FBG
BOUT
COMOUT
FBB
SIGCENT
FBCOM
FBR
ROUT
VCCCOM
GNDCOM
CSHO
CSVO
VCC2
+ 47F To LCD Panel
0.01F
GND2
49 VCC1 + 1F + 1F + 1F + 1F + 1F 50 DSDOUT 51 NC 52 VREG 53 RIN 54 GIN 55 BIN 56 RESET 57 SYNC IN 58 VSEP TC 0.33F *1
VSS2 32 VD 31 ENB 30 XENB 29 CKV1 28 CKV2 27 STV 26 To LCD Panel
R G B
22000pF
LV4141W
XSTV 25 DSG 24 XDSG 23 TEST7 22 TEST6 21 CKH1 20 CKH2 19 STH 18 XSTH 17 To LCD Panel
59 VDIN (VD) *2 60 HDIN CSYNC,(HD) 61 TEST1 62 TEST2 63 CLPIN 64 GND1
TEST8
TEST4
TEST5
TEST3
LOAD
VDD1
VDD0
BLSW
VDD2
DATA
SCLK
BLHD
VSS1
RPD
+3V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
HD
16
0.01F
47F
+
1k
10k
To Serial Controller +
+3V
1F
+
6800pF
47F
0.01F
*1 Delete (open) at input of external VD. *2 Connect pin 59 to GND at input of composite sink
VSS0
SHIN
No.8927-26/27
LV4141W
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of April, 2007. Specifications and information herein are subject to change without notice. PS No.8927-27/27

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