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ST7FLCD1
8-bit MCU for LCD Monitors with 60 KBytes Flash, 2 KBytes RAM, 2 DDC Ports and Infrared Controller
Key Features
60 KBytes Flash Program Memory In-Circuit Debugging and Programming In-Application Programming Data RAM: up to 2 KBytes (256 bytes stack, 2 x 256 bytes for DDCs) 8 MHz, up to 9 MHz Internal Clock Frequency True Bit Manipulation Run and Wait CPU Modes Programmable Watchdog for System Reliability Protection against Illegal Opcode Execution 2 DDC Bus Interfaces with:

SO28 ORDER CODE: ST7FLCD1
General Description
The ST7FLCD1 is a microcontroller (MCU) from the ST7 family with dedicated peripherals for LCD monitor applications. The ST7FLCD1 is an industry standard 8-bit core that offers an enhanced instruction set. The 5V supplied processor runs with an external clock at 24 MHz (27 MHz maximum). Under software control, the MCU mode changes to Wait mode thus reducing power consumption. The enhanced instruction set and addressing modes offer real programming potential. In addition to standard 8-bit data management, the MCU features also include true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. The device gathers the on-chip oscillator, CPU, 60-Kbyte Flash, 2-KByte RAM, I/Os, two 8-bit timers, infrared preprocessor, 4-channel Analog-toDigital Converter, 2 DDCs, IC single master, watchdog, reset and six 8-bit PWM outputs for analog DC control of external functions.
DDC 2B protocol implemented in hardware Programmable DDC CI modes Enhanced DDC (EDDC) address decoding HDCP Encryption keys
Fast IC Single Master Interface 8-bit Timer with Programmable Pre-scaler, Auto-reload and independent Buzzer Output 8-bit Timer with External Trigger 4-channel, 8-bit Analog to Digital Converter 4 + 2 8-bit PWM Digital to Analog Outputs with Frequency Adjustment Infrared Controller (IFR) Up to 22 I/O Lines in 28-pin Package 2 Lines Programmable as Interrupt Inputs Master Reset and Low Voltage Detector (LVD) Reset Complete Development Support on PCWindows Full Software Package (Assembler, Linker, C-compiler and Source Level Debugger)
February 2005
Revision 2.10
eDocs No. CD00003537
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ST7FLCD1
Table of Contents
Chapter 1
1.1 1.2 1.3 1.4 1.5 1.6
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Block Diagram ..................................................................................................................... 6 Abbreviations ....................................................................................................................... 6 Reference Documents ......................................................................................................... 7 Pin Description .................................................................................................................... 8 External Connections ......................................................................................................... 10 Memory Map ..................................................................................................................... 11
Chapter 2
2.1
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Main Features .................................................................................................................... 15
2.1.1 CPU Registers ...................................................................................................................................15
Chapter 3
3.1 3.2 3.3 3.4
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Low Voltage Detector and Watchdog Reset ...................................................................... 22 Watchdog or Illegal Opcode Access Reset ........................................................................ 23 External Reset .................................................................................................................... 23 Reset Procedure ................................................................................................................ 23
Chapter 4
4.1 4.2 4.3 4.4 4.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Software ............................................................................................................................. 24 External Interrupts (ITA, ITB) ............................................................................................. 24 Peripheral Interrupts ........................................................................................................... 24 Processing ......................................................................................................................... 24 Register Description .......................................................................................................... 26
Chapter 5
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8
Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Introduction ........................................................................................................................ 28 Main Features .................................................................................................................... 28 Structure ............................................................................................................................. 28 Program Memory Read-out Protection .............................................................................. 28 In-Circuit Programming (ICP) ............................................................................................. 29 In-Application Programming (IAP) ...................................................................................... 30 Register Description ........................................................................................................... 30 Flash Option Bytes ............................................................................................................. 31
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ST7FLCD1 Chapter 6
6.1
Clocks & Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Clock System ..................................................................................................................... 32
6.1.1 6.1.2 6.1.3 6.1.4 General Description ...........................................................................................................................32 Crystal Oscillator Mode ......................................................................................................................32 External Clock Mode ..........................................................................................................................32 Clock Signals .....................................................................................................................................33
6.2
Power Saving Modes ......................................................................................................... 33
6.2.1 6.2.2 6.2.3 6.2.4 HALT Mode ........................................................................................................................................33 WAIT Mode ........................................................................................................................................33 Exit from HALT and WAIT Modes ......................................................................................................33 Selected Peripherals Mode ................................................................................................................34
Chapter 7
7.1 7.2 7.3 7.4 7.5 7.6 7.7
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Introduction ........................................................................................................................ 35 Common Functional Description ........................................................................................ 36 Port A ................................................................................................................................. 37 Port B ................................................................................................................................. 39 Port C ................................................................................................................................. 40 Port D ................................................................................................................................. 41 Register Description ........................................................................................................... 42
Chapter 8
8.1 8.2 8.3 8.4
PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Introduction ........................................................................................................................ 43 Main Features .................................................................................................................... 43 Functional Description ........................................................................................................ 43 Register Description ........................................................................................................... 46
Chapter 9
9.1 9.2 9.3 9.4
8-bit Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Introduction ........................................................................................................................ 49 Main Features .................................................................................................................... 49 Functional Description ........................................................................................................ 49 Register Description ........................................................................................................... 50
Chapter 10
10.1 10.2 10.3 10.4 10.5
IC Single-Master Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Introduction ........................................................................................................................ 52 Main Features .................................................................................................................... 52 General Description ........................................................................................................... 52 Functional Description (Master Mode) ............................................................................... 54 Transfer Sequencing .......................................................................................................... 54
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10.5.1 10.5.2 Master Receiver .................................................................................................................................54 Master Transmitter .............................................................................................................................54
10.6
Register Description ........................................................................................................... 56
Chapter 11
11.1 11.2
Display Data Channel Interfaces (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Introduction ........................................................................................................................ 60 DDC Interface Features ..................................................................................................... 60
11.2.1 11.2.2 Hardware DDC2B Interface Features ................................................................................................60 DDC/CI Factory Interface Features ....................................................................................................60
11.3
Signal Description .............................................................................................................. 62
11.3.1 11.3.2 Serial Data (SDA) ..............................................................................................................................62 Serial Clock (SCL) .............................................................................................................................62
11.4
DDC Standard .................................................................................................................... 62
11.4.1 11.4.2 DDC2B Interface ................................................................................................................................62 Mode Description ...............................................................................................................................63
11.5 11.6 11.7
DDC/CI Factory Alignment Interface .................................................................................. 66
11.5.1 IC Modes ..........................................................................................................................................66
Transfer Sequencing .......................................................................................................... 68 Register Description ........................................................................................................... 69
Chapter 12
12.1 12.2 12.3 12.4 12.5 12.6
Watchdog Timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Introduction ........................................................................................................................ 75 Main Features .................................................................................................................... 75 Main Watchdog Counter .................................................................................................... 75 Lock-up Counter ................................................................................................................. 76 Interrupts ............................................................................................................................ 76 Register Description ........................................................................................................... 76
Chapter 13
13.1 13.2 13.3 13.4
8-bit Timer (TIMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Introduction ........................................................................................................................ 77 Main Features .................................................................................................................... 77 Functional Description ........................................................................................................ 77 Register Description ........................................................................................................... 78
Chapter 14
14.1 14.2 14.3
8-bit Timer with External Trigger (TIMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Introduction ........................................................................................................................ 80 Main Features .................................................................................................................... 80 Functional Description ........................................................................................................ 80
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ST7FLCD1 Chapter 15
15.1 15.2 15.3
Infrared Preprocessor (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Main Features .................................................................................................................... 83 Functional Description ........................................................................................................ 83 Register Description ........................................................................................................... 84
Chapter 16
16.1
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Register Description ........................................................................................................... 85
Chapter 17
17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Absolute Maximum Ratings .............................................................................................. 87 Power Considerations ........................................................................................................ 87 Thermal Characteristics .................................................................................................... 88 AC/DC Electrical Characteristics ........................................................................................ 88 Power On/Off Electrical Specifications ............................................................................... 90 8-bit Analog-to-Digital Converter ....................................................................................... 90 I2C/DDC Bus Electrical Specifications .............................................................................. 91 I2C/DDC Bus Timings ....................................................................................................... 91
Chapter 18 Chapter 19
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
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General Information
ST7FLCD1
1
1.1
General Information
Block Diagram
Figure 1: ST7FLCD1 Functional Diagram
5V GND
ST7FLCD1
60 KByte Flash 2 KByte RAM Power Management Port A PWM PA0 ... PA4 PWM0 ... PWM4 PA5 / PWM5 / BUZOUT PA6 / ITA / EXTRIG PA7 / ITB PB0 / AIN0 PB1 / AIN1 PB2 / AIN2 PB3 / AIN3 / IFR
Port B ADC
ADDRESS AND DATA BUS
VPP
LVD
IFR
RESET
Control 8-bit Core ALU
Port C ICD
PC0 / ICC_CLK PC1 / ICC_DATA
Watchdog Timer A
Port D IC Timer B OSCIN OSCOUT DDC2B DDC/CI A DDC2B DDC/CI B
OSC
PD0 / I2C_SCL PD1 / I2C_SDA PD2 / DDCA_SCL PD3 / DDCA_SDA PD4 / DDCB_SCL PD5 / DDCB_SDA PD6 PD7
1.2
Abbreviations
Abbreviation
ADC ALU CPU DDC DMA IC or IIC IAP ICC ICP ICT IFR Analog-to-Digital Converter Arithmetical and Logical Unit Central Processing Unit Display Data Channel Direct Memory Access Inter-Integrated Circuit bus In-Application Programming In-Circuit Communication In-Circuit Programming In-Circuit Testing Infrared Controller
Description
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ST7FLCD1
General Information
Abbreviation
IT LCD LVD MCU OSC PWM TIM WDG Interrupt Liquid Crystal Display Low Voltage Detector Microcontroller Unit Oscillator Pulse Width Modulator Timer Watchdog
Description
1.3
Reference Documents
Book: ST7 MCU Family Manual CD: MCU on CD Many libraries, software and applications notes are available. Ask your STMicroelectronics sales office, your local support or search the company web site at www.st.com
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General Information
ST7FLCD1
1.4
Pin Description
Figure 2: 28-pin Small Outline Package (SO28) Pinout
OSCOUT OSCIN RESET PB0/AIN0 PB1/AIN1 PB2/AIN2 PB3/AIN3/IFR PA0/PWM0 PA1/PWM1 PA2/PWM2 PA3/PWM3 PA4/PWM4 PA5/PWM5/BUZOUT PA6/ITA/EXTRIG
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD VSS VPP PC1/ICC_DATA PC0/ICC_CLK PD7 PD6 PD5/DDCB_SDA PD4/DDCB_SCL PD3/DDCA_SDA PD2/DDCA_SCL PD1/I2C_SDA PD0/I2C_SCL PA7/ITB
Table 1: 28-pin Small Outline Package (SO28) Pin Description (Sheet 1 of 2) Pin
1 2 3 4 5 6 7 8 9 10 11 12
Pin Name
OSCOUT OSCIN RESET PB0/AIN0 PB1/AIN1 PB2/AIN2 PB3/AIN3/IFR PA0/PWM0 PA1/PWM1 PA2/PWM2 PA3/PWM3 PA4/PWM4
Type
O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Oscillator Input
Description
Remark
Normal use at 24 MHz
Oscillator Output Reset Port B0 or ADC Analog Input 0 Port B1 or ADC Analog Input 1 Port B2 or ADC Analog Input 2 Port B3 or ADC Analog Input 3 or IFR Input Port A0 or PWM Output 0 Port A1 or PWM Output 1 Port A2 or PWM Output 2 Port A3 or PWM Output 3 Port A4 or PWM Output 4
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ST7FLCD1
General Information
Table 1: 28-pin Small Outline Package (SO28) Pin Description (Sheet 2 of 2)
Pin
13 14 15 16 17 18 19 20 21 22 23 24 25 26
Pin Name
PA5/PWM5/BUZOUT PA6/ITA/EXTRIG PA7/ITB PD0/I2C_SCL PD1/I2C_SDA PD2/DDCA_SCL PD3/DDCA_SDA PD4/DDCB_SCL PD5/DDCB_SDA PD6 PD7 PC0/ICC_CLK PC1/ICC_DATA VPP
Type
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PS
Description
Port A5 or PWM Output 5 or Buzzer Output Port A6 or Interrupt Input A or External Trigger Timer B Port A7 or Interrupt Input B Port D0 or IC Serial Bus Clock Port D1 or IC Serial Bus Data Port D2 or DDC A Serial Bus Clock Port D3 or DDC A Serial Bus Data Port D4 or DDC B Serial Bus Clock Port D5 or DDC B Serial Bus Data Port D6 Port D7 Port C0 or ICC Clock Port C1 or ICC Data Flash Programming Supply Voltage
Remark
Normal op. mode: 0 V, see Note 1 0V 5V
27 28
VSS VDD
PS PS
Ground Power Supply
1. This pin must be connected to a 10K pulldown resistor (refer to Section 1.5).
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General Information
ST7FLCD1
1.5
External Connections
Figure 3 shows the recommended external connections for the device. The VPP pin is only used for programming or erasing the Flash memory array, and must be tied to a 10 K pulldown resistor for normal operation. The 10 nF and 0.1 F decoupling capacitors on the power supply lines are a suggested EMC performance/cost tradeoff. The external RC reset network (including the mandatory 1K serial resistor) is intended to protect the device against parasitic resets, especially in noisy environments. Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up.
Figure 3: Recommended External Connections
VPP
10K
VDD
10nF
+
VDD
0.1F
VSS
VDD
4.7K 0.1F EXTERNAL RESET CIRCUIT 0.1F 1K
RESET
See Clocks Section Or configure unused I/O ports by software as input with pull-up
OSCIN OSCOUT
VDD
10K
Unused I/O
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ST7FLCD1
General Information
1.6
Memory Map
Figure 4: Program Memory Map 0000h HW Registers 003Fh 0040h
(See Note 1)
Short Addressing RAM (zero page) Stack 2 Kbytes RAM FF00h FFDFh
0100h 01FFh 0200h 0600h EDIDA EDIDB 083Fh 0840h 0FFFh 1000h 52 K 60 Kbytes FLASH SECTOR 2 E000h F000h 4K FFE0h Interrupt & Reset Vectors FFFFh
(See Note 3)
16-bit Addressing RAM
4K
SECTOR 1 SECTOR 0
(See Note 2)
Note:1. Refer to Table 2: Hardware Register Memory Map. 2. Area FF00h to FFDFh is reserved in the event of ICD use. (For more information, refer to Application Note 1581.) 3. Refer to Table 3: Interrupt Vector Map.
Table 2: Hardware Register Memory Map (Sheet 1 of 3) Address
0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h Port C Port B
Block
NAME MISC Port A
Register
NAMER MISCR PADR PADDR PBDR PBDDR PCDR PCDDR
Register Name
Circuit Name Register Miscellaneous Register Port A Data Register Port A Data Direction Register Port B Data Register Port B Data Direction Register Port C Data Register Port C Data Direction Register
Reset Status
00h 00h 00h 00h 00h 00h 00h 00h
Remarks
Read R/W R/W R/W R/W R/W R/W R/W
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General Information
Table 2: Hardware Register Memory Map (Sheet 2 of 3) Address
0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h DDC A FLASH Reserved WDG IC WDGCR I2CCR I2CSR I2CCCR I2CDR DDCCRA DDCSR1A DDCSR2A DDCOAR1A DDCOAR2A DDCDRA RESERVED DDCDCRA DDC2B A Control Register 00h Watchdog Control Register IC Control Register IC Status Register IC Clock Control Register IC Data Register DDC A Control Register DDC A Status 1 Register DDC A Status 2 Register DDC (7-bit) A Slave address 1 Register DDC (7-bit) A Slave address 2 Register DDC A Data Register 7Fh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h PWM INTERRUPT TIMA ADC
ST7FLCD1
Block
Port D
Register
PDDR PDDDR ADCDR ADCCSR ITRFRE TIMCSRA TIMCPRA PWMDCR0 PWMDCR1 PWMDCR2 PWMDCR3 PWMCRA PWMARRA PWMDCR4 PWMDCR5 PWMCRB PWMARRB FCSR
Register Name
Port D Data Register Port D Data Direction Register ADC Data Register ADC Control Status Register External Interrupt Register Timer Control Status Register Timer Counter Preload Register 8-bit PWM0 Duty Cycle Register 8-bit PWM1 Duty Cycle Register 8-bit PWM2 Duty Cycle Register 8-bit PWM3 Duty Cycle Register PWM[0...3] Control Register PWM[0...3] Auto Reload Register 8-bit PWM4 Duty Cycle Register 8-bit PWM5 Duty Cycle Register PWM[4...5] Control Register PWM[4...5] Auto Reload Register Flash Control/Status Register
Reset Status
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh 00h 00h 00h FFh 00h
Remarks
R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R R/W R/W R/W R R R/W R/W R/W
R/W
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ST7FLCD1
Table 2: Hardware Register Memory Map (Sheet 3 of 3) Address
0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah RESERVED TIMB IFR DM
General Information
Block
DDC B
Register
DDCCRB DDCSR1B DDCSR2B DDCOAR1B DDCOAR2B DDCDRB RESERVED DDCDCRB DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L IFRDR IFRCR TIMCSRB TIMCPRB
Register Name
DDC B Control Register DDC B Status 1 Register DDC B Status 2 Register DDC (7-bit) B Slave address 1 Register DDC (7-bit) B Slave address 2 Register DDC B Data Register
Reset Status
00h 00h 00h 00h 00h 00h
Remarks
R/W R R R/W R/W R/W
DDC2B B Control Register Debug Control Register Debug Status Register Debug Breakpoint 1 MSB Register Debug Breakpoint 1 LSB Register Debug Breakpoint 2 MSB Register Debug Breakpoint 2 LSB Register Counter Data Register Control Register Timer Control Status Register Timer Counter Preload Register
00h 00h 10h FFh FFh FFh FFh 00h 00h 00h 01h
R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W
Table 3: Interrupt Vector Map Vector Address
FFE0 to FFE1h FFE2 to FFE3h FFE4 to FFE5h FFE6 to FFE7h FFE8 to FFE9h FFEA to FFEBh FFEC to FFEDh FFEE to FFEFh FFF0 to FFF1h FFF2 to FFF3h FFF4 to FFF5h FFF6 to FFF7h FFF8 to FFF9h FFFA to FFFBh Not Used Timer A Overflow Interrupt Vector Timer B Overflow Interrupt Vector Not Used IC Interrupt Vector ITB Interrupt Vector ITA Interrupt Vector IFR Interrupt Vector Not Used DDC2B B Interrupt Vector DDC/CI B Interrupt Vector DDC2B A Interrupt Vector DDC/CI A Interrupt Vector Not Used Internal Interrupt Internal Interrupt Internal Interrupt Internal Interrupt Internal Interrupt External Interrupt External Interrupt Internal Interrupt Internal Interrupt Internal Interrupt
Description
Remarks
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General Information
Table 3: Interrupt Vector Map Vector Address
FFFC to FFFDh FFFE to FFFFh
ST7FLCD1
Description
Trap (Software) Interrupt Vector Reset Vector
Remarks
CPU Interrupt
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ST7FLCD1
Central Processing Unit (CPU)
2
Central Processing Unit (CPU)
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.
2.1
Main Features

Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer 8 MHz CPU internal frequency (9 MHz maximum) Wait and Halt Low Power modes Maskable hardware interrupts Non-maskable software interrupt
2.1.1
CPU Registers
The 6 CPU registers shown in Figure 5 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register that holds operands and results of arithmetic and logic calculations. It also manipulates data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a previous instruction (PRE) to indicate that next instruction refers to the Y register.) The Y register is not affected by interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of next instruction the CPU executes. The program counter consists of two 8-bit registers: PCL (Program Counter Low which is the LSB) PCH (Program Counter High which is the MSB).
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Central Processing Unit (CPU)
Figure 5: CPU Registers
ST7FLCD1
7 Reset Value = XXh 7 Reset Value = XXh 7
0
Accumulator
0
X Index Register
0
Y Index Register
Reset Value = XXh 15 PCH 8 7 PCL 0
Program Counter
Reset Value = Reset Vector @ FFFEh-FFFFh 7 111HI Reset Value = 15 8 0 NZC
Condition Code Register
111X1XXX 7 0
Stack Pointer
Reset Value = Stack Higher Address X = Undefined Value
CONDITION CODE REGISTER (CC)
Read/Write Reset Value: 111x1XXX
7
1 1 1 H I N Z
0 C
The 8-bit Condition Code register contains the interrupt mask and four flags resulting from the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: 1: No half carry has occurred. A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Note: Instruction Groups are defined in Table 5.
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Bit 3 = I Interrupt mask.
Central Processing Unit (CPU)
This bit is set by hardware by an interrupt or by software that disables all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: 1: Interrupts are enabled. Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Interrupts requested when the I bit is set are latched and processed when the I bit is cleared. By default an interrupt routine is not interruptible as the I bit is set by hardware when you enter it and reset by the IRET instruction at the end of interrupt routine. In case the I bit is cleared by software during the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: 1: The last operation result is positive or null. The last operation result is negative (i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: 1: The result of the last operation is different from zero. The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. Informs if an overflow or underflow occurred during the last arithmetic operation. 0: 1: No overflow or underflow has occurred. An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.
STACK POINTER (SP)
Read/Write Reset Value: 01 FFh
15 0 7
SP7 SP6 SP5 SP4 SP3 SP2 SP1
8 0 0 0 0 0 0 1 0 SP0
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Central Processing Unit (CPU)
ST7FLCD1
The Stack Pointer is a 16-bit register always pointing to the next free location in the stack. The pointer value increments when data is taken from the stack, it decrements once data is transferred into the stack (see Figure 6). Since the stack is 256 bytes deep, the most significant byte is forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack highest address. The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around the stack upper limit, without indicating a stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. You can directly manipulate the stack using PUSH and POP instructions. In case of interrupt, the PCL is stored at the first location pointed to by the SP. Other registers are then stored in the next locations as shown in Figure 6. When interrupt is received, the SP value decrements and the context is pushed to the stack. On return from interrupt, the SP value increments and the context is popped from the stack. A subroutine call and interrupt occupy two and five locations in the stack area respectively.
Figure 6: Stack Manipulation Example
Subroutine Call h Interrupt Event PUSH Y POP Y IRET RET or RSP
SP SP CC A X PCH PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL
SP PCH PCL SP
h
PCH PCL
Stack Higher Address = 01FFh Stack Lower Address = 0100h
Table 4: Instruction Set (Sheet 1 of 2) Bit 7
Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations LD PUSH INC CP AND
Bit 6
CLR POP DEC TNZ OR
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RSP
BCP XOR CPL NEG
18/95
ST7FLCD1
Table 4: Instruction Set (Sheet 2 of 2) Bit 7
Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Code Condition Flag modification BSET BTJT ADC SLL JRA JRXX TRAP SIM WFI RIM HALT SCF IRET RCF
Central Processing Unit (CPU)
Bit 6
BRES BTJF ADD SRL JRT
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SUB SRA JRF
SBC RLC JP
MUL RRC CALL SWAP CALLR SLA NOP RET
Table 5: Instruction Groups (Sheet 1 of 3) Mnemo
ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH
Description
Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if ext. interrupt = 1 Jump if ext. interrupt = 0 Jump if H = 1
Function/Example
A=A+M+C A=A+M A=AxM tst (A x M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1
DST
A A A A M M M M
SRC
M M M M
H
H H
I
N
N N N N
Z
Z Z Z Z
C
C C
C C
reg, M tst(Reg - M) A = FFH-A dec Y reset when WDG active Pop CC, A, X, PC inc X jp [TBL.w] reg, M H reg reg, M reg, M 0 I M
0 N N N
1 Z Z Z C 1
N N
Z Z
C
jrf *
H = 1?
19/95
Central Processing Unit (CPU)
Table 5: Instruction Groups (Sheet 2 of 3) Mnemo
JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT JRULE LD MUL NEG NOP OR POP
ST7FLCD1
Description
Jump if H = 0 Jump if I = 1 Jump if I = 0 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack
Function/Example
H = 0? I = 1? I = 0? N = 1? N = 0? Z = 1? Z = 0? C = 1? C = 0? Unsigned < Jump if unsigned > = Unsigned > Unsigned < = DST < = SRC X,A = X * A neg $10
DST
SRC
H
I
N
Z
C
reg, M A, X, Y reg, M
M, reg X, Y, A 0
N
Z 0
N
Z
C
A = A+M Pop reg Pop CC
A reg CC M
M M M reg, CC H I
N
Z
N
Z
C
PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB
Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Subtract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Subtraction
Push Y C=0
0
I=0 C < = DST < = C C = > DST = > C S = Max allowed A = A-M-C C=1 I=1 C < = DST < = 0 C < = DST < = 0 0 = > DST = > C DST7 = > DST = > C A = A-M reg, M reg, M reg, M reg, M A M A M reg, M reg, M
0 N N Z Z C C
N
Z
C 1
1 N N 0 N N Z Z Z Z Z C C C C C
20/95
ST7FLCD1
Central Processing Unit (CPU)
Table 5: Instruction Groups (Sheet 3 of 3)
Mnemo
SWAP TNZ TRAP WFI XOR
Description
SWAP nibbles Test for Neg & Zero Software trap Wait for Interrupt Exclusive OR
Function/Example
DST[7..4] < = > DST[3..0] TNZ LBL1 Software interrupt
DST
reg, M
SRC
H
I
N
N N
Z
Z Z
C
1 0
A = A XOR M
A
M
N
Z
21/95
Reset
ST7FLCD1
3
Reset
The Reset procedure provides an orderly software start-up or is used to exit Low Power modes. Three reset modes are provided: 1. Low Voltage Detector reset, 2. Watchdog or Illegal Opcode Access reset, 3. External Reset using the RESET pin. At reset, the reset vector is fetched from addresses FFFEh and FFFFh and loaded into the PC (the program is executed starting at this point). Internal circuitry provides a 4096 CPU clock cycle delay as soon as the oscillator becomes active.
3.1
Low Voltage Detector and Watchdog Reset
The Low Voltage Detector generates a reset when:

VDD is above VTRM, VDD is below VTRH when VDD is rising, VDD is below VTRL when VDD is falling (Figure 7)
Figure 7: Low Voltage Detector
VDD VTRH
VTRL
VTRM
RESET
Note:
Typical hysteresis (VTRH-VTRL) of 50 mV. This circuitry is active only when VDD is higher than VTRM. During the Low Voltage Detector reset, the RESET pin is held low, permitting the MCU to reset other devices. During a Watchdog reset, the RESET pin is pulled low permitting the MCU to reset other devices as during a Low Voltage reset (Figure 8). The reset cycle is pulled low for 500 ns (typical).
22/95
ST7FLCD1
Figure 8: Reset Generation Diagram
Reset
RESLVD VDD Low Voltage Detector Reset RESET Watchdog Illegal Opcode Access External Reset
3.2
Watchdog or Illegal Opcode Access Reset
For more information about the Watchdog, please refer to Section 12: Watchdog Timer (WDG) An Illegal Opcode reset occurs if the MCU attempts to execute a code that does not match a valid ST7 instruction.
3.3
External Reset
The external reset is an active low input signal applied to the RESET pin of the MCU. As shown in Figure 9, the RESET signal must remain low for a minimum of 1 s. An internal Schmitt trigger and filter provided at the RESET pin improve noise immunity.
3.4
Reset Procedure
At power-up, the MCU follows the sequence described in Figure 9.
Figure 9: Reset Timing Diagram
tDDR VDD
OSCIN tOXOV fCPU PC RESET FFFE FFFF
4096 CPU Clock Cycle Delay
Watchdog Reset
Note:
Refer to Electrical Characteristics for values of tDDR, tOXOV, VTRH, VTRL and VTRM.
23/95
Interrupts
ST7FLCD1
4
Interrupts
There are two different methods to interrupt the ST7: 1. a maskable hardware interrupt as listed in Table 7 2. a non-maskable software interrupt (TRAP). The Interrupt Processing flowchart is shown in Figure 10. Only enabled maskable interrupts are serviced. However, disabled interrupts are latched and processed. For an interrupt to be serviced, the PC, X, A and CC registers are saved onto the stack, the interrupt mask (bit I of the Condition Code Register) is set to prevent additional interrupts. The Y register is not automatically saved. The PC is then loaded with the interrupt vector and the interrupt service routine runs (refer to Table 7 for vector addresses) and ends with the IRET instruction. At the IRET instruction, the contents of the registers are recovered from the stack and normal processing resumes. Note that the I bit is then cleared if the corresponding bit stored in the stack is zero. Though many interrupts can be run simultaneously, an order of priority is defined (see Table 7). The RESET pin has the highest priority. If the I bit is set, only the TRAP interrupt is enabled. All interrupts allow the processor to exit the WAIT Low Power mode.
4.1
Software
The software interrupt is the executable TRAP instruction. The interrupt is recognized when the TRAP instruction is executed, regardless of the state of the I bit. When an interrupt is recognized, it is serviced according to flowchart described in Figure 10.
Note:
During ICC communication, the TRAP interrupt is reserved.
4.2
External Interrupts (ITA, ITB)
The ITA (PA6), ITB (PA7) pins generate an interrupt when a falling or rising edge occurs on these pins. These interrupts are enabled by the ITAITE and ITBITE bits (respectively) in the ITRFRE register, provided that the I bit from the CC register is reset. Each external interrupt has its own interrupt vector.
4.3
Peripheral Interrupts
The various peripheral devices with interrupts include both Display Data Channels (DDC A and DDC B), the Infrared Controller (IFR), two 8-bit timers (Timer A and Timer B) and the IC interface. Different peripheral interrupt flags fetch an interrupt if the I bit from the CC register is reset and the corresponding Enable bit is set. If any of these conditions is not fulfilled, the interrupt is latched but not serviced, thus remaining pending.
4.4
Processing
Interrupt flags are located in the status register. The Enable bits are in the control register. When an enabled interrupt occurs, normal processing is suspended at the end of the current instruction execution. It is then serviced according to the flowchart shown in Figure 10.
24/95
ST7FLCD1
Interrupts
The general sequence for clearing an interrupt is an access to the status register when the flag is set followed by a read or write of the associated register. Note that the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be enabled) will therefore be lost if the Clear sequence is executed.
Figure 10: Interrupt Processing Flowchart
From Reset
Y TRAP?
N
N I Bit set?
Y
N Fetch Next Instruction Interrupt?
Y N Execute Instruction IRET? Stack PC, X, A, CC Set I Bit Load PC from Interrupt Vector
Y
Restore PC, X, A, CC from Stack This clears I bit by default
25/95
Interrupts
ST7FLCD1
4.5
Register Description
Table 6: External Interrupt Register Map
Address
000Ch
Reset
00h R/W
Register
ITRFRE
bit 7
0
bit 6
0
bit 5
ITB EDGE
bit 4
bit 3
bit 2
ITA EDGE
bit 1
ITALAT
bit 0
ITAITE
ITBLAT ITBITE
EXTERNAL INTERRUPT REGISTER (ITRFRE) Read/Write Reset value:00h
7
0
6
0
5
ITBEDGE
4
ITBLAT
3
ITBITE
2
ITAEDGE
1
ITALAT
0
ITAITE
Bits [7:6] = Reserved. Forced by hardware to 0. Bit 5 = ITBEDGE Interrupt B Edge Selection. This bit is set and cleared by software. 0 1 Falling edge selected on ITB (default) Rising edge selected on ITB
Bit 4 = ITBLAT Falling or Rising Edge Detector Latch. This bit is set by hardware, when a falling or rising edge, depending on the sensitivity, occurs on the ITB/PA7 pin. An interrupt is generated if ITBITE = 1. It must be cleared by software. 0 1 No edge detected on ITB (default) Edge detected on ITB
Bit 3 = ITBITE ITB Interrupt Enable. This bit is set and cleared by software. 0 1 ITB interrupt disabled (default) ITB interrupt enabled
Bit 2 = ITAEDGE Interrupt A Edge Selection. This bit is set and cleared by software. 0 1 Falling edge selected on ITA (default) Rising edge selected on ITA
Bit 1 = ITALAT Falling or Rising Edge Detector Latch. This bit is set by hardware when a falling or a rising edge, depending on the sensitivity, occurs on the ITA/PA6 pin. An interrupt is generated if ITAITE = 1. It must be cleared by software. 0 1 No edge detected on ITA (default) Edge detected on ITA
Bit 0 = ITAITE ITA Interrupt Enable. This bit is set and cleared by software. 0 1 ITA interrupt disabled (default) ITA interrupt enabled
26/95
ST7FLCD1
Table 7: Interrupt Mapping Source Block
RESET TRAP Not used DDC/CI A DDC2B A DDC Interrupt End of communication Interrupt End of download Interrupt DDC/CI B DDC2B B DDC Interrupt End of communication Interrupt End of download Interrupt Not used IFR Port A bit 6 Port A bit 7 IC IFR Interrupt External Interrupt ITA External Interrupt ITB IC Peripheral Interrupts IFRCR ITRFRE ITRFRE I2CSR1 I2CSR2 Not used TIMB TIMA Not used Timer B overflow Timer A overflow TIMCSRB TIMCSRA TOF TOF Yes Yes FFE6h to FFE7h FFE4h to FFE5h FFE2h to FFE3h FFE0h to FFE1h ITALAT ITBLAT ** Yes Yes Yes DDCSR1B DDCSR2B DDCDCRB DDCSR1A DDCSR2A DDCDCRA ** ENDCF EDF ** ENDCF EDF Yes Yes Yes Yes Yes Yes Reset Software
Interrupts
Description
Register
N/A N/A N/A N/A
Flag
Maskable
No No
Vector Address
FFFEh to FFFFh FFFCh to FFFDh FFFAh to FFFBh FFF8h to FFF9h FFF6h to FFF7h FFF6h to FFF7h FFF4h to FFF5h FFF2h to FFF3h FFF2h to FFF3h FFF0h to FFF1h FFEEh to FFEFh FFECh to FFEDh FFEAh to FFEBh FFE8h to FFE9h
Priority Order
Highest Priority
Lowest Priority
** Many flags can cause an interrupt, see peripheral interrupt status register description.
27/95
Flash Program Memory
ST7FLCD1
5
5.1
Flash Program Memory
Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by-byte basis using an external Vpp supply. HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or onboard using In-Circuit Programming (ICP) and In-Application Programming (IAP). The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.
5.2
Main Features
Three Flash programming modes: - Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. - ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. - IAP (In-Application programming). In this mode, all sectors except Sector 0 can be programmed or erased without removing the device from the application board and when the application is running.

ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Read-out protection against piracy Register Access Security System (RASS) to prevent accidental programming or erasing.
5.3
Structure
The Flash memory is organized in sectors and can be used for both code and data storage. Depending on the overall size of the Flash memory in the microcontroller device, three user sectors are available. Each sector is independently erasable. Thus, having to completely erase the entire Flash memory is not necessary when only partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 11). They are mapped in the upper part of the ST7 addressing space. The reset and interrupt vectors are located in Sector 0 (F000h to FFFFh).
5.4
Program Memory Read-out Protection
The read-out protection is enabled through an option bit. When this option is selected, the programs and data stored in the program memory (Flash or ROM) are protected against read-out piracy (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the Option Byte, the entire program memory is first automatically erased. Refer to the Section 5.8 for more details.
28/95
ST7FLCD1
Flash Program Memory
Figure 11: Memory Map and Sector Address 60 KBytes 1000h DV Flash Memory Size
Sector 2 DFFFh EFFFh FFFFh 52 KBytes Sector 1 Sector 0
5.5
In-Circuit Programming (ICP)
To perform In-Circuit Programming (ICP), the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations or selection of serial communication interface for downloading). When using a STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user only needs to implement the ICP hardware interface on the application board (see Figure 12). For more details on the pin locations, refer to the device pin description. ICP needs between 4 and 6 pins to be connected to the programming tool. Depending on the desired type of programming, these pins are:

RESET: device reset VSS: device power supply ground ICC_CLK: ICC output serial clock pin ICC_DATA: ICC input serial data pin VPP: programming voltage VDD: application board power supply
CAUTION:
1. If the ICC_CLK or ICC_DATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in progress, the ICC_CLK and ICC_DATA pins are not available for the application. If they are used as inputs by the application, an isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5 mA at high level (push-pull output or pull-up resistor (< 1 k)). A Schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with a resistor (> 1 k) or a reset management IC with open-drain output and pull-up resistor
29/95
Flash Program Memory
ST7FLCD1
(> 1 k) , no additional components are needed. In any case, the user must ensure that an external reset is not generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.
Figure 12: Typical ICP Interface
Programming Tool ICC Connector ICC Cable Application Board Optional (See Note 3) ICC Connector HE10 Male-type Connector 9 10 7 8 5 6 3 4 1 2 Application Reset Source See Note 2 10k Application Power Supply CL2 CL1 See Note 1 See Note 1 RESET ICCDATA OSCOUT ICCCLK OSCIN VPP VDD VSS Application I/O
ST7
5.6
In-Application Programming (IAP)
This mode uses a Boot Loader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully-controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from either DDC interface and program it in the Flash memory. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
5.7
Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write Reset Value: 0000 0000 (00h)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
30/95
ST7FLCD1
Flash Program Memory
This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations. For details on customizing Flash programming methods and In-Circuit Testing, refer to the ST7 Flash Programming Reference Manual and relevant Application Notes.
5.8
Flash Option Bytes
Each device is available for production in user programmable versions (Flash) as well as in factory coded versions (ROM). Flash devices are shipped to customers with a default content (FFh), while ROM factory coded parts contain the code supplied by the customer. This implies that Flash devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured. The option bytes are used to select the hardware configuration of the microcontroller. They have no address in the memory map and can be accessed only in programming mode (for example, using a standard ST7 programming tool). The default content of the Flash is fixed to FFh. To program directly the Flash devices using ICP, Flash devices are shipped to customers with the internal RC clock source enabled. In masked ROM devices, the option bytes are fixed in hardware by the ROM code. Static Option Byte 1
7 6 5 4 3 2 1 0
FMP_R Default 1 1 1 1 1 1 1 1
OPT0 = FMP_R Flash memory read-out protection This option indicates if the user Flash memory is protected against read-out piracy. This protection is based on a read and write protection of the memory in Test and ICP modes. Erasing the option bytes when the FMP_R option is selected causes the entire user memory to be erased first. 0 1 Read-out protection enabled Read-out protection disabled
Static Option Byte 2
7 6 5 4 3 2 1 0
Default
1
1
1
1
1
1
1
1
31/95
Clocks & Low Power Modes
ST7FLCD1
6
6.1
6.1.1
Clocks & Low Power Modes
Clock System
General Description
The device requires a certain number of clock signals in order to operate. All clock signals are derived from the root clock signal CkXT provided at the output of the "OSC" circuit (refer to Figure 13). If a crystal oscillator or ceramic resonator is applied on pins OSCIN and OSCOUT, the OSC operates in a crystal-controlled oscillator mode. An external clock signal can also be applied on the OSCIN pin, putting the OSC in external clock mode operation. The block diagram in Figure 13 shows the basic configuration of the clock system.
Figure 13: Main Clock Generation
CkXT
CkXT
OSC
OSC
VSS
OSCIN
VSS
OSCOUT
OSCIN
External Clock
Crystal Oscillator Mode
External Clock Mode
6.1.2
Crystal Oscillator Mode
In this mode, the root clock is generated by the on-chip oscillator controlled by an external parallel fundamental-mode crystal oscillator or a ceramic resonator. General design precautions must be followed to ensure maximum stability. Foot capacitors CL1 and CL2 must be adapted to match the crystal oscillator or ceramic resonator. A 100-k resistor is internally connected between pins OSCIN and OSCOUT.
Note:
If a Murata ceramic resonator is to be used, Murata recommends their CERALOCK(R) CSTCGseries (fundamental type) with built-in CL1 and CL2 capacitors, such as: - CSTCG24M0V51-R0 for 24-MHz external, 8-MHz internal clock operation - CSTCG27M0V51-R0 for 27-MHz external, 9-MHz internal clock operation No additional external capacitor is therefore needed with either model of this series.
6.1.3
External Clock Mode
In this mode, an external clock is provided on pin OSCIN, while pin OSCOUT is left open. The signal is internally buffered before feeding the subsequent stages. There is the same emphasis on stability of the external clock as in Crystal Oscillator mode.
32/95
OSCOUT
ST7FLCD1 6.1.4 Clock Signals
Clocks & Low Power Modes
The root clock is divided by a factor of 3 to obtain the CPU clock (fCPU).
Figure 14: Clock System Diagram
OSCOUT OSCIN
OSC
:3
fCPU and other peripherals
6.2
Power Saving Modes
The MCU offers the possibility to decrease power consumption at any time by software operation.
6.2.1
HALT Mode
HALT mode is the MCU lowest power consumption mode. Also, HALT mode also stops the oscillator stage completely which is the most critical condition (the MCU cannot recover by itself). For this reason, HALT mode is not compatible with the watchdog protection.
Table 8: Watchdog Compatibility Watchdog
Enabled Disabled
Executing HALT Instruction
Generates an immediate reset Puts the MCU in HALT mode
6.2.2
WAIT Mode
This is a low power consumption mode. The WFI instruction sets the MCU in WAIT mode. The internal clock remains active but all CPU processing is stopped. However, all other peripherals still run.
Note:
In WAIT mode, DMA (DDC A and DDC B) accesses are possible.
6.2.3
Exit from HALT and WAIT Modes
The MCU can exit HALT mode upon reception of an external interrupt on pins ITA or ITB. The oscillator is then turned back on and a stabilizing time is necessary before releasing CPU operation (4096 CPU clock cycles). After this delay, the CPU continues operation according to the cause of its release, either by servicing an interrupt or by fetching the reset vector in case of reset. During WAIT mode, the I bit from the Condition Code register is cleared, enabling all interrupts. This leads the MCU to exit WAIT mode, the corresponding interrupt vector tois fetched, the interrupt routine is executed and normal processing resumes. A reset causes the program counter to fetch the reset vector. Processing starts as with a normal reset.
33/95
Clocks & Low Power Modes
Figure 15: WAIT Flow Chart
MCU WFI instruction
ST7FLCD1
Oscillator: ON Periph. clock: ON CPU clock: ON I bit: Cleared
N Reset N Interrupt Y Oscillator: ON Periph. clock: ON CPU clock: ON I bit: Set Y
Note:
Before servicing an interrupt, the CC register is pushed on the stack. The I bit is set during the interrupt routine and cleared when the CC register is popped.
If reset 4096 CPU Clock Cycles Delay
Fetch Reset, Vector or Service Interrupt
MDP Run Mode
6.2.4
Selected Peripherals Mode
Certain peripherals have an "On/Off "bit to disconnect the block (or part of it) and decrease MCU power consumption.
Table 9: Peripheral Modes Bits
PORTs ADC PWMi DDC WDG I2C PxDDi ADON OEi PE, DDC2BPE WGDA PE
Register
PxDDR ADCSR PWMCRx DDCCR, DDCDCR WDGCR I2CCR
Comment
Cut the output function pad (input mode) Cut analog consumption and clock Cut the pad consumption Cut the output reset
Default at Reset
OFF OFF OFF OFF OFF OFF
34/95
ST7FLCD1
I/O Ports
7
7.1
I/O Ports
Introduction
I/O ports are used to transfer data through digital inputs and outputs. For specific pins, I/O ports allow the input of analog signals or the Input/Output of alternate signals for on-chip peripherals (DDC, Timer, etc.). Each pin can be independently programmed as digital input or output. Each pin can be an analog input when an analog switch is connected to the Analog-to-Digital Converter (ADC).
Figure 16: I/O Pin Critical Circuit
Alternate enable Alternate 1 output 0 DR Latch Data Bus VDD
P-Buffer (if required)
Alternate enable
Common Analog Rail
DDR Latch PAD Analog Enable (ADC) DDR SEL Analog Switch (if required)
N-Buffer DR SEL 1 0 Alternate Enable VSS Digital Enable
Alternate Input
Note:1. This is a typical I/O pin configuration. Each port is customized with a specific configuration in order to handle certain functions.
35/95
I/O Ports
Table 10: I/O Pin Function DDR
0 1
ST7FLCD1
Mode
Input Output
7.2
Common Functional Description
Each port pin of the I/O Ports can be individually configured as either an input or an output, under software control. Each bit of Data Direction Register (DDR) corresponds to an I/O pin of the associated port. This corresponding bit must be set to configure its associated pin as an output and must be cleared to configure its associated pin as an input (see Note 1 on page 35). The Data Direction Registers can be read and written. A typical I/O circuit is shown in Figure 16. Any write to an I/O port updates the port data register even when configured as an input. Any read of an I/O port returns either the data latched in the port data register (pins configured as output) or the value of the I/O pins (pins configured as an input). Remark: When there is no I/O pin inside an I/O port, the returned value is logic 0 (pin configured as an input). At reset, all DDR registers are cleared, configuring all I/O ports as inputs. Data Registers (DR) are also cleared at reset. Input mode When DDR = 0, the corresponding I/O is configured in Input mode. In this case, the output buffer is switched off and the state of the I/O is readable through the Data Register address, coming directly from the TTL Schmitt Trigger output and not from the Data Register output. Output mode When DDR = 1, the corresponding I/O is configured in Output mode. In this case, the output buffer is activated according to the Data Register content. A read operation is directly performed from the Data Register output. Analog input Each I/O can be used as an analog input by adding an analog switch driven by the ADC. The I/O must be configured as an input before using it as analog input. When the analog channel is selected by the ADC, the analog value is directly driven to the ADC through an analog switch. Alternate mode A signal coming from an on-chip peripheral is output on the I/O which is then automatically configured in output mode. The signal coming from the peripheral enables the alternate signal to be output. A signal coming from an I/O can be input to an on-chip peripheral.
36/95
ST7FLCD1
I/O Ports
An alternate Input must first be configured in Input mode (DDR = 0). Alternate and I/O Input configurations are identical without pull-up. The signal to be input in the peripheral is taken after the TTL Schmitt trigger when available. The I/O state is readable as in Input mode by addressing the corresponding I/O Data Register.
7.3
Port A
Each Port A bit can be defined as an Input line or as a Push-Pull. It can be also be used to output the PWM outputs.
Table 11: Port A Description I/O Port A Input1
PA0 PA1 PA2 PA3 PA4 PA5 with Weak Pull-up PA6 PA7 with Weak Pull-up with Weak Pull-up Push-pull Push-pull with Weak Pull-up with Weak Pull-up with Weak Pull-up with Weak Pull-up with Weak Pull-up with Weak Pull-up Push-pull BUZOUT External Interrupt ITA External Interrupt ITB BUZEN = 1 (Timer A)2 see External Interrupt Register Description
Alternate Function Output Signal
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5
Condition
OE0 = 1 (PWM) OE1 = 1 (PWM) OE2 = 1 (PWM) OE3 = 1 (PWM) OE4 = 1 (PWM) OE5 = 1 (PWM)
Push-pull Push-pull Push-pull Push-pull Push-pull
1. Reset state. 2. If both PWM5 and BUZOUT are enabled, BUZOUT has priority over PWM5.
Outputs PA4 and PA5 may also be configured as high current (8 mA) push-pull outputs by means of the MISCR register. MISCELLANEOUS REGISTER (MISCR) Read/Write Reset value:00h
7
0
6
0
5
0
4
0
3
0
2
PA5OVD
1
PA4OVD
0
0
Bits [7:3] = Reserved. Forced by hardware to 0. Bit 2 = PA5OVD Port A Bit 5 Overdrive This bit is set and cleared by software. It is used only if Port A Bit 5 is set as an output (PADDR, PWM5 or BUZOUT). It has no effect if set as an input. 0 1 2 mA Push-pull Output 8 mA Push-pull Output
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I/O Ports
ST7FLCD1
Bit 1 = PA4OVD Port A Bit 4 Overdrive This bit is set and cleared by software. It is used only if Port A Bit 4 is set as an output (PADDR or PWM4). It has no effect if set as an input. 0 1 2 mA Push-pull Output 8 mA Push-pull Output
Bit 0 = Reserved. Must be cleared by software.
Figure 17: Port A [5:0] Alternate Output Enable 1 Alternate Output Enable Alternate Output 0 DR latch DDR latch
VDD
Data Bus
DDR SEL
DR SEL
1 0 TTL Schmitt Trigger
PAD
Figure 18: Port A [7:6] Alternate Output Enable 1 Alternate Output Enable Alternate Output 0 DR latch DDR latch DDR SEL
VDD
Data Bus
DR SEL
1 0 PAD TTL Schmitt Trigger
alternate input
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ST7FLCD1
I/O Ports
7.4
Port B
Each Port B bit can be used as the Analog source to the Analog-to-Digital Converter. Only one I/O line at a time must be configured as an analog input. Pins levels are all limited to 5V. All unused I/O lines should be tied to an appropriate logic level (either VDD or VSS). Since ADC and microprocessor are on the same chip and if high precision is required, the user should not switch heavily loaded signals during conversion. Such switching will affect the supply voltages used as analog references. The conversion accuracy depends on the quality of power supplies (VDD and VSS). The user must take special care to ensure that a well regulated reference voltage is present on pins VDD and VSS (power supply variations must be less than 3.3 V/ms). This implies, in particular, that a suitable decoupling capacitor is used at pin VDD.
Table 12: Port B Description I/O Alternate Function Output
Push-pull Push-pull Push-pull Push-pull
PORT B Input1
PB0 PB1 PB2 PB3 with Weak Pull-up when Digital Input with Weak Pull-up when Digital Input with Weak Pull-up when Digital Input with Weak Pull-up when Digital Input
Signal
Analog Input (ADC):AIN0 Analog Input (ADC) AIN1 Analog Input (ADC) AIN2 Analog Input (ADC) AIN3/ IFR
Condition
ADON = 1 & CH[1:0] = 00 (ADCCSR) ADON = 1 & CH[1:0] = 01 (ADCCSR) ADON = 1 & CH[1:0] = 10 (ADCCSR) ADON = 1 & CH[1:0] = 11 (ADCCSR) for analog input. In this case, IFR is disabled.
1. Reset state.
Figure 19: Port B [2:0]
DATA BUS
Analog enable (ADC) DR latch DDR latch Analog enable (ADC) Analog switch
VDD
Common Analog Rail
DDR SEL
DR SEL
1 0 TTL Schmitt Trigger
PAD
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I/O Ports
Figure 20: Port B [3] Analog enable ( ADC) DATA BUS VDD DR Latch DR Latch Analog enable (ADC) Analog switch
ST7FLCD1
Common Analog Rail
DDR SEL
DR SEL
1 0 TTL Schmitt Trigger
PAD
Alternate Input
7.5
Port C
The available port pins of port C may be used as general purpose I/Os.
Table 13: Port C Description I/O PORT C Input1
PC0 PC1 Without Pull-up Without Pull-up
Alternate Function Output
Open-drain Open-drain
Signal
Condition
1. Reset state.
For more information, refer to the relevant Application Notes. Note: These 2 pins are reserved for ICC use during ICC communication. If ICC is not used at all, they can be used as general purpose I/Os.
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ST7FLCD1
I/O Ports
Figure 21: Port C
DR Latch DDR Latch DATA BUS DDR SEL
DR SEL
1 0 TTL Schmitt Trigger VSS
VDD
7.6
Port D
The alternate functions are:

the I/O pins of the on-chip IC SCLI & SDAI for PD[1:0], the I/O pins of the on-chip DDC A SCLD & SDAD for PD[3:2], the I/O pins of the on-chip DDC B SCLD & SDAD for PD[5:4] input and output on PD[7:6].
Table 14: Port D Description I/O Alternate Function Output
Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain
PORT D Input1
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Without Pull-up Without Pull-up Without Pull-up Without Pull-up Without Pull-up Without Pull-up Without Pull-up Without Pull-up
Signal
SCLI (input with TTL Schmitt trigger or Open-drain output) SDAI (input with TTL Schmitt trigger or Open-drain output) SCLD A (input with TTL Schmitt trigger or Open-drain output) SDAD A (input with TTL Schmitt trigger or Open-drain output) SCLD B (input with TTL Schmitt trigger or Open-drain output) SDAD B (input with TTL Schmitt trigger or Open-drain output)
Condition
IC enable IC enable DDC A enable DDC A enable DDC B enable DDC B enable
1. Reset state.
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I/O Ports
Figure 22: Port D
ST7FLCD1
Alternate Output Enable Alternate output 1
DR Latch
0
Alternate Output Enable
DDR Latch DATA BUS
DDR SEL
DR SEL
1 0 VSS
TTL Schmitt Trigger
Alternate Input
7.7
Register Description
DATA REGISTERS (PXDR) DATA DIRECTION REGISTERS (PXDDR) (`x' corresponds to the I/O pin of the associated port. In Input mode, the value is 00h by default).I
Table 15: I/O Port Register Map Address
0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h
Reset
00h 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W
Register
PADR PADDR PBDR PBDDR PCDR PCDDR PDDR PDDDR
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PADR[7:0] PADDR[7:0] PBDR[7:0] PBDDR[7:0] PCDR[7:0] PCDDR[7:0] PDDR[7:0] PDDDR[7:0]
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ST7FLCD1
PWM Generator
8
8.1
PWM Generator
Introduction
This PWM on-chip peripheral consists of two blocks, each one with its own 8-bit auto-reload counter. The first block (Block A) outputs up to 4 separate PWM signals at the same frequency. The second block (Block B) outputs up to 2 separate PWM signals at another frequency. Each PWM output may be enabled or disabled independently of the other. The polarity of each PWM output may also be independently set.
8.2
Main Features

2 distinct programmable frequencies between 31.250 kHz and 8 MHz. Resolution: tCPU
8.3
Functional Description
The free-running 8-bit counter is fed by the CPU clock and increments on every rising edge of the clock signal. When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARR register. Each PWMx output signal can be enabled independently using the corresponding OEx bit in the PWM control register (PWMCR). When this bit is set, the corresponding I/O is configured as an output push-pull alternate function. PWM[3:0] all have the same frequency which is controlled by counter period A and the ARRA register value. fPWMA = fCOUNTERA / (256-ARRA) PWM[5:4] all have the same frequency which is controlled by counter period B and the ARRB register value. fPWMB = fCOUNTERB / (256-ARRB) When a counter overflow occurs, the PWMx pin level is toggled depending on the corresponding OPx (output polarity) bit in the PWMCR register. When the counter reaches the value contained in one of the Duty Cycle registers (DCRIx), the corresponding PWMx pin level is restored. This DCRIx register can not be accessed directly, it is loaded from the Duty Cycle register (DCRx) at each overflow of the counter. This double buffering method prevents glitch generation when changing the duty cycle on the fly. Note that the reload values will also affect the value and the resolution of the duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the DCRx register must be greater than or equal to the contents of the ARR register. The maximum available resolution for duty cycle is 1/(256-ARR).
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PWM Generator
Figure 23: PWM Block Diagram
PWMCR OEx OPx DCRIx Register 8 LOAD PWMx Port Alternate Function Polarity Control COMPARE DCRx Register
ST7FLCD1
8 ARR Register fCPU 8 8-bit Counter
Figure 24: PWM Generation
Counter 255 DCR Overflow Overflow Overflow
ARR
t
PWM Output
t
tCPU x(256 - ARR)
Figure 25: PWM Generation
Counter fCPU ARR DCR PWM Output
FC
FD
FE
FF
FC
FD
FE
FF ... ... ... ... ... ... ...
FC
FD
FE
FF
FC
FD
FC FD FC
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ST7FLCD1
Equations:
Table 16: Pulse WIdth in tCPU Pulse WIdth in tCPU
DCR ARR DCR = ARR DCR < ARR DCR - ARR + 1 1 0 (Output will not toggle)
PWM Generator
Duty Cycle =
DCR + 1 256 - ARR
This Pulse Width modulated signal must be filtered, using an external RC network placed as close as possible to the associated pin. This provides an analog voltage proportional to the average charge through the external capacitor. Thus for a higher mark/space ratio (High time much greater than Low time) the average output voltage is higher. The external components of the RC network should be selected for the filtering level required for control of the system variable.
Table 17: 8-bit PWM Ripple after Filtering CEXT
470 nF 1 F 4.7 F
VRIPPLE
60 mV 27 mV 6 mV
VRIPPLE =
(1 - e 1/(2 x CEXT x REXT x fPWM))2 |1 - e
1/(C
EXT
x VDD
xR
EXT
xf
PWM
)
|
With: REXT = 1 k fPWM = fCPU / (256 - ARR) fCPU = 8 MHz VDD = 5 V Worst case, PWM Duty Cycle 50%
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PWM Generator
Figure 26: PWM Simplified Voltage Output after Filtering
ST7FLCD1
V DD PWMOUT 0V V DD Output Voltage VRIPPLE (mV) VOUTAVG
0V "Charge" "Discharge" "Charge" "Discharge"
V
DD
PWMOUT 0V V DD V RIPPLE (mV) Output Voltage 0V "Charge" "Discharge" "Charge" "Discharge"
V OUTAVG
8.4
Register Description
Each PWM is associated with two control bits (OEx and OPx) and a control register (DCRx).
Table 18: PWM Register Map Address
000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h
Reset
00h 00h 00h 00h 00h FFh 00h 00h 00h FFh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Register
PWMDCR0 PWMDCR1 PWMDCR2 PWMDCR3 PWMCRA PWMARRA PWMDCR4 PWMDCR5 PWMCRB PWMARRB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DCR0[7:0] DCR1[7:0] DCR2[7:0] DCR3[7:0] OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0
ARRA[7:0] DCR4[7:0] DCR5[7:0] 0 0 OE5 OE4 0 0 OP5 OP4
ARRB[7:0]
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ST7FLCD1
DUTY CYCLE REGISTERS (PWMDCRx) Read/Write Reset Value 0000 0000 (00h)
7
DC7
PWM Generator
6
DC6
5
DC5
4
DC4
3
DC3
2
DC2
1
DC1
0
DC0
Bits [7:0] = DC[7:0] Duty Cycle Data These bits are set and cleared by software. A DCRx register is associated with the DCRix register of each PWM channel to determine the second edge location of the PWM signal (the first edge location is common to all 4 channels and given by the ARR register). These DCR registers allow the duty cycle to be set independently for each PWM channel. CONTROL REGISTER A (PWMCRA) Read/Write Reset Value: 0000 0000 (00h)
7
OE3
6
OE2
5
OE1
4
OE0
3
OP3
2
OP2
1
OP1
0
OP0
Bits [7:4] = OE [3:0] PWM Output Enable. These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin. 0 1 the PWM pin is a general I/O. the PWM pin is driven by the PWM peripheral.
Bits [3:0] = OP[3:0] PWM Output Polarity. These bits are set and cleared by software. They independently select the polarity of the 4 PWM output signals. 0 1 Note: positive polarity. negative polarity.
When an OPx bit is modified, the PWMx output signal is immediately updated. AUTO-RELOAD REGISTER A (PWMARRA) Read/Write Reset Value: 1111 1111(FFh)
7
AR73
6
AR6
5
AR5
4
AR4
3
AR3
2
AR2
1
AR1
0
AR0
Bits [7:0] = AR[7:0] Counter Auto-Reload Data. These bits are set and cleared by software. They are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. Writing in this register reload the PWM counter to ARR A value. At the same time, the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register.
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PWM Generator
ST7FLCD1
This register adjusts the PWM frequency (setting the PWM duty cycle resolution) for outputs PWM[3:0]. CONTROL REGISTER B (PWMCRB) Read/Write Reset Value: 0000 0000 (00h)
7
0
6
0
5
OE5
4
OE4
3
0
2
0
1
OP5
0
OP4
Bits [7:6] = Reserved. Forced by hardware to 0. Bits [5:4] = OE[5:4] PWM Output Enable. These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin. 0 1 the PWM pin is a general I/O. the PWM pin is driven by the PWM peripheral.
Bits [3:2] = Reserved. Forced by hardware to 0. Bit [1:0] = OP[5:4] PWM Output Polarity. These bits are set and cleared by software. They independently select the polarity of the 4 PWM output signals. 0 1 Note: positive polarity. negative polarity.
When an OPx bit is modified, the PWMx output signal is immediately reversed. AUTO-RELOAD REGISTER B (PWMARRB) Read/Write Reset Value: 1111 1111 (FFh)
7
AR73
6
AR6
5
AR5
4
AR4
3
AR3
2
AR2
1
AR1
0
AR0
Bits [7:0] = AR [7:0] Counter Auto-Reload Data. These bits are set and cleared by software. They are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. Writing in this register reload the PWM counter to ARR B value. At the same time, the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register. This register adjusts the PWM frequency (by setting the PWM duty cycle resolution) for outputs PWM[5:4].
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ST7FLCD1
8-bit Analog-to-Digital Converter (ADC)
9
9.1
8-bit Analog-to-Digital Converter (ADC)
Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal Sample and Hold circuitry. This peripheral has up to 4 multiplexed analog input channels (refer to device pin out description) that allows the peripheral to convert the analog voltage levels from up to 4 different sources. The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control/Status Register.
Figure 27: ADC Block Diagram
COCO
-
ADON
-
-
-
CH1
CH0
(Control Status Register) CSR AIN0 AIN1 AIN2 AIN3
Analog Mux
Sample & Hold
Analog to Digital Converter
fCPU / 4
AD7 AD6 AD5
AD4 AD3 AD2 AD1 AD0 (Data Register) DR
9.2
Main Features

8-bit conversion Up to 4 channels with multiplexed input Linear successive approximation Data register (DR) which contains the results Conversion complete status flag On/Off bit (to reduce power consumption)
9.3
Functional Description
The high and low level reference voltages are VDD and VSS, respectively. Consequently, conversion accuracy is degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines.
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8-bit Analog-to-Digital Converter (ADC) Characteristics
ST7FLCD1
The conversion is monotonic, the result never decreases or increases if the analog input does not also drecrease or increase. If the input voltage is greater than or equal to VDD (voltage reference high), the results are equal to FFh (full scale) without overflow indication. If the input voltage is less than or equal to VSS (voltage reference low), the results are equal to 00h. The A/D converter is linear, the digital result of the conversion is given by the formula:
Digital result = 255 x Input Voltage Supply Voltage
The conversion accuracy is described in Section 17: Electrical Characteristics. When the A/D converter is continuously "ON", the conversion time is 16 ADC clock cycles which corresponds to 64 CPU clock cycles. The internal circuitry is in auto-calibration during the conversion cycle. This process prevents offset drifts. Still, calibration cycles are required at start-up or after any A/D converter re-start.
Procedure
Refer to the CSR and SR registers in Section 9.4: Register Description for the bit definitions. At start-up, the A/D converter is OFF (ADON bit equal to `0'). Prior to using the A/D converter, the analog input ports must be configured as inputs. Refer to Section 7: I/O Ports. Using these pins as analog inputs does not affect the ability to read the port as a logic input. Then, the ADON bit must be set to 1. As internal AD circuitry starts calibration, it is mandatory to respect the stabilizing time (several tens of milliseconds) prior to using A/D results. In the CSR register, bits CH1 to CH0 select the analog channel to be converted (see Table 19). These bits are set and cleared by software. The A/D converter performs a continuous conversion of the selected channel. When a conversion is complete, the COCO bit is set by hardware, but no interrupt is generated. The result is written in the DR register. Reading the DR result register resets the COCO bit. Writing to the CSR register aborts the current conversion, the COCO bit is reset and a new conversion is started. Note: Resetting the ADON bit disables the A/D converter. Thus, power consumption is reduced when no conversions are needed. The A/D converter is not affected by WAIT mode.
9.4
Register Description
Table 19: ADC Register Map Address
000Ah 000Bh
Reset
00h 00h R R/W
Register
ADCDR ADCCSR
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AD[7:0]
COCO
0
ADON
0
0
0
CH[1:0]
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ST7FLCD1
CONTROL/STATUS REGISTER (ADCCSR) Read/Write Reset Value: (00h)
7
COCO
8-bit Analog-to-Digital Converter (ADC)
6
0
5
ADON
4
0
3
0
2
0
1
CH1
0
CH0
Bit 7 = COCO Conversion Complete This bit is set by hardware. It is cleared by software by reading the result in the DR register or writing to the CSR register. 0 1 Conversion is not complete (default) Conversion can be read from the DR register.
Bit 6 = Reserved. This bit must be cleared by software. Bit 5 = ADON A/D converter On This bit is set and cleared by software. 0 1 Note: A/D converter is switched off (default) A/D converter is switched on
Remember that the ADC needs time to stabilize after the ADON bit is set. Bits [4:2] = Reserved. Forced to 0 by hardware. Bits [1:0] = CH[1:0] Channel Selection. These bits are set and cleared by software. They select the analog input to be converted.
Table 20: Channel Selection Pin
AIN0 (Default) AIN1 AIN2 AIN3
CH1
0 0 1 1
CH0
0 1 0 1
DATA REGISTER (ADCDR) Read Only Reset Value: (00h)
7
AD7
6
AD6
5
AD5
4
AD4
3
AD3
2
AD2
1
AD1
0
AD0
Bits [7:0] = AD[7:0] Analog Converted Value. This register contains the converted analog value in the range 00h to FFh. Reading this register resets the COCO flag.
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IC Single-Master Bus Interface
ST7FLCD1
10
10.1
IC Single-Master Bus Interface
Introduction
The IC Bus Interface serves as an interface between the microcontroller and the serial IC bus. It provides single-master functions, and controls all IC bus-specific sequencing, protocol and timing. It supports Fast IC mode (400 kHz) and up to 800 kHz for certain applications.
10.2
Main Features

Parallel / IC bus protocol converter Interrupt generation Standard IC mode/Fast IC mode (up to 800 kHz for certain applications) 7-bit Addressing End of byte transmission flag Transmitter /Receiver flag Clock generation
IC Single Master Mode

10.3
General Description
In addition to receiving and transmitting data, this interface converts data from serial to parallel format and vice versa, using either an interrupt or a polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the IC bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard IC bus and a Fast IC bus. This selection is made by software. Mode Selection The interface can operate in the two following modes: 1. Master transmitter/receiver, 2. Idle (default). The interface automatically switches from Idle to Master mode after it generates a START condition and from Master to Idle mode after it generates a STOP condition. Communication Flow The interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the start condition is the address byte. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 28. Acknowledge is enabled and disabled by software. The speed of the IC interface is selected as Standard (0 to 100 kHz) and Fast IC (100 to 400 kHz) and up to 800 kHz for certain applications.
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ST7FLCD1
Figure 28: IC Bus Protocol
IC Single-Master Bus Interface
SDA MSB SCL 1 Start Condition 2 8
ACK
9 Stop Condition
SDA/SCL Line Control
Transmitter mode: The interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register. Receiver mode: The interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. The SCL frequency (fSCL) is controlled by a programmable clock divider which depends on the IC bus mode. When the IC cell is enabled, the SDA and SCL ports must be configured as a floating open-drain output or a floating input. In this case, the value of the external pull-up resistor used depends on the application. When the IC cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
Figure 29: IC Interface Block Diagram
Data Register (DR)
SDAI SDA Data Control Data Shift Register
SCLI SCL
Clock Control
Clock Control Register (CCR)
Control Register (CR) Control Logic Status Register (SR) Interrupt
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IC Single-Master Bus Interface
ST7FLCD1
10.4
Functional Description (Master Mode)
By default, the IC interface operates in Idle mode (M/IDL bit is cleared) except when it initiates a transmit or receive sequence. To switch from default Idle mode to Master mode a Start condition must be generated. Setting the START bit causes the interface to switch to Master mode (M/IDL bit set) and generates a Start condition. Once the Start condition is sent, the EVF and SB bits are set by hardware and an interrupt is generated if the ITE bit is set. Then the master waits for a read of the SR register followed by a write in the DR register with the Slave address byte, holding the SCL line low (EV1). Then the slave address byte is sent to the SDA line via the internal shift register. After completion of this transfer (and the reception of an acknowledge from the slave if the ACK bit is set), the EVF bit is set by hardware and an interrupt is generated if the ITE bit is set. Then the master waits for a read of the SR register followed by a write in the CR register (for example set PE bit), holding the SCL line low (EV2). Next the master must enter Receiver or Transmitter mode.
10.5
Transfer Sequencing
10.5.1 Master Receiver
Following the address transmission and after SR and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:

an Acknowledge pulse if the ACK bit is set EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR register followed by a read of the DR register, holding the SCL line low (EV3). To close the communication, before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface automatically returns to Idle mode (M/IDL bit cleared). Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte.
10.5.2 Master Transmitter
Following the address transmission and after SR register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR register followed by a write in the DR register, holding the SCL line low (EV4). When the acknowledge bit is received, the interface sets the EVF and BTF bits with an interrupt if the ITE bit is set. To close the communication, after writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface automatically returns to Idle mode (M/IDL bit cleared).
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ST7FLCD1
Error Case:
IC Single-Master Bus Interface
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit. Note: The SCL line is not held low if AF = 1.
Figure 30: Transfer Sequencing
Master Receiver:
S EV1 Address A EV2 Data1 A EV3 Data2 A ..... EV3 EV3-1 EV3-2 Data N-1 A Data N NA P
Master Transmitter:
S EV1 Address A EV2 EV4 Data1 A EV4 Data2 A ..... EV4 EV4 DataN A P
Slave Not Responding:
S EV1 Address NA EV2-1 P
Legend: S = Start, P = Stop, A = Acknowledge, NA = Non-acknowledge EVx = Event (with interrupt if ITE = 1)
EV1: EV2:
EVF = 1, SB = 1, cleared by reading the SR register followed by writing to the DR register. EVF = 1, cleared by reading the SR register followed by writing to the CR register (for example PE = 1).
EV2-1: EVF = 1, AF = 1, cleared by reading the SR register followed by writing STOP = 1 in the CR register. EV3: EVF = 1, BTF = 1, cleared by reading the SR register followed by reading the DR register.
EV3-1: Same as EV3, but ACK bit in CR register must be cleared before reading the DR register in order to send a NAK pulse after the "Data N" byte. EV3-2: Same as EV3, but STOP = 1 must be written in the CR register. EV4: EVF = 1, BTF = 1, cleared by reading the SR register followed by writing to the DR register.
Figure 31: Event Flags and Interrupt Generation
BTF SB AF
ITE
Interrupt
EVF * * EVF can also be set by EV6 or an error from the SR2 register.
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IC Single-Master Bus Interface
ST7FLCD1
10.6
Register Description
Table 21: IC Register Map
Addr. Reset (Hex.)
001Ch 001Dh 001Eh 001Fh 00h 00h 00h 00h
R/W
R/W Read only R/W R/W
Register
I2CCR I2CSR I2CCCR I2CDR
Bit 7
00 EVF FM/SM
Bit 6
Bit 5
PE
Bit 4
0 0
Bit 3
START BTF
Bit 2
ACK 0
Bit 1
STOP M/IDL
Bit 0
ITE SB
AF FILTOFF
TRA
CC[5:0] DR7[:0]
IC CONTROL REGISTER (I2CCR) Read / Write Reset Value: 0000 0000 (00h)
7
0
6
0
5
PE
4
0
3
START
2
ACK
1
STOP
0
ITE
Bits [7:6] = Reserved. Forced to 0 by hardware. Bit 5 = PE Peripheral enable. This bit is set and cleared by software. 0 1 Note: Peripheral disabled Master capability
When PE = 0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released when PE = 0. When PE = 1, the corresponding I/O pins are selected by hardware as alternate functions. To enable the IC interface, write the CR register TWICE with PE = 1 as the first write only activates the interface (only PE is set). Bit 4 = Reserved. Forced to 0 by hardware Bit 3 = START Generation of a Start condition. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE = 0) or when the Start condition is sent (with interrupt generation if ITE = 1). In Master mode: 0 1 0 1 No start generation Repeated start generation No start generation Start generation when the bus is free
In Idle mode:
Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software. Cleared by hardware when the interface is disabled (PE = 0). 0 1 No acknowledge returned Acknowledge returned after an address byte or a data byte is received
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Bit 1 = STOP Generation of a Stop condition. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE = 0) or when the Stop condition is sent. In Master mode only: 0 1 No stop generation Stop generation after the current byte transfer or after the current Start condition is sent.
Bit 0 = ITE Interrupt enable. This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE = 0). 0 1 Interrupt disabled Interrupt enabled
IC STATUS REGISTER (I2CSR) Read Only Reset Value: 0000 0000 (00h)
7
EVF
6
AF
5
TRA
4
0
3
BTF
2
0
1
M/IDL
0
SB
Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event occurs. It is cleared by software by reading the SR register in case of error event or as described in Section 10.5: Transfer Sequencing. It is also cleared by hardware when the interface is disabled (PE = 0). 0 1 No event One of the following events has occurred: BTF = 1 (Byte received or transmitted) SB = 1 (Start condition generated) AF = 1 (No acknowledge received after byte transmission if ACK = 1) Address byte successfully transmitted. Bit 6 = AF Acknowledge Failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE = 1. It is cleared by software by reading the SR register or by hardware when the interface is disabled (PE = 0). The SCL line is not held low when AF = 1. 0 1 No acknowledge failure Acknowledge failure
Bit 5 = TRA Transmitter/Receiver. When BTF is set, TRA = 1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware when the interface is disabled (PE = 0). 0 1 Data byte received (if BTF = 1) Data byte transmitted
Bit 4 = Reserved. Forced to 0 by hardware. Bit 3 = BTF Byte transfer finished. This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt
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generation if ITE = 1. It is cleared by software by reading the SR register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE = 0). Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV2 event (See Section 10.5: Transfer Sequencing). BTF is cleared by reading SR register followed by writing the next byte in DR register. Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK = 1. BTF is cleared by reading SR register followed by reading the byte from DR register. The SCL line is held low when BTF = 1. 0 1 Byte transfer not done Byte transfer succeeded
Bit 2 = Reserved. Forced to 0 by hardware. Bit 1 = M/IDL Master/Idle. This bit is set by hardware when the interface is in Master mode (writing START = 1). It is cleared by hardware after a Stop condition on the bus. It is also cleared by hardware when the interface is disabled (PE = 0). 0 1 Idle mode Master mode
Bit 0 = SB Start bit. This bit is set by hardware when a Start condition is generated (following a write START = 1). An interrupt is generated if ITE = 1. It is cleared by software by reading the SR register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE = 0). 0 1 No Start condition Start condition generated
IC CLOCK CONTROL REGISTER (I2CCCR) Read / Write Reset Value: 0000 0000 (00h)
7
FM/SM
6
FILTOFF
5
CC5
4
CC4
3
CC3
2
CC2
1
CC1
0
CC0
Bit 7 = FM/SM Fast/Standard IC mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE = 0). 0 1 Fast IC mode Standard IC mode
Bit 6 = FILTOFF Filter Off. This bit is set and cleared by software, it is not taken into account in the EMU version and is considered as always set to 1 (inactive filter). When set, it disables the filter of the IC pads in order to achieve speeds of over 400 kHz on a shortlength IC bus (at the user's responsibility). Such high frequencies are computed with the Fast mode formula given below.
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Bits [5:0] = CC[5:0] 6-bit clock divider. These bits select the speed of the bus (fSCL) depending on the IC mode. They are not cleared when the interface is disabled (PE = 0). The value of the 6-bit clock divider, CC[5:0] 03h Fast mode (FM/SM = 0): fSCL > 100 kHz fSCL = fCPU/([2x([CC5...CC0]+3)]+1) Standard mode (FM/SM = 1): fSCL 100 kHz fSCL = fCPU/(3x([CC5...CC0]+3)) Note: The programmed fSCL speed assumes that there is no load on the SCL and SDA lines.
IC DATA REGISTER (I2CDR) Read / Write Reset Value: 0000 0000 (00h)
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
Bits [7:0] = D[7:0] 8-bit Data Register. These bits contain the byte to be received or transmitted on the bus. Transmitter mode: Bytes are automatically transmitted when the software writes to the DR register. Receiver mode: The first data byte is automatically received in the DR register using the least significant bit of the address. Then, the subsequent data bytes are received one-by-one after reading the DR register.
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11
11.1
Display Data Channel Interfaces (DDC)
Introduction
The DDC (Display Data Channel) bus interfaces are mainly used by the monitor to identify itself to the video controller, by the monitor manufacturer to perform factory alignment, and by the user to adjust the monitor's parameters. Both DDC interfaces consist of:
A fully hardware-implemented interface, supporting DDC2B (VESA specification 3.0 compliant). It accesses the ST7 on-chip memory directly through a built-in DMA engine. A second interface, supporting the slave IC functions for handling DDC/CI mode (DDC2Bi), factory alignment, HDCP, Enhanced DDC (EDDC) or other addresses by software.
Each DDC interface has its own dedicated DMA area in RAM. In the event of concurrent DMA accesses, the DDC A cell has priority over the DDC B cell.
11.2
DDC Interface Features
11.2.1 Hardware DDC2B Interface Features

Full hardware support for DDC2B communications (VESA specification version 3) Hardware detection of DDC2B addresses A0h/A1h Separate mapping of EDID version 1: Base (128 bytes) and Extended (128 bytes) Support for error recovery mechanism Detection of misplaced Start and Stop conditions Random and Sequential IC byte read modes DMA transfer from any memory location and to RAM Automatic memory address increment End of data downloading flag, end of communication flag and interrupt capability
11.2.2 DDC/CI Factory Interface Features
General IC Features

Parallel bus /IC protocol converter Interrupt generation Standard IC mode 7-bit Addressing
IC Slave Features

IC bus busy flag Start bit detection flag Detection of misplaced Start or Stop condition Transfer problem detection Address Matched detection 2 Programmable Address detection and/or Hardware detection of DDC/CI addresses (6Eh/ 6Fh) End of byte transmission flag Transmitter/Receiver flag Stop condition Detection
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Figure 32: DDC Interface Overview
SDA
SDAD
IC Slave Interface (DDC/CI - Factory Alignment)
SCL
SCLD Hardware DDC2B Interface
Figure 33: DDC Interface Block Diagram
DDC2B Control Register (DCR) Address Low Address High DMA Controller
Address/Data Control Logic SDAD Data Control Data Shift Register SCLD DDC2B Control Logic DDC2B (for Monitor Identification) DDC2B Interrupt
Data Register (DR)
Data Control
Data Shift Register
Comparator
Own Address Register 1 (OAR1) Own Address Register 2 (OAR2)
Hardware Address
DDC/CI Factory Control Register (CR) Status Register 1 (SR1) Status Register 2 (SR2) DDC/CI (for Monitor Adjustment and Control)
Control Logic
DDC/CI Interrupt
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11.3
Signal Description
11.3.1 Serial Data (SDA)
The SDA bidirectional pin is used to transfer data in and out of the device. An external pull-up resistor must be connected to the SDA line. Its value depends on the load of the line and the transfer rate.
11.3.2 Serial Clock (SCL)
The SCL input pin is used to synchronize all data in and out of the device when in IC bidirectional mode. An external pull-up resistor must be connected to the SCL line. Its value depends on the load of the line and the transfer rate. Note: When the DDC2B and DDC/CI Factory Interfaces are disabled (HWPE bit = 0 in the DCR register and PE bit = 0 in the CR register), the SDA and SCL pins revert to being standard I/O pins.
11.4
DDC Standard
The DDC standard is divided into several data transfer protocols: DDC2B, DDC/CI and other slave communication standards (HDCP, E-DDC, etc.). For DDC2B, refer to the "VESA DDC Standard v3.0" specification. For DDC/CI refer to the "VESA DDC Commands Interface v1.0" DDC2B is a unidirectional channel from display to host. The host computer uses base-level IC commands to read the EDID data from the display which is always in Slave mode. DDC/CI is a bidirectional channel between the host computer and the display. The DDC/CI offers a display control interface based on IC bus. Only the DDC2Bi interface is supported (and not the DDC2B+ or DDC2AB interfaces).
11.4.1 DDC2B Interface
The DDC2B Interface acts as an I/O interface between a DDC bus and the MCU memory. In addition to receiving and transmitting serial data, this interface directly transfers parallel data to and from memory using a DMA engine, only halting CPU activity for 2 clock cycles during each byte transfer. The interface supports the following by hardware:

DDC2B communication protocol write operations into RAM read operations from RAM
In DDC2B mode, it operates in IC Slave mode. Device addresses A0h/A1h are recognized. EDID version 1 is used. The Write and Read operations allow the EDID data to be downloaded during factory alignment (for example). Writing to the memory by the DMA engine is inhibited by the WP bit in the DCR register. A write of the last data structure byte sets a flag and may be programmed to generate an interrupt request. The Data address (sub-address) is either the second byte of write transfers or is pointed to by the internal address counter which automatically increments after each byte transfer. The physical address mapping of the data structure is fixed by hardware in a dedicated RAM area (see Table 24:
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EDID DMA Pointer Configuration).
Display Data Channel Interfaces (DDC)
11.4.2 Mode Description
DDC2B Mode: The DDC2B Interface enters DDC2B mode from the initial state if the software sets the HWPE bit. Once in DDC2B mode, the Interface always acts as a slave following the protocol described in Figure 34. The DDC2B Interface continuously monitors the SDA and SCL lines for a START condition and will not respond (no acknowledge) until one is found. A STOP condition at the end of a Read command (after a NACK) forces the stand-by state. A STOP condition at the end of a Write command triggers the internal DMA write cycle. The Interface samples the SDA line on the rising edge of the SCL signal and outputs data on the falling edge of the SCL signal. In any case, the SDA line can only change when the SCL line is low.
Figure 34: DDC2B Protocol Example
SDA SCL Ack Start A0h Device Slave Address Legend: Ack Ack Ack Data1 DataN Stop Start A1h 00h Data Address Device Slave 128 / 256 bytes EDID Address Nack Stop
Bold = data / control signal from host Italics = data / control signal from display
Figure 35: DDC1/2B Operation Flowchart
Wait for HWPE = 1
HWPE bit = 0
DMA Low Pointer Address = 0
Received valid Device Address? Y Send Acknowledge Respond to Command
N DDC2B Mode
EDID Data structure mapping: An internal address pointer defines the memory location being addressed.
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It defines the 256-byte block within the RAM address space containing the data structure. The LSB is loaded with the data address sent by the master after a write Device Address. It defines the byte within the data structure currently addressed. It is reset upon entry into the DDC2B mode.
Figure 36: Mapping of DDC2B Data Structure
Basic EDID v1 FFFFh
Extended EDID v1 (if present) FFFFh
256 bytes
256 bytes
128-byte Data Structure
128-byte Data Structure
LSB : 00h -> 7Fh
LSB : 80h -> FFh 15 Addr Pointer in RAM
87 MSB LSB
0
0000h A0h/A1h
0000h A0h/A1h
Note: Refer to Table 23 for RAM address mapping.
Write Operation Once the DDC2B Interface has acknowledged a write transfer request, i.e. a Device Address with RW = 0, it waits for a data address. When the latter is received, it is acknowledged and loaded into the LSB. Then, the master may send any number of data bytes that are all acknowledged by the DDC2B Interface. The data bytes are written in RAM if the WP bit = 0 in the DCR register, otherwise the RAM location is not modified. Write operations are always performed in RAM and therefore do not delay DDC transfers. Meanwhile, concurrent software execution is halted for 2 clock cycles.
Figure 37: Write Sequence
Addr. Pointer
XXXXh DEV ADDR
ADDR
ADDR + 1
ADDR + n -1 ADDR + n
SDA Start R/W ACK
Data Address ACK
Data IN 1 ACK
Data IN 2 ACK
Data IN n ACK STOP
Read Operations
All read operations consist of retrieving the data pointed to by an internal address counter which is initialized by a dummy write and which increments with any read. The DDC2B Interface always waits for an acknowledge during the 9th bit-time. If the master does not pull the SDA line low during this bit-time, the DDC2B Interface ends the transfer and switches to a stand-by state. Current address read: After generating a START condition the master sends a read device address (RW = 1). The DDC2B Interface acknowledges this and outputs the data byte pointed to by the internal address pointer which subsequently increments. The master must NOT acknowledge this byte and must terminate the transfer with a STOP condition.
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Random address read: The master performs a dummy write to load the data address into the pointer LSB. Then the master sends a RESTART condition followed by a read Device Address (RW = 1). Sequential address read: This mode is similar to the current and random address reads, except that the master DOES acknowledge the data byte for the DDC2B Interface to output the next byte in sequence. To terminate the read operation the master must NOT acknowledge the last data byte and must generate a STOP condition. The data output are issued from consecutive memory addresses. End of communication: Upon a detection of NACK or STOP conditions at the end of a read transfer, the bit ENDCF is set and an interrupt is generated if ENDCE is set.
Figure 38: Read Sequences
Current Address Read Addr. Pointer ADDR DEV ADDR SDA START R/W ACK DATA OUT NO ACK STOP ADDR + 1
or
ENDCF flag is set
Random Address Read Addr. Pointer XXXXh DEV ADDR SDA START R/W ACK DATA ADDR. ACK RESTART R/W ACK ADDR DEV ADDR DATA OUT NO ACK
or
ADDR + 1
Sequential Address Read Addr. Pointer ADDR DEV ADDR SDA START R/W ACK DATA OUT 1 ACK DATA OUT 2 ACK DATA OUT n NO ACK ADDR + 1 ADDR + n -1
ENDCF flag is set
ADDR + n
or ENDCF flag is set
STOP
STOP
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ST7FLCD1
After each byte transfer, the internal address counter automatically increments. If the counter is pointing to the top of the structure, it rolls over to the bottom since the increment is performed only on the 7 or 8 LSBs of the pointer depending on the selected data structure size. It rolls over from 7Fh to 00h or from FFh to 80h depending on the MSB of the last data address received. Then after that last byte has been effectively written or read in RAM at LSB address 7Fh or FFh, the EDF flag is set and an interrupt is generated if EDE is set. The transfer is terminated by the master generating a STOP condition.
11.5
DDC/CI Factory Alignment Interface
Refer to the CR, SR1 and SR2 registers in Section 11.7: Register Description for the bit definitions. The DDC/CI interface works as an I/O interface between the microcontroller and the DDC2Bi, HDCP, E-DDC or Factory alignment protocols. It receives and transmits data in Slave IC mode using an interrupt or polled handshaking. The interface is connected to the IC bus through a data pin (SDAD) and a clock pin (SCLD) configured as an open-drain output. The DDC/CI interface has five internal register locations. Two of them are used to initialize the interface: 1. 2 Own Address Registers OAR1 and OAR2 2. Control register CR The following four registers are used during data transmission/reception: 1. Data Register DR 2. Control Register CR 3. Status Register 1 SR1 4. Status Register 2 SR2 The interface decodes an IC or DDC2Bi address stored by software in either OAR register and/or the DDC/CI address (6Eh/6Fh) as its default hardware address. After a reset, the interface is disabled.
11.5.1 IC Modes
The interface operates in Slave Transmitter/Receiver modes. The master generates both Start and Stop conditions. The IC clock (SCL) is always received by the interface from a master, but the interface is able to stretch the clock line. The interface can recognize its two programmable addresses (7-bit) and its default hardware address (DDC/CI address: 6Eh/6Fh). The DDC/CI address detection may be enabled or disabled by software. It never recognizes the Start byte (01h) whatever its own address is. Slave mode As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register where it is compared to the programmable addresses or to the DDC/CI address (if selected by software). Address not matched: the interface ignores it and waits for another Start condition. Address matched: the following events occur in sequence:
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Acknowledge pulse is generated if the ACK bit is set. EVF and ADSL bits are set. An interrupt is generated if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see EV1 in Section 11.6: Transfer Sequencing). Next, the DR register must be read to determine from the least significant bit if the slave must enter Receiver or Transmitter mode. Slave Receiver Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte, the following events occur in sequence:

an Acknowledge pulse is generated if the ACK bit is set. the EVF and BTF bits are set. an interrupt is generated if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see EV2 in Section 11.6: Transfer Sequencing). Slave Transmitter Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register. The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see EV3 in Section 11.6: Transfer Sequencing). When the acknowledge pulse is received:

the EVF and BTF bits are set. an interrupt is generated if the ITE bit is set.
Closing Slave Communication After the last data byte is transferred, a Stop Condition is generated by the master. The interface detects this condition and in this case:

the EVF and STOPF bits are set. an interrupt is generated if the ITE bit is set.
Then the interface waits for a read of the SR2 register (see EV4 in Section 11.6: Transfer Sequencing). Error Cases BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the BERR bits are set and an interrupt is generated if the ITE bit is set. If it is a Stop condition, then the interface discards the data, releases the lines and waits for another Start condition. If it is a Start condition, then the interface discards the data and waits for the next slave address on the bus. AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set and an interrupt is generated if the ITE bit is set. Note: In both cases, the SCL line is not held low. However, the SDA line can remain low due to possible `0' bits transmitted last. It is then necessary to release both lines by software.
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Display Data Channel Interfaces (DDC)
How to Release the SDA / SCL Lines
ST7FLCD1
Set and subsequently clear the STOP bit when BTF is set. The SDA/SCL lines are released after the transfer of the current byte. Other Events ADSL: Detection of a Start condition after an acknowledge time-slot. The state machine is reset and starts a new process. The ADSL bit is set and an interrupt is generated if the ITE bit is set. The SCL line is stretched low. STOPF: Detection of a Stop condition after an acknowledge time-slot. The state machine is reset. Then the STOPF flag is set and an interrupt is generated if the ITE bit is set.
11.6
Transfer Sequencing
Slave Receiver
S Address A EV1 Data1 A EV2 Data2 A ..... EV2 EV2 EV4 DataN A P
Slave Transmitter
S Address A EV1 EV3 Data1 A EV3 Data2 A ..... EV3 EV3-1 EV4 DataN NA P
Legend: S = Start, P = Stop, A = Acknowledge, NA = Non-acknowledge and EVx = Event (with interrupt if ITE = 1) EV1: EVF = 1, ADSL = 1, cleared by reading register SR1. EV2: EVF = 1, BTF = 1, cleared by reading register SR1 followed by reading DR register. EV3: EVF = 1, BTF = 1, cleared by reading register SR1 followed by writing DR register. EV3-1: EVF = 1, AF = 1 and BTF = 1, AF is cleared by reading register SR2, BTF is cleared by releasing the lines (write STOP = 1, STOP = 0 in register CR) or by writing to register DR (DR = FFh). Note: If the lines are released by STOP = 1, STOP = 0, the subsequent EV4 is not seen. EV4: EVF = 1, STOPF = 1, cleared by reading register SR2.
Figure 39: Event Flags and Interrupt Generation
ITE BTF ADSL AF STOPF BERR Interrupt
EVF
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11.7
Register Description
Table 22: DDCA Register Map
Address Reset
0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 00h 00h 00h 00h 00h 00h 00h 00h R/W R R
Register
DDCCRA DDCSR1A DDCSR2A
Bit 7
0 EVF 0
Bit 6
0 0 0
Bit 5
PE TRA 0
Bit 4
DDCCIEN BUSY AF ADD[7:1] ADD[7:1]
Bit 3
0 BTF STOPF
Bit 2
ACK ADSL 0
Bit 1
STOP 0 BERR
Bit 0
ITE 0 DDCIF 0 0
R/W DDCOAR1A R/W DDCOAR2A R/W R/W R/W DDCDCRA 0 0 ENDCF DDCDRA
DR[7:0] Reserved ENDCE EDF EDE WP DDC2BPE
Table 23: DDCB Register Map Address Reset
0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 00h 00h 00h 00h 00h 00h 00h 00h R/W R R
Register
DDCCRB DDCSR1B DDCSR2B
Bit 7
0 EVF 0
Bit 6
0 0 0
Bit 5
PE TRA 0
Bit 4
DDCCIEN BUSY AF ADD[7:1] ADD[7:1]
Bit 3
0 BTF STOPF
Bit 2
ACK ADSL 0
Bit 1
STOP 0 BERR
Bit 0
ITE 0 DDCIF 0 0
R/W DDCOAR1B R/W DDCOAR2B R/W R/W R/W DDCDCRB 0 0 ENDCF DDCDRB
DR[7:0] Reserved ENDCE EDF EDE WP DDC2BPE
Table 24: EDID DMA Pointer Configuration Cell
DDCA DDCB
Basic EDID
600h to 67Fh 700h to 77Fh
Extended EDID
680h to 6FFh 780h to 7FFh
DDC CONTROL REGISTER (DDCCR) Read / Write Reset Value: 0000 0000 (00h)
7
0
6
0
5
PE
4
DDCCIEN
3
0
2
ACK
1
STOP
0
ITE
Bits [7:6] = Reserved. Forced to 0 by hardware.
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Bit 5 = PE DDC/CI Peripheral enable. This bit is set and cleared by software. 0 1 Note: Peripheral disabled Peripheral enabled
ST7FLCD1
When PE = 0, all the bits of the CR, SR1 and SR2 registers are reset. All outputs are released when PE = 0 When PE = 1, the corresponding I/O pins are selected by hardware as alternate functions. To enable the IC interface, write the CR register TWICE with PE = 1 as the first write only activates the interface (only PE is set). Bit 4 = DDCCIEN DDC/CI address detection enabled. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE = 0). The 6Eh/6Fh DDC/CI address is acknowledged. 0 1 DDC/CI address detection disabled DDC/CI address detection enabled
Bit 3 = Reserved. Forced to 0 by hardware. Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE = 0). 0 1 No acknowledge returned Acknowledge returned after an address byte or a data byte is received
Bit 1 = STOP Release IC bus. This bit is set and cleared by software or when the interface is disabled (PE = 0). Slave Mode: 0 1 Nothing Release the SCL and SDA lines after the current byte transfer (BTF = 1). The STOP bit has to be cleared by software.
Bit 0 = ITE Interrupt enable. This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE = 0). 0 1 Interrupt disabled Interrupt enabled
Refer to Figure 39 for the relationship between the events and the interrupt. SCL is held low when the BTF or ADSL is detected.
DDC STATUS REGISTER 1 (DDCSR1) Read Only Reset Value: 0000 0000 (00h)
7
EVF
6
0
5
TRA
4
BUSY
3
BTF
2
ADSL
1
0
0
0
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Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event occurs. It is cleared by software by reading the SR2 register in case of an error event or as described in Figure 39. It is also cleared by hardware when the interface is disabled (PE = 0). 0 1 No event One of the following events has occurred: BTF = 1 (Byte received or transmitted) ADSL = 1 (Either address matched in Slave mode when ACK = 1) AF = 1 (No acknowledge received after byte transmission if ACK = 1) STOPF = 1 (Stop condition detected in Slave mode) BERR = 1 (Bus error, misplaced Start or Stop condition detected) Bit 6 = Reserved. Forced to 0 by hardware. Bit 5 = TRA Transmitter/Receiver. When BTF is set, TRA = 1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after a Stop condition (STOPF = 1) is detected or when the interface is disabled (PE = 0). 0 1 Data byte received (if BTF = 1) Data byte transmitted
Bit 4 = BUSY Bus busy. This bit is set by hardware on detection of a Start condition and cleared by hardware when a Stop condition is detected. It indicates that a communication is in progress on the bus. This information is still updated when the interface is disabled (PE = 0). 0 1 No communication on the bus Communication ongoing on the bus
Bit 3 = BTF Byte transfer finished. This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE = 1. It is cleared by software by reading the SR1 register followed by a read or a write to the DR register. It is also cleared by hardware when the interface is disabled (PE = 0). Following a byte transmission, this bit is set after reception of the acknowledge clock pulse BTF is cleared by reading the SR1 register followed by writing the next byte in the DR register. Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK = 1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low when BTF = 1. 0 1 Byte transfer not completed Byte transfer succeeded
Bit 2 = ADSL Address matched (Slave mode). This bit is set by hardware as soon as the received slave address matched with the OARx registers content or the DDC/CI address is recognized. An interrupt is generated if ITE = 1. It is cleared by software by reading the SR1 register or by hardware when the interface is disabled (PE = 0). The SCL line is held low when ADSL = 1. 0 1 Address mismatched or not received Received address matched
Bits [1:0] = Reserved. Forced to 0 by hardware.
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DDC STATUS REGISTER 2 (DDCSR2) Read Only Reset Value: 0000 0000 (00h)
7
0
ST7FLCD1
6
0
5
0
4
AF
3
STOPF
2
0
1
BERR
0
DDCIF
Bits [7:5] = Reserved. Forced to 0 by hardware. Bit 4 = AF Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE = 1. It is cleared by software by reading the SR2 register or by hardware when the interface is disabled (PE = 0). The SCL line is not held low when AF = 1. 0 1 No acknowledge failure Acknowledge failure
Bit 3 = STOPF Stop detection. This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK = 1). An interrupt is generated if ITE = 1. It is cleared by software by reading the SR2 register or by hardware when the interface is disabled (PE = 0). The SCL line is not held low when STOPF = 1. 0 1 No Stop condition detected Stop condition detected
Bit 2 = Reserved. Forced to 0 by hardware. Bit 1 = BERR Bus error. This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE = 1. It is cleared by software by reading the SR2 register or by hardware when the interface is disabled (PE = 0). The SCL line is not held low when BERR = 1. 0 1 No misplaced Start or Stop condition Misplaced Start or Stop condition
Bit 0 = DDCIF DDC/CI address detected. This bit is set by hardware when the DDC/CI address (6Eh/6Fh) is detected on the bus when DDCIEN = 1. It is cleared by hardware when a Stop condition (STOPF = 1) is detected, or when the interface is disabled (PE = 0). 0 1 No DDC/CI address detected on bus DDC/CI address detected on bus
DDC DATA REGISTER (DDCDR) Read / Write Reset Value: 0000 0000 (00h)
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
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ST7FLCD1
Display Data Channel Interfaces (DDC)
Bits [7:0] = D[7:0] 8-bit Data Register. These bits contain the byte to be received or transmitted on the bus. Transmitter mode: Bytes are automatically transmitted when the software writes to the DR register. Receiver mode: The first data byte is automatically received in the DR register using the least significant bit of the address. Then, the next data bytes are received one by one after reading the DR register.
DDC OWN ADDRESS REGISTER 1 (DDCOAR1) Read / Write Reset Value: 0000 0000 (00h)
7
ADD7
6
ADD6
5
ADD5
4
ADD4
3
ADD3
2
ADD2
1
ADD1
0
0
Bits [7:1] = ADD[7:1] Interface address. These bits define the IC bus programmable address of the interface. They are not cleared when the interface is disabled (PE = 0). Bit 0 = Reserved. Forced to 0 by hardware.
DDC OWN ADDRESS REGISTER 2 (DDCOAR2) Read / Write Reset Value: 0000 0000 (00h)
7
ADD7
6
ADD6
5
ADD5
4
ADD4
3
ADD3
2
ADD2
1
ADD1
0
0
Bits [7:1] = ADD[7:1] Interface address. These bits define the IC bus programmable address of the interface. They are not cleared when the interface is disabled (PE = 0). Bit 0 = Reserved. Forced to 0 by hardware.
DDC2B CONTROL REGISTER (DDCDCR) Read / Write Reset Value: 0000 0000 (00h)
7
0
6
0
5
ENDCF
4
ENDCE
3
EDF
2
EDE
1
WP
0
DDC2BPE
Bits [7:6] = Reserved. Forced by hardware to 0. Bit 5 = ENDCF End of Communication interrupt Flag. This bit is set by hardware. An interrupt is generated if ENDCE = 1. It must be cleared by software. 0 NACK or STOP condition not met in Read mode.
73/95
Display Data Channel Interfaces (DDC)
1 NACK or STOP condition met in Read mode.
ST7FLCD1
Bit 4 = ENDCE End of Communication interrupt Enable. This bit is set and cleared by software. 0 1 End of Communication interrupt disabled. End of Communication interrupt enabled.
Bit 3 = EDF End of Download interrupt Flag. This bit is set by hardware. An interrupt is generated if EDE = 1. It must be cleared by software. 0 1 Download not started or not completed yet. Download completed. Last byte of data structure (relative address 7Fh or FFh) has been stored or read in RAM.
In Read Mode: EDF is set upon reading the next byte after the internal address counter has rolled over from 7Fh to 00h, or FFh to 80h. In Write Mode: EDF is set when the last byte of data structure has been stored in RAM, and only if writing to the RAM is enabled (bit WP = 0). if writing occurs but WP=1, EDF is not set. Bit 2 = EDE End of Download interrupt Enable. This bit is set and cleared by software. 0 1 End of Download interrupt disabled. End of Download interrupt enabled.
Bit 1 = WP Write Protect. This bit is set and cleared by software. 0 1 Enable writes to the RAM. Disable DMA write transfers and protect the RAM content. CPU writes to the RAM are not affected.
Bit 0 = DDC2BPE DDC2B Peripheral Enable. This bit is set and cleared by software. 0 1 Note: Release the SDA port pin and ignore SCL port pin. The other bits of the DCR are left unchanged. Enable the DDC Interface and respond to the DDC2B protocol.
When DDC2BPE = 1, all the bits of the DCR register are locked and cannot be changed. The desired configuration therefore must be written in the DCR register with DDC2BPE = 0 and then set the DDC2BPE bit in a second step.
74/95
ST7FLCD1
Watchdog Timer (WDG)
12
12.1
Watchdog Timer (WDG)
Introduction
The Watchdog Timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset when the programmed time period expires, unless the program refreshes the counter's contents before the T6 bit is cleared. In addition, a second counter prevents the Watchdog register from being updated at intervals that are too close.
12.2
Main Features

Programmable timer (64 increments of 50000 CPU cycles) Programmable reset Reset (if watchdog enabled) when the T6 bit reaches zero Reset (if watchdog enabled) on HALT instruction Lock-up Counter for preventing short time refreshes
Figure 40: Watchdog Block Diagram
Reset
Watchdog Control Register (CR) WDGA T6 T5 T4 T3 T2 T1 T0 Lock-up Counter (256 fCPU) Write Access
7-bit Downcounter
Clock Divider /50000 fCPU
12.3
Main Watchdog Counter
The counter value stored in the CR register (bits T[6:0]), is decremented every 50000 clock cycles, and the length of the time out period can be programmed by the user in 64 increments. If the watchdog is enabled (bit WDGA is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 is cleared), it initiates a reset cycle pulling low the reset pin for typically 500 ns:

The WDGA bit is set (watchdog enabled) Bit T6 is set to prevent generating an immediate reset Bits T[5:0] contain the number of increments which represents the time delay before the watchdog produces a reset.
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset.
75/95
Watchdog Timer (WDG)
ST7FLCD1
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 25).
12.4
Lock-up Counter
An 8-bit counter starts after a reset or by writing to the CR register. It disables the writing of the CR register during the next 256 cycles of CPU clock (typical value of 32 s at 8 MHz). If a writing order takes place during this time, this 8-bit counter is reset but not the main watchdog downcounter (no writing to the CR register occurs). Thus after several too close writings of the CR register, the main downcounter reaches the reset value and a reset occurs. If the CR register is normally refreshed every 32 s or more, write commands are always enabled.
Table 25: Watchdog Timing (fCPU = 8 MHz) CR Register Initial Value WDG Timeout (ms)
400 6.250
Lock-up Timeout (s)
32
Maximum Minimum
FFh C0h
12.5
Interrupts
None.
12.6
Register Description
Table 26: Watchdog Register Map Address
001Bh
Reset
7F R/W
Register
WDGCR
Bit 7
WDGA
Bit 6
Bit 5
Bit 4
Bit 3
T[6:0]
Bit 2
Bit 1
Bit 0
WDG CONTROL REGISTER (WDGCR) Read/Write Reset Value: 2 1111 (7Fh)
7
WDGA
6
T6
5
T5
4
T4
3
T3
2
T2
1
T1
0
T0
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0 1 Watchdog disabled Watchdog enabled
Bits [6:0] = T[6:0] 7-bit Timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 is cleared).
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ST7FLCD1
8-bit Timer (TIMA)
13
13.1
8-bit Timer (TIMA)
Introduction
Timer A is an 8-bit programmable free-running downcounter driven by a programmable prescaler. This block also has a buzzer. The block diagram is shown in Figure 41.
13.2
Main Features

Programmable Prescaler: fCPU divided by 1, 8 or 64. Overflow status flag and maskable interrupt Reduced power mode Independent buzzer output with 4 programmable tones
Figure 41: Timer A (TIMA) Block Diagram
fCPU
Fixed Prescaler % 2048
fTIMER
Prescaler 1 / 8 / 64
8-bit downcounter
8
TIMCPRA
Preload Register
OVF Interrupt Request
Interrupt
TIMCSRA
TB1
TB0
OVF
OVFE
TAR
BUZ1 BUZ0
BUZE
Buzzer Prescaler
Buzzer Output
BUZOUT Pin
13.3
Functional Description
Timer A is a 8-bit downcounter and its associated 8-bit register is loaded as start value of the downcounter each time it has reached the 00h value. A flag indicates that the downcounter rolled over the 00h value. The buzzer has 4 distinct tones. Before the downcounter prescaler block, the frequency is divided by 2048. fTIMER = fCPU/2048
Note:
In One-shot mode, the counter stops at 00h (low power state).
77/95
8-bit Timer (TIMA)
ST7FLCD1
13.4
Register Description
Table 27: Timer Controller Register Map Address
000Dh 000Eh
Reset
00h 00h R/W R/W
Register
TIMCSRA TIMCPRA
Bit 7
TB1 PR7
Bit 6
TB0 PR6
Bit 5
OVF PR5
Bit 4
OVFE PR4
Bit 3
TAR PR3
Bit 2
BUZ1 PR2
Bit 1
BUZ0 PR1
Bit 0
BUZE PR0
TIMER A CONTROL STATUS REGISTER (TIMCSRA) Read/Write Reset Value: (00h)
7
TB1
6
TB0
5
OVF
4
OVFE
3
TAR
2
BUZ1
1
BUZ0
0
BUZE
Bits [7:6] = TB[1:0] Time Base period selection These bits are set and cleared by software. 00 Time base period = tTIMER (256 s @ 8 MHz) 01 Time base period = tTIMER x 8 (2048 s @ 8 MHz) 10 Time base period = tTIMER x 64 (16384 s @ 8 MHz) 11 Reserved Bit 5 = OVF Timer Overflow Flag. This bit is set by hardware. An interrupt is generated if OVFE = 1. It must be cleared by reading the TIMCSRA register. 0 1 No timer overflow. The free-running downcounter reached 00h.
Bit 4 = OVFE Timer Overflow Interrupt Enable. This bit is set and cleared by software. 0 1 Interrupt disabled Interrupt enabled
Bit 3 = TAR Timer Auto-Reload This bit is set and cleared by software. 0 1 One-shot mode. The counter restarts after a write in the TIMCPRA register. Auto-Reload mode. The counter is reloaded automatically by the TIMCPRA register after the downcounter reaches 00h.
Bits [2:1] = BUZ[1:0] Buzzer tone selection These bits are set and cleared by software. 00 Time base frequency = fTIMER/16 (244 Hz @ 8 MHz) 01 Time base frequency = fTIMER/8 (488 Hz @ 8 MHz) 10 Time base frequency = fTIMER/4 (976 Hz@ 8 MHz) 11 Time base frequency = fTIMER/2 (1.95 kHz @ 8 MHz)
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ST7FLCD1
Bit 0 = BUZE Buzzer enable This bit is set and cleared by software. 0 1 Buzzer disabled
8-bit Timer (TIMA)
Buzzer enabled. It has priority over any other alternate function mapped onto the same pin (PWM).
TIMER A COUNTER PRELOAD REGISTER (TIMCPRA) Read/Write Reset Value: (00h)
7
PR7
6
PR6
5
PR5
4
PR4
3
PR3
2
PR2
1
PR1
0
PR0
Bits [7:0] = PR[7:0] Counter Preload Data These bits are set and cleared by software. They are used to hold the reload value which is immediately loaded in the counter. Note: The N number loaded in TIMCPRA register corresponds to a time of (N + 1) x Period timer. The "00" value is prohobited.
79/95
8-bit Timer with External Trigger (TIMB)
ST7FLCD1
14
14.1
8-bit Timer with External Trigger (TIMB)
Introduction
Timer B is an 8 bit-programmable free-running downcounter, driven by a programmable prescaler. An external signal can also trigger the countdown. The Timer B block diagram is shown in Figure 42.
14.2
Main Features

Programmable Prescaler: fCPU divided by 1, 8 or 16 Overflow status flag and maskable interrupt Auto reload capability An external signal with programmable polarity can trigger the count-down
Figure 42: External Timer Block Diagram
Preload register EDG EXT EEF EXTRIG Control Logic fCPU Fixed Prescaler % 128 fTIMER Prescaler 1 / 8 / 16 8-bit downcounter
TIMCPRB
8 Auto reload
OVF interrupt request
Interrupt
TIMCSRB
TB1
TB0
OVF
OVFE TAR
EXT
EDG
EEF
14.3
Functional Description
The 8 bit-downcounter timer counts from a start value down to 00h. The start value is preloaded from the associated 8-bit TIMCPRB register every time it is written, or when the counter has reached the 00h value (Auto Reload feature) if the TAR bit is set. The OVF flag is set when the downcounter reaches 00h. An interrupt is generated if the OVFE bit is set. When the EXT bit is set, an external signal edge triggers the countdown start. The EDG bit controls the rising or falling signal edge. Once detected, the selected edge sets the EEF flag, preloads the downcounter with the start value and starts the countdown as usual. During the countdown, the downcounter cannot be retriggered and subsequent pulses occurring after the countdown has started are ignored until the counter reaches 00h.
80/95
ST7FLCD1
8-bit Timer with External Trigger (TIMB)
The four possible operating modes are described in Table 28.
Table 28: Timer Operating Mode TAR
0 0 1
EXT
0 1 0
Timer mode
One-shot after the TIMCPRB register write (no auto reload) One-shot after the external signal detection (no auto reload). Only the very first external pulse triggers the countdown (Note 2) Downcounter auto-reload when 00h reached Downcounter reloaded with TIMCPRB register value, count-down restarts
1
1
One-shot for each external signal detection. Downcounter preloaded with TIMCPRB when 00h reached. Countdown restarts after the next external signal detection.
Note:1. The downcounter value cannot be read. 2. Change the EXT value to exit the External One-shot mode.
Table 29: Timer Controller Register Map Address
0038h 0039h
Reset
00h 01h
R/W
R/W R/W
Register
TIMCSRB TIMCPRB
Bit 7
TB1 PR7
Bit 6
TB0 PR6
Bit 5
OVF PR5
Bit 4
OVFE PR4
Bit 3
TAR PR3
Bit 2
EXT PR2
Bit 1
EDG PR1
Bit 0
EEF PR0
TIMER B CONTROL STATUS REGISTER (TIMCSRB) Read/Write Reset value: (00h)
7 TB1 TB0 OVF OVFE TAR EXT EDG 0 EEF
Bits [7:6] = TB[1:0] Time Base period selection These bits are set and cleared by software. 00 Time base period = tTIMER (16 s @ 8 MHz) 01 Time base period = tTIMER x 8 (128 s @ 8 MHz) 10 Time base period = tTIMER x 16 (256 s @ 8 MHz) 11 Reserved Bit 5 = OVF Timer Overflow Flag This bit is set by hardware. An interrupt is generated if OVFE = 1. It must be cleared by reading the TIMCSRB register. 0 1 No timer overflow The free running downcounter rolled over from 00h
81/95
8-bit Timer with External Trigger (TIMB)
Bit 4 = OVFE Timer Overflow Interrupt Enable This bit is set and cleared by software. 0 1 Interrupt disabled Interrupt enabled
ST7FLCD1
Bit 3 = TAR Timer Auto Reload This bit is set and cleared by software. 0 1 One-shot mode. The counter restarts after writing to the TIMCPRB register. Auto reload mode. The counter is reloaded automatically from the TIMCPRB register when 00h is reached.
Bit 2 = EXT External Trigger This bit is set and cleared by software. 0 1 Internal. The downcounter restarts after writing to the TIMCPRB register or after an auto-reload if the TAR bit is set External. The downcounter is preloaded with the TIMCPRB register but the countdown starts only when the external signal is detected, not by writng to the TIMCPRB register.
Bit 1 = EDG External Signal Edge This bit is set and cleared by software. 0 1 A rising edge signal starts the count-down. A falling edge signal starts the count-down
Bit 0 = EEF External Event Flag This bit is set and cleared by hardware when an external event occurs. This bit is cleared when the counter reaches "00h" in External mode or when the value of the EXT bit is changed by software. In Internal mode, this bit is set when the selected edge is detected (the EDG bit) but it is never cleared by itself. It may then be used as a simple edge detector.
TIMER B COUNTER PRELOAD REGISTER (TIMCPRB) Read/Write Reset value: (01h)
7 PR7 PR6 PR5 PR4 PR3 PR2 PR1 0 PR0
Bits [7:0] = PR[7:0] Counter Preload Data This bit is set and cleared by software. Bits hold the reload value which is loaded in the counter either immediately (EXT = 0) or when the external signal is detected (EXT = 1). Note: The N number loaded in TIMCPRB register corresponds to a time of (N + 1) x Period timer. The "00" value is prohibited.
82/95
ST7FLCD1
Infrared Preprocessor (IFR)
15
Infrared Preprocessor (IFR)
The Infrared Preprocessor measures the intervals between 2 adjacent edges of a serial input.
15.1
Main Features

Interval measurement between 2 edges (Time Base = 12.5 kHz) @ fCPU = 8 MHz Choice of active edge Glitch filter Overflow detection (20.4 ms = 255/12.5 kHz) Maskable interrupt
15.2
Functional Description
The IR Preprocessor measures the interval between two adjacent edges of the IFR input signal. The POSED and NEGED bits determine if the intervals of interest involve:

consecutive positive edges, negative edges, or any pair of edges as described in Table 30.
Figure 43: IFR Block Diagram
fCPU
Clock Generation
12.5 kHz 8-bit Counter
IFR
Filter Pulse
Edge Detection
IFRCR
ITE FLSEL POSED NEGED
8-bit Latch IFRDR
Interrupt
The measurement is a count resulting from a 12.5 kHz clock. Therefore, any pulse width that is less than 80 s cannot be detected. Whenever an edge of the specified polarity is detected, the count accumulated since the previously detected edge is latched into the IFRDR register, an interrupt is generated and the counter is reset. If an edge is not detected within 20.4 ms (fCPU = 8 MHz) and the count reaches its maximum value of 255, it is latched immediately. The internal interrupt flag and also an internal overflow flag are set. The latch content remains unchanged as long as the overflow flag is set. The count stored in the latch register is overwritten in case the microcontroller fails to execute the read before the next edge. Writing to the IFRDR register clears the interrupt and internal overflow flag.
83/95
Infrared Preprocessor (IFR)
ST7FLCD1
The IFR input signal is preprocessed by a spike filter. This filter removes all pulses with a positive level that lasts less than 2 s or 160 s, depending on the FLSEL bit. The negative level can be of any duration and is never filtered out. Note: If the interrupt is enabled but no signal is detected, an interrupt occurs every 20.4 ms.
15.3
Register Description
INFRA RED DATA REGISTER (IFRDR) Read/Write Reset Value: (00h)
7
IR7
6
IR6
5
IR5
4
IR4
3
IR3
2
IR2
1
IR1
0
IR0
Bits [7:0] = IR[7:0] Infra red pulse width The 8-bit counter value is transferred in this register when an expected edge occurs on the IFR pin or when the counter overflows. A write to this register resets the internal overflow flag.
INFRA RED CONTROL REGISTER (IFRCR) Read/Write Reset Value: (00h)
7
0
6
0
5
0
4
ITE
3
FLSEL
2
POSED
1
NEGED
0
0
Bits [7:5] = Reserved. Forced by hardware to 0. Bit 4 = ITE Interrupt enable 0 1 Interrupt disabled Interrupt enabled. It is generated when an edge (falling and/or rising depending on bits POSED and NEGED) occurs or after a counter overflow. Filter positive pulses narrower than 2 s Filter positive pulses narrower than 160 s
Bit 3 = FLSEL Spike filter pulse width selection 0 1
Bits [2:1] = POSED, NEGED Edge selection for the duration measurement
Table 30: Duration Measurement POSED
0 0 1 1
NEGED
0 1 0 1 When count reaches 255
Count latch at...
Negative transition of IFR or when count reaches 255 Positive transition of IFR or when count reaches 255 Positive or negative transition of IFR or when count reached 255
Bit 0 = Reserved. Forced by hardware to 0.
84/95
ST7FLCD1
Registers
16
16.1
Registers
Register Description
NAME REGISTER (NAMER) Read only Reset value: 00h
7 6 5 4
N[7:0]
3
2
1
0
Bits [7:0] = N[7:0]Circuit Name This register indicates the version number of the circuit. The current value is 01h.
Table 31: ST7FLCD1 Register Summary (Sheet 1 of 2) Address Reset
0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh 00h 00h 00h FFh 00h R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Register
NAMER MISCR PADR PADDR PBDR PBDDR PCDR PCDDR PDDR PDDDR ADCDR ADCCSR ITRFRE TIMCSRA TIMCPRA PWMDCR0 PWMDCR1 PWMDCR2 PWMDCR3 PWMCRA PWMARRA PWMDCR4 PWMDCR5 PWMCRB PWMARRB FCSR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0 PADR[7:0]
0
PA5OVD PA4OVD
0
PADDR[7:0] PBDR[7:0] PBDDR[7:0] PCDR[7:0] PCDDR[7:0] PDDR[7:0] PDDDR[7:0] AD[7:0] COCO 0 TB1 PR7 0 0 TB0 PR6 ADON ITB EDGE OVF PR5 0 ITBLAT OVFE PR4 0 ITBITE TAR PR3 0 ITA EDGE BUZ1 PR2 CH[1:0] ITALAT BUZ0 PR1 ITAITE BUZE PR0
DCR0[7:0] DCR1[7:0] DCR2[7:0] DCR3[7:0] OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0
ARRA[7:0] DCR4[7:0] DCR5[7:0] 0 0 OE5 OE4 ARRB[7:0] 0 0 OP5 OP4
85/95
Registers
Table 31: ST7FLCD1 Register Summary (Sheet 2 of 2) Address Reset
001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 00h 00h 10h FFh FFh FFh FFh 00h 00h 00h 01h R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W DDCDCRB DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L IFRDR IFRCR TIMCSRB TIMCPRB 0 WDGOFF WP BK1H7 BK1L7 BK2H7 BK2L7 IR7 0 TB1 PR7 0 MTR STE BK1H6 BK1L6 BK2H6 BK2L6 IR6 0 TB0 PR6 ENDCF BC2 STF BK1H5 BK1L5 BK2H5 BK2L5 IR5 0 OVF PR5 00h 00h 00h 00h 00h 00h 00h R/W R/W R R R/W R/W R/W DDCDCRA DDCCRB DDCSR1B DDCSR2B DDCOAR1B DDCOAR2B DDCDRB 0 0 EVF 0 0 0 0 0 ENDCF PE TRA 0 7F 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h R/W R/W R R/W R/W R/W R R R/W R/W R/W
ST7FLCD1
Register
Reserved WDGCR I2CCR I2CSR I2CCCR I2CDR DDCCRA DDCSR1A DDCSR2A DDCOAR1A DDCOAR2A DDCDRA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDGA 00 EVF FM/SM AF Filteroff PE TRA 0 0
T[6:0] START BTF CC[5:0] DR[7:0] ACK 0 STOP M/IDL ITE SB
0 EVF 0
0 0 0
PE TRA 0
DDCCIEN BUSY AF ADD[7:1] ADD[7:1] DR[7:0] Reserved ENDCE DDCCIEN BUSY AF ADD[7:1] ADD[7:1] DR[7:0] Reserved ENDCE BC1 RST BK1H4 BK1L4 BK2H4 BK2L4 IR4 ITE OVFE PR4 Reserved
0 BTF STOPF
ACK ADSL 0
STOP 0 BERR
ITE 0 DDCCIF 0 0
EDF 0 BTF STOPF
EDE ACK ADSL 0
WP STOP 0 BERR
DDC2BP E ITE 0 DDCCIF 0 0
EDF BC0 BRW BK1H3 BK1L3 BK2H3 BK2L3 IR3 FLSEL TAR PR3
EDE BIR BK2F BK1H2 BK1L2 BK2H2 BK22L IR2 POSED EXT PR2
WP BIW BK1F BK1H1 BK1L1 BK2H1 BK2L1 IR1 NEGED EDG PR1
DDC2BP E AIE AF BK1H0 BK1L0 BK2H0 BK2L0 IR0 0 EEF PR0
86/95
ST7FLCD1
Electrical Characteristics
17
Electrical Characteristics
The ST7FLCD1 device contains circuitry to protect the inputs against damage due to high static voltage or electric field. Nevertheless it is advised to take normal precautions and to avoid applying to this high impedance voltage circuit any voltage higher than the maximum rated voltages. It is recommended for proper operation that VIN and VOUT be constrained to the range: VSS (VIN or VOUT) VDD To enhance reliability of operation, it is recommended to connect unused inputs to an appropriate logic voltage level such as VSS or VDD. All the voltages in the following table, are referenced to VSS.
17.1
Absolute Maximum Ratings
Table 32: Absolute Maximum Ratings
Symbol
VDD VIN VAIN VOUT IIN IOUT IINJ TA TSTG TJ PD ESD
Ratings
Recommended Supply Voltage Input Voltage Analog Input Voltage (A/D Converter) Output Voltage Input Current Output Current Accumulated injected current of all I/O pins (VDD, VSS) Operating Temperature Range Storage Temperature Range Junction Temperature Power Dissipation ESD susceptibility
Value
-0.3 to +6.0 VSS -0.3 to VDD + 0.3 VSS -0.3 to VDD + 0.3 VSS -0.3 to VDD + 0.3 -10 to +10 -10 to +10 40 0 to +70 -65 to +150 150 TBD 2000
Unit
V V V V mA mA mA C C C mW V
17.2
Power Considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation: TJ = TA + (PD x JA) (1) Where:

TA is the Ambient Temperature in C, JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, PD is the sum of PINT and PI/O, PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power PI/O represents the Power Dissipation on Input and Output Pins; User Determined.
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Electrical Characteristics
ST7FLCD1
For most applications PI/O K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ ay be obtained by solving equations (1) and (2) iteratively for any value of TA.
17.3
Thermal Characteristics
Table 33: Thermal Characteristics
Symbol
JA
Package
28-pin Small Outline Packqge (SO28)
Value
69
Unit
C/W
17.4
AC/DC Electrical Characteristics
All voltages are referred to VSS and TA = 0 to +70C (unless otherwise specified)
Symbol
General
Parameter
Conditions
Min.
Typ.
Max.
Unit
Operating Supply Voltage VDD Operating Voltage for FLASH access READ WRITE/ERASE CPU RUN mode IDD CPU WAIT mode CPU HALT mode Control Timing fOSC fCPU tBU tRL tPORL tPOWL tDOG External frequency Internal frequency Startup Time Built-Up Time External RESET Input pulse Width Internal Power Reset Duration Watchdog RESET Output Pulse Width Watchdog Time-out fCPU = 8 MHz Crystal Resonator I/O in input mode VDD = 5V fCPU = 8 MHz, TA = 20 C
4.5 3.8 4.5
5
5.5
V V
5.5 14 12 1 18 18 10
V mA mA uA
24 8 8 1000 4096 500 50000 6.25
27 9 20
MHz MHz ms ns tCPU ns
3200000 400
tCPU ms
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ST7FLCD1
Electrical Characteristics
Symbol
tILIL tOXOV tDDR
Parameter
Interrupt Pulse Period Crystal Oscillator Start-up Time Power-up rise time
Conditions
Min.
Typ.
See Note 1
Max.
Unit
tCPU
50 VDD min. 1 100
ms ms
Standard I/O Port Pins VOL VOL VOL Output Low Level Voltage Port A[7:6,3:0], Port B[3:0], Push Pull Output Low Level Voltage Port C[1:0] Open Drain Output Low Level Voltage Port A[5:4] (See Note 2) Output Low Level Voltage Port D[7:0] Open Drain Output High Level Voltage Port A[7:6,3:0], Port B[3:0], Push Pull VOH Output High Level Voltage Port A[5:4] Output High Level Voltage Port C[1:0], Port D (See Note 3) Input High Level Voltage Port A [7:0], Port B [3:0], Port C [1:0], Port D[7:0], RESET Input Low Level Voltage Port A [7:0], Port B [3:0], Port C [1:0], Port D[7:0], RESET I/O Ports Hi-Z Leakage Current Port A[7:0], Port B[3:0], Port C[1:0], Port D[7:0], RESET COUT CIN IRPU Capacitance: Ports (as Input or Output), RESET VDD = 5V VIN = VSS T = 25C Leading Edge 0.7 * VDD IOL = 2 mA and VDD = 5 V IOL = 4 mA and VDD = 5 V IOL = 8 mA and VDD = 5 V IOL = 2 mA and VDD = 5 V IOL = 4 mA and VDD = 5 V IOH = 2 mA IOH = 2 mA IOH = 8 mA VDD-0.8 0.4 0.4 V V
0.4
V
VOL VOH
0.4
V
V
VDD-0.8 VDD
V
VOH VIH
V
VDD
V
VIL
Trailing Edge
VSS
0.2 * VDD
V
IIL
10 12 8 30 60 100
A
pF
Pull-up resistor current
A
Note:1. The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles. 2. For the case of IOL = 8 mA, 8 mA output current if corresponding overdrive bit = 1 in MISCR register. 3. Output high level by means of external pull-up resistor.
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Electrical Characteristics
ST7FLCD1
17.5
Power On/Off Electrical Specifications
Parameter
Power ON/OFF Reset Trigger VDD rising edge Power ON/OFF Reset Trigger VDD falling edge VDD minimum for Power ON/OFF Reset active
Symbol
VTRH
Conditions
VDD Variation 50mV/mS
Min.
3.8
Typ.
4
Max.
4.2
Unit
V
VTRL
VDD Variation 50mV/mS
3.75
4
4.2
V
VTRM
VDD Variation 50mV/mS
TBD
V
17.6
8-bit Analog-to-Digital Converter
Parameter
Analog control frequency Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Conversion range voltage A/D conversion supply current Stabilization time after enable ADC Sample capacitor loading time fCPU = 8 MHz, fADC = 2MHz VDD = 5 V
Symbol
fADC |TUE| OE GE |DLE| |ILE| VAIN IADC tSTAB tLOAD tCONV RAIN RADC CSAMPLE
Conditions
VDD = 5 V fCPU = 8 MHz, fADC = 2MHz VDD = 5 V
Min.
Typ.
Max.
2
Unit
MHz LSB
0 -2 -2 0 0 VSS
1 1 1 0.5 1
2 2 2 1 2 VDD
V mA
1 1 1 4 2 8 15 1.5 6
s s 1/fADC s 1/fADC k k pF
Conversion time
External input resistor Internal input resistor Sample capacitor
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ST7FLCD1
Electrical Characteristics
17.7
I2C/DDC Bus Electrical Specifications
Standard mode Fast mode Unit Min.
Hysteresis of Schmitt trigger inputs
Symbol
Parameter Max. Min. Max.
VHYS
Fixed input levels VDD-related input levels
na na na
na na na
0.2 0.05 VDD 0 ns 50 ns
V
TSP
Pulse width of spikes which must be suppressed by the input filter Output fall time from VIH min to VIL max with a bus capacitance from 10 pF to 400 pF
ns
TOF
with up to 3 mA sink current at VOL1 with up to 6 mA sink current at VOL2 na - 10
250 na 10 10
20+0.1Cb 20+0.1Cb -10
250 250 10 10
ns
I C
Input current each I/O pin with an input voltage between 0.4V and 0.9 VDD max Capacitance for each I/O pin
A pF
Note:
na = not applicable Cb = capacitance of one bus in pF
17.8
I2C/DDC Bus Timings
Standard I2C Fast I2C Unit Min. Max. Min.
1.3 0.6 1.3 0.6 0.6 0 (1) 100 1000 300 4.0 400 20+0.1Cb 20+0.1Cb 0.6 400 300 300 0.9(2)
Symbol
Parameter Max.
Bus free time between a STOP and START condition Hold time START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Capacitive load for each bus line
tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO Cb
4.7 4.0 4.7 4.0 4.7 0 (1) 250
ms s s s s ns ns ns ns ns pF
Note:1. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
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Electrical Characteristics
ST7FLCD1
2. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 3. Cb = total capacitance of one bus line in pF. 4. IC parameters compliant with IC Bus Specification for speeds up to 400 kHz only. Faster speeds are at user responsibility.
Figure 44: IC Bus Timing
SDA
t BUF t LOW t SU,DAT
SCL t HD,STA tR t HD,DAT t HIGH tF t SU,STO
SDA
t SU,STA
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ST7FLCD1
Package Mechanical Data
18
Package Mechanical Data
L C c1
S E
e3 D
28
15 F
1
14
Mm Dimensions Min. A a1 b b1 c c1 D E e e3 F L S
7.4 0.4 17.7 10 1.27 16.51 7.6 1.27 0.291 0.016 8 (max.) 18.1 10.65 0.1 0.35 0.23 0.5 45 (typ.) 0.697 0.394
Inch Max.
2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020
Typ.
Min.
Typ.
a1
e
0.050 0.65 0.299 0.050
b1
b
A
Max.
0.104 0.012 0.019 0.013
0.713 0.419
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Revision History
ST7FLCD1
19
Revision History
Table 34: Summary of Modifications Date
May 2002
Version
2.1
Description
Addition of Section 5.5: In-Circuit Programming (ICP) and Section 5.6: In-Application Programming (IAP). Update of Chapter numbering system. Update of Figure 2: 28-pin Small Outline Package (SO28) Pinout, Figure 12: Typical ICP Interface, Pin 14 becomes PA6/ITA/EXTRIG. Addition of MISCR register (0001h) and update of DDC2B Control Register data. Lock-up Counter info added in Section 12: Watchdog Timer (WDG). Buzzer output info added in Section 13: 8-bit Timer (TIMA). Modification of oscillator frequency from 24 MHz to maximum of 27 MHz, Fast IC mode up to 800 kHz (for certain applications), Section 8: PWM Generator, Section 10.5: Transfer Sequencing and Section 11.6: Transfer Sequencing. Addition of Section 17: Electrical Characteristics and Section 19: Revision History. Modification of Figure 4: Program Memory Map. Modification of Figure 4: Program Memory Map and Table 34: Summary of Modifications. Modification of IC Clock Control register. Change of VTRH and VTRL values in Section 17.4: AC/DC Electrical Characteristics. Addition of Section 1.5: External Connections. Update of DDC2B Control Register (Bit 3) information in Section 11.7: Register Description. Change of VDD values in Section 17.4: AC/DC Electrical Characteristics. Modification of values in Section 17.4: AC/DC Electrical Characteristics, Section 17.5: Power On/Off Electrical Specifications and Section 17.6: 8-bit Analog-to-Digital Converter. Addition of VOH row in Standard I/O Port Pins on page 89. Addition of Note 1 on page 9. Update of Section 6.1.2: Crystal Oscillator Mode on page 32.
19 Aug 2002
2.2
24 Sept 2002 14 Oct 2002 4 Dec 2002 6 Feb 2003 11 Feb 2003 2 Sept 2003 13 April 2004 9 Feb 2005
2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10
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ST7FLCD1
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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