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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
March 2008
FAN5355 1A / 0.8A, 3MHz Digitally Programmable TinyBuckTM Regulator
Features
91% Efficiency at 3MHz 800mA or 1A Output Current
(1)
Description
The FAN5355 device is a high-frequency, ultra-fast transient response, synchronous step-down DC-DC converter optimized for low-power applications using small, low-cost inductors and capacitors. The FAN5355 supports up to (1) 800mA or 1A load current. The device is ideal for mobile phones and similar portable applications powered by a single-cell Lithium-Ion battery. With 2 an output voltage range adjustable via I CTM interface from 0.75V to 1.975V, the device supports low-voltage DSPs and processors, core power supplies in smart phones, PDAs, and handheld computers. The FAN5355 operates at 3MHz (nominal) fixed switching frequency using either its internal oscillator or external SYNC frequency. During light-load conditions, the regulator includes a PFM mode to enhance light-load efficiency. The regulator transitions smoothly between PWM and PFM modes with no glitches on VOUT. Normal PFM (NPFM) mode offers the lowest quiescent current, at the expense of setpoint accuracy. Enhanced PFM (EPFM) mode features higher accuracy, as well as a 25kHz minimum PFM frequency, designed to prevent the regulator from operating in the audible range. In shutdown, the current consumption is reduced to less than 2A, using software shutdown (EN = 1 with EN_DCDC = 0), and less than 200nA in hardware shutdown (EN = 0). The serial interface is compatible with Fast/Standard and 2 High-Speed mode I C specifications, allowing transfers up to 3.4Mbps. This interface is used for dynamic voltage scaling with 12.5mV voltage steps, for reprogramming the mode of operation (PFM or Forced PWM), or to disable/enable the output voltage. The chip's advanced protection features include short-circuit protection and current and temperature limits. During a sustained over-current event, the IC shuts down and restarts after a delay to reduce average power dissipation into a fault. During start-up, the IC controls the output slew rate to minimize input current and output overshoot at the end of softstart. The IC maintains a consistent soft-start ramp, regardless of output load during start-up. The FAN5355 is available in 10-lead MLP (3x3mm) and 12-bump CSP packages.
2.7V to 5.5V Input Voltage Range 6 or 7-bit VOUT Programmable from 0.75 to 1.975V 3MHz Fixed-Frequency Operation Excellent Load and Line Transient Response Small Size, 1H Inductor Solution 2% PWM DC Voltage Accuracy 35ns Minimum On-Time High-Efficiency, Low-Ripple, Light-Load PFM Smooth Transition between PWM and PFM 37A Operating PFM Quiescent Current Software Selectable 25kHz Minimum PFM Frequency Prevents Audible Noise in PFM Mode I CTM-Compatible Interface up to 3.4Mbps Pin-Selectable or I CTM Programmable Output Voltage On-the-Fly External Clock Synchronization 10-lead MLP (3 x 3mm) or 12-bump CSP Packages
2 2
Applications
SmartReflexTM-Compliant Power Supply Split Supply DSPs and P Solutions OMAPTM, XSCALETM Cell Phones, Smart Phones, PDAs, Digital Cameras, and Portable Media Players Micro DC-DC Converter Modules Handset Graphic Processors (NVIDIA , ATI)
(R)
I2C is a trademark of Philips Corporation. SmartReflex and OMAP are trademarks of Texas Instruments. XSCALE is a trademark of Intel Corporation. NVIDIA is a registered trademark of NVIDIA Corporation.
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4
www.fairchildsemi.com
FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Ordering Information
Slave Address LSB Order Number
(4)
VOUT Programming DAC 6 6 6 6 6 7 7 MIN. 0.7500 0.7500 0.7500 0.7500 1.1875 0.7500 0.7500
(3) (3)
Power-up Defaults VSEL0 VSEL1 1.05 1.05 1.05 1.00 1.80 1.05 1.05 1.35 1.35 1.20 1.20 1.80 1.35 1.35 Package
(4)
Option 00 00 02 03 (1) 06 (1) 07 07
(1)
A1 0 0 1 0 0 1 1
A0 0 0 0 0 0 1 1
MAX. 1.5375 1.5375 1.4375 1.5375 1.9750 1.9750 1.9750
(2)
FAN5355UC00X FAN5355MP00X FAN5355UC02X FAN5355UC03X FAN5355UC06X FAN5355UC07X FAN5355MP07X
WLCSP-12, 2.23x1.46mm MLP-10, 3x3mm WLCSP-12, 2.23x1.46mm WLCSP-12, 2.23x1.46mm WLCSP-12, 2.23x1.46mm WLCSP-12, 2.23x1.46mm MLP-10, 3x3mm
Notes: 1. Option 06 and 07 is rated for 1A output current. All other options are rated for 800mA output current. 2. VOUT is limited to the maximum voltage for all VSEL codes greater than the maximum VOUT listed. 3. VOUT may be programmed down 100mV for option 07. Performance below 0.75V is not guaranteed. 4. All packages are "green" per JEDEC: J-STD-020B standard. The "X" designator specifies tape and reel packaging.
Typical Application
AVIN
Q1
PVIN CIN
VIN
EN VSEL SYNC VCCIO SW VOUT L OUT COUT PGND VOUT
MODULATOR
SDA SCL AGND
Q2
Figure 1. Typical Application Component
L1 (LOUT) COUT CIN
Description
1H nominal 0603 (1.6x0.8x0.8) 10F X5R or better 0603 (1.6x0.8x0.8) 4.7F X5R or better
Vendor
Murata LQM31P or FDK MIPSA2520 Murata or equivalent GRM188R60G106ME47D Murata or equivalent GRM188R60J475KE19D
Parameter
L(5) DCR (series R) C(6) C(6)
Min.
0.7
Typ.
1.0 100
Max.
1.2
Units
H m
5.6 3.0
10.0 4.7
12.0 5.6
F F
Table 1. Recommended External Components Notes: 5. Minimum L incorporates both tolerance, temperature, and partial saturation effects (L decreases with increasing current). 6. Minimum C is a function of initial tolerance, maximum temperature, and the effective capacitance being reduced due to frequency, dielectric, and voltage bias effects.
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Pin Configuration
A1 A2 A3 A3 A2 A1
PVIN 1 AVIN 2
10 SW 9 PGND
B1
B2
B3
B3
B2
B1
PAD
SDA 3 8 AGND AGND SCL 4 VSEL 5 7 EN 6 VOUT
C1
C2
C3
C3
C2
C1
D1
D2
D3
D3
D2
D1
Top View
Bottom View
Top View Figure 3. MLP10, 3x3mm
Figure 2. WLCSP- 12, 2.23x1.46mm
Pin Definitions
Pin # WLCSP
A1, B1 A2 A3
MLP
9 10 1
Name
PGND SW PVIN
Description
Power GND. Power return for gate drive and power transistors. Connect to AGND on PCB. The connection from this pin to the bottom of CIN should be as short as possible. Switching Node. Connect to output inductor. Power Input Voltage. Connect to input power source. The connection from this pin to CIN should be as short as possible. Sync. When toggling and SYNC_EN bit is HIGH, the regulator synchronizes to the frequency on this pin. In PWM mode, when this pin is statically LOW or statically HIGH, or when its frequency is outside of the specified capture range, the regulator's frequency is controlled by its internal 3MHz clock. Analog Input Voltage. Connect to input power source as close as possible to the input bypass capacitor. Analog GND. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. Enable. When this pin is HIGH, the circuit is enabled. When LOW, quiescent current is minimized. This pin should not be left floating. SDA. I2C interface serial data. Output Voltage Monitor. Tie this pin to the output voltage. This is a signal input pin to the control circuit and does not carry DC current. Voltage Select. When HIGH, VOUT is set by VSEL1. When LOW, VOUT is set by VSEL0. This behavior can be overridden through I2C register settings. This pin should not be left floating. SCL. I2C interface serial clock.
B2
N/A
SYNC
B3 C1 C2 C3 D1 D2 D3
2 8, PAD 7 3 6 5 4
AVIN AGND EN SDA VOUT VSEL SCL
Note: 7. All logic inputs (SDA, SCL, SYNC, EN, and VSEL) are high impedance and should not be left floating. For minimum quiescent power consumption, tie unused logic inputs to AVIN or AGND. If I2C control is unused, tie SDA and SCL to AVIN.
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol
VCC ESD TJ TSTG TL
Parameter
AVIN, SW, PVIN Pins Other Pins Electrostatic Discharge Protection Level Junction Temperature Storage Temperature Lead Soldering Temperature, 10 Seconds Human Body Model per JESD22-A114 Charged Device Model per JESD22-C101
Min.
-0.3 -0.3 3.5 1.5 -40 -65
Max.
6.5 AVIN + 0.3
(8)
Units
V V KV KV
+150 +150 +260
C C C
Note: 8. Lesser of 6.5V or VCC+0.3V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol
VIN f VSW TA TJ
Parameter
Supply Voltage Frequency Range SDA and SCL Voltage Swing(9) Ambient Temperature Junction Temperature
Min.
2.7 2.7 -40 -40
Max.
5.5 3.3 2.5 +85 +125
Units
V MHz V C C
Note: 9. The I C interface operates with tHD;DAT = 0 as long as the pull-up voltage for SDA and SCL is less than 2.5V. If voltage 2 swings greater than 2.5V are required (for example if the I C bus is pulled up to VIN), the minimum tHD;DAT must be 2 increased to 80ns. Most I C masters change SDA near the midpoint between the falling and rising edges of SCL, which provides ample tHD;DAT .
2
Dissipation Ratings(10)
Package
Molded Leadless Package (MLP) Wafer-Level Chip-Scale Package (WLCSP)
RJA
(11)
Power Rating at TA 25C
2050mW 900mW
Derating Factor > TA = 25C
21mW/C 9mW/C
49C/W 110C/W
Notes: 10. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = [TJ(max) - TA ] / JA. 11. This thermal data is measured with high-K board (four-layer board according to JESD51-7 JEDEC standard).
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Electrical Specifications
VIN = 3.6V, EN = VIN, VSEL = VIN, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = 25C. Circuit and components according to Figure 1. Symbol
VIN IQ
Parameter
Input Voltage Range
Conditions
Min.
2.7
Typ.
Max.
5.5
Units
V A A mA
Power Supplies IO = 0mA, EPFM Mode, FPFM = 25kHz Quiescent Current IO = 0mA, NPFM Mode IO = 0mA, 3MHz PWM Mode EN = GND I SD Shutdown Supply Current EN = VIN, EN_DCDC bit = 0, SDA = SCL = VIN VIN Rising VIN Falling 2.00 200 1.2 0.4 Input tied to GND or VIN VIN = 3.6V, CSP Package RDS(ON)P ILKGP RDS(ON)N ILKGN RDIS P-channel MOSFET On Resistance P-channel Leakage Current N-channel MOSFET On Resistance N-channel Leakage Current Discharge Resistor for Power-down Sequence VIN = 3.6V, MLP Package VIN = 2.7V, MLP Package VDS = 6V VIN = 3.6V, CSP Package VIN = 3.6V, MLP Package VIN = 2.7V, MLP Package VDS = 6V Options 03, 06, 07 2.7V VIN 4.2V, All Options Except 06 and 07 ILIMPK P-MOS Current Limit 2.7V VIN 5.5V, All Options Except 06 and 07 2.7V VIN 4.2V, 06 and 07 Option TLIMIT THYST fSW fSYNC DSYNC fSYNCVAL fPFM(MIN) Thermal Shutdown Thermal Shutdown Hysteresis Oscillator Frequency Synchronization Range Synchronization Duty Cycle SYNC Frequency Rejection Minimum PFM Frequency EPFM Mode, ILOAD = 0 2.65 2.7 20 1.6 25 1150 1050 1300 15 1350 1350 1550 150 20 3.00 3.0 3.35 3.3 80 4.3 75 95 101 1 50 1600 1600 1800 C C MHz MHz % MHz kHz mA A m 0.01 145 165 200 1 A m 1.00 110 37 4.8 0.1 0.1 2.40 2.15 250 2.0 2.0 2.60 2.30 300 A V V mV V V A 150 50
VUVLO VUVHYST VIH VIL IIN
Under-Voltage Lockout Threshold Under-Voltage Lockout Hysteresis HIGH-Level Input Voltage LOW-Level Input Voltage Input Bias Current
ENABLE, VSEL, SDA, SCL, SYNC
Power Switch and Protection
Frequency Control
Continued on the following page...
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4 5 www.fairchildsemi.com
FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Electrical Specifications (Continued)
VIN = 3.6V, EN = VIN, VSEL = VIN, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = 25C. Circuit and components according to Figure 1 Symbol Parameter Conditions
IOUT(DC) = 0, Forced PWM, VOUT = 1.35V Option 00 2.7V VIN 5.5V, VOUT from 0.75 to 1.5375, IOUT(DC) = 0 to 800mA, Forced PWM 2.7V VIN 5.5V, VOUT from 0.75 to 1.5375, IOUT(DC) = 0 to 800mA, NPFM Mode IOUT(DC) = 0, Forced PWM, VOUT = 1.20V Option 02 2.7V VIN 5.5V, VOUT from 0.75 to 1.4375, IOUT(DC) = 0 to 800mA, Forced PWM 2.7V VIN 5.5V, VOUT from 0.75 to 1.4375, IOUT(DC) = 0 to 800mA, NPFM Mode IOUT(DC) = 0, Forced PWM, VOUT = 1.20V 2.7V VIN 5.5V, VOUT from 0.75 to 1.5375, IOUT(DC) = 0 to 800mA, Forced PWM Option 03 VOUT VOUT Accuracy 2.7V VIN 5.5V, VOUT from 0.75 to 1.5375, IOUT(DC) = 0 to 800mA, NPFM Mode 2.7V VIN 5.5V, VOUT from 0.75 to 1.5375, IOUT(DC) = 0 to 800mA, EPFM Mode IOUT(DC) = 0, Forced PWM, VOUT = 1.800V 2.7V VIN 5.5V, VOUT from 1.185 to 1.975, IOUT(DC) = 0 to 1A, Forced PWM Option 06 2.7V VIN 5.5V, VOUT from 1.185 to 1.975, IOUT(DC) = 0 to 1A, NPFM Mode 2.7V VIN 5.5V, VOUT from 1.185 to 1.975, IOUT(DC) = 0 to 1A, EPFM Mode IOUT(DC) = 0, Forced PWM, VOUT = 1.35V 2.7V VIN 5.5V, VOUT from 0.75 to 1.6875, IOUT(DC) = 0 to 1A, Forced PWM Option 07 2.7V VIN 5.5V, VOUT from 0.75 to 1.6875, IOUT(DC) = 0 to 1A, NPFM Mode 2.7V VIN 5.5V, VOUT from 0.75 to 1.6875, IOUT(DC) = 0 to 1A, EPFM Mode
VOUT ILOAD VOUT VIN
Min.
-1.5 -2 -1.5 -1.5 -2 -1.5 -1.5 -2 -1.5 -0.5 -1.5 -2 -1.5 -0.5 -1.5 -2 -1.5 -0.5
Typ.
Max.
1.5 2 3.5 1.5 2 3.5 1.5 2 3.5 2 1.5 2 3.5 2 1.5 2 3.5 2
Units
% % % % % % % % % % % % % % % % % % %/A
Output Regulation
Load Regulation
IOUT(DC) = 0 to 800mA, Forced PWM
-0.5
Line Regulation
2.7V VIN 5.5V, IOUT(DC) = 300mA PWM Mode, VOUT = 1.35V PFM Mode, IOUT(DC) = 10mA
0 2.2 20
%/V mVP-P mVP-P
VRIPPLE
Output Ripple Voltage
Continued on the following page...
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Electrical Specifications (Continued)
VIN = 3.6V, EN = VIN, VSEL = VIN, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = 25C. Circuit and components according to Figure 1. Symbol
DAC Resolution Differential Nonlinearity Timing I2CEN tV(L-H) Soft-Start tSS VSLEW Regulator Enable to Regulated VOUT Option 06 All Other Options RLOAD > 5, to VOUT = 1.8000V RLOAD > 5, to VOUT = Power-up Default 170 140 18.75 210 180 s s V/ms EN HIGH to I2C Start VOUT LOW to HIGH Settling RLOAD = 75, Transition from 1.0 to 1.5375V VOUT Settled to within 2% of Setpoint 250 7 s s Option 07 All Other Options Monotonicity Assured by Design 7 6 0.8 Bits Bits LSB
Parameter
Conditions
Min.
Typ.
Max.
Units
Soft-start VOUT Slew Rate(12)
Note: 12. Option 06 slew rate is 35.5V/ms during the first 16s of soft-start.
AVIN
Q1
PVIN CIN
VIN
EN VSEL SYNC SDA SCL
7-bit DAC I2C INTERFACE AND LOGIC
REF SW
Q2
VOUT L OUT COUT
SOFT START FPWM EN_REG CLK
MODULATOR
PGND VOUT
3 MHz Osc
Figure 4. Block Diagram
AGND
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
I2C Timing Specifications
Guaranteed by design. Symbol
fSCL
Parameter
SCL Clock Frequency
Conditions
Standard mode Fast mode High-Speed mode, CB < 100pF High-Speed mode, CB < 400pF Standard mode Fast mode Standard mode Fast mode High-Speed mode Standard mode Fast mode High-Speed mode, CB < 100pF High-Speed mode, CB < 400pF Standard mode Fast mode High-Speed mode, CB < 100pF High-Speed mode, CB < 400pF Standard mode Fast mode High-Speed mode Standard mode Fast mode High-Speed mode Standard mode Fast mode High-Speed mode, CB < 100pF High-Speed mode, CB < 400pF Standard mode Fast mode High-Speed mode, CB < 100pF High-Speed mode, CB < 400pF Standard mode Fast mode High-Speed mode, CB < 100pF High-Speed mode, CB < 400pF Standard mode Fast mode High-Speed mode, CB < 100pF High-Speed mode, CB < 400pF Standard mode Fast mode High-Speed mode, CB < 100pF High-Speed mode, CB < 400pF Standard mode Fast mode High-Speed mode
Min.
Typ.
Max.
100 400 3400 1700
Units
kHz kHz kHz kHz s s s ns ns s ns ns ns s ns ns ns s ns ns ns ns ns
tBUF
Bus-free Time between STOP and START Conditions START or Repeated START Hold Time
4.7 1.3 4 600 160 4.7 1.3 160 320 4 600 60 120 4.7 600 160 250 100 10 0 0 0 0 20+0.1CB 20+0.1CB 10 20 20+0.1CB 20+0.1CB 10 20 20+0.1CB 20+0.1CB 10 20 20+0.1CB 20+0.1CB 10 20 4 600 160 3.45 900 70 150 1000 300 80 160 300 300 40 80 1000 300 80 160 300 300 80 160
tHD;STA
tLOW
SCL LOW Period
tHIGH
SCL HIGH Period
tSU;STA
Repeated START Setup Time
tSU;DAT
Data Setup Time
tHD;DAT
Data Hold Time
(9)
tRCL
SCL Rise Time
tFCL
SCL Fall Time
tRDA tRCL1
SDA Rise Time Rise Time of SCL After a Repeated START Condition and After ACK Bit
tFDA
SDA Fall Time
s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns pF
tSU;STO CB
Stop Condition Setup Time Capacitive Load for SDA and SCL
400
8
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Timing Diagrams
tF
tSU;STA
tBUF
SDA
tR TSU;DAT tHIGH tHD;DAT tHD;STA REPEATED START STOP START tHD;STO
SCL
tHD;STA
tLOW
START
2
Figure 5. I C Interface Timing for Fast and Slow Modes
tFDA
tRDA
tSU;DAT
REPEATED START
STOP
SDAH
tSU;STA tRCL1 tLOW tHD;STA REPEATED START tFCL tHIGH tHD;DAT note A tRCL tSU;STO
SCLH
= MCS Current Source Pull-up = RP Resistor Pull-up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 6. I C Interface Timing for High-Speed Mode
2
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Typical Performance Characteristics
Unless otherwise specified, Auto-PWM/NPFM, VIN = 3.6V, TA = 25C, and recommended components as specified in Table 1.
Efficiency
100% 90% 80% 70% Efficiency Efficiency 60% 50% 40% 30% 20% 10% 0% 1 10 100 1000 I LOAD Output Current (ma)
VIN = 3.6 V VOUT = 1.05 V Auto PWM/NPFM Forced PWM
100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 1 10 100 1000 I LOAD Output Current (mA)
VIN = 3.6 V VOUT = 1.35 V Auto PWM/NPFM Forced PWM
Figure 7. Efficiency vs. Load at VOUT = 1.05V
100% 90% 80% 70% Efficiency 60% 50% 40% 30% 20% 10% 0% 1 10 100 1000 I LOAD Output Current (ma)
VIN = 3.6 V VOUT = 1.5 V Auto PWM/NPFM Forced PWM
Figure 8. Efficiency vs. Load at VOUT = 1.35V
Figure 9. Efficiency vs. Load at VOUT = 1.50V
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Typical Performance Characteristics
Unless otherwise specified, Auto-PWM/NPFM, VIN = 3.6V, TA = 25C, and recommended components as specified in Table 1.
1.064 1.062 1.060 VOUT (V)
Auto PWM/NPFM Forced PWM
1.364 1.362 1.360 VOUT (V) 1.358 1.356 1.354 1.352 1.350 1.348 1 10 100 1000 1 10 100 1000 I LOAD Output Current (mA) I LOAD Output Current (mA)
Auto PWM/NPFM Forced PWM
1.058 1.056 1.054 1.052 1.050 1.048
Figure 10. Load Regulation at VOUT = 1.05V
70 65 60 55 50 45 40 35 30 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN Input Voltage (V)
VSEL = 1.8V VSEL = 0V
Figure 11. Load Regulation at VOUT = 1.35V
6.0
Quiescent Current (A)
Quiescent Current (A)
5.0
VSEL = 1.8V
4.0 3.0 2.0 1.0 2.5 3.0
VSEL = 0V
3.5
4.0
4.5
5.0
5.5
VIN Input Voltage (V)
Figure 12. Quiescent Current, ILOAD = 0, EN = 1.8V
0.10% 0.05% Output Voltage (V) 0.00% -0.05% -0.10% -0.15% -0.20% -0.25% -0.30% -40 -20 0 20 40 60 80 Temperature (C)
VIN = 2.7V VIN = 3.6V VIN = 5.5V
Figure 13. Shutdown Current, ILOAD = 0, EN = 0
230 210 190 170 RDS(ON) (m) 150 130 110 90 70 50 30 2 2.5 3 3.5 4 4.5 5 5.5 VIN Input Voltage (V)
P-Channel N-Channel
Figure 14. % VOUT Shift vs. Temperature (Normalized)
Figure 15. Output Stage RDS(ON) vs. VIN
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Typical Performance Characteristics (Continued)
Unless otherwise specified, VIN = 3.6V, VOUT = 1.35V, and load step tR = tF < 100ns.
Load Transient Response
Figure 16. 50mA to 400mA to 50mA, Forced PWM
Figure 17. 50mA to 400mA to 50mA, Auto PWM/NPFM
Figure 18. 400mA to 750mA to 400mA, Auto PWM/NPFM
Figure 19. 0mA to 125mA to 0mA, Auto PWM/NPFM
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Typical Performance Characteristics (Continued)
Unless otherwise specified, VIN = 3.6V.
VSEL Transitions
Figure 20. Single-Step, RLOAD = 6.2
Figure 21. Single-Step, RLOAD = 6.2
Figure 22. Single-Step, RLOAD = 50
Figure 23. Single-Step, RLOAD = 50
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Typical Performance Characteristics (Continued)
Unless otherwise specified, VIN = 3.6V.
VSEL Transitions
Figure 24. Single-Step from Forced PWM (MODE1=0), RLOAD = 50
Figure 25. Single Step, RLOAD = 6.2
Figure 26. Single-Step from Auto PWM/PFM (MODE1=1), RLOAD = 50
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Typical Performance Characteristics (Continued)
RLOAD is switched with N-channel MOSFET from VOUT to GND. VIN = 3.6V, initial VOUT = 1.35V, initial ILOAD = 0mA.
Short Circuit and Over-Current Fault Response
Figure 27. Metallic Short Applied at VOUT
Figure 28. Metallic Short Applied at VOUT
Figure 29. RLOAD = 660m
Figure 30. RLOAD = 660m
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Typical Performance Characteristics (Continued)
Unless otherwise specified, VIN = 3.6V.
Figure 31. SW-Node Jitter (Infinite Persistence), ILOAD = 200mA
Figure 32. SW-Node Jitter, External Synchronization (Infinite Persistence), ILOAD = 200mA
70 Attenuation (dB) 60 50 40 30 20 10 (10) 0.1 1.0 10.0 Frequency (KHz) 100.0 1,000.0
IOUT=500mA IOUT=150mA IOUT=20mA
PSRR
Figure 33. Soft-Start, RLOAD = 50
Figure 34. VIN Ripple Rejection (PSRR)
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Circuit Description
Overview
The FAN5355 is a synchronous buck regulator that typically operates at 3MHz with moderate to heavy load currents. At light load currents, the converter operates in power-saving PFM mode. The regulator automatically transitions between fixed-frequency PWM and variable-frequency PFM mode to maintain the highest possible efficiency over the full range of load current. The FAN5355 uses a very fast non-linear control architecture to achieve excellent transient response with minimum-sized external components. The FAN5355 integrates an I C-compatible interface, allowing transfers up to 3.4Mbps. This communication interface can be used to: 1. 2. 3. 4. 5. Dynamically re-program the output voltage in 12.5mV increments. Reprogram the mode of operation to enable or disable PFM mode. Control voltage transition slew rate. Control the frequency of operation by synchronizing to an external clock. Enable / disable the regulator.
2 2
Power-up, EN, and Soft-start
All internal circuits remain de-biased and the IC is in a very low quiescent current state until the following are true: 1. 2. VIN is above its rising UVLO threshold, and EN is HIGH.
2
At that point, the IC begins a soft-start cycle, its I C interface is enabled, and its registers loaded with their default values. During the initial soft-start, VOUT ramps linearly to the setpoint programmed in the VSEL register selected by the VSEL pin. The soft start features a fixed output voltage slew rate of 18.75V/ms, and achieves regulation approximately 90s after EN rises. PFM mode is enabled during soft-start until the output is in regulation, regardless of the MODE bit settings. This allows the regulator to start into a partially charged output without discharging it; in other words, the regulator does not allow current to flow from the load back to the battery. As soon as the output has reached its setpoint, the control forces PWM mode for about 85s to allow all internal control circuits to calibrate. Symbol Description
tSSDLY tREG tPOK tCAL Time from EN to start of soft-start ramp VOUT ramp start to Opt 06 regulation Others PWROK (CONTROL2[5]) rising from tREG Regulator stays in PWM mode during this time
Value (s)
25 16 +(VSEL-0.7) X 53 (VSEL-0.1) X 53 11 10
For more details, refer to the I C Interface and Register Description sections.
Output Voltage Programming
Option
00, 02, 03
VOUT Equation
VOUT = 0.75 + NVSEL * 12.5mV VOUT = 0.100 + NVSEL * 25mV
for NVSEL = 0 to 23
(1)
Table 2. Soft-Start Timing (see Figure 35)
EN
07
VOUT = 0.675 + (N VSEL - 23 ) * 12.5mV
for NVSEL > 23
(2)
VOUT
TSSDLY
TREG
VSEL
TCAL (FPWM)
06
VOUT = 1.1875 + NVSEL * 12.5mV
(3)
PWROK
0
TPOK
where NVSEL is the decimal value of the setting of the VSEL register that controls VOUT. Note: 13. Option 02 maximum voltage is 1.4375V (see Table 3).
Figure 35. Soft-start Timing
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
VSEL Value Dec Binary Hex 0 000000 00 1 000001 01 2 000010 02 3 000011 03 4 000100 04 5 000101 05 6 000110 06 7 000111 07 8 001000 08 9 001001 09 10 001010 0A 11 001011 0B 12 001100 0C 13 001101 0D 14 001110 0E 15 001111 0F 16 010000 10 17 010001 11 18 010010 12 19 010011 13 20 010100 14 21 010101 15 22 010110 16 23 010111 17 24 011000 18 25 011001 19 26 011010 1A 27 011011 1B 28 011100 1C 29 011101 1D 30 011110 1E 31 011111 1F 32 100000 20 33 100001 21 34 100010 22 35 100011 23 36 100100 24 37 100101 25 38 100110 26 39 100111 27 40 101000 28 41 101001 29 42 101010 2A 43 101011 2B 44 101100 2C 45 101101 2D 46 101110 2E 47 101111 2F 48 110000 30 49 110001 31 50 110010 32 51 110011 33 52 110100 34 53 110101 35 54 110110 36 55 110111 37 56 111000 38 57 111001 39 58 111010 3A 59 111011 3B 60 111100 3C 61 111101 3D 62 111110 3E 63 111111 3F
00, 03 0.7500 0.7625 0.7750 0.7875 0.8000 0.8125 0.8250 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375
VOUT 02 0.7500 0.7625 0.7750 0.7875 0.8000 0.8125 0.8250 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4375 1.4375 1.4375 1.4375 1.4375 1.4375 1.4375 1.4375
06 1.1875 1.2000 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000 1.6125 1.6250 1.6375 1.6500 1.6625 1.6750 1.6875 1.7000 1.7125 1.7250 1.7375 1.7500 1.7625 1.7750 1.7875 1.8000 1.8125 1.8250 1.8375 1.8500 1.8625 1.8750 1.8875 1.9000 1.9125 1.9250 1.9375 1.9500 1.9625 1.9750
VSEL Dec Hex 0 00 1 01 2 02 3 03 4 04 5 05 6 06 7 07 8 08 9 09 10 0A 11 0B 12 0C 13 0D 14 0E 15 0F 16 10 17 11 18 12 19 13 20 14 21 15 22 16 23 17 24 18 25 19 26 1A 27 1B 28 1C 29 1D 30 1E 31 1F 32 20 33 21 34 22 35 23 36 24 37 25 38 26 39 27 40 28 41 29 42 2A 43 2B 44 2C 45 2D 46 2E 47 2F 48 30 49 31 50 32 51 33 52 34 53 35 54 36 55 37 56 38 57 39 58 3A 59 3B 60 3C 61 3D 62 3E 63 3F
VOUT 0.1000 0.1250 0.1500 0.1750 0.2000 0.2250 0.2500 0.2750 0.3000 0.3250 0.3500 0.3750 0.4000 0.4250 0.4500 0.4750 0.5000 0.5250 0.5500 0.5750 0.6000 0.6250 0.6500 0.6750 0.6875 0.7000 0.7125 0.7250 0.7375 0.7500 0.7625 0.7750 0.7875 0.8000 0.8125 0.8250 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750
VSEL Dec Hex 64 00 65 01 66 02 67 03 68 04 69 05 70 06 71 07 72 08 73 09 74 0A 75 0B 76 0C 77 0D 78 0E 79 0F 80 10 81 11 82 12 83 13 84 14 85 15 86 16 87 17 88 18 89 19 90 1A 91 1B 92 1C 93 1D 94 1E 95 1F 96 20 97 21 98 22 99 23 100 24 101 25 102 26 103 27 104 28 105 29 106 2A 107 2B 108 2C 109 2D 110 2E 111 2F 112 30 113 31 114 32 115 33 116 34 117 35 118 36 119 37 120 38 121 39 122 3A 123 3B 124 3C 125 3D 126 3E 127 3F
VOUT 1.1875 1.2000 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000 1.6125 1.6250 1.6375 1.6500 1.6625 1.6750 1.6875 1.7000 1.7125 1.7250 1.7375 1.7500 1.7625 1.7750 1.7875 1.8000 1.8125 1.8250 1.8375 1.8500 1.8625 1.8750 1.8875 1.9000 1.9125 1.9250 1.9375 1.9500 1.9625 1.9750
Table 3. VSEL vs. VOUT for Options 00, 02, 03, 06
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4 18
Table 4. VSEL vs. VOUT for Option 07
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Software Enable
The EN_DCDC bit, VSELx[7] can be used to enable the regulator in conjunction with the EN pin. Setting EN_DCDC with EN HIGH begins the soft-start sequence described above. EN_DCDC Bit
0 1 1 0
EN Pin
0 1 0 1
IC
OFF ON OFF ON
2
REGULATOR
OFF ON OFF OFF
"create demand" for a pulse if no pulse had been required for 40s. The minimum frequency limit circuit takes effect with load currents below about 3.5mA. Above that load point, the natural PFM period is less than 40s. This circuit only activates when ILOAD is greater than ~3.5mA. If the load remains above 3.5mA, there is no quiescent current penalty for EPFM mode and there is some accuracy advantage. NPFM allows the switching frequency (fSW) to go as low as required to support the load current. This achieves a lower quiescent current than EPFM, but sacrifices up to 15mV of DC accuracy when compared to EPFM or PWM modes. As shown in Table 6, EPFM and NPFM modes have the same frequency when the load is above 4mA. If the load is above 4mA, EPFM is the preferred mode, since it has tighter DC regulation with the same efficiency. EPFM can only be enabled by setting the MODE_CTRL bits to 11. In versions with MODE_CTRL disabled (see Table 12), the PFM mode is NPFM. Mode
IQUIESCENT typical at ILOAD = 0 DC Accuracy fSW at ILOAD = 0 fSW at ILOAD > 3.5mA
Table 5. EN_DCDC Behavior
Light-Load (PFM) Operation
The FAN5355 offers both a Normal PFM (NPFM) and Enhanced PFM (EPFM) mode. NPFM is normally used when the load current is very low and when quiescent current must be minimized. EPFM provides more accurate DC regulation and limits the minimum frequency to 25kHz typical to prevent operation in the audio band. VOUT ripple is identical in both modes (less than 20mV), and both modes feature very fast response to load transients. The FAN5355 incorporates a single-pulse, light-load modulation that ensures: Smooth transitions between PFM and PWM modes Minimum frequency, of 25kHz typical, to avoid audible noise (EPFM only) Single-pulse operation for low ripple Predictable PFM entry and exit currents. PFM begins after the inductor current has become discontinuous, crossing zero during the PWM cycle in 32 consecutive cycles. PFM exit occurs when discontinuous current mode (DCM) operation cannot supply sufficient current to maintain regulation. During PFM mode, the inductor current ripple is about 40% higher than in PWM mode. The load current required to exit PFM mode is thereby about 20% higher than the load current required to enter PFM mode, providing sufficient hysteresis to prevent "mode chatter." While PWM ripple voltage is typically less than 4mVP-P, PFM ripple voltage can be up to 30mVP-P during very light load. To prevent significant undershoot when a load transient occurs, the initial DC setpoint for the regulator in PFM mode is set 10mV higher than in PWM mode. This offset decays to about 5mV after the regulator has been in PFM mode for ~100s. The maximum instantaneous voltage in PFM is 30mV above the setpoint. In Enhanced PFM (EPFM) mode, the regulator maintains a minimum frequency of 25kHz (typical) to prevent audible noise being generated by the external components. To achieve this, the regulator turns on the low-side MOSFET to
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4 19
EPFM
110A Better 25 kHz > 33 kHz
NPFM
38A Good to 0 Hz > 33 kHz
Table 6. PFM Modes Comparison PFM mode can be disabled by writing to the mode control bits: CONTROL1[3:0] (see Table 12 for details).
Switching Frequency Control and Synchronization
The nominal internal oscillator frequency is 3MHz. The regulator runs at its internal clock frequency until these conditions are met: 1. EN_SYNC bit, CONTROL1[5], is set; and 2. A valid frequency appears on the SYNC pin. CONTROL2 PLL_MULT
00 01 10 11
FSYNC Valid Min.
2.25 1.13 0.75 0.56
fSYNC Divider
1 2 3 4
Typ.
3.00 1.50 1.00 0.75
Max.
4.00 2.00 1.33 1.00
Table 7. SYNC Frequency Validation for fOSC(INTERNAL)=3.0MHz If the EN_SYNC is set and SYNC fails validation, the regulator continues to run at its internal oscillator frequency. The regulator is functional if fSYNC is valid, as defined in Table 7, but its performance is compromised if fSYNC is outside the fSYNC window in the Electrical Specifications. When CONTROL1[3:2] = 00 and the VSEL line is LOW, the converter operates according to the MODE0 bit, CONTROL1[0], with synchronization disabled regardless of the state of the EN_SYNC and HW_nSW bits.
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Output Voltage Transitions
The IC regulates VOUT to one of two setpoint voltages, as determined by the VSEL pin and the HW_nSW bit. VSEL Pin HW_nSW Bit VOUT Setpoint
0 1 x 1 1 0 VSEL0 VSEL1 VSEL1
(14)
setpoint and is typically 7s for a full-range transition (from 00000 to 11111 for 6-bit DAC options). The PWROK bit, CONTROL2[5], goes LOW until the transition is complete and VOUT settled. This typically occurs ~2s after tV(L-H). It is good practice to reduce the load current before making positive VSEL transitions. This reduces the time required to make positive load transitions and avoids current-limitinduced overshoot.
VHIGH
PFM
Allowed Per MODE1 Per MODE1
Table 8. VOUT Setpoint and Mode Control MODE_CTRL, CONTROL1[3:2] = 00 Note: 14. Option 07 uses VSELx[6:0] to set VOUT, while all other options use VSELx[5:0]. If HW_nSW =0, VOUT transitions are initiated through the following sequence: 1. Write the new setpoint in VSEL1. 2. Write desired transition rate in DEFSLEW, CONTROL2[2:0], and set the GO bit in CONTROL2[7]. If HW_nSW =1, VOUT transitions are initiated either by changing the state of the VSEL pin or by writing to the VSEL register selected by the VSEL pin.
tV(L-H)
98% VHIGH
VOUT
VLOW
VSEL PWROK
tPOK(L-H)
Figure 37. Single-Step VOUT Transition All positive VOUT transitions inhibit PFM until the transition is complete, which occurs at the end of tPOK(L-H).
Positive Transitions
When transitioning to a higher VOUT, the regulator can perform the transition using multi-step or single-step mode. Multi-step Mode: The internal DAC is stepped at a rate defined by DEFSLEW, CONTROL2[2:0], ranging from 000 to 110. This mode minimizes the current required to charge COUT and thereby minimizes the current drain from the battery when transitioning. The PWROK bit, CONTROL2[5], remains LOW until about 1.5s after the DAC completes its ramp.
VHIGH
Negative Transitions
When moving from VSEL=1 to VSEL=0, the regulator enters PFM mode, regardless of the condition of the SYNC pin or MODE bits, and remains in PFM until the transition is completed. Reverse current through the inductor is blocked, and the PFM minimum frequency control inhibited, until the new setpoint is reached, at which time the regulator resumes control using the mode established by MODE_CTRL. The transition time from VHIGH to VLOW is controlled by the load current and output capacitance as:
t V (H-L ) = COUT *
VHIGH - VLOW ILOAD
VHIGH
(4)
VOUT
VLOW
VSEL PWROK
tPOK(L-H)
VOUT VSEL PWROK
tV(L-H)
VLOW
Figure 36. Multi-step VOUT Transition Single-step Mode: Used if DEFSLEW, CONTROL2[2:0] = 111. The internal DAC is immediately set to the higher voltage and the regulator performs the transition as quickly as its current limit circuit allows, while avoiding excessive overshoot. Figure 37 shows single-step transition timing. tV(L-H) is the time it takes the regulator to settle to within 2% of the new
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4 20
tPOK(L-H)
Figure 38. Negative VOUT Transition
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Protection Features
Current Limit / Auto-Restart
The regulator includes cycle-by-cycle current limiting, which prevents the instantaneous inductor current from exceeding ~1350mA. The IC enters "fault" mode after sustained over-current. If current limit is asserted for more than 32 consecutive cycles (about 20s), the IC returns to shutdown state and remains in that condition for ~80s. After that time, the regulator attempts to restart with a normal soft-start cycle. If the fault has not cleared, it shuts down ~10s later. If the fault is a short circuit, the initial current limit is ~30% of the normal current limit, which produces a very small drain on the system power source.
Slave Address
In Table 10, A1 and A0 are according to the Ordering Information table on page 2. 7
1
6
0
2
5
0
4
1
3
0
2
A1
1
A0
0
R/ W
Table 10. I C Slave Address
Bus Timing
As shown in Figure 39, data is normally transferred when SCL is LOW. Data is clocked in on the rising edge of SCL. Typically, data transitions shortly at or after the falling edge of SCL to allow ample time for the data to set up before the next SCL rising edge.
Data change allowed
Thermal Protection
When the junction temperature of the IC exceeds 150C, the device turns off all output MOSFETs and remains in a low quiescent current state until the die cools to 130C before commencing a normal soft-start cycle.
SDA
TH
Under-Voltage Lockout (UVLO)
The IC turns off all MOSFETs and remains in a very low quiescent current state until VIN rises above the UVLO threshold.
SCL
TSU
Figure 39. Data Transfer Timing Each bus transaction begins and ends with SDA and SCL HIGH. A transaction begins with a "START" condition, which is defined as SDA transitioning from 1 to 0 with SCL HIGH, as shown in Figure 40.
SDA
THD;STA Slave Address MS Bit
I2C Interface
The FAN5355's serial interface is compatible with standard, 2 fast, and HS mode I C bus specifications. The FAN5355's SCL line is an input and its SDA line is a bi-directional opendrain output; it can only pull down the bus when active. The SDA line only pulls LOW during data reads and when signaling ACK. All data is shifted in MSB (bit 7) first. SDA and SCL are normally pulled up to a system I/O power 2 supply (VCCIO), as shown in Figure 1. If the I C interface is not used, SDA and SCL should be tied to AVIN to minimize quiescent current consumption.
SCL
Figure 40. Start Bit A transaction ends with a "STOP" condition, which is defined as SDA transitioning from 0 to 1 with SCL HIGH, as shown in Figure 41.
Slave Releases Master Drives tHD;STO
Addressing
FAN5355 has four user-accessible registers: Address 7
VSEL0 VSEL1 CONTROL1 CONTROL2
2
SDA
6
0 0 0 0
5
0 0 0 0
4
0 0 0 0
3
0 0 0 0
2
0 0 0 0
1
0 0 1 1
0
0 1 0 1
SCL
ACK(0) or NACK(1)
0 0 0 0
Table 9. I C Register Addresses
Figure 41. Stop Bit During a read from the FAN5355 (Figure 44), the master issues a "Repeated Start" after sending the register address, and before resending the slave address. The "Repeated Start" is a 1 to 0 transition on SDA while SCL is HIGH, as shown in Figure 42.
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
High-Speed (HS) Mode
The protocols for High-Speed (HS), Low-Speed (LS), and Fast-Speed (FS) modes are identical, except the bus speed for HS mode is 3.4MHz. HS mode is entered when the bus master sends the HS master code 00001XXX after a start condition. The master code is sent in FS mode (less than 400kHz clock) and slaves do not ACK this transmission. The master then generates a repeated start condition (Figure 42) that causes all slaves on the bus to switch to HS 2 mode. The master then sends I C packets, as described above, using the HS mode clock rate and timing. The bus remains in HS mode until a stop bit (Figure 41) is sent by the master. While in HS mode, packets are separated by repeated start conditions (Figure 42).
Slave Releases tSU;STA tHD;STA SLADDR MS Bit ACK(0) or NACK(1)
Read and Write Transactions
The following figures outline the sequences for data read and write. Bus control is signified by the shading of the packet, defined as
Master Drives Bus
and
Slave Drives Bus
.
All addresses and data are MSB first. Symbol Definition
S A
A
SDA
R P
START, see Figure 40. ACK. The slave drives SDA to 0 to acknowledge the preceding packet. NACK. The slave sends a 1 to NACK the preceding packet. Repeated START, see Figure 42. STOP, see Figure 41.
2
Table 11. I C Bit Definitions for Figure 43 - Figure 44
SCL
Figure 42. Repeated Start Timing
7 bits
S Slave Address 0
0 A
8 bits
Reg Addr
0 A
8 bits
Data
0 A P
Figure 43. Write Transaction
7 bits
S Slave Address 0
0 A
8 bits
Reg Addr
0 A R
7 bits
Slave Address 1
0 A
8 bits
Data
1 A P
Figure 44. Read Transaction
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Register Descriptions
Default Values
Each option of the FAN5355 (see Ordering Information on page 2) has different default values for the some of the register bits. Table 12 defines both the default values and the bit's type (as defined in Table 13) for each available option.
VSEL0 Option
00 02 03 07 06
VSEL1 3
1 1 0 1 0
7
1 1 1 1 1
6
1 1 1 1 1
5
0 0 0 0 1
4
1 1 1 1 1
2
0 0 1 0 0
1
0 0 0 0 0
0
0 0 0 0 1
VOUT
1.05 1.05 1.00 1.05 1.80
Option
00 02 03 07 06
7
1 1 1 1 1
6
1 1 1 1 1
5
1 1 1 1 1
4
1 0 0 1 1
3
0 0 0 0 0
2
0 1 1 0 0
1
0 0 0 0 0
0
0 0 0 0 1
VOUT
1.35 1.20 1.20 1.35 1.80
CONTROL1 Option
00, 02 03 06, 07
CONTROL2 3
0 0 0
7
1 0 1
6
0 0 0
5
0 0 0
4
1 1 1
2
0 0 0
1
0 0 0
0
0 0 0
Option
00, 02 03 06, 07
7
0 0 0
6
0 0 0
5
0 0 0
4
0 0 0
3
0 0 0
2
1 1 1
1
1 1 1
0
1 1 1
Table 12. Default Values and Bit Types for VSEL and CONTROL Registers
# # #
Active bit. Disabled. Read-only.
Changing this bit changes the behavior of the converter, as described below. Converter logic ignores changes made to this bit. Bit can be written to and read-back. Writing to this bit through I2C does not change the read-back value, nor does it change converter behavior.
Table 13. Bit Type Definitions for Table 12.
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FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Bit Definitions
The following table defines the operation of each register bit. Superscript characters define the default state for each option. 0,2,3,6,7 A Superscripts signify the default values for options 00, 02, 03, 06, and 07, respectively. signifies the default for all options. Bit Name Value Description
VSEL0
7 6
EN_DCDC
0,2,3,6
0 1A
Table 12
Reserved or DAC6 7 DAC[5:0] 5:0 VSEL1
Register Address: 00 Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL1. A write to bit 7 in either register establishes the EN_DCDC value. Device enabled when EN pin is HIGH, disabled when EN is LOW. Has no effect in options 00, 02, 03, 06, and defaults to 1. In option 07, it is the MSB of the 7-bit DAC value to set VOUT. 6-bit DAC value to set VOUT. The six LSBs of the 7-bit value for option 07. Register Address: 01 Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL0. A write to bit 7 in either register establishes the EN_DCDC value. Device enabled when EN pin is HIGH, disabled when EN is LOW. Has no effect in options 00, 02, 03, 06, and defaults to 1. In option 07, it is the MSB of the 7-bit DAC value to set VOUT. 6-bit DAC value to set VOUT. The six LSBs of the 7-bit value for option 07.
7 6
EN_DCDC
0,2,3,6
0 1A
Table 12
Reserved or DAC6 7 DAC[5:0] 5:0 CONTROL1 7:6 5 4 Reserved
EN_SYNC HW_nSW
3:2 MODE_CTRL
1 0
MODE1 MODE0
CONTROL2
7 6 5
GO OUTPUT_ DISCHARGE PWROK (read only)
4:3
PLL_MULT
2:0
DEFSLEW
Register Address: 02 100,2,5,6 Vendor ID bits. Writing to these bits has no effect on regulator operation. These bits can be used to distinguish between vendors via I2C. 003 A 0 Disables external signal on SYNC from affecting the regulator. When a valid frequency is detected on SYNC, the regulator synchronizes to it and PFM is disabled, except 1 when MODE = 00, VSEL pin = LOW, and HW_nSW = 1. 0 VOUT is controlled by VSEL1. Voltage transitions occur by writing to the VSEL1, then setting the GO bit. VOUT is programmed by the VSEL pin. VOUT = VSEL1 when VSEL is HIGH, and VSEL0 when VSEL is LOW. 1A 00A Operation follows MODE0, MODE1. 01 NPFM with automatically transitions to PWM, regardless of VSEL. 10 PFM disabled (forced PWM), regardless of VSEL. 11 EPFM (FSW(MIN) = 25kHz) with automatically transitions to PWM, regardless of VSEL. 0A PFM disabled (forced PWM) when regulator output is controlled by VSEL1. 1 NPFM with automatic transitions to PWM when regulator output is controlled by VSEL1. NPFM with automatic transitions to PWM when VSEL is LOW. Changing this bit has no effect on the operation 0A of the regulator. 1 Register Address: 03 0A This bit has no effect when HW_nSW = 1. At the end of a VOUT transition, this bit is reset to 0. 1 Starts a VOUT transition if HW_nSW = 0. 0A When the regulator is disabled, VOUT is not discharged. 1 When the regulator is disabled, VOUT discharges through an internal pull-down. 0 VOUT is not in regulation or is in current limit. 1 VOUT is in regulation. 00A fSW = fSYNC when synchronization is enabled. 01 fSW = 2 X fSYNC when synchronization is enabled. 10 fSW = 3 X fSYNC when synchronization is enabled. 11 fSW = 4 X fSYNC when synchronization is enabled. 000 VOUT slews at 0.15mV/s during positive VOUT transitions. 001 VOUT slews at 0.30mV/s during positive VOUT transitions. 010 VOUT slews at 0.60mV/s during positive VOUT transitions. 011 VOUT slews at 1.20mV/s during positive VOUT transitions. 100 VOUT slews at 2.40mV/s during positive VOUT transitions. 101 VOUT slews at 4.80mV/s during positive VOUT transitions. 110 VOUT slews at 9.60mV/s during positive VOUT transitions. 111A Positive VOUT transitions use single-step mode (see Figure 37).
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4
24
www.fairchildsemi.com
FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Physical Dimensions
BALL A1 INDEX AREA 0.03 C
E
A B
(O0.25) Cu PAD
0.50
2X
D
A1
0.50
1.00
(O0.35) SOLDER MASK OPENING
TOP VIEW
0.03 C
2X
RECOMMENDED LAND PATTERN (NSMD)
0.06 C
0.05 C
0.625 0.539
0.3320.018
0.2500.025
D
C
SEATING PLANE
SIDE VIEWS
(X)+/-.018
0.50 0.005 CAB
12 X O0.315 +/- .025
D
0.50
C B A 12 3
A. NO JEDEC REGISTRATION APPLIES B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D DATUM C, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS.
F FOR DIMENSIONS D, E, X, AND Y SEE
(Y)+/-.018
BOTTOM VIEW
PRODUCT DATASHEET. F. BALL COMPOSITION: Sn95.5Ag3.9Cu0.6 SAC405 ALLOY G. DRAWING FILENAME: MKT-UC012AArev2
Figure 45. 12-Bump WLCSP, 0.5mm Pitch
Product-Specific Dimensions
Product
FAN5355UC
D
2.230 +/-0.030
E
1.460 +/-0.030
X
0.230
Y
0.365
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4 25 www.fairchildsemi.com
FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
Physical Dimensions
0.10 C 3.0 A B
0.78 0.55
10
2X
2.25 2.40 2.00
6
2.33
3.0
0.10 C
0.23 0.02 D 1 0.50 5 0.25
0.8 MAX
0.10 C
TOP VIEW
2X
(0.20) 0.08 C
0.05 0.00
S E A TING P LA NE
RECOMMENDED LAND PATTERN
C
SIDE VIEW
(3.000.10)
PIN #1 IDENT 1
2.40 (0.38) 5
1.40 (3.000.10)
E
0.550.10 10 0.5 2.0
0.30 0.20
6 0.10 0.05 CAB C
BOTTOM VIEW
A. CONFORMS TO JEDEC REGISTRATION MO-229, VARIATION WEED-5 EXCEPT WHERE NOTED B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LAND PATTERN DIMENSIONS ARE NOMINAL REFERENCE VALUES ONLY E. NOT COMPLIANT MLP10ArevB
Figure 46. 10-pin, 3x3mm Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4 26 www.fairchildsemi.com
1.55 2.00 3.10
FAN5355 -- 1A / 0.8A, 3Mhz. Digitally Programmable TinyBuckTM Regulator
(c) 2008 Fairchild Semiconductor Corporation FAN5355 * Rev. 1.0.4
27
www.fairchildsemi.com

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