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HD74HC590 8-bit Binary Counter/Register (with 3-state outputs) REJ03D0632-0200 (Previous ADE-205-512) Rev.2.00 Mar 30, 2006 Description This device each contains an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR and a count enable input CCKEN. For cascading a ripple carry output RCO is provided. Expansion is easily accomplished by tying RCO of the first stage to CCKEN of the second stage, etc. Both the counter and register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register, Internal circuitry prevents clocking from the clock enable. Features * High Speed Operation: tpd (RCK to Q) = 18.5 ns typ (CL = 50 pF) * High Output Current: Fanout of 15 LSTTL Loads * Wide Operating Voltage: VCC = 2 to 6 V * Low Input Current: 1 A max * Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) * Ordering Information Part Name HD74HC590P HD74HC590FPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) P Package Abbreviation -- EL (2,000 pcs/reel) Taping Abbreviation (Quantity) PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability. Function Table G H L X X X X X X X X X X RCK X X Inputs CCLR X X X X L H H H CCKEN X X X X X L L H CCK X X X X X Function Q output disabled Q output enabled Contents of counter stored to register No change in register Counter clear Count up No count No count X RCO = QA'*QB'*QC'*QD'*QE'*QF'*QG'*QH'* (CCKEN) (QA' to QH': Output of Internal Counter) Rev.2.00 Mar 30, 2006 page 1 of 9 HD74HC590 Pin Arrangement QB 1 QC 2 QD 3 QE 4 QF 5 QG 6 QH 7 GND 8 (Top view) 16 VCC 15 QA 14 C 13 RCK 12 CCKEN 11 CCK 10 CCLR 9 RCO Rev.2.00 Mar 30, 2006 page 2 of 9 HD74HC590 Logic Diagram T Q CCK CCLR CCK T Q REC Out RCK RCK G REC Out RCK RCK G QA CCK CCLR CCK T Q CCK CCLR CCK T Q QB REC Out RCK RCK G QC CCK CCLR CCK T Q CCK CCLR CCK T Q CCK CCLR CCK T Q CCK CCLR CCK T Q REC Out RCK RCK G QD REC Out RCK RCK G QE REC Out RCK RCK G QF REC Out RCK RCK G QG CCK CCLR CCK REC Out RCK RCK G QH CCKEN CCK CCLR RCK G RCO Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Symbol VCC VIN, VOUT IIK, IOK IOUT ICC or IGND PT Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 35 75 500 Unit V V mA mA mA mW Storage temperature Tstg -65 to +150 C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.2.00 Mar 30, 2006 page 3 of 9 HD74HC590 Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time Note: *1 Symbol VCC VIN, VOUT Ta tr , tf Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400 Unit V V C Conditions VCC = 2.0 V ns VCC = 4.5 V VCC = 6.0 V 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Ta = 25C Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 VIL 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL 2.0 4.5 6.0 4.5 Output voltage VOH 6.0 2.0 4.5 6.0 4.5 6.0 VOL 2.0 4.5 6.0 4.5 Off-state output current Input current Quiescent supply current IOZ Iin ICC 6.0 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- Max -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.5 0.1 4.0 Ta = -40 to+85C Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- Max -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 5.0 1.0 40 V V V V Unit V Test Conditions Output voltage VOH V QA to QH IOH = -20 A Vin = VIH or VIL IOH = -6 mA IOH = -7.8 mA QA to QH IOL = 20 A Vin = VIH or VIL IOL = 6 mA IOL = 7.8 mA IOH = -20 A RCO Vin = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 A RCO Vin = VIH or VIL IOL = 4 mA IOL = 5.2 mA A Vin = VIH or VIL, Vout = VCC or GND A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A Rev.2.00 Mar 30, 2006 page 4 of 9 HD74HC590 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = 25C Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 tPLH tPHL tPLH 2.0 4.5 6.0 2.0 4.5 6.0 tPLH tPHL Output enable time Output disable time Pulse width tZL tZH tLZ tHZ tw 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Removal time trem 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 Hold time th 6.0 2.0 4.5 6.0 Output rise/fall time tTLH tTHL tTLH tTHL Input capacitance Cin 2.0 4.5 6.0 2.0 4.5 6.0 -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 5 5 5 100 20 17 200 40 34 5 5 5 -- -- -- -- -- -- -- Typ -- -- -- -- 18 -- -- 17 -- -- 18 -- -- 16 -- -- 17 -- -- 6 -- -- -- -- -- -3 -- -- 10 -- -- -- -- -- 4 -- -- 5 -- 5 Max 5 25 29 200 40 34 250 50 43 200 40 34 150 30 26 150 30 26 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60 12 10 75 15 13 10 Ta = -40 to +85C Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 5 5 5 125 25 21 250 50 43 5 5 5 -- -- -- -- -- -- -- Max 4 20 24 250 50 43 315 63 54 250 50 43 190 39 33 190 38 33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 75 15 13 95 19 16 10 pF ns ns CCK to RCK ns CCLR to CCK ns ns RCK to Q ns CCK to RCO Unit MHz Test Conditions ns CCLR to RCO ns ns Setup time tsu ns CCKEN to CCK ns CCKEN to CCK CCK to RCK Q ns RCO Rev.2.00 Mar 30, 2006 page 5 of 9 HD74HC590 Test Circuit VCC VCC Output 1 k Input QA to QH S1 OPEN GND CL = 50 pF Output RCO 1 k S1 VCC OPEN GND CL = 50 pF TEST t PLH / t PHL t ZH/ t HZ t ZL / t LZ VCC S1 OPEN GND VCC Pulse Generator Zout = 50 Input Pulse Generator Zout = 50 See Function Table CCKEN CCK CCLR RCK G Note : 1. CL includes probe and jig capacitance. Waveforms * Waveform - 1 (CCK to RCO) tr Input CCK 10 % 90 % 50 % 50 % tf VCC 50 % 10 % tw(H) t PHL tw(L) t PLH 90 % 0V Output RCO 90 % 50 % 10 % 50 % 10 % VOH VOL t THL t TLH Note : 1. Input waveform : PRR 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns * Waveform - 2 (CCLR to RCO, CCLR to CCK) tf Input D 90 % 50 % 10 % 50 % 10 % tr 90 % VCC 0V tW t PLH Output RCO 10 % 90 % 50 % VOH VOL 90 % t TLH Output CCK t rem VOH VOL 50 % 10 % t TLH Note : 1. Input waveform : PRR 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns Rev.2.00 Mar 30, 2006 page 6 of 9 HD74HC590 * Waveform - 3 (RCK to Q) tr Input RCK 10 % tf 90 % 50 % 50 % 10 % VCC 50 % tw(H) t PLH 90 % tw(L) t PHL 90 % 50 % 10 % 0V VOH VOL Output QA to QH 50 % 10 % t TLH t THL Note : 1. Input waveform : PRR 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns * Waveform - 4 (CCKEN to CCK) tr Input CCKEN 10 % 90 % 50 % 90 % 50 % 10 % 50 % tf VCC 0V th VCC 50 % 10 % 50 % t su th 90 % t su Input CCK 50 % 10 % 0V tr tf Note : 1. Input waveform : PRR 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns Rev.2.00 Mar 30, 2006 page 7 of 9 HD74HC590 * Waveform - 5 (CCK to RCK) tr Input CCK 10 % 90 % 50 % 10 % 90 % 50 % tf VCC 0V th 90 % t su VCC 50 % 10 % Input RCK 50 % 10 % 0V tr tf Note : 1. Input waveform : PRR 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns * Waveform - 6 (tZL, tZH, tLZ, tHZ) tf Input G 90 % 50 % 10 % t ZL Waveform - A 50 % t ZH Waveform - B 50 % VOL Notes : 1. Input waveform : PRR 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns 2. Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. 10 % t HZ 90 % VOL VOH 10 % t LZ VOH tr 90 % 50 % VCC 0V Rev.2.00 Mar 30, 2006 page 8 of 9 HD74HC590 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g D 16 9 1 0.89 b3 8 Z A1 A E Reference Symbol Dimension in Millimeters Min e bp e1 c ( Ni/Pd/Au plating ) e1 D E A A1 bp b3 c e Z L Nom Max 7.62 19.2 20.32 6.3 7.4 5.06 L 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0 15 2.29 2.54 2.79 1.12 2.54 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B Previous Code FP-16DAV MASS[Typ.] 0.24g *1 D F 9 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp HE E Index mark *2 Terminal cross section ( Ni/Pd/Au plating ) 1 Z e *3 8 bp x M L1 Reference Symbol c Dimension in Millimeters A1 y L Detail F D E A2 A1 A bp b1 c c1 HE e x y Z L L1 Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Rev.2.00 Mar 30, 2006 page 9 of 9 A Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. 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The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. 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