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HD74LV393A
Dual 4-bit Binary Counters
REJ03D0333-0300Z (Previous ADE-205-276A (Z)) Rev.3.00 Jun. 28, 2004
Description
The HD74LV393A contain two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by256 counter. The HD74LV393A is incremented on the high to low transition (negative edge) of the clock input, and each has an independent clear input. When clear is set high all four bits of each counter is set to a low level. This enables count truncation and allows the implementation of divide-by-N counter configurations. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
* * * * * * * VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25C) Output current 6 mA (@VCC = 3.0 V to 3.6 V), 12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information
Package Type SOP-14 pin(JEITA) SOP-14 pin(JEDEC) TSSOP-14 pin Package Code FP-14DAV FP-14DNV TTP-14DV Package Abbreviation FP RP T Taping Abbreviation (Quantity) EL (2,000 pcs/reel) EL (2,500 pcs/reel) ELL (2,000 pcs/reel)
Part Name HD74LV393AFPEL HD74LV393ARPEL HD74LV393ATELL
Note: Please consult the sales office for the above package availability.
Rev.3.00 Jun. 28, 2004 page 1 of 10
HD74LV393A
Function Table
Inputs CLK X H L Note: H: L: X: : : High level Low level Immaterial Low to high transition High to low transition CLR H L L L L Output L No change No change No change Count up
Pin Arrangement
1CLK 1 1CLR 2 1QA 3 1QB 4 1QC 5 1QD 6 GND 7
14 VCC 13 2CLK 12 2CLR 11 2QA 10 2QB 9 2QC 8 2QD
(Top view)
Rev.3.00 Jun. 28, 2004 page 2 of 10
HD74LV393A
Absolute Maximum Ratings
Item Supply voltage range Input voltage range*1 Output voltage range*1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25C (in still air)*3 Storage temperature Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to 7.0 -20 50 25 50 785 500 -65 to 150 Unit V V V mA mA mA mA mW C Conditions
Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
SOP TSSOP
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C.
Recommended Operating Conditions
Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOH Min 2.0 0 0 -- -- -- -- -- -- -- -- 0 0 0 -40 Max 5.5 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 85 Unit V V V A mA Conditions
IOL
A mA
Input transition rise or fall rate
t /v
ns/V
H or L VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V
Operating free-air temperature
Ta
C
Note: Unused or floating inputs must be held high or low.
Rev.3.00 Jun. 28, 2004 page 3 of 10
HD74LV393A
Logic Diagram
D
D
D
D
CLK
CK
R
Q
CK
R
Q
CK
R
Q
CK
R
Q
CLR
QA
QB
QC
QD
Timing Diagram
CLK CLR QA QB QC QD
Rev.3.00 Jun. 28, 2004 page 4 of 10
HD74LV393A
DC Electrical Characteristics
Ta = -40 to 85C Item Input voltage Symbol VIH VCC (V)* 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 0 3.3 Min 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 -- -- -- -- VCC - 0.1 2.0 2.48 3.8 -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.7 Max -- -- -- -- 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 -- -- -- -- 0.1 0.4 0.44 0.55 1 20 5 -- Unit V Test Conditions
VIL
Output voltage
VOH
V
VOL
V
Input current Quiescent supply current Output leakage current Input capacitance
IIN ICC IOFF CIN
A A A pF
IOH = -50 A IOH = -2 mA IOH = -6 mA IOH = -12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VIN = 5.5 V or GND VIN = VCC or GND, IO = 0 VI or VO = 0 V to 5.5 V VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Switching Characteristics
VCC = 2.5 0.2 V Ta = 25C Item Maximum clock frequency Propagation delay time Symbol fmax tPLH/tPHL Min 50 30 -- -- -- -- -- -- -- -- -- -- 6.0 5.0 5.0 Typ 90 60 11.8 15.1 13.4 16.7 14.9 18.2 16.2 19.5 10.8 14.2 -- -- -- Max -- -- 17.7 21.3 20.3 23.9 22.5 26.1 24.2 27.8 14.8 17.4 -- -- -- Ta = -40 to 85C Min 40 25 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 6.0 5.0 5.0 Max -- -- 20.5 24.5 23.5 27.5 26.0 30.0 28.0 32.0 17.0 20.0 -- -- -- Unit MHz ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns ns FROM (Input) TO (Output)
CLK
QA QB QC QD
tPHL Setup time Pulse width tsu tw
CLR
Qn
CLR L before CLK CLR H CLK H or L
Rev.3.00 Jun. 28, 2004 page 5 of 10
HD74LV393A
Switching Characteristics (cont)
VCC = 3.3 0.3 V Ta = 25C Item Maximum clock frequency Propagation delay time Symbol fmax tPLH/tPHL Min 75 45 -- -- -- -- -- -- -- -- -- -- 5.0 5.0 5.0 Typ 120 65 8.6 11.1 10.2 12.7 11.7 14.2 13.0 15.5 7.9 10.4 -- -- -- Max -- -- 13.2 16.7 15.8 19.3 18.0 21.5 19.7 23.2 12.3 15.8 -- -- -- Ta = -40 to 85C Min 65 35 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 5.0 5.0 Max -- -- 15.5 19.0 18.5 22.0 21.0 24.5 23.0 26.5 14.5 18.0 -- -- -- Unit MHz ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CLK QA QB QC QD CLR Qn FROM (Input) TO (Output)
tPHL Setup time Pulse width tsu tw
ns ns
CLR L before CLK CLR H CLK H or L VCC = 5.0 0.5 V
Ta = 25C Item Maximum clock frequency Propagation delay time Symbol fmax tPLH/tPHL Min 125 85 -- -- -- -- -- -- -- -- -- -- 4.0 5.0 5.0 Typ 170 115 5.8 7.3 6.8 8.3 7.7 9.2 8.5 10.0 5.4 6.9 -- -- -- Max -- -- 8.5 10.5 9.8 11.8 11.2 13.2 12.5 14.5 8.1 10.1 -- -- --
Ta = -40 to 85C Min 105 75 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.0 5.0 5.0 Max -- -- 10.0 12.0 11.5 13.5 13.0 15.0 14.5 16.5 9.5 11.5 -- -- -- Unit MHz ns
Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF
FROM (Input)
TO (Output)
CLK
QA QB QC QD
tPHL Setup time Pulse width tsu tw
CLR
Qn
ns ns
CLR L before CLK CLR H CLK H or L
Operating Characteristics
CL = 50 pF Ta = 25C Item Power dissipation capacitance Symbol CPD VCC (V) 3.3 5.0 Min -- -- Typ 12.0 15.0 Max -- -- Unit pF Test Conditions f = 10 MHz
Rev.3.00 Jun. 28, 2004 page 6 of 10
HD74LV393A
Noise Characteristics
CL = 50 pF Ta = 25C Item Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage Low-level dynamic input voltage Symbol VOL (P) VOL (V) VOH (V) VIH (D) VIL (D) VCC = (V) 3.3 3.3 3.3 3.3 3.3 Min -- -- -- 2.31 -- Typ 0.4 -0.4 3.2 -- -- Max 0.8 -0.8 -- -- 0.99 Unit V V V V V Test Conditions
Test Circuit
Measurement point
CL*
Note: C L includes the probe and jig capacitance.
Rev.3.00 Jun. 28, 2004 page 7 of 10
HD74LV393A
* Waveforms - 1
tr 90 % 50 % V CC tw
tf VCC 10 % tf 90 % 50 % V CC t su tr 90 % 50 % V CC tw t PHL VOH VCC 0V 0V
CLR 10 %
CLK
10 % tw t PLH
Qn
50 % V CC
50 % V CC VOL
* Waveforms - 2
tr 90 % 50 % V CC VCC CLK 0V 90 % 50 % V CC
tf VCC 10 % t PHL 0V
CLR 10 %
VOH Qn t PHL VOH Qn 50 % V CC VOL Qn 50 % V CC VOL 50 % V CC VOL t PLH VOH
Notes: 1. Input waveform: PRR 10 MHz, Zo = 50 , t r 3 ns, t f 3 ns 2. The output are measured one at a time with one transition per measurement.
Rev.3.00 Jun. 28, 2004 page 8 of 10
HD74LV393A
Package Dimensions
As of January, 2003
Unit: mm
10.06 10.5 Max 14 8
1
7
5.5
*0.20 0.05
2.20 Max
0.20 7.80 + 0.30 -
1.42 Max
1.15 0 - 8 0.70 0.20
1.27 *0.40 0.06
0.12 M
Package Code JEDEC JEITA Mass (reference value) FP-14DAV -- Conforms 0.23 g
*Ni/Pd/Au plating
0.10 0.10
0.15
As of January, 2003
Unit: mm
8.65 9.05 Max 14 8
1
1.75 Max
*0.20 0.05
7
3.95
6.10 - 0.30 1.08
+ 0.10
0.635 Max
0 - 8
+ 0.11
1.27 *0.40 0.06
0.14 - 0.04
0.60 - 0.20
+ 0.67
0.15 0.25 M
Package Code JEDEC JEITA Mass (reference value) FP-14DNV Conforms Conforms 0.13 g
*Ni/Pd/Au plating
Rev.3.00 Jun. 28, 2004 page 9 of 10
HD74LV393A
As of January, 2003
Unit: mm
5.00 5.30 Max 14 8
1
7 0.65 1.0 0.13 M 6.40 0.20 0.83 Max 0 - 8 0.50 0.10
*0.20 0.05
4.40
*0.15 0.05
1.10 Max
0.10
0.07 +0.03 -0.04
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-14DV -- -- 0.05 g
Rev.3.00 Jun. 28, 2004 page 10 of 10
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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