View M65580MAP-XXXFP_4240166.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M65580MAP-XXXFP
Digital Video/Chroma/Deflection +MCU
REJ03F0184-0201 Rev.2.01 Mar 31, 2008
Description
The M65580MAP-XXXFP are semiconductor integrated circuits designed with CMOS silicon gate technology for NTSC television system, include 8 bit MCU (M37272MA core) with a closed caption decoder and circuits needed for TV base-band signals (Video and Chroma) processor and Deflection in a chip. PCB area and EMI noise can be reduced by one chip and 80QFP, and internal connection of OSD signals. And it can realize an adjustment free system by builtin MCU and get a high performance adaptive YC separation by 1 line memory. The above technology makes its performance more stable and better.
Features
* Y/C processor: 8 bit Input, 10 bit Output digital processing * Deflection processor: optimized system by conventional analog and digital mixed solution * ADC & DAC: 8 bit high speed video ADC & 10 bit high speed video DAC [MCU Block] MCU (single microcomputer) in this IC has almost same function and performance as M37272MA-XXXSP/FP in mass-production. And it is operated by simple instruction in the same memory space as that of built-in ROM, RAM, I/O. It has an OSD, data slicer, and I2C-BUS interface. So it is very useful for a channel selection system for NTSC TV with a closed caption decoder. [ASIC Block] ASIC block consists of the following blocks. (1) Analog front-end block; Analog SW (2 CVBS (TV & EXT) inputs, Y/C signals to one signal, 2 channels 8 bit high speed video ADCs, and ACC amplifiers. (2) Video and Chroma block; A high performance 2 line adaptive YC separation by 1 line memory, Video blocks including sharpness, YNR, a high performance black-stretch circuits, Chroma decoder, and RGB matrix including OSD mixing circuit. (3) Deflection block; A high performance sync separation by analog and digital mixed solution. (4) Analog backend block; 3 channels 10 bit high speed video DACs for Cutoff & Drive, and Mute circuit.
Application
NTSC TV with a closed caption decoder
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 1 of 33
M65580MAP-XXXFP
Block Diagram (Whole)
Chroma APC filter Neck protector V-RAMP OUT
Vdd (VCXO)
Vdd (Input)
Vss (Input)
Vdd (DEF)
AFC1 filter
33 19 21 25 23 42 41 37
44 43 40 35 34
38 39
VZ OUT Vss (Output) Vdd (Output)
27 31 29
HVCO F/B
Vss (DEF)
FBP IN
H OUT
XTAL
Vrb
Vrt
36 12 14 16 26
X-ray Protect Vss (Digital) Vdd (Digital) RESET
17 18
SYNC SEP IN Y SW OUT
24
C IN Y IN EXT IN
Signal processor
22 20
13
CLK-2 OUT
Intelligent Monitor
3 bit Digital OSD
HALF TONE
FAST BLK
46 45
SCL SDA
30 28 15
G OUT R OUT
HD
VD
CLK (fsc) OUT
48 49 51 50 53 56 58 57 55 Vss VCC 1 3 77
OSD (B) IN OSD (G) IN OSD (R) IN FAST BLK OSD H-SYNC FAST BLK OSD (R) OUT OSD (G) OUT OSD (B) OUT HALF TONE OSD V-SYNC OSD V-SYNC HALF TONE 11 59 52 54 47 Intelligent monitor
OSD
FAST BLK
HD
VD
HALF TONE
78
CNVss
To TV IN of ASIC
CV IN
79 80
X IN X OUT FSC IN
CCD
75
HLF
MCU core M37272MA
5 6 2 RESET RESET FILT
76 SCL SDA P12/SCL2
VHOLD
2in1 Tuner
60 62 61
10
P15/AD1/INT3 P20/SCLK/AD6 P21/S OUT/AD7
I/O port
9 8
EEPROM
63 64 65 66 67 68 69 70 71 72 73 74
4
7
P05/AD3
P14/SDA2
P00/PWM0
P01/PWM1
P02/PWM2
P03/PWM3
P04/PWM4
P06/INT2/AD4
P07/INT1
P23/TIM3
P24/TIM2
P25/AD5
P27/XCOUT
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 2 of 33
P22/S IN/AD8
RGB OUT
32
B OUT
CVBS/YC input
TV IN
M65580MAP-XXXFP
Pin Arrangement
P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/AD3 P06/INT2/AD4 P07/INT1 P23/TIM3 P24/TIM2 P25/AD5 HLF VHOLD CV IN CN VSS X IN X OUT 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 3 of 33
M65580MAP-XXXFP (Top view) Outline: PRQP0080GB-A (80P6N-A)
VSS FILT VCC P27/XCOUT P26/FSCIN/XCIN RESETB P22/SIN/AD8 P21/SOUT/AD7 P20/SCLK/AD6 P15/AD1/INT3/FSCIN P16/AD2/TIM2 VSS (DIGITAL) OSD CLK VDD (DIGITAL) CLK OUT RESETB (ASIC) SYNC SEP IN Y SW OUT VDD (INPUT) EXT IN VSS (INPUT) Y IN VRT C IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P00/PWM0 P14/SDA2 P13/SDA1 P12/SCL2 P11/SCL1 P10/OUT2 P31/B P30/G P53/OUT1 P52/R P51/VSYNC P50/HSYNC IN/OUT V-PULSE OUT OSD (R) IN FAST BLK OSD (G) IN OSD (B) IN HALF TONE SCL SDA H OUT FBP IN VDD (DEF) VSS (DEF)
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NECK PROTECTOR HVCO F/B V-RAMP OUT AFC1 FILTER X-RAY PROTECT X-TAL CHROMA APC FILTER VDD (VCXO) B OUT VSS (OUTPUT) G OUT VDD (OUTPUT) R OUT VZ OUT TV IN VRB
M65580MAP-XXXFP
Pin Description
Pin No. 1 2 Name Vss (MCU) FILT Peripheral Circuit of Pins -- Note Power source for MCU. 0V
2
Y
3 4 5
VCC (MCU) P27/XCONT P26/FSCIN/XCIN
--
Power source for MCU. 5.0 V 5%
4
5
6
RESETB
Y
6
CMOS INPUT (Impedance > 100 k) VOL = 0 V: Reset state VOH = 5 V: Release from reset state
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 4 of 33
M65580MAP-XXXFP
Pin No. 7 8 9 10
Name P22/SIN/AD8 P21/SOUT/AD8 P20/SCLK/AD6 P15/AD1/INT3/FSCIN
C
Peripheral Circuit of Pins
A
Note CMOS IN/OUT 1 Impedance > 100 k (input) Impedance 250 (output)
Y
11
P16/AD2/TIM2
C 11 A
CMOS IN/OUT 1 Impedance > 100 k (input) Impedance 250 (output) Intelligent monitor output (Analog/Digital)
Y
12 13
Vss (Digtal) OSD CLK
C
--
0V CMOS IN/OUT 1 Impedance > 100 k (input) Impedance < 100 (output)
13 A
Y
14
Vdd (Digital)
--
Power source for digital block. 5.0 V 5%
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 5 of 33
M65580MAP-XXXFP
Pin No. 15
Name CLK OUT
Peripheral Circuit of Pins
Note Impedance 400
ESD Protect
15
16
RESET
16
CMOS INPUT (Impedance > 100 k) VIL = 0 V: Reset state VIH = 5 V: Release from reset state
Y
17
C.Sync IN
ESD Protect
Sync Sep. input impedance = N.A. DC 2.5 V
17
18
CVBS OUT
Impedance 150 DC: 0.55 V (sync) AC: 1.75 Vp-p (typ.)
18
19 20 22 26
Vdd (Input) EXT (CVBS) IN Y IN TV (CVBS) IN
--
Power source for A/D etc. 3.3 V 5% Impedance = N.A. DC: 0.5 V (sync) AC: 1.0 Vp-p (typ.)
20 22 26
21
Vss (Input)
--
Power source for A/D etc. 0V
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 6 of 33
M65580MAP-XXXFP
Pin No. 23 25
Name VRT VRB
Peripheral Circuit of Pins
Note Impedance > 50 DC: 1.7 V (VRT) 0.5 V (VRB)
23
25
24
C IN
Impedance 7.5 k DC: 1.0 V AC: 0.286 Vp-p (burst)
24
27
VZ OUT
Impedance 400 DC: 2.05 V
27
28 30 32
R OUT G OUT B OUT
Impedance 1 k DC: 3 V (blanking)
28 30 32
29 31 33
Vdd (Output) Vss (Output) Vdd (VCXO)
-- -- --
Power source for D/A etc. 3.3 V 5% Power source for D/A etc. 0V Power source for VCXO etc. 5.0 V 5%
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 7 of 33
M65580MAP-XXXFP
Pin No. 34
Name APC Filter
Peripheral Circuit of Pins
34
Note Impedance = N.A. (Additional filter on PCB Board) DC: 2.9 V
35
X'tal
Impedance 1 k
35
36
X-ray Protector
ESD Protect
36
Impedance > 100 k 0.0-3.0: Normal 3.2-3.3: Hold down 3.7-5.0: Shut down
37
AFC1 Filter
Impedance = N.A. (Additional filter on PCB Board) DC: 2.5 V
37
38
V RAMP OUT
Impedance 400 2.5 Vp-p (typ.)
38
39
HVCO F/B
Impedance = N.A. (Additional filter on PCB Board) DC: 3.0 V
39
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 8 of 33
M65580MAP-XXXFP
Pin No. 40
Name Neck Protector
Peripheral Circuit of Pins
40
Note Impedance 5 k 0.0-1.0: RGB off 1.6-3.0: Normal 4.0-5.0: Test mode
41
Vss (DEF)
--
Power source for deflection block. 0V Power source for deflection block. 5.0 V 5% CMOS IN/OUT 1 Impedance > 100 k (input) Impedance < 100 (output) VIL = 0 V: RGB output VIH = 5 V: Blanking
42
Vdd (DEF)
--
43
FBP IN
C 43 A
Y
44
H OUT
C 44 A
CMOS IN/OUT 1 Impedance > 100 k (input) Impedance < 100 (output) VOL = 0 V VOH = 5 V
Y
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 9 of 33
M65580MAP-XXXFP
Pin No. 45
Name SDA
C A
Peripheral Circuit of Pins
45
Note CMOS IN/OUT 2 Impedance > 100 k (input) Impedance < 100 (output) VIL = 0 V VIH = 5 V
Y
S
46
SCL
Y
S
46
CMOS Schmitt IN Impedance > 100 k VIL = 0 V VIH = 5 V
47
Half Tone IN
C 47 A
CMOS IN/OUT 1 Impedance > 100 k (input) Impedance < 100 (output) VIL = 0 V: RGB output VIH = 5 V: Half tone on
Y
48 49 51
OSD (B) IN OSD (G) IN OSD (R) IN
C
A
48 49 51
CMOS IN/OUT 1 Impedance > 100 k (input) Impedance < 100 (output) VIL = 0 V VIH = 5 V
Y
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 10 of 33
M65580MAP-XXXFP
Pin No. 50
Name Fast BLK IN
C
Peripheral Circuit of Pins
50 A
Note CMOS IN/OUT 1 Impedance > 100 k (input) Impedance < 100 (output) VIL = 0 V: RGB output VIH = 5 V: OSD output
Y
52
V sync OUT
C 52 A
CMOS IN/OUT 1 Impedance > 100 k (input) Impedance < 100 (output) VOL = 0 V VOH = 5 V
Y
53
H sync OUT
C 53 A
CMOS IN/OUT 1 Impedance > 100 k (input) Impedance < 100 (output) VOL = 0 V VOH = 5 V
Y
54
P51/VSYNC
CMOS INPUT Impedance > 100 k
Y 54
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 11 of 33
M65580MAP-XXXFP
Pin No. 55 56 57 58 59
Name P52/R P53/OUT1 P30/G P31/B P10/OUT2
C
Peripheral Circuit of Pins
A
Note CMOS IN/OUT 1 Impedance > 100 k (input) Impedance < 100 (output)
Y
60 61 62 63
P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2
C
A
CMOS IN/OUT 1 Impedance > 100 k (input) Impedance 250 (output)
Y
64 65 66 67 68
P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4
CMOS IN/OUT Impedance > 100 k (input) Impedance 250 (output)
Y
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 12 of 33
M65580MAP-XXXFP
Pin No. 69 70
Name P05/AD3 P06/INT2/AD4
Peripheral Circuit of Pins
Note CMOS IN/OUT Impedance > 100 k (input) Impedance 250 (output)
Y
71
P07/INT1
71
CMOS IN/OUT Impedance > 100 k (input) Impedance 250 (output)
Y
72 73
P23/TIM3 P24/TIM2
C
A
CMOS IN/OUT 1 Impedance > 100 k (input) Impedance < 100 (output)
Y
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 13 of 33
M65580MAP-XXXFP
Pin No. 74
Name P25/AD5
C
Peripheral Circuit of Pins
74 A
Note CMOS IN/OUT 1 Impedance > 100 k (input) Impedance 250 (output)
Y
75
HLF
Impedance = N.A. (Additional filter on PCB board)
75
76
VHOLD
76
77
CV IN
77
78
CN VSS
78
CMOS IN/OUT Impedance > 100 k (input) Impedance 250 (output)
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 14 of 33
M65580MAP-XXXFP
Pin No. 79 80
Name X IN X OUT
Peripheral Circuit of Pins
Note
79
80
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 15 of 33
M65580MAP-XXXFP
Absolute Maximum Ratings
Item Supply voltage (MCU) Supply voltage (ASIC 5 V) Supply voltage (ASIC 3.3 V) Input voltage (MCU) Output voltage (MCU) Circuit current (MCU) Circuit current (P00-P07, P10, P15, P16, P20-P27, P30, P31, P52, P53) Circuit current (P11-P14) Digital input voltage Analog output current Power dissipation Thermal derating Operating temperature Storage temperature Symbol VDD (MCU) VDD (ASIC 5 V) VDD (ASIC 3.3 V) VI (MCU) VO (MCU) IOH (MCU) IOL1 (MCU) IOL2 (MCU) VID (ASIC) IOUT (ASIC) Pd K Topr Tstg Ratings -0.3 to 6.0 -0.3 to 6.0 -0.3 to 4.0 -0.3 to VCC+0.3 -0.3 to VCC+0.3 0 to 1Note1 0 to 2Note2 0 to 6Note2 -0.3 to VCC+0.3 -30 1460 14.6 -20 to 65 -40 to 125 Unit V V V V V mA mA mA V mA mW mW/C C C Conditions All voltage are based on Vss. Output transistors are cut off.
Notes: 1. The total current that flows out the MCU must be 20 mA or less. 2. The total input current to MCU (IOL1 + IOL2) must be 30 mA or less.
Thermal Derating (Maximum Rating)
2.0
Power Dissipation Pd (W)
1.5
1.46
1.0
0.88
0.5
0
0
25
50
65
75
100
125
150
Ambient Temperature Ta (C)
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 16 of 33
M65580MAP-XXXFP
Recommended Operating Condition
(Ta = -20 to 65C, unless otherwise noted)
Item Supply voltage (MCU) Supply voltage (Digital) Supply voltage (Input) Supply voltage (Output) Supply voltage (VCXO) Supply voltage (DEF) High input voltage High input voltage High input voltage Low input voltage Low input voltage Low input voltage Note4 Low input voltage High average output Note1 current Low average output Note2 current Low average output Note2 current Oscillation frequency Note5 (for CPU operation) Oscillation frequency (for sub-clock operation) Oscillation frequency (for OSD standard clock) Input frequency Input frequency Input frequency Input amplitude video signal
Note3
P00-P07, P10-P16, P20-P27, P50, P51, RESETB, XIN SCL1, SCL2, SDA1, SDA2 2 (When using I C-Bus) RESETB, FBP IN, HALF TONE, OSD (R/G/B) IN, FAST BLK P00-P07, P10-P16, P20-P27 SCL1, SCL2, SDA1, SDA2 2 (When using I C-Bus) P50, P51, RESETB, XIN, TIM2, TIM3, INT1, INT2, INT3, SIN, SCLK RESETB, FBP IN, HALF TONE, OSD (R/G/B) IN, FAST BLK P10-P16, P20-P27, P30, P31, P52, P53 P00-P07, P10, P15, P16, P20-P27, P30, P31, P52, P53 P11-P14 XIN XCIN FSCIN TIM2, TIM3, INT1, INT2, INT3 SCLK SCL1, SCL2 CVIN
Symbol VDD (MCU) VDD (Digital) VDD (Input) VDD (Output) VDD (VCXO) VDD (DEF) VIH1 (MCU) VIH2 (MCU) VIH3 (ASIC) VIL1 (MCU) VIL2 (MCU) VIL3 (MCU) VIL4 (ASIC) IOH (MCU) IOL1 (MCU) IOL2 (MCU) f(XIN) (MCU) f(XCIN) (MCU) FSCIN (MCU) fhs1 (MCU) fhs2 (MCU) fhs3 (MCU) VI (MCU)
Min 4.75 4.75 3.13 3.13 4.75 4.75 0.8 VCC 0.7 VCC 0.8 VCC 0 0 0 0 -- -- -- 7.9 29 -- -- -- -- 1.5
Typ 5.0 5.0 3.3 3.3 5.0 5.0 -- -- -- -- -- -- -- -- -- -- 8.0 32 3.58 -- -- -- 2.0
Max 5.25 5.25 3.47 3.47 5.25 5.25 VCC VCC VCC 0.4 VCC 0.3 VCC 0.2 VCC 0.2 VCC 1 2 6 8.1 35 -- 100 1 400 2.5
Unit V V V V V V V V V V V V V mA mA mA MHz kHz MHz kHz MHz kHz V
Notes: 1. The total current that flows out the MCU must be 20 mA or less. 2. The total input current to MCU (IOL1 + IOL2) must be 30 mA or less. 3. Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 4. Pin name in each parameter is described pin names. (1) Dedicated pins: dedicated pin name. (2) Double-/Triple-function ports. When the same limits: I/O port name. When the limits of function except ports are different from I/O port limits; function pin name. 5. P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer pins. 2 P11-P14 have the hysteresis when these pins are used as multi-master I C-Bus interface ports. P20-P22 have the hysteresis when these pins are used as serial I/O pins.
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 17 of 33
M65580MAP-XXXFP
[MCU Block (M37272MA)]
Description MCU (single microcomputers) in this IC has almost same function and performance as M37272MA-XXXSP/FP in mass production. And it is operated by simple instruction in the same memory space as that of built-in ROM, RAM, I/O. It has an OSD, data slicer, and I2C-BUS interface, so it is very useful for a channel selection system for NTSC TV with a closed caption decoder. Features * Number of basic instructions ......... 71 * Memory size ROM ......... 40 Kbytes RAM ......... 1152 bytes (ROM correction memory: 64 bytes included) * Minimum instruction execution time ......... 0.5 s (at 8 MHz oscillation frequency) * Power source voltage ......... 5 V 10% * Subroutine nesting ......... 128 levels (max.) * Interrupts ......... 17 bytes 16 vector * 8-bit timers ......... 6 * Programmable I/O ports (Ports P0, P1, P2) ......... 23 * Input ports (Ports P50, P51) ......... 2 * Output ports (Ports P30, P31, P52, P53) ......... 4 * Serial I/O ......... 8-bit x 1channel 2 * Multi-master I C-BUS interface ......... 1 (2 systems) * A/D comparator (7-bit resolution) ......... 8 channels * PWM output circuit ......... 8-bit x 5 * ROM correction function ......... 32 bytes x 2 Power dissipation ......... 165 mW (at VCC = 5.5 V, 8 MHz oscillation frequency, OSD on, and Data slicer on) * Closed caption data slicer * OSD function Display characters ......... 32 characters x 2 lines (possible to display 3 lines or more by software) Kinds of characters 254 kinds Character display area CC mode: 16 x 26 dots OSD mode: 16 x 20 dots Kinds of character sizes CC mode: 1 kind OSD mode: 8 kinds Kinds of character colors 8 colors (R, G, B) (coloring unit: a character) Kinds of background colors CC mode: 1 kind (black) OSD mode: 8 kinds (possible to select color in character unit) Display position horizontal: 128 levels, Vertical: 512 levels Attribute CC mode: smooth italic, underline, flash, automatic solid space OSD mode: border (black) Kinds of raster colors 8 kinds Smooth roll-up Window function
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 18 of 33
M65580MAP-XXXFP
[ASIC Block]
Description CVBS (TV/EXT) signals or Y/C signals input to this IC are converted to 8 bit digital signal by 2 channels high speed video ADCs. These signals are input to digital section to obtain high performance R/G/B signals. First, CVBS signals are separated to high quality Y/C signals by 2 dimensional adaptive YC separation circuit, and then Y/C signals are converted to R-Y & B-Y signals by digital chroma decoder, after that, to R/G/B signals by RGB matrix circuit. These signals are mixed with OSD signals come from MCU block, are converted to analog R/G/B signals by 3 channel 10 bit high speed video DACs. In deflection block, to get a better Horizontal & Vertical signals, a conventional analog solution by analog CMOS technology is used. ASIC block consists of the followings blocks. (1) Analog front-end block; Analog SW (2 CVBS (TV & EXT) inputs, Y/C signals to one signal), 2 channels 8 bit high speed video ADCs, and ACC amplifiers. (2) Video and Chroma block; A high performance 2 line adaptive YC separation by 1 line memory, Video blocks including sharpness, YNR, a high performance black-stretch circuits, Chroma decoder, and RGB matrix including OSD mixing circuit. (3) Deflection block; A high performance sync separation by analog and digital mixed solution. (4) Analog backend block; 3 channels 10 bit high speed video DACs for Cutoff & Drive, and Mute circuit. Features [Video/Chroma Block] * * * * * * * * * * * * * Built-in 1 Video SW for TV/EXT signal input 2 additional pins for S (Y/C) input YUV input signal available (T.B.D) 2 channel 8 bit Video ADCs for CVBS (TV & EXT) or Y/C signal inputs Built-in adaptive 2 line comb filter (2DYCS) Few dot crawl & cross-color, and clear color transition Built-in a high performance Black-stretch Dynamic & detailed picture Digital Luminance delay circuit stable Y/C timing adjustment Built-in VCXO circuit (4 fsc) High resolution R/G/B output Built-in 10 bit high speed Video DACs Internal connection of 8 color digital OSD (R/G/B, F.B, H.T) Reference CLK output for tuner (fsc or 4 MHz) Built-in YNR (about fsc 1 MHz) Gamma correction (for R/G/B signals)
[Deflection Block] * * * * * Analog (conventional) sync separation Double AFC Circuit Built-in Horizontal reference Oscillator HD and VD pulse by Countdown Built-in digital Vramp generator Better performance by abundant experience Stable Horizontal scanning No ceramic resonator and Adjustment free Stable HD & VD
[List of Main I2C Bus Controllable Items] * * * * * * * Chip: Analog Input Stage: Luminance Processing: Chroma Processing: RGB Matrix: Analog Output Stage: Deflection Block: Power-down mode CVBS/Y & C Input SW Sharpness, Black-stretch Color, Tint, Killer level ACL, OSD Input Level, Contrast, Brightness Drive adj.(R/G/B), Cutoff adj.(R/G/B) H-Phase, V-size, V-shift, V-Linearity
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 19 of 33
From MCU
To MCU for CCD F.B in Vz out + H.T in Vrt = 1.7 V Vss (Dig) 14 50 29 + (Contrast, Sharpness Delaytime, Black stretch) Ref. current 31 Vss (output) 28 R-out Drive Y-processing Cutoff Drive HPF 2DYCS by 1H SW (Color&Tint&Killeroff) 10b-DAC Cutoff SW C-processing 8b-ADC Drive 10b-DAC C-signal (Slice level) (AFC1 gain) Cutoff (Halftone, Blueback, ACL, Mute) H AFC2 (Drive, Cutoff) 39 H AFC1 37 + H-AFC2 & H out pulse gen. 44 42 43 (V-shift) To digital block 1/4 BGP 38 VSYNC SEP V countdown P.D Burst gate X-ray Protect 1/m (Vsize, Linearity, Service SW) V-ramp gen. 41 VCXO C.P GND (Def.) V-out (H-Phase, H-STOP) F.B.P in Vdd (Def.) =5V + H-out 32 B-out RGB processor (Inc.MTX) 30 G-out 10b-DAC 47 47 & 49 & 51 12 27 33 Vdd (output) = 3.3 V 18 (TV/EXT/YC SW) (CVBS/YC SW) x2 Y-signal TV EXT 8b-ADC 1H Y/C CVBS 25 23 Vdd (VCXO) =5V OSD (RGB) in
Vdd (input) = 3.3 V Vdd (Dig) =5V + Vrb = 0.5 V
+
V-SW out (2 Vp-p)
M65580MAP-XXXFP
Vss (input)
19
21
Clamp
TV Iin 1.23 Vp-p( typ.)
20
Clamp
ASIC Block Detailed Diagram
EXT in 1.23 Vp-p (typ.)
22
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 20 of 33
(CVBS/YC SW) "OFF" @ Y/C input Sync sepa. I2C BUS CNTL BGP 14.3 MHz (Reference CLK) H-AFC1 HVCO H countdown 35 X'tal Chroma APC filter + 34 13 40 36 53 52 + CLK-2 out Neck protector F.B.P To MCU : Pins connected to MCU block HD out VD out : Pins connected to external
Clamp
Yin 1 Vp-p (typ.)
24
BIAS
Cin 0.7 Vp-p (typ.)
26
(Monitoring)
Sync Sep in
17
To MCU
11
Intelligent monitoring
From MCU
45
SDA (5 V I/F) SCL (5 V I/F)
46
I2C receiver
Vdd
Reset
Reset IC M51953AL
16
1/4
15
CLK (fsc) out
To MCU & Tuner
M65580MAP-XXXFP
Function and Outline of ASIC Block
Chip Power down mode: Service SW: Analog Block * Input stage CVBS & Y/C input signals Input level (CVBS): 1.23 Vp-p (173 IRE) @max. / 1.0 Vp-p @typ. Input level (Y/C): Y: 1.00 Vp-p (140 IRE) @typ. / C: 0.7 Vp-p @typ. * Output stage RGB output signals Output level: 0.7 Vp-p (typ.) Drive (R & G & B): -3 to +4 dB by 7 bit (White Balance) Cutoff (R & G & B): 0.5 V by 9 bit (Start lighting point) Digital Block * 2DYCS Adaptive YC separation by using of 1H line memory and original algorithm * Luminance processing Contrast: 0 to 200 LSB by 7 bit Brightness: -20 to 20 LSB by 8 bit (Pedestal DC level) Sharpness: 0 to 3 dB by 5 bit (by 0, 70, 140, 210 ns) Delay adjustment: 0 to 210 ns by 2 bit (70 ns step) to Chroma signal Black-stretch: 3 selectable stretch point [Stretch areas (0 to 25/30/40 IRE), through areas (25/30/40 IRE )] 4 selectable black-stretch curves (1/4, 2/4, 3/4, 4/4) * Chroma processing Tint: -45 to 45 degree by 7 bit about 0.7 degree Variable demodulator (R-Y) axis (-22.5 to +22.5 degree by 6 bit about 0.7 degree) Color: 0 to 200% by 7 bit * RGB matrix Matrix (R-Y signal) ratio selectable (12/8, 13/8, 14/8) ACL: Automatic Contrast Limiter by MCU port (ADC) and I2C bus EXT/RGB: clip to 7 LSB @ data < 0Fh BlueBack: ON/OFF selectable Mute: ON/OFF of R/G/B output Neck Protector: R/G/B output to zero (no signal) Deflection Block * Horizontal Output AFC2 phase: Hold Shut down: AFC1 gain: * Vertical Output V position: V size: Linearity: +5 to -5 s by 5 bit fh@Hold-down: in about 16.5 kHz fh@Shutdown: H-STOP Normal/High selectable for VTR skew 0 to 16 H by 3 bit 2H unit (connected with BLK) 1.4 to 2.6 V by 7 bit 0 to 30% by 7 bit 3 modes [PD0 & PD1 & PD2] stop of Vertical (Vramp) output (For cutoff adjustment)
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 21 of 33
M65580MAP-XXXFP
Electrical characteristics
(Ta = 25C, Vdd = 5.0 V, 3.3 V)
Limits Item Standard conditions 5.0 V supply current 3.3 V supply current Standard conditions of video character Video SW output level (TV input) Video SW output level (External input) Video standard output Video frequency characteristics Y/C separation function 1 Y/C separation function 2 Y/C separation function 3 Y total delay time Y delay time 1 Y delay time 2 Y delay time 3 Video tone control characteristic 1 Video tone control characteristic 2 Video tone control characteristic 3 Black-stretch characteristic Half Tone function Symbol ICC ICC50 ICC33 VIDEO 2AGTV 2AGEV Vtyp FBY Y/C1 Y/C2 Y/C3 YDL0 YDL1 YDL2 YDL3 GTnor GTmax GTmin BLS Min -- 102 47 -- 1.5 1.5 590 -3 -- -3 -- 2.4 50 50 50 640 1 -7 20 Typ -- 116 56 -- 1.7 1.7 740 0 -30 0 -30 3.0 70 70 70 800 2.5 -4 50 Max -- 130 65 -- 1.9 1.9 890 3 -20 3 -20 3.6 90 90 90 960 4 -1 80 Unit -- mA mA -- Vp-p Vp-p mVp-p dB dB dB dB s ns ns ns mV dB dB mV Input Signal Pins -- -- -- -- 26 20 26 26 26 26 26 26 26 26 26 26 26 26 26 SG -- -- -- -- SG.A SG.A SG.A SG.B SG.E SG.E SG.E SG.A SG.A SG.A SG.A SG.B SG.B SG.B SG.D Test Point -- 3, 14, 33, 42 18, 29 -- 18 18 28, 30, 32 28, 30, 32 28, 30, 32 28, 30, 32 28, 30, 32 28, 30, 32 28,30, 32 28,30, 32 28,30, 32 28,30, 32 28,30, 32 28,30, 32 28,30, 32 28,30, 32 YDL1 = measure - YDL0 YDL2 = measure - YDL1 YDL3 = measure - YDL2 f = 2.5 MHz f = 2.5 MHz f = 2.5 MHz Vy = 0.18 V, 45H = 80h (BLS ON) / 00h (BLS OFF) f = 5 MHz feb = fec = fsc feb = fsc, fec = fsc 1/2fH feb = fsc, fec = fsc fH Supply of MCU, Digital, VCXO and Deflection Supply of A/D and D/A Remarks
HT
-9
-6
-3
dB
26
SG.A
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 22 of 33
M65580MAP-XXXFP
Electrical characteristics (cont.)
Limits Item Standard condition of chroma parameter Chroma standard output (R-Y) Chroma standard output (B-Y) ACC characteristic 1 ACC characteristic 2 Killer operation input level Color residual at killer on APC pull-in range (upper) APC pull-in range (lower) Demodulated output ratio Demodulation phase angle Color control characteristic 1 Color control characteristic 2 TINT control characteristic 1 TINT control characteristic 2 CLK output frequency CLK output amplitude Symbol
CHROMA
Input Signal Max -- 205 345 3 3 -30 -28 -- -400 0.67 95 240 10 60 -30 3.580 650 Unit -- mV mV dB dB dB dB Hz Hz -- deg % % deg deg MHz mVp-p Pins -- 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 SG -- SG.E SG.E SG.E SG.E SG.E SG.E SG.E SG.E SG.E SG.F SG.E SG.E SG.F SG.F SG.C SG.C
Min -- 155 275 -3 -3 -40 -- 400 -- 0.47 85 160 -- 30 -60 3.578 350
Typ -- 180 310 0 0 -35 -40 -- -- 0.57 90 200 0 45 -45 3.579 500
Test Point -- 28 32 28 28 28 28 28 28 28, 32 28, 32 28 28 28, 32 28, 32 15 15
Remarks 5DH = 03h feb = fec + 50 kHz feb = fec + 50 kHz Veb, Vec: +6 dB of typical input level Veb, Vec: -20 dB of typical input level Veb, Vec: variable Veb = 0 mV feb = fec: variable feb = fec: variable feb = fec + 50 kHz feb = fec + 50 kHz feb = fec + 50 kHz
CnorR CnorB ACC1 ACC2 VikN KillP APCU APCL DEMR DEMP Ccon 1 Ccon 2 TC1 TC2 Fclk Vclk
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 23 of 33
M65580MAP-XXXFP
Electrical characteristics (cont.)
Limits Item Standard condition of RGB parameter Output pedestal voltage Matrix ratio R/B Matrix ratio G/B Contrast control characteristic 1 Contrast control characteristic 2 Contrast control characteristic 5 Brightness control characteristic 2 Brightness control characteristic 3 R Drive control characteristic 1 G Drive control characteristic 1 B Drive control characteristic 1 R Drive control characteristic 2 G Drive control characteristic 2 B Drive control characteristic 2 R Cut off control characteristic 1 G Cut off control characteristic 1 B Cut off control characteristic 1 R Cut off control characteristic 2 G Cut off control characteristic 2 B Cut off control characteristic 2 OSD (R) output level OSD (G) output level OSD (B) output level OSD speed characteristic 1 OSD speed characteristic 2 Offset voltage between R and OSD (R) Offset voltage between G and OSD (G) Offset voltage between B and OSD (B) Neck protector function threshold voltage Symbol RGB VPED MTXRB MTXGB GYmax GYmin GYEclip Lum max Lum min D (R) 1 D (G) 1 D (B) 1 D (R) 2 D (G) 2 D (B) 2 C (R) 1 C (G) 1 C (B) 1 C (R) 2 C (G) 2 C (B) 2 OSD (R) OSD (G) OSD (B) SOSD1 SOSD2 OFF (R) OFF (G) OFF (B) NECK Min -- 2.7 0.74 0.24 160 -- 250 100 -200 1.5 1.5 1.5 -4.6 -4.6 -4.6 210 210 210 -310 -310 -310 500 500 500 -- -- -50 -50 -50 1.0 Typ -- 3.0 0.92 0.33 200 0 300 150 -150 3.5 3.5 3.5 -2.6 -2.6 -2.6 260 260 260 -260 -260 -260 600 600 600 100 100 0 0 0 1.3 Max -- 3.3 1.10 0.42 240 10 350 200 -100 5.5 5.5 5.5 -0.6 -0.6 -0.6 310 310 310 -210 -210 -210 700 700 700 200 200 50 50 50 1.6 Unit -- V -- -- % % mV mV mV dB dB dB dB dB dB mV mV mV mV mV mV mVp-p mVp-p mVp-p ns ns mV mV mV V Input Signal Pins -- 26 26 26 26 26 48, 49, 51 26 26 26 26 26 26 26 26 26 26 26 26 26 26 51 49 48 48, 49, 51 48, 49, 51 -- -- -- 26 SG -- SG.D SG.H SG.H SG.D SG.D SG.G SG.D SG.D SG.D SG.D SG.D SG.D SG.D SG.D SG.D SG.D SG.D SG.D SG.D SG.D SG.G SG.G SG.G SG.G SG.G -- -- -- SG.A Test Point -- 28, 30, 32 28, 32 30, 32 28, 30, 32 28, 30, 32 28, 30, 32 28, 30, 32 28, 30, 32 28 30 32 28 30 32 28 30 32 28 30 32 28 30 32 28, 30, 32 28, 30, 32 -- -- -- 40 Difference at pedestal level Difference at pedestal level Difference at pedestal level While monitoring at pins 28, 30, 32 Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.286 V Vy = 0.0 V Remarks
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 24 of 33
M65580MAP-XXXFP
Electrical characteristics (cont.)
Limits Item Standard condition of deflection parameter Horizontal free-running frequency 1 Horizontal free-running frequency 2 Horizontal free-running frequency 3 Horizontal pull-in range (upper) Horizontal pull-in range (lower) Horizontal pulse amplitude Horizontal pulse width Horizontal pulse duty cycle Horizontal pulse timing 1 Horizontal pulse timing 2 Horizontal pulse timing variable range Hold down function threshold voltage Shut down function threshold voltage Vertical free-running frequency Service mode function Vertical pull-in frequency (upper) Vertical pull-in frequency (lower) Vertical ramp size Vertical ramp size control range 1 Vertical ramp size control range 2 Vertical ramp linearity control range 1 Vertical ramp linearity control range 2 Vertical ramp position control range 1 Vertical ramp position control range 2 Vertical pulse width Vertical blanking width Minimum vertical sync detection width Symbol DEF fH1 fH2 fH3 FPHU FPHL HPV HPTW HPD HPT1 HPT2 HPT3 HDOWN SDOWN fV SVC FPVU FPVL VRsi 1 VRsc 1 VRsc 2 VLin 1 VLin 2 VRpo 1 VRpo 2 VW VBLKW WVSS Min -- 15.53 13.72 17.25 250 -- 4.0 19.3 30 8.7 2.2 4.5 3.0 3.3 55 2.5 -- 57 2.1 20 -35 -5 19 0 790 0.35 1.52 13 Typ -- 15.73 14.32 17.85 500 -500 4.5 22.3 35 10.7 4.2 6.5 3.1 3.5 60 2.8 -- -- 2.5 27 -27 0 24 50 940 0.53 1.64 18 Max -- 15.93 14.92 18.45 -- -250 5.0 25.3 40 12.7 6.2 8.5 3.2 3.7 65 3.1 63 -- 2.9 35 -20 5 29 200 1090 0.65 1.76 23 Unit -- kHz kHz kHz Hz Hz V s % s s s V V Hz V Hz Hz Vp-p % % % % s s ms ms s Input Signal Pins -- -- -- -- 17 17 26 26 26 26 26 26 26 26 -- -- 17 17 26 26 26 26 26 26 26 26 26 26 SG -- -- -- -- SG.I SG.I SG.A SG.A SG.A SG.A SG.A SG.A SG.A SG.A -- -- SG.J SG.J SG.A SG.A SG.A SG.A SG.A SG.A SG.A SG.A SG.A SG.A Test Point -- 44 44 44 44 44 44 44 44 44 44 44 36 36 38 38 38 38 38 38 38 38 38 38 38 52 28, 30, 32 11 (Measured value) - (Vrpo 1) Vary frequency of input signal. Vary frequency of input signal. HPT2 - HPT1 While monitoring at pin 44 While monitoring at pin 44 Vary frequency of input signal. Vary frequency of input signal. Remarks
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 25 of 33
M65580MAP-XXXFP
Electrical Characteristics (MCU Part)
(VCC = 5 V 10%, Vss = 0 V, f (XIN) = 8 MHz, Ta = -20C to 65C, unless otherwise noted)
Limits Item Power source current System operation Symbol ICC Min -- -- -- Typ 15 30 60 Max 30 45 200 A f (XCIN) = 32 kHz, OSD OFF, Data slicer OFF, Low-power dissipation mode set (CM5 = "0", CM6 = "1") Wait mode -- -- 2 25 4 100 mA A VCC = 5.5 V, f (XIN) = 8 MHz VCC = 5.5 V, f (XIN) = 0, f (XCIN) = 32 kHz, Low-power dissipation mode set (CM5 = "0", CM6 = "1") -- HIGH output voltage LOW output voltage P10-P16, P20-P27, P30, P31, P52, P53 P00-P07, P10, P15, P16, P20-P27, P30, P31, P52, P53 LOW output voltage Hysteresis
Note1
Unit mA
Test Circuit 1
Test Conditions VCC = 5.5 V, f (XIN) = 8 MHz OSD OFF Data slicer OFF OSD ON VCC = 5.5 V, f (XIN) = 0,
1 -- --
10 -- 0.4 V V 2
VCC = 5.5 V, f (XIN) = 0, f (XCIN) = 0 VCC = 4.5 V IOH = -0.5 mA VCC = 4.5 V IOL = 0.5 mA
VOH VOL
2.4 --
P11-P14 VT+ - VT-
-- -- --
-- -- 0.5
0.4 0.6 1.3 V 3
VCC = 4.5 V VCC = 5.0 V
IOL = 3 mA IOL = 6 mA
RESET, P50-P51, INT1, INT2, INT3, TIM2, TIM3, SIN, SCLK, SCL1, SCL2, SDA1, SDA2 HIGH input leak current P00-P07, P10-P16, P20-P27, P50, P51, RESET LOW input leak current P00-P07, P10-P16, P20-P27, P50, P51, RESET I C-BUS * BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2)
2
IIZH
--
--
5
A
4
VCC = 5.5 V VI = 5.5 V
IIZL
--
--
5
A
4
VCC = 5.5 V VI = 0 V
RBS
--
--
130
5
VCC = 4.5 V
Notes: 1. P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11-P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P20- P22 have the hysteresis when these pins are used as serial I/O pins. 2. Connect 0.1 F or more capacitor externally between the power source pins VCC-Vss so as to reduce power source noise. Also connect 0.1 F or more capacitor externally between the pins VCC-CNVss. 3. Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 4. Pin names in each parameter is described as bellow. (1) Dedicated pin: dedicated pin names. (2) Double-/triple-function ports * When the same limits: I/O port name. * When the limits of functions except ports are different from I/O port limits: function pin name.
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 26 of 33
M65580MAP-XXXFP
I2C Bus Table
Slave Address = BAH (Write), BBH (Read)
A6 1 A5 0 A4 1 A3 1 A2 1 A1 0 A0 1 R/W 1/0
Write Table (Input Bytes)
Sub Address HEX
00H 01H 02H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 51H
Data D7
0
BIN
00000000
D6
0 YUV input 0 (not asigned) 0 V0 V0
D5
(not asigned) 0 Y/C input 0 0 V1 V1
D4
0 EXT input 0 VRT voltage 0 V0 V0 YNR SW V0 V1 V0 V0 V1 V1 V1 V1 V0 0 2D Y/C 0 V0 0 1 0 1 Cut off (R) V0 V0 Cut off (G) V0 V0 Cut off (B) V0 V0 0 0 H VCO adjust 0
D3
0 TV input 1 1 V0 V0 V0 V0 Tint control V1 Color control V1 Contrast control V1 OSD level (R) V1 OSD level (G) V1 OSD level (B) V1 V0 1 0
D2
0 Y/C through 0 0 V0 V0 V0 V1 V0 V0 V0 V1 V1 V1 V0 H phase control 0
D1
1
D0
H Stop 0
Initial
02H 08H
Power Down Mode
00000001 00000010 00000100 00000101 00000110 00000111
X-ray enable 0 Ped clamp 0 V1 V1 (not asigned) V0
(for evaluation) 0 Sync-tip clamp 0 V0 V0 V0 V0 V0 V0 V1 V1 V1 V1 V0 0 0 0
08H A0H V0 A0H V0 00H V0 15H V1 29H V1 28H V0 3BH V1 1EH V0 5EH V0 0EH V0 80H V0 08H 0 00H 0 40H V0 80H 0 10H 0 40H 0 FFH 1 00H V0 00H V0 00H V0 00H V0 00H V0 00H V0 00H 0 00H 0 00H 0
Sharpness delay (front) Sharpness delay (rear) Y DL time adj. V0 (not asigned) V0 V0 V0 V0 V0 Half tone V0 V0 V0 OSD comp V0 V0 V0 H free 0 (not asigned) 0 0 Black Stre. SW V1 0 0 1 1 V0 V0 V0 V0 V0 V0 (not asigned) 0 0 (not asigned) 0 0 0 0 I/M (D) enable 0 0 V0 (inhibited) 0 V-shift 0 0 1 V0 V0 V0 V0 V0 V0 (not asigned) V0 RGB mute 1 Service SW 0
V-Blanking Stop
Sharpness gain (front) Sharpness gain (rear) YNR limiter level Sharpness limiter level V0 V1 V1 V1 V0 V0 V0 V0 AFC1 gain 0 (for evaluation) 0
V0
00001000 00001001 00001010 00001011 00001100 00001101 00001110
(not asigned) V0 (not asigned) V0 (not asigned) V0
RGB matrix ratio V1
Brightness control V1 (not asigned) 0
00001111 00010000 00010001 00010010 00010011 00010100 00010101 00010110
(for evaluation) 0 (for evaluation) V0 0 (inhibited) 0 V-ramp size 0 V-ramp linearity 1 V0 Drive (R) V0 V0 Drive (G) V0 V0 Drive (B) V0 0 0 0 V0 0 Intelligent monitor (digital) 0 0 0 0 V0 0 Intelligent monitor (analog) V0 V0 V0 V0 V0 V0 V0 V0 1 V0 1 V0 0 0 0 V0 0 V0 0 Hold down level 0 Gamma control 0
0
V-Ramp Invert
1 V0 00010111 00011000 V0 00011001 00011010 V0 00011011 00011100 00011101 01010001 0 Cut off (B) MSB V0 Cut off (G) MSB V0 Cut off (R) MSB V0
Note:
V0 / V1 V Latch bit
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 27 of 33
M65580MAP-XXXFP Read Table (Output Bytes)
Sub Address
60H 61H 62H 63H 01100000 01100001 01100010 01100011
D7
KILLER
B2 ROM MSB
D6
H COINCI
D5
V COINCI
D4
B_W
D3
D2
MV_180
D1
DET NZ
D0
K_MONI
IIC_STILL B2 ROM (not asigned)
C Gain (not asigned)
BLKDETV
Bus Function Write
Function H STOP Power Down Input Video SW X-ray Enable Y/C through Sync-tip Clamp Bit 1 2 4 1 1 3 Sub Add 00H 00H 01H 01H 01H 02H Data D0 D1-D2 D3-D6 D7 D2 D0-D2 Description Horizontal output switch (0: H OUT, 1: H STOP) Power down mode control (0: normal, 1: PD0, 2: PD1, 3: PD2) Video SW Selector (1: TV, 2: EXT, 4: Y/C input, 9: YUV input) X-ray protect function switch (0: X-ray Protect OFF, 1: X-ray Protect ON) Y/C separation input switch (0: Y/C Sep ON, 1: Y/C Sep. through) Sync-tip clamp switch (0: Clamp ON, 1: TV clamp OFF, 2: EXT clamp OFF, 4: Y clamp OFF) Ped Clamp VRT Voltage Sharpness Gain (Front) Sharpness Delay (Front) Sharpness Gain (Rear) Sharpness Delay (Rear) YNR SW YNR Limiter Level Y DL Time Adj. Sharpness Limiter Level Tint Control Color Control Contrast Control OSD Level (R) Half Tone OSD Level (G) RGB Matrix Ratio OSD Level (B) OSD Comp Brightness Control AFC2 H Phase AFC1 Gain 1 2 6 2 6 2 7 1 2 6 7 7 7 6 2 6 2 6 2 8 5 1 02H 02H 04H 04H 05H 05H 06H 06H 06H 07H 08H 09H 0AH 0BH 0BH 0CH 0CH 0DH 0DH 0EH 0FH 0FH D7 D3-D4 D0-D5 D6-D7 D0-D5 D6-D7 D4 D0-D3 D5-D6 D0-D5 D0-D6 D0-D6 D0-D6 D0-D5 D6-D7 D0-D5 D6-D7 D0-D5 D6-D7 D0-D7 D0-D4 D5 Pedestal clamp switch (0: Pedestal clamp OFF, 1: Pedestal clamp ON) Reference voltage adjustment for A/D Over-shoot gain control by 6 bit Over-shoot width control (0: 0 ns, 1: 70 ns, 2: 140 ns, 3: 210 ns) Pre-shoot gain control by 6 bit Pre-shoot width control (0: 0 ns, 1: 70 ns, 2: 140 ns, 3: 210 ns) YNR control switch (0: YNR OFF, 1: YNR ON) YNR limiter level control Delay time adjustment of luminance signal (0: 0 ns, 1: 70 ns, 2: 140 ns, 3: 210 ns) Maximum level control of sharpness Tint Control by 7 bit Color Saturation control by 7 bit Contrast control by 7 bit Digital OSD (R) level adjustment by 6 bit Setting of Half Tone mode Digital OSD (G) level adjustment by 6 bit RGB Matrix ratio control Digital OSD (B) level adjustment by 6 bit Digital OSD threshold voltage control of input signal Brightness control by 8 bit Horizontal phase adjustment by 5 bit Horizontal AFC gain switch (0: Low, 1: High) 010101 0101001 0101000 0111011 011110 00 011110 10 011110 00 10000000 01000 0 V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch V Latch 0 0000 00 V Latch V Latch V Latch 100000 10 V Latch V Latch 01 100000 10 V Latch V Latch 0 000 0 0 0001 0 01 Initial Note
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 28 of 33
M65580MAP-XXXFP Write (cont.)
Function H-free 2D Y/C Black Stretch SW Gamma Control RGB Mute Hold Down Level V Shift Service SW V-Ramp Size Test V-Ramp Linearity V-Ramp Invert Cut Off (R) Drive (R) Cut Off (G) Drive (G) Cut Off (B) Drive (B) Intelligent Monitor (Analog) Intelligent Monitor (Digital) Intelligent Monitor (D) Enable H VCO Adj. Bit 1 1 1 1 1 3 3 1 7 1 7 1 9 7 9 7 9 7 4 5 1 8 Sub Add 0FH 10H 11H 12H 12H 13H 13H 13H 14H 14H 15H 15H 16H 17H 17H 18H 19H 19H 1AH 1BH 1BH 1CH 1DH 1DH 51H Data D6 D4 D6 D0-D3 D7 D0-D2 D4-D6 D3 D0-D6 D7 D0-D6 D7 D0-D7 D7 D0-D6 D0-D7 D7 D0-D6 D0-D7 D7 D0-D6 D0-D3 D0-D4 D5 D0-D7 B OUT amplitude adjustment by 7 bit Intelligent Monitor (Analog) mode selector Intelligent Monitor (Digital) mode selector Intelligent Monitor (Digital) function switch (0: OFF, 1: ON) H VCO free-running frequency adjustment by 8 bit 00000000 G OUT amplitude adjustment by 7 bit B OUT pedestal level adjustment by 9 bit R OUT amplitude adjustment by 7 bit G OUT pedestal level adjustment by 9 bit Description Horizontal forced free-running mode switch (0: OFF, 1: Forced Free-running) Y/C separation mode switch (0: Y/C Sep ON, 1: Y/C Sep. through) Black Stretch function ON/OFF switch (0: OFF, 1: ON) RGB gamma threshold control (0:Gamma OFF) RGB signal mute ON/OFF switch (0: Mute 1: RGB output) Hold Down level adjustment by 3 bit V RAMP start timing adjustment 2 Line/Step Service mode switch (0: Vertical output ON, 1: Vertical output OFF) V-Ramp amplitude adjustment by 7 bit No use for customer (Test mode) V-Ramp linearity adjustment by 7 bit V-Ramp polarity switch R OUT pedestal level adjustment by 9 bit 1000000 0 1111111 1 00000000 0 0000000 00000000 0 0000000 00000000 0 0000000 0000 00000 0 V Latch V Latch V Latch V Latch V Latch V Latch 000 001 0 0000 1 0 0 0 Initial Note
Read
Function K_MONI DET_NZ MV_180 IIC_STILL B_W V COINCI H COINCI KILLER B2ROM C Gain BLKDETV Bit 1 1 1 1 1 1 1 1 9 2 4 Sub Add 60H 60H 60H 60H 60H 60H 60H 60H 61H 62H 62H 63H Data D0 D1 D2 D3 D4 D5 D6 D7 D0-D7 D7 D0-D1 D4-D7 Description C-processor Killer det. output (1: C-pro Killer ON) Noise Killer det. output (1: Noise Killer ON) Reversed Burst signal (all reversed) det. output (1: Reversed Burst) VCR Still mode det. output (1: Still mode) PLL Killer (Chroma) det. output (1: PLL Killer ON) Vertical Coincidence det. output (1: V Coincident) Horizontal Coincidence det. output (1: H Coincident) Color/Killer condition (1: color output, 0: Killer (color off)) B2ROM output ACC amplifier status Black det. output of Black Stretch circuit
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 29 of 33
M65580MAP-XXXFP
M65580MAP I2C Bus Standard Data
Sub Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh Data 00 08 08 21 C0 C0 00 15 40 40 40 1E 9E 1E 80 10 10 4A 8D 00 40 40 00 C0 00 C0 00 C0 00 00 Sub Address 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh Data 20 05 04 81 8D 63 79 50 55 25 21 19 B3 0F 06 08 00 01 C0 04 64 3D 15 00 83 00 A0 00 15 01 6E 38 Sub Address 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh Data 00 00 00 35 22 94 14 A6 00 A6 00 00 00 80
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 30 of 33
M65580MAP-XXXFP
Memory Map
000016 Zero page 00BF16 00C016 00FF16 010016 01FF16 020016 RAM (1152 bytes) SFR2 area 020F16 030016 032016 05BF16 Not used OSD RAM (128 bytes) (note) 080016 087F16 Not used ROM correction function Vector 1: addresses 030016 Vector 2: addresses 032016 OSD ROM (10 Kbytes) 1140016 13BFF16 SFR1 area 1000016
Not used
Not used Not used 600016 Not used ROM (40 Kbytes) FF0016 FFDE16 Interrupt vector area FFFF16
Special page 1FFFF16
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 31 of 33
M65580MAP-XXXFP
Application Examples
5V SW REG REG + 0.1 F 2 k 15 pF 15 pF 0.1 F + + + 470 pF ACL In FBT +200 V
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P25/AD5 CNVSS X OUT VHOLD P04/PWM4 P03/PWM3 P06/INT2/AD4
470 pF
1 Vss 2 FILT
P02/PWM2
P24/TIM2
P23/TIM3
P07/INT1
P05/AD3
P01/ PWM1
X IN
CV IN
HLF
P00/ PWM0
64 63 62
SDA 10 k 10 k
P14/ SDA2 P13/SDA1 P12/SCL2 P11/SCL1 P10/OUT2
0.1 F 1 k
3 VCC 4 P27/XCOUT
61 60
SCL
Reset
5 P26/FSCIN 6 RESET IN 7 P22/SIN/AD8 8 P21/SOUT/AD7 9 P20/SCLK/AD6
POWER ON H 0.01 F 1 M 0.1 F 470 pF
59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Vss (Def) 5V
MCU
P31/B OUT P30/G OUT P53/OUT1 P52/R OUT P51/VSYNC P50/HSYNC IN/OUT VD OUT
10 P15/AD1/INT3 11 P16/AD2/TIM2 (Int. Mon. IN/OUT) 12 Vss (Dig) 13 CLK-2 OUT 14 Vdd (Dig) 15 CLK (fsc) OUT 16 RESET IN
5V
Digital Block
R (OSD) IN F.B IN G (OSD) IN
0.1 F 3.3 V 560 0.1 F Video DET OUT (1.23 Vp-p) EXT IN (1.23 Vp-p) 0.1 F 0.1 F
17 SYNC SEP IN 18 CVBS (x2) OUT 19 Vdd (Input) 20 TV IN 21 Vss (Input) 22 EXT IN
ASIC
Analog Block
AFC1 FILTER APC FILTER Vdd (Output) Vss (Output) Vdd (VCXO) X-RAY PRO
B (OSD) IN H.T IN SCL SDA H OUT FBP IN
AFC2 filter
H-Pulse Out FBP in
23 VRT
VZ OUT R OUT VRB C IN
Vdd (Def)
NECK PRO 0.1 F 6.2 k
Y IN (1.00 Vp-p)
24 Y IN
0.1 F
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
C IN (0.70 Vp-p) 0.01 F
5V
0.22 F
3.3 V
0.01 F
47 pF
0.1 F
0.1 F
0.033 F
1 F 6.2 k 0.01 F
12 k
0
V-RAMP
G OUT
B OUT
X-TAL
- + DY
150 V
10 k 1 k 270
+ 1.5 k
470
470 pF
2.7 k
10 k
2.7 k
5V REG
3.3 V REG
9V REG 1.5 k
to H DRIVE
+
10 k
2.7 k
1.5 k
470 470 pF 270
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 32 of 33
1 k
270
FBT
470
470 pF
1 k
M65580MAP-XXXFP
Package Dimensions
JEITA Package Code P-QFP80-14x20-0.80 RENESAS Code PRQP0080GB-A Previous Code 80P6N-A MASS[Typ.] 1.6g
HD
*1
D 41
64
65
40
ZE
*2
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
HE
E
80 25
Reference Symbol
Dimension in Millimeters
1
ZD
24 Index mark F
c
D E A2 HD HE A A1 bp c
L Detail F
*3
REJ03F0184-0201 Rev.2.01 Mar 31, 2008 Page 33 of 33
A1
e
y
bp
e y ZD ZE L
Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.3 0.35 0.45 0.13 0.15 0.2 0 10 0.65 0.8 0.95 0.10 0.8 1.0 0.4 0.6 0.8
A
A2
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
(c) 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.2

▲Up To Search▲

Price & Availability of M65580MAP-XXXFP

	To Download M65580MAP-XXXFP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .