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TDA7565
Quad power amplifier with built-in voltage converter
Features

Multipower BCD technology DMOS power output Non-switching high efficiency amplifier Switching high efficiency voltage converter High output power capability 4x60W EIAJ/4 Full I C Bus driving: - St-by - Independent front/rear soft play/mute - Selectable gain 26dB - 12dB (for low noise line output function) - High efficiency enable/disable - Voltage converter enable/disable - Regulated voltage selection - Switching frequency selection Hardware mute function Full fault protection DC offset detection Four independent short circuit protection Clipping detector with selectable threshold (1 % / 10 %) via I2C bus Device summary
Order code TDA7565 Package Flexiwatt27 Packing Tube
2
Flexiwatt27
Description
The TDA7565 is a new BCD technology quad bridge type of car radio amplifier in Flexiwatt27 package specially intended for car radio applications. Thanks to the DMOS output stage the TDA7565 has a very low distortion allowing a clear powerful sound. The built-in voltage converter control block assures a very high output power with an extremely low number of added components. The dissipated power under average listening condition is aligned to the conventional solutions (4 x 40 W).

Table 1.
July 2008
Rev 2
1/18
www.st.com 1
Contents
TDA7565
Contents
1 2 Block and pins connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 2.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 3.3 3.4 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 5 6 7
Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Examples of bytes sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/18
TDA7565
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DB4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/18
List of figures
TDA7565
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Demoboard schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timing diagram on the I2C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flexiwatt27 (vertical) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . 16
4/18
TDA7565
Block and pins connection diagrams
1
Block and pins connection diagrams
Figure 1. Block diagram
VS MUTE CLK DATA VCC1 VCC2 CC GND
I2C BUS MUTE1 MUTE2
CLIP DETECTOR
VOLTAGE CONVERTER CONTROL
MG
VOLTAGE CONVERTER EXTERNAL CIRCUIT
IN RF
F OUT RF+ 12/26dB OUT RFR SHORT CIRCUIT PROTECTION OUT RR+ 12/26dB OUT RRF SHORT CIRCUIT PROTECTION OUT LF+ 12/26dB OUT LFR SHORT CIRCUIT PROTECTION OUT LR+ 12/26dB OUT LRSHORT CIRCUIT PROTECTION
IN RR
IN LF
IN LR
SVR
AC_GND
RF
RR
LF
LR
TAB
S_GND
D00AU1232A
PW_GND
Figure 2.
Pins connection (top view)
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MUTE DATA PW_GND RR OUT RRCK OUT RR+ VCC2 OUT RFPW_GND RF OUT RF+ AC_GND IN RF IN RR S_GND IN LR IN LF SVR OUT LF+ PW_GND LF OUT LFVCC1 OUT LR+ CC GND OUT LRPW_GND LR MG TAB
D00AU1233A
5/18
Electrical specification
TDA7565
2
2.1
Electrical specification
Absolute maximum ratings
Table 2.
Symbol Vopc OFF Vopc ON VS Vpeak VCK VDATA IO IO Ptot Tstg, Tj
Absolute maximum ratings
Parameter Operating supply voltage, converter off Operating supply voltage, converter on DC supply voltage Peak supply voltage (for t = 50 ms) CK pin voltage Data pin voltage Output peak current (not repetitive t = 100 s) Output peak current (repetitive f > 10 Hz) Power dissipation Tcase = 70 C Storage and junction temperature Value 18 25 28 50 6 6 8 6 80 -55 to 150 Unit V V V V V V A A W C
2.2
Thermal data
Table 3.
Symbol Rth j-case
Thermal data
Description Thermal resistance junction to case Max. Value 1 Unit C/W
2.3
Table 4.
Electrical characteristics
Electrical characteristics (Refer to the test circuit, VS = 13.5V; RL = 4; f = 1 kHz; voltage converter disabled (VCOff); Tamb = 25C; unless otherwise specified).
Parameter Test condition Min. Typ. Max. Unit
Symbol Power amplifier VS Id Id
Supply voltage range Total quiescent drain current Total quiescent drain current (VCon) Output power (VCoff) V = 14.4 V EIAJ (VS = 13.7 V) THD = 10 % THD = 1 %
8 180 TBD 35 25 20
18 300
V mA mA W W W
PO
6/18
TDA7565 Table 4.
Electrical specification Electrical characteristics (continued) (Refer to the test circuit, VS = 13.5V; RL = 4; f = 1 kHz; voltage converter disabled (VCOff); Tamb = 25C; unless otherwise specified).
Parameter Output power (VCon) V = 14.4V Test condition EIAJ (VS = 13.7V) THD = 10% THD = 1% PO = 1 W to 12 W; STDMODE HE MODE; PO = 1-2 W HE MODE; PO = 4-12 W PO = 1-12 W, f = 10 kHz Min. Typ. 60 40 31 0.03 0.03 0.1 0.15 50 60 25.5 -1 11.5 -1 Rg = 600 ; GV = 26 dB filter 20 Hz to 22 kHz Rg = 600 ; GV = 26 dB filter 20 Hz to 12 kHz f = 100 Hz to 10 kHz; Vr = 1V pk; Rg = 600 (-3 dB) 50 75 70 100 100 70 Mute and play -100 6.5 1.5 D2/D1 (IB1) 0 to 1 D2/D1 (IB1) 1 to 0 155 D0 (IB1) = 0 0 5 1.5 10 10 170 1 10 2 165 20 20 185 2 15 2.5 7 90 100 7.5 60 15 60 12 55 100 26 130 26.5 1 12.5 1 100 20 0.1 0.5 Max. Unit W W W % % % % dB K dB dB dB dB V V dB KHz dB A dB mV V V/s ms ms C % % V C
Symbol
PO
THD
Total harmonic distortion
CT RIN GV1 GV1 GV2 GV2 EIN1 EIN2 SVR BW ASB ISB AM VOS VAM
Cross talk Input impedance Voltage gain 1 Voltage gain match 1 Voltage gain 2 Voltage gain match 2 Output noise voltage 1 Output noise voltage 2 Supply voltage rejection Power bandwidth Stand-by attenuation Stand-by current Mute attenuation Offset voltage Min. supply voltage threshold Slew rate
f = 1 kHz to 10 kHz, RG = 600
TON TOFF
Turn on delay Turn off delay Thermal foldback junction temperature
CDTHD VO Thw
Clip det thd. level D0 (IB1) = 1 Offset detection Thermal warning Power amplifier = play AC Input = 0
7/18
Electrical specification Table 4.
TDA7565
Electrical characteristics (continued) (Refer to the test circuit, VS = 13.5V; RL = 4; f = 1 kHz; voltage converter disabled (VCOff); Tamb = 25C; unless otherwise specified).
Parameter Test condition Min. Typ. Max. Unit
Symbol I2C Bus interface fSCL VIL VIH
Clock frequency Input low voltage Input high voltage Amp. mute 3.5 80 90 2.3
400 1.5
KHz V V
VMin(pin27) Mute in threshold voltage VMout(pin27) Mute out threshold voltage AM(pin 27) Mute attenuation Voltage converter
1.5
V V
Vcc1, Vcc2
Converter output voltage (VC = ON)
VS = 14 V D3 (IB2) = 0; D6 (IB2) = 0 D3 (IB2) = 1; D6 (IB2) = 0 D3 (IB2) = 0; D6 (IB2) = 1 D3 (IB2) = 1; D6 (IB2) = 1 D6 (IB1) = 0; D7 (IB1) = 0 D6 (IB1) = 1; D7 (IB1) = 0 D6 (IB1) = 0; D7 (IB1) = 1 D6 (IB1) = 1; D7 (IB1) = 1 Io = 250 mA Io = 20 mA Io = 200 mA
15 16.5 17.5 18.5 100 150 260 400 1 10.5 10 TBD 20 50 0.5
V V V V kHz kHz kHz kHz V V V V ns ns V
Fs
Voltage converter switching frequency
Vmgl Vmgh Vmgcla mp tf tr Vmgl (VCoff)
MOS gate output low voltage MOS gate output high voltage
MOS gate output clamp voltage Fall time Rise time MOS gate output voltage with voltage converter disabled
Io = 5 mA Co = 1 nF Co = 1 nF Io = 5 mA
8/18
TDA7565 Figure 3. Demoboard schematic
C10 2.2nF L1 100H C8 220nF R1 50 C9 10nF R4 3.3 1W IN RF Q1 R3 10 2 STP60NE06 C1 220nF 16 23 26 7 21 R5 10 1W VCC C12 100nF
Electrical specification
VS (Vbatt) C7 2200F
STPS30L40CT D1 DGND SCL SDA C11 3300F
C13 10F
5 18
OUT RF+
20
OUT RFOUT RR+
22 C2 220nF IN RR 15
TDA7565
24
OUT RROUT LF+
C3 220nF IN LF 12
10
8 C4 220nF IN LR 13 6
OUT LFOUT LR+
4 MUTE 27 11 C6 10F 17 C5 1F 14 9 3 19 25 1
OUT LR-
D00AU1224B
9/18
I2C bus interface
TDA7565
3
I2C bus interface
Data transmission from microprocessor to the TDA7565 and vice versa takes place through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
3.1
Data validity
As shown by Figure 4, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.2
Start and stop conditions
As shown by Figure 5 a start condition is a high to low transition of the SDA line while SCL is HIGH. The stop condition is a low to high transition of the SDA line while SCL is high.
3.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
3.4
Acknowledge
The transmitter* puts a resistive high level on the SDA line during the acknowledge clock pulse (see Figure 6). The receiver** the acknowledges has to pull-down (low) the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during this clock pulse. * Transmitter - - - - Figure 4. master (P) when it writes an address to the TDA7565 slave (TDA7565) when the P reads a data byte from TDA7565 slave (TDA7565) when the P writes an address to the TDA7565 master (P) when it reads a data byte from TDA7565 Data validity on the I2C bus
SDA
** Receiver
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
10/18
TDA7565 Figure 5. Timing diagram on the I2C bus
SCL
I2C bus interface
I2CBUS SDA
D99AU1032
START
STOP
Figure 6.
SCL
Acknowledge on the I2C bus
1 2 3 7 8 9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
11/18
Software specifications
TDA7565
4
Software specifications
All the functions of the TDA7565 are activated by I2C interface. The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from P to TDA7565) or read instruction (from TDA7565 to P). Table 5.
Bit D7 D6 D5 D4 D3 D2 D1 D0(R/W) Address bit Address bit Address bit Address bit Address bit Address bit Address bit Read/Write bit 0 = Write instruction 1 = read instruction
Chip address
Instruction
If R/W = 0, the P sends 2 "Instruction Bytes": IB1 and IB2. Table 6.
Bit D7 D6 D5 Sel. freq. switch 1 Sel. freq. switch 2 Offset detection start (D5 = 1) Offset detection stop (D5 = 0) (off) Front channel Gain = 26dB (D4 = 0) Gain = 12dB (D4 = 1) Rear channel Gain = 26dB (D3 = 0) Gain = 12dB (D3 = 1) Mute front channels (D2 = 0) Unmute front channels (D2 = 1) Mute rear channels (D1 = 0) Unmute rear channels (D1 = 1) CD 1% (D0 = 0) CD 10% (D0 = 1)
IB1
Instruction
D4
D3
D2 D1 D0
12/18
TDA7565 Table 7.
Bit D7 D6 D5 D4 D3 D2 D1 Voltage converter enabled (D7 = 1) Voltage converter disabled (D7 = 0) Regulated voltage selection 1 Test speed Stand-by on - amplifier not working - (D4 = 0) Stand-by off - amplifier working - (D4 = 1) Regulated voltage selection 0) To be forced to "Level 1" Right channel Power amplifier working in standard mode (D1 = 0) Power amplifier working in Hi Eff. mode(D1 = 1) Left channel Power amplifier working in standard mode (D0 = 0) Power amplifier working in Hi Eff. mode(D0 = 1)
Software specifications IB2
Instruction
D0
Table 8.
Bit D7 D6 D5 D4 D3 D2 D1 D0
DB1
Instruction Thermal warning X X X X Offset (LF) Short circuit protection (CH1) X
Table 9.
Bit D7 D6 D5 D4 D3 D2 D1 D0
DB2
Instruction Off status X Clip detector output X X Offset (LR) Short circuit protection (CH2) X
13/18
Software specifications Table 10.
Bit D7 D6 D5 D4 D3 D2 D1 D0 St-by status X X X X Offset (RF) Short circuit protection (CH3) X
TDA7565 DB3
Instruction
Table 11.
Bit D7 D6 D5 D4 D3 D2 D1 D0
DB4
Instruction X X X X X Offset (RR) Short circuit protection (CH4) X
14/18
TDA7565
Examples of bytes sequence
5
Examples of bytes sequence
1 - Turn-on of the power amplifier with 26 dB gain, mute on, diagnostic defeat, high eff. mode, voltage converter disabled.
Start Address byte with D0 = 0 ACK IB1 XX00X000 ACK IB2 0XX1XX10 ACK STOP
2 - Turn-off of the power amplifier
Start Address byte with D0 = 0 ACK IB1 XXXXXXXX ACK IB2 XXX0XXX0 ACK STOP
4 - Offset detection procedure start
Start Address byte with D0 = 0 ACK IB1 XX1XX11X ACK IB2 XXX1XXX0 ACK STOP
5 - Offset detection procedure stop and reading operation.
Start Address byte with D0 = 1 ACK DB1 STOP

The purpose of this test is to check if a D.C. offset (2V typ.) is present on the outputs, produced by input capacitor with anomalous leakage current or humidity between pins. The delay from 3 to 4 can be selected by software, starting from 1 ms
15/18
Package information
TDA7565
6
Package information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 7.
DIM. A B C D E F (1) G G1 H (2) H1 H2 H3 L (2) L1 L2 (2) L3 L4 L5 M M1 N O R R1 R2 R3 R4 V V1 V2 V3
Flexiwatt27 (vertical) mechanical data and package dimensions
MIN. 4.45 1.80 0.75 0.37 0.80 25.75 28.90 mm TYP. 4.50 1.90 1.40 0.90 0.39 1.00 26.00 29.23 17.00 12.80 0.80 22.47 18.97 15.70 7.85 5 3.5 4.00 4.00 2.20 2 1.70 0.5 0.3 1.25 0.50 MAX. 4.65 2.00 1.05 0.42 0.57 1.20 26.25 29.30 MIN. 0.175 0.070 0.029 0.014 0.031 1.014 1.139 inch TYP. 0.177 0.074 0.055 0.035 0.015 0.040 1.023 1.150 0.669 0.503 0.031 0.884 0.747 0.618 0.309 0.197 0.138 0.157 0.157 0.086 0.079 0.067 0.02 0.12 0.049 0.019 MAX. 0.183 0.079 0.041 0.016 0.022 0.047 1.033 1.153
OUTLINE AND MECHANICAL DATA
22.07 18.57 15.50 7.70
22.87 19.37 15.90 7.95
0.869 0.731 0.610 0.303
0.904 0.762 0.626 0.313
3.70 3.60
4.30 4.40
0.145 0.142
0.169 0.173
5 (Typ.) 3 (Typ.) 20 (Typ.) 45 (Typ.)
Flexiwatt27 (vertical)
(1): dam-bar protusion not included (2): molding protusion included
V C B V H H1 H3 H2 R3 R4 V1 R2 R L L1 A
V3
L4
O
L2
N
L3
V1
V2
R2 L5 G G1 F
R1 R1 R1 E
FLEX27ME
D
Pin 1
M
M1
7139011
16/18
TDA7565
Revision history
7
Revision history
Table 12.
Date 20-Sep-2003 01-Jul-2008
Document revision history
Revision 1 2 Initial release. Document reformatted. Document status promoted from product preview to datasheet. Changes
17/18
TDA7565
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