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 HD74HC1G14
Inverter with Schmitt-trigger Input
REJ03D0186-0600Z (Previous ADE-205-299D (Z)) Rev.6.00 Jan.27.2004
Description
The HD74HC1G14 is high-speed CMOS Schmitt-trigger inverter using silicon gate CMOS process. With CMOS low power dissipation, it provides high-speed equivalent to LS-TTL series. The internal circuit of three stages construction with buffer provides wide noise margin and stable output.
Features
* The basic gate function is lined up as Renesas uni logic series. * Supplied on emboss taping for high-speed automatic mounting. * Electrical characteristics equivalent to the HD74HC14 Supply voltage range : 2 to 6 V Operating temperature range : -40 to +85C * |IOH| = IOL = 2 mA (min) * Ordering Information
Part Name HD74HC1G14CME Package Type CMPAK-5 pin Package Code CMPAK-5V Package Abbreviation CM Taping Abbreviation (Quantity) E (3,000 pcs/reel)
Rev.6.00, Jan.27.2004, page 1 of 7
HD74HC1G14
Outline and Article Indication
* HD74HC1G14
Index band Marking
H
A
CMPAK-5
= Control code
Function Table
Input A H L H : High level L : Low level Output Y L H
Pin Arrangement
NC
1
5
VCC
IN A
2
GND
3
4
OUT Y
(Top view)
Rev.6.00, Jan.27.2004, page 2 of 7
HD74HC1G14
Absolute Maximum Ratings
Item Supply voltage range Input voltage range Input clamp current Output clamp current Continuous output current
*1 *1, 2
Symbol VCC VI VO IIK IOK IO
Ratings -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 25 25 200 -65 to 150
Unit V V V mA mA mA mA mW C
Test Conditions
Output voltage range
Output : H or L VI < 0 or VI > VCC VO < 0 or VO >VCC VO = 0 to VCC
Continuous current through ICC or IGND VCC or GND Maximum power dissipation PT *3 at Ta = 25C (in still air) Storage temperature Notes: Tstg
The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C.
Recommended Operating Conditions
Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOL IOH Operating temperature Ta Min 2 0 0 -- -- -- -- -40 Note: Unused or floating inputs must be held high or low. Max 6 VCC VCC 2.0 2.6 -2.0 -2.6 85 C mA Unit V V V mA VCC = 4.5 V VCC = 6.0 V VCC = 4.5 V VCC = 6.0 V Test Conditions
Rev.6.00, Jan.27.2004, page 3 of 7
HD74HC1G14
Electrical Characteristics
VCC Item Threshold voltage Symbol (V) VT
+
Ta = 25C Min 1.0 2.3 3.0 0.3 1.13 1.5 0.3 0.6 0.8 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Typ 1.29 2.73 3.56 0.70 1.66 2.24 0.59 1.08 1.31 2.0 4.5 6.0 4.31 5.80 0.0 0.0 0.0 0.17 0.18 -- -- Max 1.5 3.15 4.2 0.9 2.0 2.6 1.0 1.4 1.7 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 1.0
Ta = -40 to 85C
Min 1.0 2.3 3.0 0.3 1.13 1.5 0.3 0.6 0.8 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- --
Max 1.5 3.15 4.2 0.9 2.0 2.6 1.0 1.4 1.7 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 10.0
Unit Test Conditions V
2.0 4.5 6.0
VT
-
2.0 4.5 6.0
VT
2.0 4.5 6.0
Output voltage
VOH
2.0 4.5 6.0 4.5 6.0
V
VIN = VIL
IOH = -20 A
IOH = -2 mA IOH = -2.6 mA VIN = VIH IOL = 20 A
VOL
2.0 4.5 6.0 4.5 6.0
IOL = 2 mA IOL = 2.6 mA A A VIN = VCC or GND VIN = VCC or GND
Input current Operating current
IIN ICC
6.0 6.0
Rev.6.00, Jan.27.2004, page 4 of 7
HD74HC1G14
Switching Characteristics
Ta = 25C Item Output rise / fall time Propagation delay time Symbol Min tTLH tTHL tPLH tPHL -- -- Typ 5 10 Max 8 21 Unit ns ns Test Conditions Test circuit Test circuit
(CL = 15 pF, tr = tf = 6 ns, VCC = 5 V)
VCC Item Output rise / fall time Symbol (V) tTLH tTHL Propagation delay time tPLH tPHL Input capacitance Equivalent capacitance CIN CPD 2.0 4.5 6.0 2.0 4.5 6.0 -- --
Ta = 25C Min -- -- -- -- -- -- -- -- Typ 50 14 12 48 12 9 2.5 10 Max 125 25 21 100 20 17 5 --
Ta = -40 to 85C
Min -- -- -- -- -- -- -- --
Max 145 30 24 125 25 21 5 --
Unit Test Conditions ns Test circuit
ns
Test circuit
pF pF
(CL = 50 pF, tr = tf = 6 ns) Note: CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test circuit). The average operating current without load is calculated according to the expression below. ICC (opr) = CPD * VCC * fIN + ICC
Rev.6.00, Jan.27.2004, page 5 of 7
HD74HC1G14
Test Circuit
VCC
Pulse generator
Input
Output
50
CL
Note: 1. C L includes probe and jig capacitance.
* Waveforms
t r = 6 ns t f = 6 ns
90% Input 50% 10% t THL 90% Output 50% 10% t PHL
90% 50% 10% t TLH 90% 50% 10% t PLH
VCC
GND
VOH
VOL
Rev.6.00, Jan.27.2004, page 6 of 7
HD74HC1G14
Package Dimensions
Unit: mm
(0.65)
(0.65)
(0.425)
1.3 0.2
0.15- 0.05
2.1 0.3
+ 0.1
1.25 0.1
0 - 0.1
2.0 0.2
0.9 0.1
(0.2)
(0.425)
5 - 0.2 0.05
Package Code JEDEC JEITA Mass (reference value)
CMPAK-5V -- Conforms 0.006 g
Rev.6.00, Jan.27.2004, page 7 of 7
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0


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