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IRFBC40A, SiHFBC40A
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
VDS (V) RDS(on) () Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 42 10 20 Single
D
FEATURES
600 1.2
* Low Gate Charge Qg Results in Simple Drive Requirement Ruggedness
Available
* Improved Gate, Avalanche and Dynamic dV/dt RoHS*
COMPLIANT
* Fully Characterized Capacitance and Avalanche Voltage and Current * Effective Coss Specified * Lead (Pb)-free Available
TO-220
APPLICATIONS
* Switch Mode Power Supply (SMPS)
G
* Uninterruptible Power Supply * High Speed Power Switching
S G D S N-Channel MOSFET
TYPICAL SMPS TOPOLOGIES
* Single Transistor Forward
ORDERING INFORMATION
Package Lead (Pb)-free SnPb TO-220 IRFBC40APbF SiHFBC40A-E3 IRFBC40A SiHFBC40A
ABSOLUTE MAXIMUM RATINGS TC = 25 C, unless otherwise noted
PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb EAS IAR EAR TC = 25 C PD dV/dt TJ, Tstg for 10 s 6-32 or M3 screw Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque VGS at 10 V TC = 25 C TC = 100 C SYMBOL VDS VGS ID IDM LIMIT 600 30 6.2 3.9 25 1.0 570 6.2 13 125 6.0 - 55 to + 150 300d 10 1.1 W/C mJ A mJ W V/ns C lbf * in N*m A UNIT V
Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 C, L = 29.6 mH, RG = 25 , IAS = 6.2 A (see fig. 12). c. ISD 6.2 A, dI/dt 80 A/s, VDD VDS, TJ 150 C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91112 S-81262-Rev. B, 07-Jul-08 www.vishay.com 1
IRFBC40A, SiHFBC40A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER Maximum Junction-to-Ambient Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain) SYMBOL RthJA RthCS RthJC TYP. 0.50 MAX. 62 1.0 C/W UNIT
SPECIFICATIONS TJ = 25 C, unless otherwise noted
PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode
D
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS VDS/TJ VGS(th) IGSS IDSS RDS(on) gfs
VGS = 0 V, ID = 250 A Reference to 25 C, ID = 1 mA VDS = VGS, ID = 250 A VGS = 30 V VDS = 600 V, VGS = 0 V VDS = 480 V, VGS = 0 V, TJ = 125 C VGS = 10 V ID = 3.7 Ab VDS = 50 V, ID = 3.7 A
600 2.0 3.4
0.66 -
4.0 100 25 250 1.2 -
V V/C V nA A S
Ciss Coss Crss Coss Coss eff. Qg Qgs Qgd td(on) tr td(off) tf
VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VDS = 1.0 V, f = 1.0 MHz VGS = 0 V VDS = 480 V, f = 1.0 MHz VDS = 0 V to 480 Vc ID = 6.2 A, VDS = 480 V see fig. 6 and 13b
-
1036 136 7.0 1487 36 48 13 23 31 18
42 10 20 ns nC pF
VGS = 10 V
-
VDD = 300 V, ID = 6.2 A RG = 9.1 , RD = 47 , see fig. 10b
-
-
431 1.8
6.2 A 25 1.5 647 2.8 V ns C
G
S
TJ = 25 C, IS = 6.2 A, VGS = 0
Vb
TJ = 25 C, IF = 6.2 A, dI/dt = 100 A/sb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 s; duty cycle 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
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Document Number: 91112 S-81262-Rev. B, 07-Jul-08
IRFBC40A, SiHFBC40A
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 C, unless otherwise noted
100
Top VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V
100
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
10
Bottom
TJ = 150 C 10
1 4.5 V
TJ = 25 C 1
0.1
0.01 0.1
20 s PULSE WIDTH TJ = 25 C 1 10 100 VDS, Drain-to-Source Voltage (V)
0.1 4.0 5.0
VDS = 50 V 20 s PULSE WIDTH 9.0 8.0 7.0 6.0 VGS, Gate-to-Source Voltage (V) 10.0
Fig. 1 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
RDS(on), Drain-to-Source On Resistance (Normalized)
100
Top
ID, Drain-to-Source Current (A)
10
VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V
3.0
ID = 6.2 A
2.5
2.0
1.5
4.5 V 1
1.0
0.5 VGS = 10 V -60 -40 -20 0 20 40 60 80 100 120 140 160
0.1 1
20 s PULSE WIDTH TJ = 150 C 10 VDS, Drain-to-Source Voltage (V) 100
0.0 TJ, Junction Temperature
Fig. 2 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91112 S-81262-Rev. B, 07-Jul-08
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IRFBC40A, SiHFBC40A
Vishay Siliconix
100000 100
ISD, Reverse Drain Current (A)
10000 C, Capacitance (pF)
VGS = 0 V, Ciss = Cgs + Cgd, Cds Crss = Cgd Coss = Cds + Cgd
f = 1 MHz SHORTED
10
TJ = 150 C
1000
Ciss
100
Coss
TJ = 25 C 1
10
Crss VGS = 0 V 1.0 0.8 0.6 VSD, Source-to-Drain Voltage (V) 1.2
1 1 100 10 VDS, Drain-to-Source Voltage (V) 1000
0.1 0.4
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
20
100 ID = 6.2 A VDS = 480 V VDS = 300 V VDS = 120 V ID, Drain Current (A) 10 100 s OPERATING IN THIS AREA LIMITED BY RDS(on) 10 s
VGS, Gate-to-Source Voltage (V)
16
12
8
1 ms 1 10 ms
4 For Test Circuit See Fig. 13 0 8 32 16 24 QG, Total Gate Charge (nC) 40 TC = 25 C TJ = 150 C Single Pulse 0.1 10 100 1000 10000 VDS, Drain-to-Source Voltage (V)
0
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
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Document Number: 91112 S-81262-Rev. B, 07-Jul-08
IRFBC40A, SiHFBC40A
Vishay Siliconix
RD
7.0
VGS
VDS D.U.T. + - VDD 10 V
6.0 5.0 ID, Drain Current (A)
RG
4.0 3.0 2.0
Pulse width 1 s Duty factor 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS 90 %
1.0 0
25
50
75
100
125
150
TC, Case Temperature (C)
10 % VGS td(on) tr td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
10
Thermal Response (ZthJC)
1 D = 0.50 0.20 0.1 0.10 0.05 0.02 0.01 0.01 0.00001 0.0001 0.001 0.01
t 1, Rectangular Pulse Duration (s) PDM t1 t2 Notes: 1. Duty factor D = t1/ t2 2. Peak TJ = PDM x ZthJC + TC
SINGLE PULSE (THERMAL RESPONSE)
0.1
1
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
15 V
VDS tp
VDS
L
Driver
RG 20 V tp
D.U.T IAS 0.01
+ A - VDD
IAS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
Document Number: 91112 S-81262-Rev. B, 07-Jul-08
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IRFBC40A, SiHFBC40A
Vishay Siliconix
1400 TOP EAS, Single Pulse Avalanche Energy (mJ) 1200 BOTTOM 1000
820
VDSav, Avalanche Voltage (V)
ID 2.8 A 3.9 A 6.2 A
800
780
800
600
760
400
740
200 0 25 50 75 100 125 150 Starting TJ, Junction Temperature (C)
720 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
IAV, Avalanche Current (A)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 12d - Typical Drain-to-Source Voltage vs. Avalanche Current
Current regulator Same type as D.U.T.
50 k
12 V
10 V QGS
QG
0.2 F
0.3 F
QGD D.U.T.
+ -
VDS
VG
VGS
3 mA
Charge
IG ID Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
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Document Number: 91112 S-81262-Rev. B, 07-Jul-08
IRFBC40A, SiHFBC40A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T
+
Circuit layout considerations * Low stray inductance * Ground plane * Low leakage inductance current transformer
+ +
-
RG
* * * *
dV/dt controlled by R G Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test
+ VDD
Driver gate drive P.W. Period D=
P.W. Period VGS = 10 V*
D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt
VDD
Re-applied voltage Inductor current
Body diode
forward drop
Ripple 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91112.
Document Number: 91112 S-81262-Rev. B, 07-Jul-08
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Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, "Vishay"), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000 Revision: 18-Jul-08
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