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Jitter Attenuating, Multiplying Phase Locked Loop for OC-12/STM-4 ADVANCED COMMUNICATIONS Introduction FINAL Features DATASHEET
ACS8944 JAM PLL
The ACS8944 JAM PLL is a Jitter- Attenuating, Multiplying Phase-Locked Loop, for generating low jitter output clocks compliant up to SONET OC-12 and STM-4 622.08 MHz specifications. Its primary function is to clean up clock jitter for high performance optical line cards which have OC-3 or OC-12 SONET serializers or framers, and is the entry level device in Semtech's range of JAM PLLs. The ACS8944 JAM PLL has a single differential LVPECL input and a single differential LVPECL output. Both input and output clock frequencies are individually programmable and can be hardware configured to be any of 19.44 MHz, 38.88 MHz, 77.76 MHz or 155.52 MHz. The headline jitter figures quoted for the ACS8944 depend on the frequency band over which the jitter is measured. For example, typical stand-alone output jitter is typically 2.8 ps rms (well within GR-253-CORE[8] specification requirements of 16.1 ps rms for OC-12 and 64.3 ps rms for OC-3). The device's operating bandwidth (and consequently the jitter attenuation point relating to this bandwidth) is set by external passive components in a differential arrangement which offers good noise immunity.
Meets rms jitter requirements of: Telcordia GR-253-CORE[8] for OC-3 and OC-12 ITU-T G.813[4]/G.812[3] for STM-1 and STM-4 rates ETSI EN300-462-7[1]/EN302-084[2] up to STM-16 rates Typical jitter generation down to: * 0.3 ps rms for 250 kHz to 5 MHz band for G.813, or EN300-462, at STM-4 (OC-12) rates * 2.8 ps rms for 12 kHz to 20 MHz band (against 4.02 ps rms for GR-253-CORE at OC-48 rate) Pull-in range 400 ppm about center input frequency Frequency translation e.g. 19.44 MHz to 155.52 MHz 3.3 V operation, - 40 to +85C temperature range Small outline leadless 7 mm x 7 mm QFN48 package Demonstration Board available on request PLL bandwidth and jitter peaking are fully adjustable. Supports bandwidths from 2 kHz for superior input jitter filtering Lead (Pb)-free version available (ACS8944T), RoHS[9] and WEEE[10] compliant
Note...For items marked [1],[2], etc. references are given in full in the Reference Section on page 21.
Block Diagram
Figure 1 Simplified Block Diagram of the ACS8944 JAM PLL
RESETB VC Differential Input Reference LVPECL 155.52 MHz 77.76 MHz 38.88 MHz 19.44 MHz Frequency Divider PFD Charge Pump
Loop Filter
Differential Clock Output LVPECL 2.5 GHz VCO Frequency Divider 155.52 MHz 77.76 MHz 38.88 MHz 19.44 MHz
LVPECL
LVPECL
Control and Monitor
CFG_OUT0 CFG_OUT1 CFG_OUT2 CFG_OUT3
OP_FSEL
LOCKB
EXT1 EXT2 EXT3
F8944D_001Blockdiag_02
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Table of Contents ADVANCED COMMUNICATIONS Table of Contents
Section
ACS8944 JAM PLL
DATASHEET
Page
FINAL
Introduction................................................................................................................................................................................................ 1 Block Diagram............................................................................................................................................................................................ 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 3 Pin Description........................................................................................................................................................................................... 3 Description ................................................................................................................................................................................................. 5 Input....................................................................................................................................................................................................5 Input Configuration ............................................................................................................................................................................5 Output .................................................................................................................................................................................................5 Voltage Controlled Oscillator.............................................................................................................................................................6 Jitter Filtering......................................................................................................................................................................................6 Jitter Filtering: Partnering with Semtech Line Card Protection Part ...............................................................................................6 Input Jitter Tolerance.........................................................................................................................................................................6 Jitter Transfer .....................................................................................................................................................................................6 Phase Noise Performance.................................................................................................................................................................7 Loop Filter Components ....................................................................................................................................................................7 Output Jitter........................................................................................................................................................................................8 System Reset .....................................................................................................................................................................................8 Layout Recommendations ................................................................................................................................................................8 Lock Detector .....................................................................................................................................................................................8 Applications ........................................................................................................................................................................................9 Application Schematic of Combined ACS8525 and ACS8944 .................................................................................................... 10 Electrical Specifications ......................................................................................................................................................................... 11 Maximum Ratings ........................................................................................................................................................................... 11 Operating Conditions ...................................................................................................................................................................... 11 Thermal Characteristics ................................................................................................................................................................. 12 AC Characteristics........................................................................................................................................................................... 12 DC Characteristics .......................................................................................................................................................................... 12 Input and Output Interface Terminations...................................................................................................................................... 14 Input/Output Timing ....................................................................................................................................................................... 14 Jitter Performance .......................................................................................................................................................................... 15 Package Information .............................................................................................................................................................................. 19 Thermal Conditions......................................................................................................................................................................... 20 References and Related Standards ...................................................................................................................................................... 21 Abbreviations .......................................................................................................................................................................................... 21 Trademark Acknowledgements ............................................................................................................................................................. 22 Revision Status/History ......................................................................................................................................................................... 22 Notes ....................................................................................................................................................................................................... 23 Ordering Information .............................................................................................................................................................................. 24 Disclaimers...................................................................................................................................................................................... 24 Contacts........................................................................................................................................................................................... 24
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS Pin Diagram
Figure 2 ACS8944 Pin Diagram
FINAL
DATASHEET
OP_FSEL
VDDOSC 38
RESETB
VDDP2
NC18
NC16
NC17
IC5
VSSOSC
NC19
IC4
48
39
45
44
46
43
42
40
1 2 3 4 5 6 7 8 9
VDDO1 OUTN OUTP NC1 NC2 NC3 NC4 NC5 NC6
37
41
47
IC3
36 35 34 33 32 31 30
VCN VCP VDDARF NC15 NC14 NC13 NC12 VDDP1 CLKP CLKN VDDADIV VDDADIV
ACS8944
29 28 27 26 25
10 NC7 11 NC8 12 NC9
14 CFG_OUT1
15 CFG_OUT2
16 CFG_OUT3
13 CFG_OUT0
LOCKB
21 NC11
20 NC10
22 EXT1
Connect large central pad to GND
23 EXT2
19 IC2
18 IC1
24
17
EXT3
Dimensions: 7 mm x 7 mm Lead Pitch: 0.5 mm (Leads centered on package)
F8944_D_002PINDIAG_04
Pin Description
Table 1 Power Pins
Pin No. 1 25, 26 29, 43 34 38 39 49 Symbol VDDO1 VDDADIV VDDP1,VDDP2 VDDARF VDDOSC VSSOSC VSS0 I/O P P P P P P P Type Description Supply voltage. Supply to OUTP & OUTN clock output pins, +3.3 Volts 5%. Supply voltage. Supply for internal dividers in VCO loop, kept as an isolated supply to allow for low supply noise for the output divider stages. +3.3 Volts 5%. Supply voltage. Supply to input and output pins. +3.3 Volts 5%. Supply voltage. Supply for phase and frequency detector (PFD), kept as an isolated supply to allow for low supply noise. +3.3 Volts 5%. Supply voltage. Supply input to the internal VCO. +3.3 Volts +5%/-10% Supply ground. 0 V for VCO. Supply ground. Common 0 V. This is the central leadframe pad on the underneath of the package.
Note...I = Input, O = Output, P = Power, LVTTL/LVCMOSU = LVTTL/LVCMOS input with pull-up resistor, LVTTL/LVCMOSD = LVTTL/LVCMOS input with pull-down resistor.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Pin No. 18,19, 37, 41 42 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 30, 31, 32, 33, 44, 45, 47, 48 Symbol IC1, IC2, IC3, IC4, IC5 NC1, NC2, NC3, NC4, NC5, NC6, NC7, NC8, NC9, NC10, NC11, NC12 NC13, NC14, NC15, NC16, NC17, NC18, NC19 I/O Type -
FINAL
Description Internally connected. Connect to ground. Internally connected. Connect to VDD. Not connected. Leave to float.
DATASHEET
Table 2 Internally Connected (IC)/ Not Connected (NC) Pins
Table 3 Functional Pins
Pin No. 2 3 Symbol OUTN OUTP I/O O O Type LVPECL LVPECL Description LVPECL differential output at a rate from 19.44 MHz up to 155.52 MHz. Partnered with pin 3. See pin 3 description for more detail. LVPECL differential output at a rate from 19.44 MHz up to 155.52 MHz. Partnered with pin 2. The output frequency selection is preset by externally connecting OP_FSEL pin (pin 46), to one from a set of four output frequency pins CFG_OUT[3:0] (Pins 16, 15, 14 and 13); which, on reset will give a corresponding generated output frequency of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz. Configuration pin used to set input reference frequency for CLK (N and P) and output clock frequency for OUT (N and P) used in conjunction with pins 14, 15, 16, and 46 as defined in Tables 4 and 5. Configuration pin used to set input reference frequency for CLK (N and P) and output clock frequency for OUT (N and P) used in conjunction with pins 13, 15, 16 and 46 as defined in Tables 4 and 5. Configuration pin used to set input reference frequency for CLK (N and P) and output clock frequency for OUT (N and P) used in conjunction with pins 13, 14, 16 and 46 as defined in Tables 4 and 5. Configuration pin used to set input reference frequency for CLK (N and P) and output clock frequency for OUT (N and P) used in conjunction with pins 13, 14, 15 and 46 as defined in Tables 4 and 5. Lock detect output. This is a pulse width modulated output current, with each pulse typically +10 A. The output produces a pulse with a width in proportion to the phase error seen at the internal phase detector. This pin should be connected via an external parallel capacitor and resistor to ground. The pin voltage will then give an indication of phase lock: When low, the device is phase locked; when high the device has frequent large phase errors and so is not phase locked. The value of the RC components used determines the time and level of consistency required for lock indication.
13
CFG_OUT0
O
LVTTL/LVCMOS
14
CFG_OUT1
O
LVTTL/LVCMOS
15
CFG_OUT2
O
LVTTL/LVCMOS
16
CFG_OUT3
O
LVTTL/LVCMOS
17
LOCKB
O
Analog
22 23
EXT1 EXT2
I I
LVTTL/LVCMOSD Input frequency configuration pin. See Table 4. LVTTL/LVCMOSD Input frequency configuration pin. See Table 4.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Table 3 Functional Pins (cont...)
Pin No. 24 27 Symbol EXT3 CLKN I/O I I Type Description
FINAL
DATASHEET
LVTTL/LVCMOSD Input frequency configuration pin. See Table 4. LVPECL Input reference clock to which the PLL will phase and frequency lock (negative pin of differential pair, partnered with pin 28). Can accept 19.44 MHz, 38.88 MHz, 77.76 MHz or 155.52 MHz to within 400 ppm. Input reference clock to which the PLL will phase and frequency lock (positive pin of differential pair, partnered with pin 27). Can accept 19.44 MHz, 38.88 MHz, 77.76 MHz or 155.52 MHz to within 400 ppm. Connection for external loop filter components. This is the differential control voltage input to the internal VCO and the internal differential charge pump output. Connection for external loop filter components. This is the differential control voltage input to the internal VCO and the internal differential charge pump output.
28
CLKP
I
LVPECL
35 36 40 46
VCP VCN RESETB OP_FSEL
I/O I/O I I
Analog Analog
LVTTL/LVCMOSU Active low reset signal with pull up and Schmitt type input. Used to apply a Power On Reset Schmitt Trigger (POR) signal during system initialization. Should be connected via a capacitor to ground. LVTTL/ LVCMOSD Output Frequency Select Pin. Used with the Output Frequency Configuration pins (pins 13 to 16) to configure the output frequency (on power-up/reset) of the differential output OUT(N/P). See Table 5.
Note...I = Input, O = Output, P = Power, LVTTL/LVCMOSU = LVTTL/LVCMOS input with pull-up resistor, LVTTL/LVCMOSD = LVTTL/LVCMOS input with pull-down resistor
Description
The ACS8944 is a low jitter integrated PLL for clock dejittering and clock rate translation, meeting the jitter requirements for SONET up to and including OC-12 (622.08 MHz systems). It is compliant to the relevant ITU, Telcordia/Bellcore and ETSI standards for at least OC-3 (155.52 MHz) and OC-12 (622.08 MHz) - equivalent to the corresponding STM-1 and STM-4 rates. It can be configured for a range of applications using a minimal number of external components and is available in a small form factor QFN48 package at 7 mm x 7 mm x 0.9 mm outer dimensions.
(VSS), in accordance with the configuration scheme in Table 4, e.g. for an expected input of 155.52 MHz, connect EXT1 to VSS, EXT2 to CFG_OUT1 and EXT3 to CFG_OUT3. Table 4 Input Frequency Selection
For Expected Input Frequency of 19.44 MHz 38.88 MHZ 77.76 MHz 155.52 MHz Connect EXT1 EXT2 to CFG_OUT3 CFG_OUT0 VDD VSS VDD CFG_OUT1 VDD CFG_OUT1 CFG_OUT3 CFG_OUT3 CFG_OUT3 CFG_OUT3 EXT3
Input
The ACS8944 has a single, LVPECL, differential input (CLKN/P, pins 27 and 28). It is designed to operate with any of 19.44 MHz, 38.88 MHz, 77.76 MHz or 155.52 MHz input references, and can pull in an input which is within 400 ppm of these spot frequencies.
Output
The ACS8944 has a single, LVPECL, differential output (OUTN/P, pins 2 and 3). The frequency of the output is determined by the wiring of OP_FSEL to the appropriate CFG_OUT pin in accordance with Table 5.
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Input Configuration
The input must be configured for the expected input frequency. This is achieved by connecting the EXT[3:1] pins, to the configuration pins or to power (VDD) or ground
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Table 5 Output Frequency Selection
For Output Frequency of 19.44 MHz 38.88 MHZ 77.76 MHz 155.52 MHz Connect OP_FSEL to CFG_OUT3 CFG_OUT2 CFG_OUT1 CFG_OUT0
FINAL
DATASHEET
High input jitter attenuation and roll-off: First, second and third order roll-off points: * - 20 dB/decade 18 Hz to 750 Hz, * - 40 dB/decade 750 Hz to 200 kHz and * - 60 dB/decade for >200 kHz. Typical final output jitter, e.g. 2.9 ps rms (measured over the integration range 12 kHz-20 MHz)--dictated by the ACS8944. High frequency stability when all input clocks fail; holdover frequency control to Stratum 3--dictated by the ACS8525.
Voltage Controlled Oscillator
The internal VCO operates at 2.48832 GHz and is internally divided down to the selected rate giving a precise 50/50 balanced mark/space ratio for the output.
Jitter Filtering
Input jitter is attenuated by the PLL with the frequency cutoff point (Fc) at which jitter is either tracked or attenuated being defined by the -3 dB point, i.e. the position of the first pole of the PLL loop filter. The bandwidth (frequency at which the first pole occurs) is defined by the component value selected for the filter from Table 6. For 19.44 MHz input, using a loop filter bandwidth of 2 kHz gives: High input jitter attenuation and roll off: * - 20 dB/decade from first loop filter pole, (Fc) * - 40 dB/decade from 2nd pole (typically 10 x Fc) Jitter peaking is less than 1 dB (dependent on the loop filter components) Typical final output jitter, e.g. 2.8 ps rms measured over the integration range of 12 kHz-20 MHz offset from carrier.
Input Jitter Tolerance
Jitter tolerance is defined as the maximum amplitude of sinusoidal jitter that can exist on the input reference clock above which the device fails to maintain lock. For the ACS8944 device, the jitter tolerance is shown in Figure 3. Figure 3 Jitter Tolerance; ACS8944 Standalone
Input Jitter Tolerance With 2kHz PLL Bandwidth
1000
100
Input Jitter Amplitude p-p (U I)
ACS8946 Jitter Tolerance
10
OC_12 Tolerance Mask OC_48 Tolerance Mask
1 10 100 1000 10000 100000 1000000
Jitter Filtering: Partnering with Semtech Line Card Protection Part
One "Real World" application for the ACS8944 is to use it to dejitter the clock output from a Semtech ACS8525 LC/P device. In this case it is recommended to set the ACS8944 PLL to a bandwidth of around 2 kHz to provide a low jitter total solution. The test results detailed in the electrical specifications section show the "Real World" performance of this combination of parts to be a superior solution when compared with those traditionally using simple discrete PLLs, and has the following advantages: Low overall bandwidth, 18 Hz for example--dictated by the ACS8525.
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0.1
0.01
Jitter Frequency Offset from Carrier (Hz)
Jitter Transfer
Jitter transfer is a ratio of input jitter present on the reference clock to the filtered jitter present on the output clock. Standalone, the Jitter Transfer Characteristic is defined solely by the loop filter bandwidth and is shown in Figure 4.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Figure 4 Jitter Transfer Characteristic, ACS8944 Stand-alone
ACS8944 RMS Jitter Transfer Curve
3.0 0.0 -3.0 -6.0
FINAL
Typical Phase Noise @ 155.52MHz
1.0E+02 0 1.0E+03 1.0E+04 1.0E+05
DATASHEET
Figure 6 Phase Offset from Carrier, ACS8944
Frequency (Hz)
1.0E+06 1.0E+07
-20
(dBc/Hz) Phase Noise
1000 Frequency (Hz) 10000 100000
-9.0 H(s) dB -12.0 -15.0 -18.0 -21.0 -24.0 -27.0 100
-40
-60
-80
-100
-120
-140
In the combined solution, the ACS8525 device provides additional low frequency jitter filtering. The jitter transfer characteristic of the combined ACS8944 and ACS8525 is shown in Figure 5. Figure 5 Jitter Transfer Characteristic, ACS8525 and ACS8944 combined
-160
In the combined line card solution, the inherent jitter generated by the ACS8525 is attenuated by the ACS8944 as shown in the phase noise plot in Figure 7, which uses a PLL bandwidth of 2 kHz. Figure 7 Phase Offset from Carrier, ACS8525 with/without ACS8944
Typical Phase Noise Cleaning of ACS8525
1.0E+02 -10 -30 (dBc/Hz) -50 -70 -90 -110 -130 -150 -170 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 Frequency (Hz) 1.0E+08
TBIL
Phase Noise
ACS8525 + ACS8944
ACS8525 alone
Phase Noise Performance
The inherent jitter generation by the ACS8944 is shown in the phase noise plot in Figure 6 for a PLL bandwidth of 2 kHz, output frequency of 155.52 MHz and input of 19.44 MHz.
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Loop Filter Components
The loop filter comprises two identical sets of passive RC components that connect to the differential charge pump outputs and internal VCO control inputs. Pins VCN and
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ACS8944 JAM PLL
FINAL VCP are the combined differential charge pump outputs Output Jitter
and VCO control voltage inputs. Figure 5 shows the arrangement. Figure 8 Loop Filter Components
JAM PLL
ADVANCED COMMUNICATIONS
DATASHEET
VCP VCN
The output jitter meets all requirements of ITU, Telcordia and ETSI standards for SONET rates up to OC-12/STM-4/622.08 MHz. See the "Electrical Specifications" sections for details on the jitter figures across the different output jitter frequency bands relevant to each specification. The recommended bandwidth of around 2 kHz is suitable for both meeting the specification on output jitter generation requirements and for filtering out the input jitter from the input clock.
R1 C1 C2 C3
R2 C4
System Reset
F8944_010Loopfilter_01
GND
All electrolytic capacitors should be low leakage and low ESR (equivalent series resistance). Ceramic (preferred) or tantalum are suitable for C1 and C3. Tables 6 and 7 are based on a damping factor of 1.2 (phase margin 80.2). Higher damping factors may be used if lower transfer peaking is required. Contact Semtech Sales Support for further details. Table 6 Loop Filter Components when using 19.44 MHz or 77.76 MHz Input Frequency
Closed Loop Bandwidth 2 kHz 4 kHz 8 kHz 1.5 kHz R1 & R2 75 150 270 56 C2 & C4 15 F 4.7 F 0.68 F 33 F C1 & C3 100 nF 33 nF 7.5 nF 200 nF
After power-up or a system reset via the RESETB (pin 40), the internal control logic waits for the presence of an input signal of approximately the correct frequency (at least 40% of the nominal) and then allows a further settling time of 60ms before allowing internal frequency tuning, frequency-locking and phase-locking on to the input clock. Consequently reset should be removed only when the input frequency is within 400 ppm of the nominal frequency.
Layout Recommendations
It is highly recommended to use a stable and filtered 3.3 V power supply to the device. A separate filtered power and ground plane is recommended with supply decoupling capacitors of 10 nF and 100 pF utilizing good high frequency chip capacitors (0402 or 0603 format surfacemount package) on each VDD. Good differential signal layout on the input and output lines should be used to ensure matched track impedance and phase. Contact Semtech directly for further layout recommendations.
Table 7 Loop Filter Components when using 38.88 MHz or 155.52 MHz Input Frequency
Closed Loop Bandwidth 2 kHz 4 kHz 8 kHz 1.5 kHz(i) Note: R1 & R2 150 300 560 110 C2 & C4 6.8 F 2.2 F 0.47 F 15 F C1 & C3 47 nF 22 nF 3.9 nF 91 nF
Lock Detector
A simple lock detector is incorporated which combines the plus and minus phase errors from the phase detector, such that if any phase error signal is present, the LOCKB output drives out a +10 A current, otherwise it is off. Consequently this output (LOCKB) is a pulse width modulated (PWM) pulse stream whose mark/space ratio indicates the current input phase error. Filtering this signal with a simple external RC parallel filter as shown in Figure 9 will give a signal whose output level indicates PLL phase and frequency lock.
(i) Not available at 155.52 MHz input frequency
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Figure 9 Lock Filter Components
LOCK_B C5 220nF LOCKB R3 470K
FINAL Applications
DATASHEET
GND
F8944_011Lockfilter_03
The filtering components are external so that the time to indicate lock or not locked can be optimized for the application. The output indicates both phase and frequency lock. During off-frequency conditions the LOCKB output will be predominately high in its PWM generation with the filtered version giving a constant high state.
The ACS8944 is targeted at applications requiring clock cleaning at 19.44 MHz, 38.88 MHz, 77.76 MHz or 155.52 MHz where input jitter is filtered out or attenuated at frequencies above the ACS8944 PLL bandwidth. It also performs the function of a clock multiplying unit (CMU) translating any one of these input frequencies to any one of 19.44 MHz, 38.88 MHz, 77.76 MHz or 155.52 MHz output frequencies. The ACS8944 can save space when compared with discrete analog + VCXO solutions or module-based solutions. In the example in Figure 10 the ACS8944 is shown symbolically as a low cost line card dejittering device. The ACS8944 carries out the appropriate frequency multiplication for onward distribution as required by the line card.
Figure 10 Typical Application
Multiple Line cards
JAM PLL
Line Card (0C-12)
Recovered Clock Master Clock Master Sync Slave Clock Slave Sync Stand-by Clock Stand-by Sync ACS8515 ACS8525 ACS8526 ACS8527 Frame Sync Multi Frame Sync E1/DS1 Clock Distribution FRAMER SERDES
LINE CARD PROTECTION
ACS8944 JAM PLL
To/from SONET/SDH/PDH Network Low Jitter/Low Skew
Low Jitter up to 155.52 MHz Backplane Slave Sync Card
Master Sync Card
Input CLK Sources
Config. Priorities mP/Serial Bus SSM Primary Ref. Input/ output CLK Line I/F Unit DATA DATA SEC SSM Processing Priorities TCLK
SETS
ACS8510 ACS8520 ACS8522 ACS8530
Output CLKs
Clock Distribution
SetsLinecardGenApp_08
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS FINAL Application Schematic of Combined ACS8525 and ACS8944
Figure 11 shows the circuit diagram of the clock solution part of an application combining an ACS8525 line card part with a dejittering ACS8944. A full design would require a microcontroller for advanced control and ACS8525 device setup; an ACS8525 line card protection
DATASHEET
device containing DPLLs/APLLs, synthesizers and monitors and the ACS8944 for jitter reduction. Just the parts relevant to the clock production are shown here, i.e. the ACS8525 and ACS8944.
Figure 11 Line Card Clock Source Example Schematic ACS8525 and ACS8944
Input Clocks uProc interface for control, monitoring or setup AGND SEC2 SEC1
VDDA R10 1M AGND C6 100nF AGND
C15 100nF
VDDA
48
PORB SCLK VDD6 VDD5 CSB SDI CLKE TMS DGND5 VDD4 VDD3 TRST VDD2 SYNC3 SEC3 SYNC2
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDDA C7 100nF 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
C8 100nF VDDA AGND
VDDA C9 100nF
AGND
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
TCK TDO TDI SDO DGND6 VDD7 IC O2 VA3+ AGND4 IC1 IC2 IC3 IC4 IC5
IC1 ACS8525
SONSDHB
VDD1 DGND4 SEC2 SEC1 SYNC1 VDD5V SEC2NEG SEC2POS SEC1NEG SEC1POS VDD_DIFF GND_DIFF O1NEG O1POS MFrSync FrSync
AGND
VDDA C10 100nF AGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C14 100nF VDDA 4 VS 3 Q C11 100nF AGND AGND C12 100nF VDDA R9 10R AGND C13 100nF R8 10R AGND VDDA R12 82 C1 12.8MHz IQXO-71 AGND LOOP FILTER COMPONENTS C2 + R1 AGND2 C3 C16 10nF C17 100pF C19 100pF AGND2 C21 100pF AGND2 VDDA2 AGND VDDA2 C18 10nF VDDA2 C20 10nF R11 82 VDDA R13 130 R14 130 1
For Loop Filter Components, see Table 6 and Table 7.
RESET CONTROLLER
2
GND
E/D
X1
+
AGND1 IC6 AGND2 VA1+ INTREQ REFCLK DGND1 VD1+ VD2+ DGND2 DGND3 VD3+ SRCSW VA2+ AGND3 IC7 C4 R2 VDDA2 AGND2 C28 100pF C27 10nF C26 100uF R15 ZERO OHM LINK VCN VCP VDDARF NC15 NC14 NC13 NC12 VDDP1 CLKP CLKN VDDADIV VDDADIV 37 25 EXT3 EXT2 EXT1 NC11 NC10 IC2 IC1 LOCKB CFG_OUT3 CFG_OUT2 CFG_OUT1 CFG_OUT0
ACS8944
R16 1M
VDDA2 C29 100nF C25 100pF AGND2 AGND2 C24 10nF
AGND3
IC3 VDDOSC VSSOSC RESETB IC4 IC5 VDDP2 NC16 NC17 OP_FSEL NC18 NC19 IC4 PIN49
C5 220nF
R3 470K AGND2 LOCKB
J1
VDD0 OUTN OUTP NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9
VDDA2 AGND2 R4 130 DOWNSTREAM DEVICE, LVPECL INPUTS OUT1N OUT1P R6 82 R7 82 R5 130
C22 100pF VDDA2 C23 10nF AGND2
13
1
AGND3
F8944D_021ExSchematic_08
Note...For optimal performance use a Low Voltage Dropout (LDO) Regulator to supply VDDA2
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS Electrical Specifications Maximum Ratings
Important Note: The Absolute Maximum Ratings, Table 8, are stress ratings only, and functional operation of the device at conditions other than those indicated in the Operating Conditions sections of this specification are not Table 8 Absolute Maximum Ratings
Parameter Supply Voltage (D.C.): VDDP1, VDDP2, VDDADIV, VDDARF, VDDOSC, VDDO Input Voltage (non-supply pins): Digital Inputs: EXT1, EXT2, RESETB, OP_FSEL Input Voltage (non-supply pins) LVPECL Inputs: CLKN, CLKP, ANALOG I/O: VCN, VCP, LOCKB Output Voltage (non-supply pins): Digital Outputs:FREQ155, FREQ77, FREQ38, FREQ19 LVPECL Outputs: OUTN, OUTP Ambient Operating Temperature Range Storage Temperature Reflow Temperature (Pb) Reflow Temperature (Pb Free) ESD HBM (Human Body Model)(i), (ii) Latchup(iii) Symbol VDD VIN VIN Minimum -0.5 -0.5 -0.5 Maximum 3.6 5.5 VDD + 0.5 Units V V V
FINAL
DATASHEET
implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product.
VOUT
-0.5
VDD + 0.5
V
TA TSTOR TREPB TREPBFREE ESDHBM ILU
-40 -50 2 100
+85 +150 245 260 -
C C C C kV mA
Notes: (i) All pins pass 2kV HBM except VCN/VCP which are rated at 500 V HBM. (ii) Tested to JEDEC standard JESD22-A114. (iii) Tested to JEDEC standard JESD78.
Operating Conditions
Table 9 Operating Conditions
Parameter Supply Voltage (D.C.): VDDP1, VDDP2, VDDADIV, VDDARF, VDDO VDDOSC Ambient Temperature Range Supply Current (including VDDOSC) VDDOSC Supply Current Symbol VDD VDDOSC TA IDD IDDOSC Minimum 3.135 3.0 -40 Typical 3.3 3.3 250 20 Maximum 3.465 3.465 +85 300 25 Units V V C mA mA
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Table 9 Operating Conditions (cont...)
Parameter Total Power Dissipation (excluding power dissipation in external biasing components Symbol PTOT Minimum Typical 870 Maximum 1040 Units mW
FINAL
DATASHEET
Thermal Characteristics
Table 10 Thermal Conditions
Parameter Thermal Resistance Junction to Ambient Operating Junction Temperature Symbol JA TJCT Minimum Maximum 25 125 Units C/W C
AC Characteristics
Table 11 AC Characteristics
Parameter Input to Output Delay Input Clock Rise/Fall Time(i) (CLK) LVPECL Output Rise/Fall Time(i), (ii) Input Clock Duty Cycle (CLK) Output Clock Duty Cycle RESETB Pulse Width after Power-up Frequency Tuning after RESETB High Notes: (i) Rise/fall time measured 10-90%. (ii) Using output load specified in Figure 14. Symbol tPDIO tCRF tPECLRF tCDF tODC tRPW tFT Minimum 0.5 40 48 Typical 0.8 50 50 Maximum 3.0 10 1.2 60 52 100 60 Units ns ns ns % % ms ms
DC Characteristics
Across all operating conditions, unless otherwise stated. Table 12 DC Characteristics: LVCMOS Inputs with Internal Pull-down/Schmitt input with Internal Pull-up
Parameter VIN High VIN Low Pull-down Resistor Pull-up Resistor (Schmitt input) Input Current Symbol VIH VIL RPD RPU IIN Minimum 2 43 53 Maximum 0.8 108 113 10 Units V V k k A
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Table 13 DC Characteristics: LVPECL Input Port
Parameter LVPECL Input Offset Voltage Differential Inputs (Note (ii)) Input Differential Voltage LVPECL Input Low Voltage Single-ended Input (Note (i)) LVPECL Input High Voltage Single-ended Input (Note (i)) Input High Current Input Differential Voltage VID = 1.4 V Input Low Current Input Differential Voltage VID = 1.4 V Symbol VIO_LVPECL VID_LVPECL VIL_LVPECL_S VIL_LVPECL_S IIH_LVPECL IIL_LVPECL Minimum VDD-2.0 0.1 VSS VDD-1.3 -10 -10 Maximum VDD-0.5 1.4 VDD-1.5 VDD +10 +10 Units V V V V A A
FINAL
DATASHEET
Notes: (i) Unused differential input terminated to VDD-1.4 V. (ii) Both pins must remain within the supply voltage, i.e. >VSS and Table 14 DC Characteristics: LVPECL Output Port
Parameter LVPECL Output Low Voltage (Note (i)) LVPECL Output High Voltage (Note (i)) LVPECL Output Differential Voltage (Note (i)) Note: (i) With a 50 ohms load on each pin to VDD -2V. Symbol VOL_LVPECL VOH_LVPECL VOD_LVPECL Minimum VDD-2.1 VDD-1.45 0.37 Maximum VDD-1.62 VDD-0.88 1.22 Units V V V
Table 15 DC Characteristics: LVTTL/CMOS Output Port
Parameter Output Low Voltage @ IOL (MAX) Output High Voltage @ IOH (MIN) Low Level Output Current @ VOL = 0.4 V High Level Output Current @ VOH = 2.4 V Symbol VOL VOH IOL IOH Minimum 2.4 2 2 Typical Maximum 0.4 Units V V mA mA
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS FINAL DATASHEET The preferred termination circuitry for the LVDS signals Input and Output Interface Terminations
Interfacing to either the same type or electrically different interface types is illustrated by the following circuit diagrams, covering translation from LVDS to LVPECL. The example of Figure 12 shows LVPECL to LVPECL terminations with D.C. coupling, so that the ACS8944 sees an equivalent load of around 50 from the R3, R4, R5, R6 resistor arrangement at the receiver end. Figure 12 LVPECL Output - DC Coupled to LVPECL or LVDS Receiver
ASC8944 or similar LVPECL Output VDD VDD These resistors may be integrated on-chip 130R OUTP OUTN Transmission Line ACS8944 or similar LVPECL/LVDS receiver 130R
between the ACS8525/26/27 and the ACS8944 LVPECL is shown in Figure 13. The bias for the LVPECL input is set for A.C. inputs at a mid point of approximately 2 V (with a 3.3 V VDD), as opposed to a normal D.C. coupled bias of VDD - 2 V. This is due to the push-pull nature of an A.C. coupled signal.
Figure 13 Generic LVDS - AC Coupled to LVPECL Receiver
VDD
LVDS Output Device OUTN OUTP
C1 220nF Transmission R1 Line Impedance 100 50 Ohms
R5 2K7
R2 2K7 LVPECL INPUT
JAM PLL
CLKN CLKP
C2 220nF
OUTP VDD -1.0 V VDD -1.4 V VDD -1.8 V
82R
82R
R3 4K3 R4 4K3
VSS Time
F8944D_015LVPECL2LVPECL_03 F8944D_017LVDS2LVPECL_02
GND
Input/Output Timing
Figure 14 Timing Diagrams
1) Input to Output Delay
CLKX OUTY tPDIO
2)
Power-up Sequence
(90% VDD) VDD RESETB
tRPW tFT
Start of Frequency Tuning Algorithm
CLKX Input frequency must be within 400 ppm of nominal before releasing reset
F8944D 021IP OPTi i g 01
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS Jitter Performance FINAL DATASHEET
Table 16 Output Jitter Generation: ACS8944 Stand-alone @155.52 MHz Input/155.52 MHz Output
Test Definition Specification Interface Frequency Filter Spec (iv) 65 kHz to 1.3 MHz 500 Hz to 1.3 MHz Spec Limit 0.1 UI p-p = 643 ps 0.5 UI p-p = 3215 ps 0.1 UI p-p = 161 ps 0.5 UI p-p = 804 ps STM-16 2.5 GHz 1 MHz to 20 MHz 0.1 UI p-p = 40 ps * * * * * * 5.1 0.5 110.4 11.0 3.2 0.3 82.4 8.2 3.7 0.4 33.7 3.4 * 5.1 0.5 * 18.1 1.8 * 18.2 1.8 * 18.4 1.8 0.1 UI p-p = 643 ps 0.01 UI rms = 64.3 ps * * 18.1 1.8 18.2 1.8 * 33.7 3.4 * 3.7 0.4 Typical 12.5 1.2 302.8 30.3 5.3 0.5 213.0 21.3 6.3 0.6 90.3 9.0 12.5 1.2 52.4 5.2 47.9 4.8 48.4 4.8 52.4 5.2 47.9 4.8 90.3 9.0 6.3 0.6 Measured Results Max Units ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms
STM-1 (optical) G.813 155 MHz Option 1[4], and ETSI EN 300 462 7 - 1[1]
STM-4 622 MHz 250 kHz to 5 MHz 1 kHz to 5 MHz
5 kHz to 20 MHz 0.5 UI p-p = 201 ps STM-1 ETSI EN 300 462 - (electrical) 155 MHz 7 - 1[1] G.813 Option 2[4] 65 kHz to 1.3 MHz 0.075 UI p-p = 482 ps 0.1 UI p-p = 643 ps -
STM-1 155 MHz 12 kHz to 1.3 MHz
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps STM-16 2.5 GHz 12 kHz to 20 MHz GR-253CORE[8] OC-3/STS-3 155 MHz OC-12/STS-12 622 MHz OC-48/STS-48 2.5 GHz 12 kHz to 1.3 MHz 0.1 UI p-p = 40 ps
12 kHz to 5 MHz 0.1 UI p-p = 161 ps 0.01 UI p-p = 16.1 ps 5 kHz to 20 MHz 1.5 UI p-p = 600 ps 1 MHz to 20 MHz 0.15 UI p-p = 60 ps -
Notes: (i) Measured on the ACS8944 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40C to +85C. (ii) "*" Derived values using the normal Gaussian crest value ratio of 10. (iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2. (iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication standards' specifications Revision 3/November 2006 (c) Semtech Corp. Page 15 www.semtech.com
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ADVANCED COMMUNICATIONS
Test Definition Specification Interface Frequency Filter Spec 65 kHz to 1.3 MHz 500 Hz to 1.3 MHz
(iv)
FINAL
Measured Results Spec Limit 0.1 UI p-p = 643 ps 0.5 UI p-p = 3215 ps 0.1 UI p-p = 161 ps 0.5 UI p-p = 804 ps * * * * 5.1 0.5 102.6 10.3 3.2 0.3 76.6 7.7 * 3.7 0.4 * 32.7 3.3 * 5.1 0.5 * 17.5 1.7 * 17.6 1.8 * 17.8 1.8 0.1 UI p-p = 643 ps 0.01 UI rms = 64.3 ps * * 17.5 1.7 17.6 1.8 * 32.7 3.3 * 3.7 0.4 Typical 12.3 1.2 281.3 28.1 5.4 0.5 197.8 19.8 6.2 0.6 87.5 8.7 12.3 1.2 50.8 5.1 46.4 4.6 46.9 4.7 50.8 5.1 46.4 4.6 87.5 8.7 6.2 0.6 Max
DATASHEET
Table 17 Output Jitter Generation: ACS8944 Stand-alone @77.76 MHz Input/155.52 MHz Output
Units ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms
G.813 STM-1 (optical) Option 1[4], 155 MHz and ETSI EN 300 462 7 - 1[1]
STM-4 622 MHz 250 kHz to 5 MHz 1 kHz to 5 MHz
STM-16 2.5 GHz 1 MHz to 20 MHz
0.1 UI p-p = 40 ps -
5 kHz to 20 MHz 0.5 UI p-p = 201 ps STM-1 ETSI EN 300 462 - (electrical) 155 MHz 7 - 1[1] G.813 Option 2[4] 65 kHz to 1.3 MHz 0.075 UI p-p = 482 ps 0.1 UI p-p = 643 ps -
STM-1 155 MHz 12 kHz to 1.3 MHz
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps STM-16 2.5 GHz 12 kHz to 20 MHz GR-253CORE[8] OC-3/STS-3 155 MHz OC-12/STS-12 622 MHz OC-48/STS-48 2.5 GHz 12 kHz to 1.3 MHz 0.1 UI p-p = 40 ps
12 kHz to 5 MHz 0.1 UI p-p = 161 ps 0.01 UI p-p = 16.1 ps 5 kHz to 20 MHz 1.5 UI p-p = 600 ps 1 MHz to 20 MHz 0.15 UI p-p = 60 ps -
Notes: (i) Measured on the ACS8944 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40C to +85C. (ii) "*" Derived values using the normal Gaussian crest value ratio of 10. (iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2. (iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication standards' specifications.
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Test Definition Specification Interface Frequency Filter Spec 65 kHz to 1.3 MHz 500 Hz to 1.3 MHz
(iv)
FINAL
Measured Results Spec Limit 0.1 UI p-p = 643 ps 0.5 UI p-p = 3215 ps 0.1 UI p-p = 161 ps 0.5 UI p-p = 804 ps * * * * 5.3 0.5 111.1 11.1 3.3 0.3 86.9 8.7 * 3.7 0.4 * 33.7 3.7 * 5.3 0.5 * 19.3 1.9 * 19.5 1.9 * 19.6 2.0 0.1 UI p-p = 643 ps 0.01 UI rms = 64.3 ps * * 19.3 1.9 19.5 1.9 * 37.3 3.7 * 3.7 0.4 Typical 12.9 1.3 304.7 30.5 5.4 0.5 224.5 22.4 6.2 0.6 100.0 10.0 12.9 1.3 56.1 5.6 51.2 5.1 51.7 5.2 56.1 5.6 51.2 5.1 100.0 10.0 6.2 0.6 Max
DATASHEET
Table 18 Output Jitter Generation: ACS8944 Stand-alone @38.88 MHz Input/155.52 MHz Output
Units ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms
G.813 STM-1 (optical) Option 1[4], 155 MHz and ETSI EN 300 462 7 - 1[1]
STM-4 622 MHz 250 kHz to 5 MHz 1 kHz to 5 MHz
STM-16 2.5 GHz 1 MHz to 20 MHz
0.1 UI p-p = 40 ps -
5 kHz to 20 MHz 0.5 UI p-p = 201 ps STM-1 ETSI EN 300 462 - (electrical) 155 MHz 7 - 1[1] G.813 Option 2[4] 65 kHz to 1.3 MHz 0.075 UI p-p = 482 ps 0.1 UI p-p = 643 ps -
STM-1 155 MHz 12 kHz to 1.3 MHz
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps STM-16 2.5 GHz 12 kHz to 20 MHz GR-253CORE[8] OC-3/STS-3 155 MHz OC-12/STS-12 622 MHz OC-48/STS-48 2.5 GHz 12 kHz to 1.3 MHz 0.1 UI p-p = 40 ps
12 kHz to 5 MHz 0.1 UI p-p = 161 ps 0.01 UI p-p = 16.1 ps 5 kHz to 20 MHz 1.5 UI p-p = 600 ps 1 MHz to 20 MHz 0.15 UI p-p = 60 ps -
Notes: (i) Measured on the ACS8944 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40C to +85C. (ii) "*" Derived values using the normal Gaussian crest value ratio of 10. (iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2. (iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication standards' specifications.
.
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Test Definition Specification Interface Frequency Filter Spec 65 kHz to 1.3 MHz 500 Hz to 1.3 MHz
(iv)
FINAL
Measured Results Spec Limit 0.1 UI p-p = 643 ps 0.5 UI p-p = 3215 ps 0.1 UI p-p = 161 ps 0.5 UI p-p = 804 ps * * * * 6.6 0.7 137.1 13.7 3.4 0.3 117.5 11.7 * 3.7 0.4 * 55.9 5.6 * 6.6 0.7 * 27.8 2.8 * 27.9 2.8 * 28.0 2.8 0.1 UI p-p = 643 ps 0.01 UI rms = 64.3 ps * * 27.8 2.8 27.9 2.8 * 55.9 5.6 * 3.7 0.4 Typical 16.0 1.6 376.0 37.6 5.6 0.6 303.5 30.3 6.2 0.6 149.6 15.0 16.0 1.6 80.6 8.1 73.3 7.3 73.6 7.4 80.6 8.1 73.3 7.3 149.6 15.0 6.2 0.6 Max
DATASHEET
Table 19 Output Jitter Generation: ACS8944 Stand-alone @19.44 MHz Input/155.52 MHz Output
Units ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms
G.813 STM-1 (optical) Option 1[4], 155 MHz and ETSI EN 300 462 7 - 1[1]
STM-4 622 MHz 250 kHz to 5 MHz 1 kHz to 5 MHz
STM-16 2.5 GHz 1 MHz to 20 MHz
0.1 UI p-p = 40 ps -
5 kHz to 20 MHz 0.5 UI p-p = 201 ps STM-1 ETSI EN 300 462 - (electrical) 155 MHz 7 - 1[1] G.813 Option 2[4] 65 kHz to 1.3 MHz 0.075 UI p-p = 482 ps 0.1 UI p-p = 643 ps -
STM-1 155 MHz 12 kHz to 1.3 MHz
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps STM-16 2.5 GHz 12 kHz to 20 MHz GR-253CORE[8] OC-3/STS-3 155 MHz OC-12/STS-12 622 MHz OC-48/STS-48 2.5 GHz 12 kHz to 1.3 MHz 0.1 UI p-p = 40 ps
12 kHz to 5 MHz 0.1 UI p-p = 161 ps 0.01 UI p-p = 16.1 ps 5 kHz to 20 MHz 1.5 UI p-p = 600 ps 1 MHz to 20 MHz 0.15 UI p-p = 60 ps -
Notes: (i) Measured on the ACS8944 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40C to +85C. (ii) "*" Derived values using the normal Gaussian crest value ratio of 10. (iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2. (iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication standards' specifications.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS Package Information
Figure 15 QFN48 Package.
FINAL
DATASHEET
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS Thermal Conditions FINAL DATASHEET
Although not essential for the ACS8944, one technique that may be used to improve heat dissipation from through the large centre pad is to include a thermal landing the same size as the centre pad on the component side of the board (and one on the opposite side of the PCB) connected to analog ground using a number of thermal vias, approximately 0.33mm diameter. These vias should be completely connected (flooded over) to the thermal landing(s) as well as to internal ground planes if using a multilayer PCB. 3 x 3 vias pitched at 1.27 mm between via centres would be more than sufficient for the ACS8944 if this method were adopted.
The device is rated for full temperature range when this package is used with a 4-layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. The device includes a large thermal die paddle which must be soldered to the PCB in addition to the pins for improved thermal dissipation characteristics and to strengthen the mechanical connection to the PCB. Figure 16 Typical 48 Pin QFN PCB Footprint
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS Abbreviations
CMU ESD ESR HBM I/O JAM PLL LDO LVCMOS LVDS LVPECL OC-3/12 PECL PFD PLL POR p-p PWM rms RoHS SDH SEC SETS SONET STM-1/4/16 STS-12 UI uP (P) WEEE VCO
FINAL DATASHEET References and Related Standards
[1] ETSI EN 300 462-7-1 v1.1.2 (06/2001) Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 7-1: Timing characteristics of slave clocks suitable for synchronization supply to equipment in local node applications [2] ETSI EN 302 084 V1.1.1 (2000-02) Transmission and Multiplexing (TM); The control of jitter and wander in transport networks [3] ITU-T G.812 (06/1998) Timing requirements of slave clocks suitable for use as node clocks in synchronization networks [4] ITU-T G.813 (08/1996) Timing characteristics of SDH equipment slave clocks (SEC) [5] ITU-T G.823 (03/2000) The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy [6] ITU-T G.824 (03/2000) The control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy [7] ITU-T G.825 (03/2000) The control of jitter and wander within digital networks which are based on the Synchronous Digital Hierarchy (SDH) [8] Telcordia GR-253-CORE, Issue 3 (09/ 2000) Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria [9] RoHS Directive 2002/95/EC: Directive 2002/95/EC of the European Parliament and of the Council of 27 January 2003 on the restriction of the use of certain hazardous substances in electrical and electronic equipment [10] Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC): Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE)
Clock Multiplier Unit Electrostatic Discharge Equivalent Series Resistance Human Body Model Input/Output Jitter Attenuating, Multiplying Phase Locked Loop Low Voltage Drop-out Low Voltage CMOS Low Voltage Differential Signal Low Voltage (3.3 V) PECL Optical Carrier Signal Level 3/12 155.52 Mbps/ 622.08 Mbps Positive Emitter Coupled Logic Phase and Frequency Detector Phase Locked Loop Power-On Reset peak-to-peak Pulse Width Modulated root-mean-square Restrictive Use of Certain Hazardous Substances (directive) Synchronous Digital Hierarchy SDH/SONET Equipment Clock Synchronous Equipment Timing source Synchronous Optical Network Synchronous Transport Module Levels 1/4: 155.52 Mbps/ 622.08 Mbps/ 2.488 Gbps (SDH) Synchronous Transport Signal Level: 12, 622.08 Mbps (SONET) Unit Interval Microprocessor Waste Electrical and Electronic Equipment (directive) Voltage Controlled Oscillator
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS Trademark Acknowledgements
Semtech and the Semtech S logo are registered trademarks of Semtech Corporation. Telcordia is a registered trademark of Telcordia Technologies.
FINAL
DATASHEET
Revision Status/History
The Revision Status, as shown in top center of the datasheet header bar, may be DRAFT, PRELIMINARY, or FINAL, and refers to the status of the device (not the datasheet), within the design cycle. DRAFT status is used when the design is being realized but is not yet physically available, and the datasheet content reflects the Table 20 Revision History
Revision Rev. 0.01/October 2004 to Rev. 0.10/May 2006 Rev. 1.00/May 2006 Rev. 2.00/October 2006 Rev. 3/November 2006 Reference See version 0.09, April 2006 All pages All pages All pages
intention of the design. The datasheet is raised to PRELIMINARY status when initial prototype devices are physically available, and the datasheet content more accurately represents the realization of the design. The datasheet is only raised to FINAL status after the device has been fully characterized, and the datasheet content updated with measured, rather than simulated parameter values. This is a "FINAL" release of the ACS8944 datasheet. Changes made for this document revision are given below.
Description of Changes Initial drafts, for details see Revision Status/History in version 0.09. Updated to Preliminary status. Updated to Final status. Revision scheme updated.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS Notes FINAL DATASHEET
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS Ordering Information
Table 21 Parts List
Part Number ACS8944 ACS8944T ACS8944EVB Description JAM PLL Jitter Attenuating, Multiplying Phase Locked Loop for OC-12/STM-4. Lead (Pb)-free packaged version of ACS8944; RoHS and WEEE compliant. ACS8944 Evaluation Board (Demo Board).
FINAL
DATASHEET
Disclaimers
Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech for such use. Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards- Operation of this device is subject to the User's implementation and design practices. It is the responsibility of the User to ensure equipment using this device is compliant to any relevant standards.
Contacts
For Additional Information, contact the following: Semtech Corporation Advanced Communications Products E-mail: Internet: USA: sales@semtech.com http://www.semtech.com 200 Flynn Road, Camarillo, CA 93012-8790 Tel: +1 805 498 2111, Fax: +1 805 498 3804 acsupport@semtech.com
FAR EAST: 12F No. 89 Sec. 5, Nanking E. Road, Taipei, 105, TWN, R.O.C. Tel: 886-2-2748-3380 Fax: 886-2-2748-3390. EUROPE: Semtech Ltd., Units 2 and 3, Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601
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