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ESDA8V2-1MX2
EOS and ESD TransilTM protection for charger and battery port
Features

Breakdown voltage VBR = 8.2 V Unidirectional device High peak power dissipation: 500 W (8/20 s waveform) ESD protection level better than IEC 61000-4-2, level 4: 30 kV contact discharge Low leakage current (< 0.5 A @ 5 V) Very small PCB area (1.45 mm2) RoHS compliant Figure 1. Functional diagram (top view)
QFN 2L package

Benefits

High EOS and ESD protection level High integration Suitable for high density boards Tiny package
Complies with the following standards:
IEC 61000-4-2 level 4 - 15 kV (air discharge) - 8 kV (contact discharge) MIL STD 883G - Method 3015-7: class 3B - HBM (human body model): 8kV
Applications
Where EOS and ESD transient overvoltage protection in sensitive equipment is required, such as:

Description
The ESDA8V2-1MX2 is a unidirectional single line Transil diode designed specifically for the protection of integrated circuits in portable equipment and miniaturized electonic devices subject to EOS and ESD transient overvoltages.
Computers Printers Communication systems Cellular phone handsets and accessories Video equipment
TM: Transil is a trademark of STMicroelectronics
August 2008
Rev 1
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www.st.com
Characteristics
ESDA8V2-1MX2
1
Table 1.
Symbol
Characteristics
Absolute maximum ratings (Tamb = 25 C)
Parameter ESD discharge: IEC 61000-4-2 air discharge on input pin IEC 61000-4-2 contact discharge on input pin MIL STD 883G - Method 3015-7: class 3B Peak pulse power dissipation (8/20 s) (1) Peak pulse current (8/20 s) Junction temperature range Storage temperature range Maximum lead temperature for soldering during 10 s Tj initial = Tamb Value Unit
VPP
30 30 30 500 27 -40 to +125 - 55 to +150 260
kV
PPP IPP Tj Tstg TL
W A C C C
1. For a surge greater than the maximum values, the diode will fail in short-circuit
Table 2.
Symbol VBR IRM VRM VCL IPP Cline
Electrical characteristics (definitions)
Parameter Breakdown voltage Leakage current @ VRM Stand-of voltage Clamping voltage Peak pulse current
Slope= 1/ Rd VCL VBR VRM I RM IR VF V I
IF
Input line capacitance
I PP
Table 3.
Symbol VBR IRM
Electrical characteristics (values, Tamb = 25 C)
Test Condition IR = 1 mA VRM = 5 V IPP = 1 A (8/20 s waveform) Min 8.2 0.1 0.5 12 13 18.5 350 430 Typ Max Unit V A V V V pF
VCL
IPP = 5 A (8/20 s waveform) Ipp = 27 A (8/20 s waveform)
Cline
VR = 0 V, Fosc = 1 MHz, Vosc = 30 mV
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Characteristics
Figure 2.
Relative variation of peak pulse power versus initial junction temperature (8/20 s, typical values)
Figure 3.
Peak pulse power versus exponential pulse duration (typical values)
Figure 4.
Clamping voltage versus peak pulse current (8/20 s, typical values)
Figure 5.
Forward voltage drop versus peak forward current (typical values)
Figure 6.
Junction capacitance versus reverse voltage applied (typical values)
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Ordering information scheme
ESDA8V2-1MX2
Figure 7.
ESD response to IEC 61000-4-2 (+30 kV air discharge)
Figure 8.
ESD response to IEC 61000-4-2 (-30 kV air discharge)
2
Ordering information scheme
Figure 9. Ordering information scheme
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ESDA8V2-1MX2
Package information
3
Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Table 4. QFN 2L dimensions
Dimensions Ref Millimetres Min A A1 b1 D E e L1 0.95 0.75 0.51 0.00 0.25 Typ 0.55 0.02 0.30 1.45 1.00 1.00 0.80 Max Min Inches Typ Max
0.60 0.020 0.022 0.024 0.05 0.000 0.001 0.002 0.35 0.010 0.012 0.014 0.057 0.039 1.05 0.037 0.039 0.041 0.85 0.030 0.031 0.033
Figure 10. Footprint (dimensions in mm) Figure 11. Marking
Note:
Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
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Package information Figure 12. Tape and reel specifications
ESDA8V2-1MX2
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ESDA8V2-1MX2
Recommendation on PCB assembly
4
4.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 13. Stencil opening dimensions
L
T
W
b)
General design rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T LxW Aspect Area = --------------------------- 0.66 2T ( L + W )
2.
Reference design a) b) Stencil opening thickness: 100 m Stencil opening for leads: Opening to footprint ratio - between 40% and 50%.
Figure 14. Recommended stencil windows position
T=100 m
95 m 95 m 0.0.62
135 m 0.83
830 m 560 m
0.55 360 m 135 m 1.72
Footprint
550 m Stencil window Footprint
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Recommendation on PCB assembly
ESDA8V2-1MX2
4.2
Solder paste
1. 2. 3. 4. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. "No clean" solder paste is recommended. Offers a high tack force to resist component movement during high speed Solder paste with fine particles: powder particle size is 20-45 m.
4.3
Placement
1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
4.4
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
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ESDA8V2-1MX2
Ordering information
4.5
Reflow profile
Figure 15. ST ECOPACK(R) recommended soldering reflow profile for PCB mounting
Temperature (C)
260C max 255C 220C 180C 125 C
2C/s recommended 2C/s recommended 6C/s max 6C/s max
3C/s max 3C/s max
0 0 1 2 3 4 5
10-30 sec 90 to 150 sec 90 sec max
6
7
Time (min)
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
5
Ordering information
Table 5. Ordering information
Marking Y(1) Weight 2.9 mg Base qty 3000 Delivery mode Tape and reel
Order code ESDA8V2-1MX2
1. The marking can be rotated by 90 to diferentiate assembly location
6
Revision history
Table 6.
Date 27-Aug-2008
Document revision history
Revision 1 Initial release Changes
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ESDA8V2-1MX2
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