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HD74LS95B
4-bit Parallel Access Shift Register
REJ03D0424-0400 Rev.4.00 May 10, 2006 The 4-bit register features parallel and serial inputs, parallel outputs, mode control, and two clock inputs. The register has three mode operation: * Parallel (broadside) load * Shift right (the direction QA toward QD) * Shift left (the direction QD toward QA) Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input. During loading, the entry of serial data is inhibited. Shift right is accomplished on the high-to-low transition of clock-1 when the mode control is low; shift left is accomplished on the high-to-low transition of clock-2 when the mode control is high by connecting the output of each flip-flop to the parallel input of the previous flip-flop (QD to input C, etc.) and serial data is entered at input D. The clock input may be applied commonly to clock-1 and clock-2 if both modes can be clocked from the same source. Changes at the mode control inputs are low; however, conditions described in the last three lines of the function table will also ensure that register contents are protected.
Features
* Ordering Information
Part Name HD74LS95BFPEL Package Type SOP-14 pin (JEITA) Package Code (Previous Code) PRSP0014DF-B (FP-14DAV) Package Abbreviation FP Taping Abbreviation (Quantity) EL (2,000 pcs/reel)
Pin Arrangement
Serial Input A B Inputs C D Mode Control GND
1 2 3 4 5 6 7 Serial Input A QA B C D Mode QB QC QD CK1 CK2
14 13 12 11 10 9 8
VCC QA QB Outputs QC QD Clock1 R-Shift Clock2 L-Shift (Load)
(Top view)
Rev.4.00, May 10, 2006, page 1 of 6
HD74LS95B
Function Table
Inputs Mode control H H H L L L Notes: 1. 2. 3. 4. 5. Clocks 2(L) H L X X L L L H H 1(R) X X X H L L H L H Serial X X X X H L X X X X X Parallel A X a QB* X X X X X X X X B X b QC* X X X X X X X X C X c QD* X X X X X X X X D X d d X X X X X X X X QA QAO a QBn QAO H L QAO QAO QAO QAO QAO Outputs QB QBO b QCn QBO QAn QAn QBO QBO QBO QBO QBO QC QCO c QDn QCO QBn QBn QCO QCO QCO QCO QCO QD QDO d d QDO QCn QCn QDO QDO QDO QDO QDO
H; high level, L; low level, X; irrelevant ; transition from low to high level ; transition from high to low level a to d; the level of steady-state input at inputs A, B, C, or D, respectively. QAO to QDO; the level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were established. 6. QAn to QDn; the level of QA, QB, QC, or QD, respectively, before the most-recent () transition of the clock. 7. *; Shifting left require external connection of QB to A, QC to B, and QD to C. Serial data is entered at input D.
Block Diagram
Data Inputs A Mode Control Serial Input B C D
Clock1 Right -shift Clock2 Left-shift R CK S QA R CK S QB R CK S QC R CK S QD
QA
QB Outputs
QC
QD
Rev.4.00, May 10, 2006, page 2 of 6
HD74LS95B
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Clock frequency Clock pulse width Setup time Hold time Enable time 1 Enable time 2 Inhibit time 1 Inhibit time 2 Symbol VCC IOH IOL Topr fclock tw (CK) tsu th tenable 1 tenable 2 tinhibit 1 tinhibit 2 Min 4.75 -- -- -20 0 20 20 10 20 20 20 20 Typ 5.00 -- -- 25 -- -- -- -- -- -- -- -- Max 5.25 -400 8 75 25 -- -- -- -- -- -- -- Unit V A mA C MHz ns ns ns ns ns ns ns
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL IIH IIL II Short-circuit output current Supply current** Input clamp voltage IOS ICC VIK min. 2.0 -- 2.7 -- -- -- -- -- -20 -- -- typ.* -- -- -- -- -- -- -- -- -- 13 -- max. -- 0.8 -- 0.4 0.5 20 -0.4 0.1 -100 21 -1.5 Unit V V V V A mA mA mA mA V Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = -18 mA
Input current
Notes: * VCC = 5 V, Ta = 25C ** ICC is measured with all outputs and serial input open; A, B, C, and D inputs grounded; mode control at 4.5 V; and momentary 3 V, then ground, applied both clock inputs.
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Maximum clock frequency Propagation delay time Symbol fmax tPLH tPHL min. 25 -- -- typ. 36 18 21 max. -- 27 32 Unit MHz ns ns Condition CL = 15 pF, RL = 2 k
Rev.4.00, May 10, 2006, page 3 of 6
HD74LS95B
Clock Enable / Inhibit Times
VIH Serial Input VIL VIH Mode Control Input 1.3V t enable 1 1.3V VIL t inhibit 1 VIH Clock1 Input 1.3V t inhibit 2 t enable 2 VIH Clock2 Input 1.3V 1.3V VIL VOH QA Output VOL 1.3V VIL
Testing Method
Test Circuit
VCC 4.5V RL QA Input
Serial Input Mode Control
Output
Load circuit 1
CL
See Testing Table
P.G. Zout = 50
CK1 CK2 A B C D GND QB
Output Same as Load Circuit 1. Output QC Output QD Same as Load Circuit 1. Same as Load Circuit 1.
Input P.G. Zout = 50
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Rev.4.00, May 10, 2006, page 4 of 6
HD74LS95B Testing Table
Item From input to output CK-1 Q CK-2 Q CK-1 Q CK-2 Q Inputs CK-1 IN 4.5 V IN 4.5 V CK-2 4.5 V IN 4.5 V IN Mode control 0V 4.5 V 0V 4.5 V Serial Inputs IN 4.5 V IN 4.5 V A 4.5 V IN 4.5 V IN B 4.5 V IN 4.5 V IN C 4.5 V IN 4.5 V IN D 4.5 V IN 4.5 V IN QA OUT OUT OUT OUT Outputs QB OUT OUT OUT OUT QC OUT OUT OUT OUT QD OUT OUT OUT OUT
fmax tPLH tPHL
Waveform
tTLH 90% 10% tTHL 90% 1.3V 10% tsu Clock1 or 2 Input th tsu th 3V 1.3V 1.3V tw (ck) 1.3V 0V tw (data) 3V 1.3V 1.3V 0V
Data Input
VOH Outputs QA, QB, QC or QD tPHL 1.3V tPLH 1.3V VOL
Note:
Input pulse; tTLH, tTHL 10 ns, Data PRR = 500 kHz, Clock PRR = 1 MHz,
Rev.4.00, May 10, 2006, page 5 of 6
HD74LS95B
Package Dimensions
JEITA Package Code P-SOP14-5.5x10.06-1.27 RENESAS Code PRSP0014DF-B Previous Code FP-14DAV MASS[Typ.] 0.23g
*1
D 8
F
14
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
7 bp x M L1
Reference Dimension in Millimeters Symbol
c
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 10.06 10.5 5.50
0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 1.42 0.50 0.70 0.90 1.15
Rev.4.00, May 10, 2006, page 6 of 6
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