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TDA8920C
2 x 110 W class-D power amplifier
Rev. 01 -- 29 September 2008 Preliminary data sheet
1. General description
The TDA8920C is a high-efficiency class-D audio power amplifier. The typical output power is 2 x 110 W with a speaker load impedance of 4 . The TDA8920C is available in both HSOP24 and DBS23P power packages. The amplifier operates over a wide supply voltage range from 12.5 V to 32.5 V and has a low quiescent current consumption.
2. Features
I Pin compatible with TDA8950/20B for both HSOP24 and DBS23P packages I Symmetrical high operating supply voltage range from 12.5 V to 32.5 V I Stereo full differential inputs, usable as stereo Single-Ended (SE) or mono Bridge-Tied Load (BTL) amplifier I High output power at typical applications: N SE 2 x 110 W, RL = 4 (VP = 30 V) N SE 2 x 125 W, RL = 4 (VP = 32 V) N SE 2 x 120 W, RL = 3 (VP = 29 V) N BTL 1 x 210 W, RL = 8 (VP = 30 V) I Low noise in BTL operation due to BD modulation I Smooth pop noise-free start-up and switch off I Zero dead time Pulse-Width Modulation (PWM) output switching I Fixed frequency I Internal or external clock switching frequency I High efficiency I Low quiescent current I Advanced protection strategy: voltage protection and output current limiting I Thermal foldback I Fixed gain of 30 dB in SE and 36 dB in BTL I Full short-circuit proof across load
3. Applications
I I I I DVD Mini and micro receiver Home Theater In A Box (HTIAB) system High power speaker system
NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
4. Quick reference data
Table 1. Quick reference data Conditions Operating mode Non-Operating mode; VDD - VSS Operating mode; no load; no filter; no RC-snubber network connected L = 22 H; C = 680 nF; Tj = 85 C THD = 10 %; RL = 4 ; VP = 30 V THD = 10 %; RL = 4 ; VP = 27 V Mono bridge-tied load configuration Po output power L = 22 H; C = 680 nF; Tj = 85 C; THD = 10 %; RL = 8 ; VP = 30 V
[2] [2] [1]
Symbol Parameter General, VP = 30 V VP VP(ovp) Iq(tot) supply voltage overvoltage protection supply voltage total quiescent current
Min
Typ
Max
Unit
12.5 30 65 50
32.5 V 70 75 V mA
Stereo single-ended configuration Po output power
-
110 80
-
W W
-
210
-
W
[1] [2]
The circuit is DC adjusted at VP = 12.5 V to 32.5 V. Output power is measured indirectly; based on RDSon measurement; see Section 13.3.
5. Ordering information
Table 2. Ordering information Package Name TDA8920CJ TDA8920CTH DBS23P HSOP24 Description plastic, heatsink small outline package; 24 leads; low stand-off height Version SOT566-3 plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1 Type number
TDA8920C_1
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Preliminary data sheet
Rev. 01 -- 29 September 2008
2 of 40
NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
6. Block diagram
VDDA
3 (20)
n.c.
10 (4)
STABI PROT 18 (12) 13 (7)
VDDP2
23 (16)
VDDP1
14 (8) 15 (9)
BOOT1
IN1M IN1P
9 (3) 8 (2) INPUT STAGE PWM MODULATOR SWITCH1 CONTROL AND HANDSHAKE DRIVER HIGH 16 (10) DRIVER LOW VSSP1 OSCILLATOR MODE MANAGER TEMPERATURE SENSOR CURRENT PROTECTION VOLTAGE PROTECTION OUT1
n.c. OSC MODE
11 (5) 7 (1) 6 (23)
mute STABI
TDA8920CTH (TDA8920CJ)
VDDP2 22 (15) BOOT2
SGND
2 (19) mute CONTROL SWITCH2 AND HANDSHAKE DRIVER HIGH 21 (14) DRIVER LOW 17 (11) 20 (13) OUT2
IN2P IN2M
5 (22) 4 (21) INPUT STAGE PWM MODULATOR
1 (18)
12 (6)
24 (17)
19 (-)
001aai852
VSSA
n.c.
VSSD
n.c.
VSSP1
VSSP2
Pin numbers in brackets refer to type number TDA8920CJ.
Fig 1.
Block diagram
TDA8920C_1
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Preliminary data sheet
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
7. Pinning information
7.1 Pinning
OSC IN1P IN1M n.c. n.c. n.c. PROT VDDP1 BOOT1
1 2 3 4 5 6 7 8 9
OUT1 10 VSSP1 11 VSSD 24 VDDP2 23 BOOT2 22 OUT2 21 VSSP2 20 n.c. 19 STABI 18 VSSP1 17 OUT1 16 BOOT1 15 VDDP1 14 PROT 13
001aai853
1 2 3 4 5
VSSA SGND VDDA IN2M IN2P MODE OSC IN1P IN1M
STABI 12 VSSP2 13 OUT2 14 BOOT2 15 VDDP2 16 VSSD 17 VSSA 18 SGND 19 VDDA 20 IN2M 21 IN2P 22 MODE 23
TDA8920CJ
TDA8920CTH
6 7 8 9
10 n.c. 11 n.c. 12 n.c.
001aai854
Fig 2.
Pin configuration TDA8920CTH
Fig 3.
Pin configuration TDA8920CJ
TDA8920C_1
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Preliminary data sheet
Rev. 01 -- 29 September 2008
4 of 40
NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
7.2 Pin description
Table 3. Symbol VSSA SGND VDDA IN2M IN2P MODE OSC IN1P IN1M n.c. n.c. n.c. PROT VDDP1 BOOT1 OUT1 VSSP1 STABI n.c. VSSP2 OUT2 BOOT2 VDDP2 VSSD Pin description Pin TDA8920CTH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TDA8920CJ 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 negative analog supply voltage signal ground positive analog supply voltage channel 2 negative audio input channel 2 positive audio input mode selection input: Standby, Mute or Operating mode oscillator frequency adjustment or tracking input channel 1 positive audio input channel 1 negative audio input not connected not connected not connected decoupling capacitor for protection (OCP) channel 1 positive power supply voltage channel 1 bootstrap capacitor channel 1 PWM output channel 1 negative power supply voltage decoupling of internal stabilizer for logic supply not connected channel 2 negative power supply voltage channel 2 PWM output channel 2 bootstrap capacitor channel 2 positive power supply voltage negative digital supply voltage Description
8. Functional description
8.1 General
The TDA8920C is a two-channel audio power amplifier using class-D technology. The audio input signal is converted into a digital pulse-width modulated signal using an analog input stage and PWM modulator; see Figure 1. To enable the output power transistors to be driven, the digital PWM signal is applied to a control and handshake block and driver circuits for both the high side and low side. This level-shifts the low-power digital PWM signal from a logic level to a high-power PWM signal switching between the main supply lines. A 2nd-order low-pass filter converts the PWM signal to an analog audio signal across the loudspeakers.
TDA8920C_1 (c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 29 September 2008
5 of 40
NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
The TDA8920C single-chip class-D amplifier has built-in high-power switches, drivers, timing and handshaking between the power switches and some control logic. In addition, to secure maximum system robustness, an advanced protection strategy is implemented for voltage, temperature and maximum current. Both of the TDA8920C audio channels contain a PWM modulator, an analog feedback loop and a differential input stage. The TDA8920C also contains circuits common to both channels such as the oscillator, all reference sources, the mode interface and a digital timing manager. The two independent amplifier channels have high output power, high efficiency, low distortion and low quiescent current. The amplifier channels can be connected in the following configurations:
* Mono Bridge-Tied Load (BTL) amplifier * Stereo Single-Ended (SE) amplifiers
The amplifier system can be switched to one of three operating modes using pin MODE:
* Standby mode: with a very low supply current * Mute mode: the amplifiers are operational but the audio signal at the output is
suppressed by disabling the voltage-to-current (VI) converter input stages
* Operating mode: the amplifiers are fully operational with the output signal
To ensure pop noise-free start-up, the DC output offset voltage is applied gradually to the output at a level between Mute mode and Operating mode levels. The bias-current setting of the VI-converters is related to the voltage on pin MODE. In Mute mode the bias-current setting of the VI-converters is zero (VI-converters are disabled). In Operating mode the bias current is at maximum. The time-constant required to apply the DC output offset voltage gradually between Mute and Operating mode levels can be generated using an RC network on pin MODE. An example of a switching circuit for driving pin MODE is illustrated in Figure 4. If the capacitor C is left out of the application the voltage on pin MODE is applied with a much smaller time-constant, which may result in audible pop noises during start-up (depending on the DC output offset voltage and loudspeaker used).
+5 V standby/ mute R MODE pin R C mute/on SGND
001aab172
Fig 4.
Example of mode selection circuit
TDA8920C_1
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Preliminary data sheet
Rev. 01 -- 29 September 2008
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
To fully charge the coupling capacitors at the inputs, the amplifier automatically remains in the Mute mode before switching to the Operating mode. A complete overview of the start-up timing is shown in Figure 5.
audio output
(1)
modulated PWM VMODE 50 % duty cycle operating
> 4.2 V
2.2 V < VMODE < 3 V
mute
0 V (SGND)
standby 100 ms 50 ms
> 350 ms
time
audio output
(1)
modulated PWM VMODE 50 % duty cycle operating
> 4.2 V
2.2 V < VMODE < 3 V
mute
0 V (SGND)
standby 100 ms 50 ms
> 350 ms
time
001aah657
(1) First 14 pulse down. Upper diagram: When switching from standby to mute there is a delay of approximately 100 ms before the output starts switching. The audio signal is available after VMODE is set to operating but not earlier than 150 ms after switching to mute. To start up pop noise-free, it is recommended that the time-constant applied to pin MODE is at least 350 ms for the transition between mute and operating. Lower diagram: When switching directly from standby to operating there is a delay of 100 ms before the outputs start switching. The audio signal is available after a second delay of 50 ms. To start up pop noise-free, it is recommended that the time-constant applied to pin MODE is at least 500 ms for the transition between standby and operating.
Fig 5.
Timing on mode selection input pin MODE
TDA8920C_1
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Preliminary data sheet
Rev. 01 -- 29 September 2008
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
8.2 Pulse-width modulation frequency
The output signal of the amplifier is a PWM signal with a carrier frequency typically between 300 kHz and 400 kHz. Using a 2nd-order LC demodulation filter in the application results in an analog audio signal across the loudspeaker. The carrier frequency is determined by an external resistor ROSC, connected between pin OSC and pin VSSA. An optimal setting for the carrier frequency is between 300 kHz and 400 kHz. The carrier frequency is set to 345 kHz by connecting a 30 k external resistor between pin OSC and VSSA. See Table 8 for more details. If two or more class-D amplifiers are used in the same audio application, it is recommended that all devices use an external clock circuit to ensure that they operate at the same switching frequency.
8.3 Protection
The following protection strategies are provided:
* Thermal protection:
- Thermal FoldBack (TFB) - OverTemperature Protection (OTP)
* OverCurrent Protection (OCP, diagnostic output on pin PROT) * Window Protection (WP) * Supply voltage protection:
- UnderVoltage Protection (UVP) - OverVoltage Protection (OVP) - UnBalance Protection (UBP) The device reacts to fault conditions differently for each protection type.
8.3.1 Thermal protection
The TDA8920C has an advanced thermal protection strategy. It consists of a TFB function that gradually reduces the output power within a defined temperature range. If the temperature continues to rise, OTP is implemented, shutting down the device completely. 8.3.1.1 Thermal FoldBack (TFB) If the junction temperature (Tj) exceeds the defined threshold value, the gain is gradually reduced. This reduces the output signal amplitude and the power dissipation, eventually stabilizing the temperature.
TDA8920C_1
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Preliminary data sheet
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
TFB is specified at the thermal foldback activation temperature Tact(th_fold) where the closed-loop voltage gain is reduced by 6 dB. The TFB range is: Tact(th_fold) - 5 C < Tact(th_fold) < Tact(th_prot) The value of Tact(th_fold) for the TDA8920C is approximately 153 C; see Table 7 for more details. 8.3.1.2 OverTemperature Protection (OTP) If despite the TFB function, the junction temperature (Tj) of the TDA8920C continues to rise exceeding the thermal protection activation temperature Tact(th_prot), the amplifier shuts down immediately. The amplifier resumes switching approximately 100 ms after the temperature drops below Tact(th_prot). The thermal behavior is illustrated in Figure 6.
Gain (dB)
30 dB
24 dB
0 dB
(Tact(th_fold) - 5C)
Tact(th_prot) Tact(th_fold) 2 3
Tj (C)
1
001aah656
(1) Duty cycle of PWM output modulated according to the audio input signal. (2) Duty cycle of PWM output reduced due to TFB. (3) Amplifier is switched off due to OTP.
Fig 6.
Behavior of TFB and OTP
8.3.2 OverCurrent Protection (OCP)
OverCurrent Protection (OCP) will detect a short-circuit applied to any of the demodulated outputs of the amplifier. If the output current exceeds the 9.2 A maximum, it is automatically limited to its maximum value by the OCP protection circuit, the amplifier is NOT shut down completely, and the amplifier outputs continue switching. If the active current limiting continues longer than time (), the TDA8920C shuts down. Activation of current limiting and the triggering of OCP are output at pin PROT. OCP can distinguish between a loudspeaker impedance drop and a low-ohmic short-circuit across the load. In the TDA8920C, the impedance threshold (Zth) depends on the supply voltage used. If a short-circuit occurs across the load causing the impedance to drop below the threshold level (< Zth), the amplifier switches off completely. After 100 ms, it tries to restart. If the short-circuit condition is still present, the cycle is repeated. The average power dissipation will be low because of the low duty cycle.
TDA8920C_1
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Preliminary data sheet
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
If an impedance drop occurs (e.g. due to dynamic behavior of the loudspeaker) OCP is activated. The maximum output current stays limited to 9.2 A but the amplifier will not switch off completely, preventing audio holes from occurring. The result is a clipped output signal. See Section 13.7 for more information on this maximum output current limiting feature.
8.3.3 Window Protection (WP)
Window Protection (WP) checks the conditions at the output terminals of the power stage and is activated:
* During the start-up sequence, when pin MODE is switched from standby to mute. In
the event of a short-circuit at one of the output terminals to pin VDDPn or pin VSSPn, the start-up procedure is interrupted. The TDA8920C waits until the short-circuit to the supply lines is removed. No large currents will flow in the event of a short-circuit because the test is done before the power stages are enabled.
* When the amplifier shuts down completely due to OCP activation because of a
short-circuit to one of the supply lines; WP is activated during a restart after 100 ms. The amplifier will not start up until the short-circuit to the supply lines is removed.
8.3.4 Supply voltage protection
If the supply voltage drops below the minimum supply voltage, the UnderVoltage Protection (UVP) circuit is activated and the system shuts down correctly. If the internal clock is used, the switch-off will be silent and without pop noise. When the supply voltage rises above the threshold level, the system restarts after 100 ms. If the supply voltage exceeds the maximum supply voltage, the OVP circuit is activated and the power stages are shut down. When the supply voltage drops below the threshold level, the system restarts after 100 ms. An additional UnBalance Protection (UBP) circuit compares the positive analog voltage (on pin VDDA) and the negative analog supply voltage (on pin VSSA) and is triggered if the voltage difference exceeds a factor of two. When the supply voltage difference drops below the threshold level, the system restarts after 100 ms. Example: With a symmetrical supply of 30 V, the protection circuit is triggered if the unbalance exceeds approximately 15 V; see Section 13.7. An overview is given of all protection strategies and their respective effects on the output signal in Table 4.
TDA8920C_1
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Preliminary data sheet
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
Overview of TDA8920C protection strategies Restart directly N N N[2] Y N N N Restart after 100 ms N Y Y[2] N Y Y Y Pin PROT detection N N Y N N N N
Table 4.
Protection name Complete shutdown TFB[1] OTP OCP WP UVP OVP UBP
[1] [2] [3]
N Y Y[2] N[3] Y Y Y
Amplifier gain depends on the junction temperature and heatsink size. Only complete shutdown of the amplifier if short-circuit impedance is below the threshold of 1 . In all other cases current limiting results in a clipped output signal. Fault condition detected during (every) transition between standby-to-mute and during a restart after activation of OCP (short-circuit to one of the supply lines).
8.4 Differential audio inputs
The audio inputs are fully differential ensuring a high common mode rejection ratio and maximum flexibility in the application.
* Stereo operation: it is advised to use the inputs in anti-phase and connect the
speakers in anti-phase, to avoid acoustical phase differences. The construction advantages are: - minimized power supply peak current - minimized supply pumping effect, especially at low audio frequencies
* Mono BTL operation: it is required that the inputs are connected in anti-parallel. The
output of one channel is inverted and the speaker load is connected between the two outputs of the TDA8920C. In principle, the output power to the speaker can be boosted to twice the output power of single-ended stereo. The input configuration for a mono BTL application is illustrated in Figure 7.
IN1P IN1M Vin IN2P IN2M
OUT1
SGND
OUT2
power stage
mbl466
Fig 7.
Input configuration for mono BTL application
TDA8920C_1
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Preliminary data sheet
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
9. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VP IORM Tstg Tamb Tj VMODE VOSC VI VPROT Vesd supply voltage repetitive peak output current storage temperature ambient temperature junction temperature voltage on pin MODE voltage on pin OSC input voltage referenced to SGND; pin IN1P; IN1M; IN2P and IN2M Human Body Model (HBM); pin VSSP1 with respect to other pins HBM; all other pins Machine Model (MM); all pins Charged Device Model (CDM) Iq(tot) total quiescent current Operating mode; no load; no filter; no RC-snubber network connected referenced to SGND Conditions Non-Operating mode; VDD - VSS maximum output current limiting Min 9.2 -55 -40 0 0 -5 0 -1800 -2000 -200 -500 Max 65 +150 +85 150 6 Unit V A C C C V
SGND V +6 +5 12 +1800 +2000 +200 +500 75 V V V V V V mA
voltage on pin PROT referenced to voltage on pin VSSD electrostatic discharge voltage
10. Thermal characteristics
Table 6. Symbol Rth(j-a) Rth(j-c) Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions in free air Typ 40 1.1 Unit K/W K/W
TDA8920C_1
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Preliminary data sheet
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
11. Static characteristics
Table 7. Static characteristics VP = 30 V; fosc = 345 kHz; Tamb = 25 C; unless otherwise specified. Symbol Supply VP VP(ovp) VP(uvp) Iq(tot) supply voltage overvoltage protection supply voltage Operating mode non-Operating mode; VDD - VSS Operating mode; no load; no filter; no RC-snubber network connected measured at 30 V referenced to SGND Standby mode Mute mode Operating mode II VI VO(offset) input current input voltage output offset voltage VI = 5.5 V DC input SE; Mute mode SE; Operating mode BTL; Mute mode BTL; Operating mode Stabilizer output; pin STABI VO(STABI) output voltage on pin STABI Mute and Operating modes; with respect to VSSP1 9.3 9.8 10.3 V
[4] [4] [2] [2] [2][3] [2][3] [2][3] [1]
Parameter
Conditions
Min 12.5 65 20 -
Typ 30 50
Max 32.5 70 25 75
Unit V V V mA
undervoltage protection supply voltage VDD - VSS total quiescent current
Istb VMODE
standby current voltage on pin MODE
0 0 2.2 4.2 -
480 110 0 -
600 6 0.8 3.0 6 150 25 150 30 210
A V V V V A V mV mV mV mV
Mode select input; pin MODE
Audio inputs; pins IN1M, IN1P, IN2P and IN2M Amplifier outputs; pins OUT1 and OUT2
Temperature protection Tact(th_prot) Tact(th_fold) thermal protection activation temperature thermal foldback activation temperature closed loop SE voltage gain reduced with 6 dB
[5]
-
154 153
-
C C
[1] [2] [3] [4] [5]
The circuit is DC adjusted at VP = 12.5 V to 32.5 V. With respect to SGND (0 V). The transition between Standby and Mute mode has hysteresis, while the slope of the transition between Mute and Operating mode is determined by the time-constant of the RC network on pin MODE; see Figure 8. DC output offset voltage is gradually applied to the output during the transition between the Mute and Operating modes. The slope caused by any DC output offset is determined by the time-constant of the RC network on pin MODE. At a junction temperature of approximately Tact(th_fold) - 5 C, gain reduction commences and at a junction temperature of approximately Tact(th_prot), the amplifier switches off.
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Preliminary data sheet
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
slope is directly related to the time-constant of the RC network on the MODE pin
VO (V) VO(offset)(on) Standby Mute On
VO(offset)(mute)
0
0.8
2.2
3.0
4.2 5.5 VMODE (V)
coa021
Fig 8.
Behavior of mode selection pin MODE
12. Dynamic characteristics
12.1 Switching characteristics
Table 8. Dynamic characteristics VP = 30 V; Tamb = 25 C; unless otherwise specified. Symbol Parameter Internal oscillator fosc(typ) fosc VOSC typical oscillator frequency oscillator frequency ROSC = 30.0 k 325 250 345 365 450 kHz kHz Conditions Min Typ Max Unit
External oscillator or frequency tracking voltage on pin OSC SGND + 4.5 SGND + 5 [1]
SGND + 6 V V kHz
Vtrip(OSC) trip voltage on pin OSC ftrack
[1]
SGND + 2.5 450
tracking frequency
250
When using an external oscillator, the frequency fosc(ext) (500 kHz minimum, 900 kHz maximum) will result in a PWM frequency ftrack (250 kHz minimum, 450 kHz maximum) due to the internal clock divider; see Section 8.2.
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
12.2 Stereo and dual SE application characteristics
Table 9. Dynamic characteristics VP = 30 V; RL = 4 ; fi = 1 kHz; fosc = 345 kHz; RsL < 0.1 [1]; Tamb = 25 C; unless otherwise specified. Symbol Po Parameter output power Conditions L = 22 H; C = 680 nF; Tj = 85 C THD = 0.5 %; RL = 4 THD = 10 %; RL = 4 THD = 10 %; VP = 27 V THD Gv(cl) SVRR total harmonic distortion closed-loop voltage gain supply voltage ripple rejection between pin VDDPn and SGND Operating mode; fi = 100 Hz Operating mode; fi = 1 kHz Mute mode; fi = 100 Hz Standby mode; fi = 100 Hz between pin VSSPn and SGND Operating mode; fi = 100 Hz Operating mode; fi = 1 kHz Mute mode; fi = 100 Hz Standby mode; fi = 100 Hz Zi Vn(o) cs |Gv| mute CMRR po input impedance output noise voltage channel separation voltage gain difference mute attenuation common mode rejection ratio output power efficiency fi = 1 kHz; Vi = 2 V (RMS) Vi(CM) = 1 V (RMS) SE, RL = 4 SE, RL = 6 BTL, RL = 8 RDSon(hs) RDSon(ls)
[1] [2] [3] [4] [5] [6] [7] [8] [9]
[8] [4] [4] [4] [4] [4] [4] [4] [4] [2]
Min [3] [3]
Typ 90 110 80
Max Unit W W W % % dB dB dB dB dB dB dB dB dB k V V dB dB dB dB % % % m m
Po = 1 W; fi = 1 kHz Po = 1 W; fi = 6 kHz
29 45 -
0.05 0.05 30 90 70 75 120 80 60 80 115 63 160 85 70 75 75 88 90 88 200 190 31 1 -
between the input pins and SGND Operating mode; Rs = 0 Mute mode
[5] [6] [7]
high-side drain-source on-state resistance low-side drain-source on-state resistance
[9] [9]
-
RsL is the series resistance of low-pass LC filter inductor in the application. Output power is measured indirectly; based on RDSon measurement; see Section 13.3. THD is measured from 22 Hz to 20 kHz, using AES17 20 kHz brickwall filter. Maximum limit is guaranteed but may not be 100 % tested. Vripple = Vripple(max) = 2 V (p-p); Rs = 0 . Measured independently between VDDPn and SGND and between VSSPn and SGND. 22 Hz to 20 kHz, using AES17 20 kHz brickwall filter. 22 Hz to 22 kHz, using AES17 20 kHz brickwall filter; independent of Rs. Po = 1 W; Rs = 0 ; fi = 1 kHz. Vi = Vi(max) = 1 V (RMS); fi = 1 kHz. Leads and bond wires included.
TDA8920C_1
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Preliminary data sheet
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TDA8920C
2 x 110 W class-D power amplifier
12.3 Mono BTL application characteristics
Table 10. Dynamic characteristics VP = 30 V; RL = 8 ; fi = 1 kHz; fosc = 345 kHz; RsL < 0.1 [1]; Tamb = 25 C; unless otherwise specified. Symbol Po Parameter output power Conditions L = 22 H; C = 680 nF; Tj = 85 C THD = 0.5 %; RL = 8 THD = 10 %; RL = 8 THD Gv(cl) SVRR total harmonic distortion closed-loop voltage gain supply voltage ripple rejection between pin VDDPn and SGND Operating mode; fi = 100 Hz Operating mode; fi = 1 kHz Mute mode; fi = 100 Hz Standby mode; fi = 100 Hz between pin VSSPn and SGND Operating mode; fi = 100 Hz Operating mode; fi = 1 kHz Mute mode; fi = 100 Hz Standby mode; fi = 100 Hz Zi Vn(o) mute CMRR
[1] [2] [3] [4] [5] [6] [7]
[4] [4] [4] [4] [4] [4] [4] [4] [2]
Min [3] [3]
Typ 170 210
Max Unit W W % % dB dB dB dB dB dB dB dB dB k V V dB dB
Po = 1 W; fi = 1 kHz Po = 1 W; fi = 6 kHz
45
0.05 0.05 36 80 80 95 120 75 75 90 130 63 190 45 75 75 -
input impedance output noise voltage mute attenuation common mode rejection ratio
measured between the input pins and SGND Operating mode; Rs = 0 Mute mode fi = 1 kHz; Vi = 2 V (RMS) Vi(CM) = 1 V (RMS)
[5] [6] [7]
-
RsL is the series resistance of low-pass LC filter inductor in the application. Output power is measured indirectly; based on RDSon measurement; see Section 13.3. Total harmonic distortion is measured from 22 Hz to 20 kHz, using an AES17 20 kHz brickwall filter. Maximum limit is guaranteed but may not be 100 % tested. Vripple = Vripple(max) = 2 V (p-p); Rs = 0 . 22 Hz to 20 kHz, using an AES17 20 kHz brickwall filter; low noise due to BD modulation. 22 Hz to 20 kHz, using an AES17 20 kHz brickwall filter; independent of Rs. Vi = Vi(max) = 1 V (RMS); fi = 1 kHz.
TDA8920C_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 29 September 2008
16 of 40
NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
13. Application information
13.1 Mono BTL application
When using the power amplifier in a mono BTL application, the inputs of both channels must be connected in parallel and the phase of one of the inputs must be inverted; see Figure 7. In principle, the loudspeaker can be connected between the outputs of the two single-ended demodulation filters.
13.2 Pin MODE
To ensure a pop noise-free start-up, an RC time-constant must be applied to pin MODE. The bias-current setting of the VI-converter input is directly related to the voltage on pin MODE. In turn the bias-current setting of the VI-converters is directly related to the DC output offset voltage. A slow dV/dt on pin MODE results in a slow dV/dt for the DC output offset voltage, ensuring a pop noise-free start-up. A time-constant of 500 ms is sufficient to guarantee pop noise-free start-up; see Figure 4, Figure 5 and Figure 8 for more information.
13.3 Output power estimation
13.3.1 SE
Maximum output power:
2 RL ---------------------------------------------------- x V P x ( 1 - t min x 0.5 f osc ) R L + R DSon ( hs ) + R sL = --------------------------------------------------------------------------------------------------------------------------------2R L
P o ( 0.5% )
(1)
Maximum output current internally limited to 9.2 A: V P x ( 1 - t min x 0.5 f osc ) I o ( peak ) = ------------------------------------------------------------R L + R DSon ( hs ) + R sL Where: (2)
* * * * * * *
RL: load impedance RsL: series impedance of the filter coil RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent) fosc: oscillator frequency tmin: minimum pulse width (typical 150 ns, temperature dependent) VP: single-sided supply voltage or 0.5 x (VDD + |VSS|) Po(0.5 %): output power at the onset of clipping
Remark: Note that Io(peak) should be below 9.2 A (Section 8.3.2). Io(peak) is the sum of the current through the load and the ripple current. The value of the ripple current is dependent on the coil inductance and voltage drop over the coil.
TDA8920C_1
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Preliminary data sheet
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
13.3.2 Bridge-Tied Load (BTL)
Maximum output power:
2 RL ------------------------------------------------------------------ x 2V P x ( 1 - t min x 0.5 f osc ) R L + R DSon ( hs ) + R DSon ( ls ) = --------------------------------------------------------------------------------------------------------------------------------------------------2R L
P o ( 0.5% )
(3)
Maximum output current internally limited to 9.2 A: 2V P x ( 1 - t min x 0.5 f osc ) I o ( peak ) = -----------------------------------------------------------------------------------------R L + ( R DSon ( hs ) + R DSon ( ls ) ) + 2R sL Where: (4)
* * * * * * * *
RL: load impedance RsL: series impedance of the filter coil RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent) RDSon(ls): low-side RDSson of power stage output DMOS (temperature dependent) fosc: oscillator frequency tmin: minimum pulse width (typical 150 ns, temperature dependent) VP: single-sided supply voltage or 0.5 x (VDD + |VSS|) Po(0.5 %): output power at the onset of clipping
Remark: Note that Io(peak) should be below 9.2 A; see Section 8.3.2. Io(peak) is the sum of the current through the load and the ripple current. The value of the ripple current is dependent on the coil inductance and voltage drop over the coil.
13.4 External clock
To ensure duty cycle independent operation of the device, the external clock input frequency is internally divided by two. This implies that the external clock frequency is twice the internal clock frequency (typically 2 x 345 kHz = 690 kHz). If several class-D amplifiers are used together it is recommended that all devices run at the same switching frequency. This can be achieved by connecting all OSC pins together and feeding them from an external oscillator. When applying an external oscillator it is necessary to force pin OSC to a DC level above SGND. This disables the internal oscillator and causes the PWM to switch at half the external clock frequency. The internal oscillator requires an external resistor ROSC and capacitor COSC connected between pin OSC and pin VSSA. The noise contribution of the internal oscillator is supply voltage dependent. An external low-noise oscillator is recommended for low-noise applications running at high supply voltages.
TDA8920C_1
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Preliminary data sheet
Rev. 01 -- 29 September 2008
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
13.5 Noise
Noise should be measured using a high-order low-pass filter with a cut-off frequency of 20 kHz. The standard audio band-pass filters used in audio analyzers, do not suppress the residue of the carrier frequency sufficiently to ensure a reliable measurement of the audible noise. Noise measurements should be carried out preferably using AES17 (`brickwall') filters or an audio precision AUX 0025 filter (designed specifically for measuring class-D switching amplifiers).
13.6 Heatsink requirements
In many applications it may be necessary to connect an external heatsink to the TDA8920C. Equation 5 shows the relationship between the maximum power dissipation before activation of TFB and the total thermal resistance from junction to ambient. T j - T amb Rth ( j - a ) = ----------------------P (5)
Power dissipation (P) is determined by the efficiency of the TDA8920C. The efficiency measured as a function of output power is given in Figure 21. Power dissipation can be derived as a function of output power as shown in Figure 20.
30 P (W)
mbl469
(1)
20
(2)
10
(3) (4) (5)
0 0 20 40 60 80 100 Tamb (C)
(1) Rth(j-a) = 5 K/W. (2) Rth(j-a) = 10 K/W. (3) Rth(j-a) = 15 K/W. (4) Rth(j-a) = 20 K/W. (5) Rth(j-a) = 35 K/W.
Fig 9.
Derating curves for power dissipation as a function of maximum ambient temperature
TDA8920C_1
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Preliminary data sheet
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
In the following example, a heatsink calculation is made for an 8 BTL application with a 30 V supply: The audio signal has a crest factor of 10 (the ratio between peak power and average power (20 dB)), this means that the average output power is 110 of the peak power. Thus, the peak RMS output power level is the 0.5 % THD level, i.e. 170 W. The average power is then 110 x 130 W = 17 W. The dissipated power at an output power of 17 W is approximately 5 W. When the maximum expected ambient temperature is 85 C, the total Rth(j-a) becomes ( 140 - 85 ) ------------------------- = 11 K/W 5 Rth(j-a) = Rth(j-c) + Rth(c-h) + Rth(h-a) Rth(j-c) (thermal resistance from junction to case) = 1.1 K/W Rth(c-h) (thermal resistance from case to heatsink) = 0.5 K/W to 1 K/W (dependent on mounting) Based on this the thermal resistance between heatsink and ambient temperature is: Rth(h-a) (thermal resistance from heatsink to ambient) = 11 - (1.1 + 1) = 8.9 K/W The derating curves for power dissipation (for several Rth(j-a) values) are illustrated in Figure 9. A maximum junction temperature Tj = 150 C is taken into account. The maximum allowable power dissipation for a given heatsink size can be derived or the required heatsink size can be determined at a required power dissipation level; see Figure 9.
13.7 Output current limiting
To guarantee the robustness of the TDA8920C, the maximum output current that can be delivered by the output stage is limited to 9.2 A. OverCurrent Protection (OCP) is built in for each output power switch. If the current flowing through any of the power switches exceeds the 9.2 A threshold current due to, for example, a short-circuit to a supply line or across the load, the maximum output current of the amplifier is regulated to 9.2 A. The TDA8920C amplifier distinguishes between low-ohmic short-circuit conditions and other overcurrent conditions such as dynamic impedance drops of the loudspeakers used. The impedance threshold (Zth) depends on the supply voltage used. Depending on the impedance of the short-circuit, the amplifier reacts as follows:
* Short-circuit impedance (> Zth): The maximum output current of the amplifier is
regulated to 9.2 A but the amplifier will not shut down the PWM outputs. Effectively this results in a clipped output signal across the load (behavior very similar to voltage clipping).
* Short-circuit impedance (< Zth): The amplifier limits the maximum output current to
9.2 A and at the same time discharges the capacitor on pin PROT. When the voltage across this capacitor drops below the threshold voltage, the amplifier shuts down completely and an internal timer is started.
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
A typical value for the capacitor connected to pin PROT can be from 10 pF to 220 pF; see Figure 10. After a fixed time of 100 ms the amplifier switches on. If the requested output current is still too high, the amplifier switches off. Thus the amplifier tries to switch to the Operating mode every 100 ms. The average power dissipation will be low in this situation because of the low duty cycle. If the overcurrent condition is removed, the amplifier stays in Operating mode after restarting. This fully protects the TDA8920C amplifier against short-circuit conditions while at the same time eliminating so-called audio holes resulting from loudspeaker impedance drops.
Table 11. Type TDA8920CJ/N1 Current limiting behavior during low output impedance conditions at different values of CPROT VP (V) VI (mV, p-p) f (Hz) CPROT PWM output stops (pF) Short (0 ) Short (0.5 ) 20 1000 20 1000 1000
[1]
Short (1 ) OVP[1] no OVP[1] no no
29.5 500
10 10 15 15 220
yes yes yes yes no
yes yes yes no no
Overvoltage protection activation caused by supply pumping due to the weak short-circuit; see Section 13.8.
13.8 Pumping effects
In a typical stereo half-bridge SE application the TDA8920C is supplied by a symmetrical voltage (e.g. VDD = 30 V and VSS = -30 V). When the amplifier is used in an SE configuration, a `pumping effect' can occur. During one switching interval, energy is taken from one supply (e.g. VDD), while a part of that energy is returned to the other supply line (e.g. VSS) and vice versa. When the voltage supply source cannot sink energy, the voltage across the output capacitors of that voltage supply source increases and the supply voltage is pumped to higher levels. The voltage increase caused by the pumping effect depends on:
* * * * *
Speaker impedance Supply voltage Audio signal frequency Value of supply line decoupling capacitors Source and sink currents of other channels
In applications using the TDA8920C ensure pumping effects are minimized and prevent malfunctions of either the audio amplifier and/or the voltage supply source. Amplifier malfunction due to the pumping effect can trigger UVP, OVP or UBP. The most effective solution against pumping effects is to use the TDA8920C in a mono full-bridge application. In the case of stereo half-bridge applications, adapt the power supply, for example, by increasing the values of the supply decoupling capacitors.
TDA8920C_1
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Preliminary data sheet
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21 of 40
NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
13.9 Application schematics
Notes for the application schematic:
* Connect a solid ground plane to VSS around the switching amplifier to prevent
emission
* * * *
Place 100 nF capacitors as close as possible to the TDA8920C power supply pins Internally connect the internal heat spreader of the TDA8920C to VSS Connect the external heatsink to the ground plane Use a thermally conductive, electrically non-conductive, Sil-Pad between the backside of the TDA8920C and a small external heatsink unbalanced signal sources. In case of hum due to floating inputs, connect the shielding or source ground to the amplifier ground. Jumpers J1 and J2 are open on set level and closed on the stand-alone demo board
* Use differential inputs for the most effective system level audio performance with
* Minimum total required capacitance for each power supply line is 3300 F
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Preliminary data sheet
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Preliminary data sheet Rev. 01 -- 29 September 2008
(c) NXP B.V. 2008. All rights reserved. TDA8920C_1
NXP Semiconductors
RVDDA 10
VDDA VDDP
VDDP
CVDDP 470 F CVP 22 F
SINGLE-ENDED OUTPUT FILTER VALUES LOAD LLC CLC mode control VDDP
ROSC 30 k CVDDP 100 nF
GND
CVSSP 470 F
VSSA VSSP
2 to 3 3 to 6 4 to 8 VSSP
CVSSP 100 nF RSN 10
10 H 15 H 22 H
1000 nF 680 nF 470 nF
VSSP
RVSSA 10
CVP 100 nF
VDDP
CSN 220 pF CSN 220 pF
VSSA OSC
VDDP1
n.c. n.c. n.c.
CIN 470 nF
+ IN1 -
IN1P
4 2
5
6
1
23
8
VSSP1 11
MODE
VSSP 10 OUT1
CBO
LLC RZO 22
CIN 470 nF
IN1M
3
9
BOOT1
+
CLC 15 nF
SGND
CIN 470 nF
19
- CZO 100 nF
TDA8920CJ
15 BOOT2
CBO 15 nF
- IN2 +
IN2P
22 14 OUT2
LLC
CIN 470 nF
IN2M
21 20 VDDA 18 VSSA 12 STABI 7 PROT 17 VSSD 16 VDDP2 13 VSSP2
RSN 10 CVSSP 100 nF
VDDP
CSN 220 pF CSN 220 pF CLC
RZO 22
-
2 x 110 W class-D power amplifier
CZO + 100 nF
CVDDA 100 nF
CVSSA 100 nF CSTAB 470 nF CPROT(1)
CVDDP 100 nF
CVP 100 nF
VSSP
TDA8920C
VDDA
VSSA
VSSP
VSSA
VDDP
VSSP
001aai855
23 of 40
(1) Value of CPROT can be in the range 10 pF to 220 pF.
Fig 10. Typical application diagram for pop noise-free start up and switch off
NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
13.10 Layout and grounding
To obtain a high-level system performance, certain grounding techniques are essential. The input reference grounds have to be tied to their respective source grounds and must have separate tracks from the power ground tracks. This prevents the large (output) signal currents from interfering with the small AC input signals. The small-signal ground tracks should be physically located as far as possible from the power ground tracks. Supply and output tracks should be as wide as possible to deliver maximum output power.
R20, R21 ground
R19 FBGND
001aai421
Fig 11. Printed-circuit board layout (quasi-single-sided); component view
TDA8920C_1
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Preliminary data sheet
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
13.11 Curves measured in reference design
10 THD (%) 1
001aai856
(1)
10-1
(2)
10-2
(3)
10-3 10-2
10-1
1
10
102 Po (W)
103
VP = 30 V, fosc = 350 kHz, 2 x 4 SE configuration. (1) OUT2, fi = 6 kHz. (2) OUT2, fi = 1 kHz. (3) OUT2, fi = 100 Hz.
Fig 12. THD as a function of output power, SE configuration with 2 x 4 load
10 THD (%) 1
001aai857
(1)
10-1
(2)
10-2
(3)
10-3 10-2
10-1
1
10
102 Po (W)
103
VP = 30 V, fosc = 350 kHz, 2 x 6 SE configuration. (1) OUT2, fi = 6 kHz. (2) OUT2, fi = 1 kHz. (3) OUT2, fi = 100 Hz.
Fig 13. THD as a function of output power, SE configuration with 2 x 6 load
TDA8920C_1
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
10 THD (%) 1
001aai858
10-1
(1)
(2)
10-2
(3)
10-3 10-2
10-1
1
10
102 Po (W)
103
VP = 30 V, fosc = 350 kHz, 1 x 8 BTL configuration. (1) fi = 6 kHz. (2) fi = 1 kHz. (3) fi = 100 Hz.
Fig 14. THD as a function of output power, BTL configuration with 1 x 8 load
10 THD (%) 1
001aai424
10-1
(1)
10-2
(2)
10-3 10
102
103
104
fi (Hz)
105
VP = 30 V, fosc = 350 kHz, 2 x 4 SE configuration. (1) OUT2, Po = 1 W. (2) OUT2, Po = 10 W.
Fig 15. THD as a function of frequency, SE configuration with 2 x 4 load
TDA8920C_1
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
10 THD (%) 1
001aai701
10-1
(1)
10-2
(2)
10-3 10
102
103
104
fi (Hz)
105
VP = 30 V, fosc = 350 kHz, 2 x 6 SE configuration. (1) OUT2, Po = 1 W. (2) OUT2, Po = 10 W.
Fig 16. THD as a function of frequency, SE configuration with 2 x 6 load
10 THD (%) 1
001aai702
10-1
10-2
(1) (2)
10-3 10
102
103
104
fi (Hz)
105
VP = 30 V, fosc = 350 kHz, 1 x 8 BTL configuration. (1) Po = 1 W. (2) Po = 10 W.
Fig 17. THD as a function of frequency, BTL configuration with 1 x 8 load
TDA8920C_1
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TDA8920C
2 x 110 W class-D power amplifier
0 cs (dB) -20
001aai703
-40
-60
-80
-100 10
102
103
104 fi (Hz)
105
VP = 30 V, fosc = 350 kHz, 2 x 4 SE configuration. OUT1 and OUT2 both 1 W and 10 W respectively.
Fig 18. Channel separation as a function of frequency, SE configuration with 2 x 4 load
0 cs (dB) -20
001aai704
-40
-60
-80
-100 10
102
103
104 fi (Hz)
105
VP = 30 V, fosc = 350 kHz, 2 x 6 SE configuration. OUT1 and OUT2 both 1 W and 10 W respectively.
Fig 19. Channel separation as a function of frequency, SE configuration with 2 x 6 load
TDA8920C_1
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
P (W)
40 35 30 25
(1)
001aai705
20
(2)
15
(3)
10 5 0 0 20 40 60 80 100 Po (W) 120
VP = 31.5 V, fi = 1 kHz, fosc = 325 kHz. (1) 2 x 4 SE configuration. (2) 2 x 6 SE configuration. (3) 2 x 8 SE configuration.
Fig 20. Power dissipation as a function of output power per channel, SE configuration
100 (%) 80
(1) (2)
001aai706
(3)
60
40
20
0 0 20 40 60 80 100 Po (W) 120
VP = 30 V, fi = 1 kHz, fosc = 325 kHz. (1) 2 x 8 SE configuration. (2) 2 x 6 SE configuration. (3) 2 x 4 SE configuration.
Fig 21. Efficiency as a function of output power per channel, SE configuration
TDA8920C_1
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Preliminary data sheet
Rev. 01 -- 29 September 2008
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
140 Po (W) 120
(1)
001aai859
100
(2)
80 60 40 20 0 12.5
(3) (4)
17.5
22.5
27.5 VP (V)
32.5
Infinite heat sink used. fi = 1 kHz, fosc = 325 kHz. (1) THD = 10 %, 4 . (2) THD = 0.5 %, 4 ; THD = 10 %, 6 . (3) THD = 10 %, 8 . (4) THD = 0.5 %, 6 . (5) THD = 0.5 %, 8 .
Fig 22. Output power as a function of supply voltage, SE configuration
300 Po (W)
(1)
001aai860
200
(2) (3)
100
(4)
0 12.5
17.5
22.5
27.5 VP (V)
32.5
Infinite heat sink used. fi = 1 kHz, fosc = 325 kHz. (1) THD = 10 %, 8 . (2) THD = 0.5 %, 8 . (3) THD = 10 %, 16 . (4) THD = 0.5 %, 16 .
Fig 23. Output power as a function of supply voltage, BTL configuration
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TDA8920C
2 x 110 W class-D power amplifier
45 Gv(cl) (dB) 40
(1)
001aai709
35
30
(2) (3) (4)
25
20 10
102
103
104 fi (Hz)
105
VP = 30 V, fosc = 350 kHz, Vi = 100 mV, Rs = 0 , Ci = 330 pF. (1) 1 x 8 BTL configuration. (2) 2 x 4 SE configuration. (3) 2 x 6 SE configuration. (4) 2 x 8 SE configuration.
Fig 24. Closed-loop voltage gain as a function of frequency, Rs = 0 , Ci = 330 pF
-20 SVRR (dB) -40 -60
(1)
001aai710
-80
(2)
-100
-120 -140 10
(3)
102
103
104 fripple (Hz)
105
Ripple on VDD, short on input pins. VP = 30 V, fosc = 350 kHz, RL = 4 , Vripple = 2 V (p-p). (1) OUT2, Mute mode. (2) OUT2, Operating mode. (3) OUT2, Standby mode.
Fig 25. SVRR as a function of ripple frequency, ripple on VDD
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TDA8920C
2 x 110 W class-D power amplifier
-20 SVRR (dB) -40 -60
001aai711
-80 -100
(2) (1)
-120 -140 10
(3)
102
103
104 fripple (Hz)
106
Ripple on VSS, short on input pins. VP = 30 V, fosc = 350 kHz, RL = 4 , Vripple = 2 V (p-p). (1) OUT2, Mute mode. (2) OUT2, Operating mode. (3) OUT2, Standby mode.
Fig 26. SVRR as a function of ripple frequency, ripple on VSS
10 Vo (V) 1 10-1 10-2 10-3 10-4
(1) (2)
001aai712
10-5 10-6 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VMODE (V)
VP = 30 V, fosc = 325 kHz. (1) OUT1, down. (2) OUT1, up.
Fig 27. Output voltage as a function of mode voltage
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Preliminary data sheet
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TDA8920C
2 x 110 W class-D power amplifier
-50 mute (dB) -60
001aai713
-70
(1) (2) (3)
-80
-90 10
102
103
104 fi (Hz)
105
VP = 30 V, fosc = 325 kHz, Vi = 2 V (RMS). (1) OUT2, 8 . (2) OUT2, 6 . (3) OUT2, 0 .
Fig 28. Mute attenuation as a function of frequency
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TDA8920C
2 x 110 W class-D power amplifier
14. Package outline
DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1
non-concave x D Dh
Eh
view B: mounting base side A2
d
A5 A4
B j
E2 E
E1
L2 L1 L3
L 1 Z e e1 wM 23
Q m
c e2
vM
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT A 2 mm A4 A5 bp c D (1) d D h E (1) e e1 e2 Eh E1 E2 j L L1 L2 L3 m Q v w x
Z (1)
12.2 4.6 1.15 1.65 0.75 0.55 30.4 28.0 12 2.54 1.27 5.08 11.8 4.3 0.85 1.35 0.60 0.35 29.9 27.5
6 10.15 6.2 1.85 3.6 9.85 5.8 1.65 2.8
14 10.7 2.4 1.43 2.1 4.3 0.6 0.25 0.03 45 13 9.9 1.6 0.78 1.8
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT411-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 98-02-20 02-04-24
Fig 29. Package outline SOT411-1 (DBS23P)
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height
SOT566-3
E D x
A X
c y E2 HE vM A
D1 D2 1 pin 1 index Q A2 E1 A4 Lp detail X 24 Z e bp 13 wM (A3) A 12
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A A2 max. 3.5 3.5 3.2 A3 0.35 A4(1) bp c D(2) D1 D2 1.1 0.9 E(2) 11.1 10.9 E1 6.2 5.8 E2 2.9 2.5 e 1 HE 14.5 13.9 Lp 1.1 0.8 Q 1.7 1.5 v w x y Z 2.7 2.2 8 0
+0.08 0.53 0.32 16.0 13.0 -0.04 0.40 0.23 15.8 12.6
0.25 0.25 0.03 0.07
Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT566-3 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 03-02-18 03-07-23
Fig 30. Package outline SOT566-3 (HSOP24)
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NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
TDA8920C_1 (c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 29 September 2008
36 of 40
NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
15.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 31) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13
Table 12. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 13. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 31.
TDA8920C_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 29 September 2008
37 of 40
NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 31. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
16. Revision history
Table 14. Revision history Release date 20080929 Data sheet status Preliminary data sheet Change notice Supersedes Document ID TDA8920C_1
TDA8920C_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 29 September 2008
38 of 40
NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA8920C_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 29 September 2008
39 of 40
NXP Semiconductors
TDA8920C
2 x 110 W class-D power amplifier
19. Contents
General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pulse-width modulation frequency . . . . . . . . . . 8 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal protection . . . . . . . . . . . . . . . . . . . . . . 8 Thermal FoldBack (TFB) . . . . . . . . . . . . . . . . . 8 OverTemperature Protection (OTP) . . . . . . . . . 9 OverCurrent Protection (OCP) . . . . . . . . . . . . . 9 Window Protection (WP). . . . . . . . . . . . . . . . . 10 Supply voltage protection . . . . . . . . . . . . . . . . 10 Differential audio inputs . . . . . . . . . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal characteristics. . . . . . . . . . . . . . . . . . 12 Static characteristics. . . . . . . . . . . . . . . . . . . . 13 Dynamic characteristics . . . . . . . . . . . . . . . . . 14 Switching characteristics . . . . . . . . . . . . . . . . 14 Stereo and dual SE application characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 15 12.3 Mono BTL application characteristics . . . . . . . 16 13 Application information. . . . . . . . . . . . . . . . . . 17 13.1 Mono BTL application . . . . . . . . . . . . . . . . . . . 17 13.2 Pin MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13.3 Output power estimation. . . . . . . . . . . . . . . . . 17 13.3.1 SE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13.3.2 Bridge-Tied Load (BTL) . . . . . . . . . . . . . . . . . 18 13.4 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.5 Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 13.6 Heatsink requirements . . . . . . . . . . . . . . . . . . 19 13.7 Output current limiting. . . . . . . . . . . . . . . . . . . 20 13.8 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 21 13.9 Application schematics . . . . . . . . . . . . . . . . . . 22 13.10 Layout and grounding . . . . . . . . . . . . . . . . . . . 24 13.11 Curves measured in reference design . . . . . . 25 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 34 15 Soldering of SMD packages . . . . . . . . . . . . . . 36 15.1 Introduction to soldering . . . . . . . . . . . . . . . . . 36 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.1.1 8.3.1.2 8.3.2 8.3.3 8.3.4 8.4 9 10 11 12 12.1 12.2 15.2 15.3 15.4 16 17 17.1 17.2 17.3 17.4 18 19 Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 37 38 39 39 39 39 39 39 40
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 September 2008 Document identifier: TDA8920C_1

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