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Features
* * * * * * * * *
Fully Integrated Fractional-N PLL ASK and Closed Loop FSK Modulation Output Power Up to +12.5 dBm from 300 MHz to 450 MHz Current Consumption is Scaled by Output Power Programming Fast Crystal Oscillator Start-up Time of Typically 200 s Low Current Consumption of Typically 7.3 mA at 5.5 dBm Only One 13.0000 MHz Crystal for 314.1 MHz to 329.5 MHz and 424.5 MHz to 439.9 MHz Operation Single Ended RF Power Amplifier Output Many Software Programmable Options Using SPI: - Output Power from -0.5 dBm to +12.5 dBm - RF Frequency from 300 MHz to 450 MHz with Different Crystals - FSK Deviation with 396 Hz Resolution - CLK Output Frequency 3.25 MHz or 1.625 MHz Data Rate Up to 40 kbit/s (Manchester) 2 KV HBM ESD Protection Including XTO Operating Temperature Range of -40C to +125C Supply Voltage Range of 1.9V to 3.6V TSSOP10 Package
Fractional-N PLL Transmitter IC ATA5749 Preliminary
* * * * *
Benefits
* * * * *
Robust Crystal Oscillator with Fast Start Up and High Reliability Lower Inventory Costs and Reduced Part Number Proliferation Longer Battery Lifetime Supports Multi-channel Operation Wide Tolerance Crystal Possible with PLL Software Compensation
1. Description
The ATA5749 is a fractional-N-PLL transmitter IC for 300 MHz to 450 MHz operation and is especially targeted for Tire Pressure Sensor Gauges, Remote Keyless Entry, and Passive Entry and other automotive applications. It operates at data rates up to 40 kbit/s Manchester for ASK and FSK with a typical 5.5 dBm output power at 7.3 mA. Transmitter parameters such as output power, output frequency, FSK deviation, and current consumption can be programmed using the SPI interface. This fully integrated PLL transmitter IC simplifies RF board design and results in very low material costs.
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Figure 1-1.
Block Diagram
ATA5749
CLK_DRV 1 4 or 8
Fractional-N-PLL CLK_ON 2 FREQ[0:14] FSEP[0:7] DIV_CNTRL FSK_mod SDIN_TXDIN 9 GND XTO_RDY XTO Signal
CLK
1
Power up/down
10
EN
Frac. Div.
SCK
3
Digital Control 433_N315 and Registers ASK_mod
PFD
8
VS
PWR[0:3]
CP
ANT2 4 7 XTO1
LP XTO (FOX)
5
ANT1
PA VCO
6
XTO2
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2. Pin Configuration
Figure 2-1. TSSOP10 Package Pinout
CLK 1 10 EN
SDIN_TXDIN
2
9
GND
ATA5749
SCK 3 8 VS
ANT2
4
7
XTO1
ANT1
5
6
XTO2
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10
Pin Description
Symbol CLK SDIN_TXDIN SCK ANT2 ANT1 XTO2 XTO1 VS GND EN Function CLK output Serial bus data input and TX data input Serial bus clock input Antenna interface Antenna interface Crystal/CLOAD2 connection Crystal/CLOAD1 connection Supply input Supply GND Enable input
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3. Functional Description
3.1 Fractional-N PLL
The ATA5749 block diagram is shown in Figure 1-1 on page 2. The operation of the PLL is determined by the contents of a 32-bit configuration register. The 15-bit value FREQ is used with the 1-bit 434_N315 flag to determine the RF carrier frequency. This results in a user-selectable frequency step size of 793 Hz (with 13.000 MHz crystal). With this level of resolution, it is possible to compensate for crystal tolerance by adjusting the value of FREQ accordingly. This enables the use of lower cost crystals without compromising final accuracy. In addition, software programming of RF carrier frequency allows this device to be used in some multi-channel applications. Modulation type is selected with the 1-bit ASK_NFSK flag. FSK modulation is achieved by modifying the divider block in the feedback loop. The benefit to this approach is that performancereducing RF spurs (common in applications that create FSK by "pulling" the load capacitance in the crystal oscillator circuit) are completely eliminated. The 8-bit value FSEP establishes the FSK frequency deviation. It is possible to obtain FSK frequency deviations from 396 Hz to 101 KHz in steps of 396 Hz. The PLL lock time is 1280/(external crystal frequency) and amounts to 98.46 s when using a 13.0000 MHz crystal. When added to the crystal oscillator start-up time, a very fast time-to-transmit is possible (typically 300 s). This feature extends battery life in applications like Tire Pressure Monitoring Systems, where the message length is often shorter than 10 ms and the time "wasted" during start-up and settling time becomes more significant.
3.2
Selecting the RF Carrier Frequency
The fractional divider can be programmed to generate an RF output frequency fRF according to the formulas shown in Table 3-1. Note that in the case of fRF ASK, the FSEP/2 value is rounded down to the next integer value if FSEP is an odd number.
Table 3-1.
RF Output Parameter Formulas
S434_N315 = LOW (24 + (FREQ + 0.5)/16384) x fXTO (24 + (FREQ + FSEP + 0.5)/16384) x fXTO FSEP/32768 x fXTO (24 + (FREQ + FSEP/2 + 0.5)/16384) x fXTO S434_N315 = HIGH (32.5 + (FREQ + 0.5)/16384) x fXTO (32.5 + (FREQ + FSEP + 0.5)/16384) x fXTO FSEP/32768 x fXTO (32.5 + (FREQ + FSEP/2 + 0.5)/16384) x fXTO
RF Output Parameter fRF_FSK_LOW fRF_FSK_HIGH fDEV__FSK fRF ASK
FSEP can take on the values of 1 to 255. Using a 13.000 MHz crystal, the range of frequency deviation fDEV_FSK is programmable from 396 Hz to 101.16 kHz in steps of 396 Hz. For example, with FSEP = 100 the output frequency is FSK modulated with fDEV_FSK = 39.6 kHz. FREQ can take values in the range of values 2500 and 22000. Using a 13.0000 MHz crystal, the output frequency f RF can be programmed to 315 MHz by setting FREQ[0:14] = 3730, FSEP[0:7] = 100 and S434_N315 = 0. By setting FREQ[0:14] = 14342, FSEP[0:7] = 100 and S434_N315 = 1, 433.92 MHz can be realized.
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The PA is enabled when the PLL is locked and the configuration register programming is completed. Upon enabling PA at FSK-mode, the RF output power will be switched on. At ASK mode, the input signal must be additionally set high for RF at output pins. The output power is user programmable from -0.5 dBm to +12.5 dBm in steps of approximately 1 dB. Changing the output power requirements, you also modify the current consumption. This gives the user the option to optimize system performance (RF link budget versus battery life). The PA is implemented as a Class-C amplifier, which uses an open-collector output to deliver a current pulse that is nearly independent from supply voltage and temperature. The working principle is shown in Figure 3-1. Figure 3-1. Class C Power Amplifier Output
VANT1
VS
IANT2 IPulse = (PWR[0:3])
VS VANT1 Power Meter C2 L1 ANT1 5 IANT2 50 ZLOPT
ANT2 4
The peak value of this current pulse IPulse is calibrated during ATA5749 production to about 20%, which corresponds to about 1.5 dB variation in output power for a given power setting under typical conditions. The actual value of IPulse can be programmed with the 4-bit value in PWR. This allows the user to scale both the output power and current consumption to optimal levels. ASK modulation is achieved by using the SDIN_TXDIN signal where a HIGH on this pin corresponds to RF carrier "ON" and a LOW corresponds to RF "OFF". FSK uses the same signal path but HIGH switch on the upper FSK-frequency.
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3.3
Crystal Oscillator
The crystal oscillator (XTO) is an amplitude-regulated Pierce oscillator. It has fixed function and is not programmable. The oscillator is enabled when the EN is "set". After the oscillator's output amplitude reaches an acceptable level, the XTO_RDY flag is "set". The CLK-pin becomes active if CLK_ON is set. The PLL receives its reference frequency. Typically, this process takes about 200 s when using a small sized crystal with a motional capacitance of 4 fF. This start-up time strongly depends on the motional capacitance of the crystal and is lower with higher motional capacitance. The high negative starting impedance of RXTO12_START > 1500 is important to minimize the failure rate due to the "sleeping crystal" phenomena (more common among very small sized 3.2 mm x 2.5 mm crystals).
3.4
Clock Driver
The clock driver block shown in Figure 1-1 on page 2 is programmed using the CLK_ONLY, CLK_ON, and DIV_CNTRL bits in the configuration register. When CLK_ONLY is "clear", normal operation is selected and the fractional-N PLL is operating. When CLK_ON is "set", the CLK output is enabled. The crystal clock divider ratio can be set to divide by 4 when DIV_CNTRL is "set" and divide by 8 when DIV_CNTRL is "clear". With a 13.0000 MHz crystal, this yields an output of 3.25 MHz or 1.625 MHz, respectively. When CLK_ON is "clear", no clock is available at CLK and the transmitter has less current consumption. The CLK signal can be used to clock a microcontroller. It is CMOS compatible and can drive up to 20 pF of load capacitance at 1.625 MHz and up to 10 pF at 3.25 MHz. When the device is in power-down mode, the CLK output stays low. Upon power up, CLK output remains low until the amplitude detector of the crystal oscillator detects sufficient amplitude and XTO_RDY and CLK_ON are "set". After this takes place, CLK output becomes active. The CLK output is synchronized with the XTO_RDY signal so that the first period of the CLK output is always a full period (no CLK output spike at activation). To lower overall current consumption, it is possible to power down the entire chip except for the crystal oscillator block. This can be achieved when the CLK_ONLY is "set".
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4. Application
4.1 Typical Application
Typical Application Circuit
IO1
Figure 4-1.
Microcontroller
CLK
CLK
1
ATA5749
CLK_DRV 1
XTO_RDY XTO Signal
Power up/down
10
EN
IO2 CLK_ON IO3 2
4 or 8
Fractional-N-PLL DIV_CNTRL FSK_mod 9 FREQ[0:14] SDIN_TXDIN FSEP[0:7] GND
Frac. Div.
C6
SCK
3
Digital Control 433_N315 and Registers ASK_mod
PFD
8
VS
PWR[0:3]
VS
CP
C3 ANT2 4 7 C4 XTO1
Loop antenna
LP XTO (FOX)
5 XTAL
ANT1
PA VCO
6
XTO2 C5
C2
L1
C1 VS
Figure 4-1 shows the typical application circuit. For C6, the supply-voltage blocking capacitor, value of 68 nF X7R is recommended. C2 and C3 are NPO capacitors used to match the loop antenna impedance to the power amplifier optimum load impedance. They are based on the PCB trace antenna and are 20 pF NPO capacitors. C1 (typically 1 nF X7R) is needed for the supply blocking of the PA. In combination with L1 (200 nH to 300 nH), they prevent the power amplifier from coupling to the supply voltage and disturbing PLL operation. They should be placed close to pin 5. L1 also provides a low resistive path to VS to deliver the DC current to ANT1.
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The PCB loop antenna should not exceed a trace width of 1.5 mm otherwise the Q-factor of the loop antenna is too high. C4 and C5 should be selected so that the XTO runs on the load resonance frequency of the crystal. A crystal with a load capacitance of 9 pF is recommended for proper start-up behavior and low current consumption. When determining values for C4 and C5, a parasitic capacitance of 3 pF should be included. With value of 15 pF for C4 and C5, an effective load capacitance of 9 pF can be achieved e.g. 9 pF = (15 pF + 3 pF)/2. The supply VS is typically delivered from a single Li-Cell. 4.1.1 Antenna Impedance Matching The maximum output power is achieved by using load impedances according to Table 4-1 and Table 4-2 on page 9 and the output power. The load impedance ZLOPT is defined as the impedance seen from the ATA5749 ANT1, ANT2 into the matching network. This is not the output impedance of the IC but essentially the peak voltage divided by the peak current with some additional parasitic effects (Cpar). Table 4-1 and Table 4-2 do not contain information pertaining to C3 in Figure 4-2, which is an option for better matching at low power steps. Figure 4-2 is the circuit that was used to obtain the typical output power measurements in Figure 4-3 on page 10 and typical current consumption in Figure 4-4 on page 10. Table 4-1 and Table 4-2 on page 9 provide recommended values and performance info at various output power levels. For reference, ZLOPT is defined as the impedance seen from the ATA5749 ANT1, ANT2 into the matching network. Figure 4-2. Output Power Measurement Circuit
ZLOPT
ANT2 4
Power Meter C2 ANT1 5 50 C3 L1 PA
C1 VS
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The used parts at Table 4-1 and Table 4-2 on page 9 are: Inductors: high Q COILCRAFT 0805CS; Capacitors: AVX ACCU-P 0402
Table 4-1.
PWR Register 3 4 5 6 7 8 9 10 11 12 13 14 15
Measured PA Matching at 315 MHz (CLK_ON = "LOW") at Typ. Samples
Desired Power (dBm) -0.5 1.0 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 L1 (nH) 110 100 100 100 82 82 68 68 68 56 47 47 47 C1 (pF) 1.2 1.5 1.5 1.5 1.8 2.2 2.7 2.7 3.3 3.6 4.7 5.6 5.6 C2 (pF) 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 RLOPT () 2950 1940 1550 1250 1000 730 580 460 350 320 250 190 160 ZLOPT () 110 + 540j 150 + 520j 190 + 520j 220 + 480j 240 + 430j 280 + 360j 290 + 300j 290 + 290j 280 + 225j 250 + 150j 215 + 85j 180 + 50j 160 + 45j Cpar (pF) 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 Actual Power (dBm) -0.37 1.12 2.11 3.23 4.38 5.42 7.14 8.22 8.63 9.79 10.52 11.67 13
Table 4-2.
PWR Register 3 4 5 6 7 8 9 10 11 12 13 14 15
Measured PA Matching at 433.92 MHz (CLK_ON = "LOW") at Typ. Samples
Desired Power (dBm) -0.5 1.0 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 L1 (nH) 68 56 56 47 47 47 43 36 33 36 36 27 27 C1 (pF) 0,9 2.7 + 2.2 1.2 1.8 1.6 1.8 2.2 2.4 3 2.7 3.6 4.7 4.7 C2 (pF) 1.5 1.5 1.5 5.6 5.6 5.6 1 1 1 1 1 1 1 RLOPT () 2800 1850 1450 1150 950 680 560 450 340 310 230 180 150 ZLOPT () 60 + 400j 90 + 390j 110 + 380j 130 + 370j 150 + 350j 180 + 300j 200 + 270j 210 + 230j 200 + 170j 195 + 150j 175 + 100j 150 + 70j 130 + 50j Cpar (pF) 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 Actual Power (dBm) -0.62 1.3 2.73 3.03 4.63 6.18 6.66 7.91 8.68 9.8 10.49 11.6 12.5
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Figure 4-3.
15 13 11
Typical Measured Output Power
VS = 3.6V, PWR[0:15] = 15]
315 MHz 433 MHz
VS = 3.0V, PWR[0:15] = 15
Pmeas [dBm]
9 7
VS = 1.9V, PWR[0:15] = 15 VS = 3.6V, PWR[0:15] = 8
5 3 1 -40 27
VS = 3.0V, PWR[0:15] = 8 VS = 1.9V, PWR[0:15] = 8
85
125
Temperature [C]
Figure 4-4.
23 21 19 17
Typical Current Consumption I at Port VS
VS = 3.6V, P WR[0:15] = 15
315MHz 433MHz
Ivs [mA]
VS = 3.0V, P WR[0:15] = 15 VS = 1.9V, P WR[0:15] = 15
15 13 11 9 7 5 -40 27
VS = 1.9V, P WR[0:15] = 8 VS = 3.6V, P WR[0:15] = 8 VS = 3.0V, P WR[0:15] = 8
85
125
Temperature [C]
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5. Pulling of Frequency due to ASK Modulation (PA Switching)
The switching effect on VCO frequency in ASK Mode is very low if a correct PCB layout and decoupling is used. Therefore, power ramping is not needed to achieve a clean spectrum (see Figure 5-1). Figure 5-1. Typical RF Spectrum of 40 kHz ASK Modulation at Pout = 12.5 dBm
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6. Configuration Register
6.1 General Description
The user must program all 32 bits of the configuration register upon power up (EN = HIGH) or whenever changes to operating parameters are desired. The configuration register bit assignments and descriptions can be found in Table 6-1 and Table 6-2.
Table 6-1.
MSB 31 CLK_ ONLY
Organization of the Control Register
20 FREQ [5] 19 FREQ [4] 18 17 16 FREQ FREQ FREQ [3] [2] [1]
30 29 28 27 26 25 24 23 22 21 S434_ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ N315 [14] [13] [12] [11] [10] [9] [8] [7] [6]
Frequency Adjust = FREQ[0..14] FREQ[0] + 2 x FREQ[1] + 4 x FREQ[2] + ... + FREQ[14] x 16384 = 0..32767
LSB 15 FREQ [0] 14 FSEP [7] 13 FSEP [6] 12 FSEP [5] 11 FSEP [4] 10 FSEP [3] 9 FSEP [2] 8 FSEP [1] 7 6 5 FSEP DIV_ PWR [0] CNTRL [3] 4 PWR [2] 3 PWR [1] 2 PWR [0] 1 ASK_ NFSK 0 CLK_ ON
FSK Shift = FSEP[0..7] FSEP[0] + ... + FSEP[7] x 128 = 0..255
Output Power = PWR[0..3] PWR[0] + .. + PWR[3] x 8 = 0..15
Table 6-2.
Name CLK_ONLY
Control Register Functional Descriptions
Bit No. 31 Size 1 Remarks Activates/deactivates CLK_ONLY Mode Low = Normal Mode High = Clock Only Mode (Figure 4-1 on page 7) VCO band selection High = 367 MHz to 450 MHz Low = 300 MHz to 368 MHz PLL frequency adjust See Table 6-1 for formula FSK deviation adjust See Table 6-1 for formula CLK output divider ratio Low = fXTO/8 High = fXTO/4 PA output power adjustment See Table 4-1 and Table 4-2 on page 9 Modulation type Low = FSK High = ASK CLK_DRV port control HIGH = CLK port is ON LOW = CLK port is OFF
S434_N315
30
1
FREQ[0:14] FSEP[0:7]
15 ... 29 7 ... 14
15 8
DIV_CNTRL
6
1
PWR[0:3]
2 ... 5
4
ASK_NFSK
1
1
CLK_ON
0
1
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6.2 Programming
The configuration register is programmed serially using the SPI bus, starting with the MSB. It consists of the Enable line (EN), the Data line (SDIN_TXDIN), and the SPI-Bus Clock (SCK). The SDIN_TXDIN data is loaded on the positive edge of the SCK. The contents of the configuration register become programmed on the negative SCK edge of the last bit (LSB) of the programming sequence. The timing of this bus is shown in Figure 6-1. Note that the maximum usable clock speed on the SPI bus is limited to 2 MHz. Figure 6-1. SPI Bus Timing
EN TEN_setup SCK TSetup SDIN_TXDIN THold
TSCK_High TSCK_Cycle TSCK_Low
TSDIN_TXDIN_setup
MSB
X
MSB-1
X
At the conclusion of the 32 bit programming sequence, the SDIN_TXDIN line becomes the modulation input for the RF transmitter. After programming is complete, the SCK signal has no effect on the device. To disable the transmitter and enter the OFF Mode, EN and SDIN_TXDIN must be returned to the LOW state. For clarity, several additional timing diagrams are included. Figure 6-2 shows the situation when the programming terminates faster then the XTO is ready. Figure 6-2. Timing Diagram if Register Programming is Faster than TXTO
TXTO
EN (Input) SDIN_TXDIN (Input) SCK (Input)
32-bit Configuration X X
TX-Data X
TPLL
CLK (Output) PA (Output Power) OFF_ Mode Start_Up_ Mode_1 Start_Up_ Mode_2 TX_ Mode1
FSK; TX_Mode2 ASK: TX_Mode1 and TX_Mode2
OFF_Mode
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Figure 6-3 shows the combination with slow programming and a faster ramp up of XTO. A diagram of the operating modes is shown in Figure 6-5 and a description of which circuit blocks are active is provided in Table 6-3 on page 15. This also contains the information needed for the calculation of consumed charge for one operation cycle. Figure 6-3. Timing Diagram if Programming is Slower than TXTO
TXTO
EN (Input)
TPLL
SDIN_TXDIN (Input) SCK (Input) 32-bit Configuration X TX-Data X
CLK (Output) PA (Output Power) OFF_ Mode Start_Up_ Mode_1 Start_Up_ Mode_2 TX_ Mode1
FSK; TX_Mode2 ASK: TX_Mode1 and TX_Mode2
OFF_Mode
6.3
Reprogramming without Stopping the Crystal Oscillator
After the configuration register is programmed and RF data transmission is completed, the OFF mode is normally entered. This stops the crystal oscillator and PLL. If it is desirable to modify the contents of the configuration register without entering the OFF mode, the Reset_Register_Mode can be used. To enter the Reset_Register_Mode, the SDIN_TXDIN must be asserted HIGH while the EN is asserted LOW for at least 10 s Reset_min time. This state is shown in Figure 6-4 on page 15, State Diagram of Operating Modes. In Reset_Register_Mode, the PA and fractional PLL remain OFF but the XTO remains active. This state must stay for minimum 10 s. At the next step you must rise first EN and SDIN_TXDIN 10 s delayed. While in this mode, the 32 bit configuration register data can be sent on the SPI bus as shown in Figure 6-2 on page 13. After data transmission, the device can be switched back to OFF_Mode by asserting EN, SCK, and SDIN_TXDIN to a LOW state. An example of programming from the Reset_Register_Mode is shown in Figure 6-4 on page 15.
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Figure 6-4. Timing Diagram when using Reset_Register_Mode
TEN_Reset TPLL TSDIN_TXDIN_setup TEN_setup
SDIN_TXDIN (Input)
EN (Input)
TPLL
32-bit Configuration
TX_ Data
32-bit Configuration
TX_ Data
SCK (Input)
CLK (Output)
PA (Output Power) Start_Up_ Start_Up_ Mode_1 Mode_2
FSK; TX_Mode2 Reset_ ConASK: Register_ figuration_ TX_Mode1 and Mode Mode_1 TX_Mode2
Configuration_ Mode_2
FSK; TX_Mode2 OFF_ ASK: Mode TX_Mode1 and TX_Mode2
TX_Mode1
TX_Mode1
Table 6-3.
OFF_Mode
Active Circuits as a Function of Operating Mode
Active Circuit Blocks -nonePower up/down; XTO; digital control Power up/down; XTO; digital control; fractional-N-PLL Power up/down; XTO; digital control; fractional-N-PLL; CLK_DRV(1) Power up/down; XTO; digital control; fractional-N-PLL; CLK_DRV(1); PA Power up/down; XTO; digital control; CLK_DRV(1) Power up/down; XTO; digital control; CLK_DRV(1) Power up/down; XTO; digital control; CLK_DRV(1) Power up/down; XTO; digital control; CLK_DRV(1); fractional-N-PLL
Operating Mode Start_Up_Mode_1 Start_Up_Mode_2 TX_Mode1 TX_Mode2 Clock_Only_Mode Reset_Register_Mode Configuration_Mode_1 Configuration_Mode_2 Note:
1. Only if activated with CLK_ON = HIGH
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Figure 6-5.
State Diagram of Operating Modes
OFF_Mode
EN = 'High' SDIN_TXDIN = 'Low'
EN = 'Low' SDIN_TXDIN = 'Low'
EN = 'Low' SDIN_TXDIN = 'Low'
EN = 'Low' SDIN_TXDIN = 'Low'
Start-Up_Mode_1
EN = 'Low' SDIN_TXDIN = 'Low' CLK_Only = 'High' register programmed2 XTO_RDY = 'High'
CLK_Only = 'Low' register parity programmed1
ASK_NFSK = 'Low' or (ASK_NFSK = 'High' and SDIN_TXDIN = 'High') PLL locked3
CLK_Only = 'Low' register programmed2 XTO_RDY = 'High'
Start-Up_Mode_2
TX_Mode_2
ASK_NFSK = 'High' and SDIN_TXDIN = 'Low'
TX_Mode_1
CLK_Only = 'Low' register programmed2 CLK_Only = 'High' register programmed2
Clock_only_Mode
Configuration_Mode_2
CLK_Only = 'Low' register parity programmed1 EN = 'Low' SDIN_TXDIN = 'High' EN = 'Low' SDIN_TXDIN = 'High' EN = 'Low' SDIN_TXDIN = 'High'
Configuration_Mode_1
1 )"register
partly programmed": negative SCK edge of 32-bit register programming MSB-1 (S433_N315)
EN = 'High' SDIN_TXDIN = 'Low'
2)
"register programmed'" negative SCK edge of 32-bit register programming LSB (CLK_ON) "PLL locked" 1280 XTO cycles (TPLL) after register programmed and XTO_RDY = 'High' To transition from one state to another, only the conditions next to the transition arrows must be fulfilled. No additional settings are required.
Reset_Register_Mode
3)
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7. ESD Protection Circuit
Figure 7-1.
VS
ESD Protection Circuit
ANT1
CLK
SCK
EN
ANT2
XTO2
XTO1
SDIN_TXDIN
GND
8. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Ambient temperature in power-down mode for 30 minutes without damage with VS 3.2V, VENABLE < 0.25V or ENABLE is open, VASK < 0.25V, VFSK < 0.25V ESD (Human Body Model ESD S5.1) every pin ESD (Machine Model JEDEC A115A) every pin excluding pin 5 (ANT1) ESD (Machine Model JEDEC A115A) for pin 5 (ANT1) ESD - STM 5.3.1-1999 every pin Symbol VS Ptot Tj Tstg Tamb1 Tamb2 HBM MM MM CDM -2 -200 -150 -55 -40 Min. -0.3 Max. +4.0 100 150 +125 +125 175 +2 +200 +150 750 Unit V mW C C C C kV V V V
9. Thermal Resistance
Parameters Thermal resistance, junction ambient Symbol RthJA Value 170 Unit K/W
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10. Electrical Characteristics
VS = 1.9V to 3.6V Tamb = -40C to +125C, CLK_ON = "High"; DIV_CNTRL = "Low", CLOAD_CLK = 10 pF. fXTO = 13.0000 MHz, fCLK = 1.625 MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with CM = 4.0 fF, C0 = 1.5 pF, CLOAD = 9 pF and RM 170. Typical values are given at VS = 3.0V and Tamb = 25C No. Parameters 1 Current Consumption V(SDIN_TXDIN,SCK,EN) = Low 1.1 Supply current, OFF_Mode Tamb +25C Tamb +85C Tamb +125C VS 3.0V VS 3.0V PWR[0:3] = 8 (5.5 dBm) VS 3.0V 5, 8 IS_Off_Mode 1 20 265 3.6 7.3 480 100 350 7000 4.7 8.8 680 nA nA nA mA mA A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1.2 1.3 1.4
Supply current, TX_Mode1 Supply current, TX_Mode2 Supply current, CLK_Only_Mode
5, 8 5, 8 5, 8
IS_TX_Mode1 IS_TX_Mode2 IS_CLK_Only _
Mode
A A A
1.5
VS 3.0V CLK_ON = "Low" Supply current + ICLKoff1 I =I reduction, Clock Driver S S_any_Mode (can be applied to all modes off except Off_Mode, add Typ. to Typ. and Max. to Max. values) VS 3.0V DIV_CNTRL = "High" fCLK = 3.24 MHz IS= IS_any__Mode + ICLKhigh (can be applied to all modes except Off_Mode add Typ. to Typ. and Max. to Max. values)
5, 8
ICLKoff1
-250
-300
A
B
1.6
Supply current increase, Clock Driver higher frequency
5, 8
ICLKhigh
150
190
A
B
IS_Reset_ 1.7 Reset_Register_Mode / VS 3.0V Configuration_Mode_1 5, 8
Register_Mode /
IS_Configuration
_ Mode_1
680
A
A
1.8
Configuration_Mode_2 / VS 3.0V Start_Up_Mode_2 VS 3.0V
5, 8
IS_Configuration _Mode_2 / IS_Start_Up
_Mode_2
4.7
mA
A
1.9 2
Start_Up_Mode_1 Power Amplifier (PA) Output power 1, TX_Mode2
5, 8
IS_Start_Up
_Mode_1
300
A
A
2.1
VS = 3.0V, Tamb = 25C PWR[0:3] = 4 ZLOAD = ZLOPT according Table 4-1 and Table 4-2 on page 9
(5)
POUT_1
-1.0
+1.0
+3.0
dBm
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: (Pin Number) in brackets mean they are measured matched to 50 according to Figure 4-2 on page 8 with component values and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
18
ATA5749 [Preliminary]
9128C-RKE-10/08
ATA5749 [Preliminary]
10. Electrical Characteristics (Continued)
VS = 1.9V to 3.6V Tamb = -40C to +125C, CLK_ON = "High"; DIV_CNTRL = "Low", CLOAD_CLK = 10 pF. fXTO = 13.0000 MHz, fCLK = 1.625 MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with CM = 4.0 fF, C0 = 1.5 pF, CLOAD = 9 pF and RM 170. Typical values are given at VS = 3.0V and Tamb = 25C No. Parameters Supply current 1, TX_Mode2 Test Conditions VS = 3.0V PWR[0:3] = 4 VS = 3.6V PWR[0:3] = 4 VS = 3.0V, Tamb = 25C PWR[0:3] = 8 ZLOAD = ZLOPT according to Table 4-1 and Table 4-2 on page 9 VS = 3.0V, PWR[0:3] = 8 [typ. 5.5 dBm; see 2.3] VS = 3.6V, PWR[0:3] = 8 [typ. 5.5 dBm; see 2.3] VS = 3.0V, Tamb = 25C PWR[0:3] = 15 ZLOAD = ZLOPT according to Table 4-1 and Table 4-2 on page 9 VS = 3.0V PWR[0:3] = 15 VS = 3.6V PWR[0:3] = 15 Pin 5, 8 5, 8 Symbol IS_P1 IS_P1 Min. Typ. 5.4 Max. 6.7 7.0 Unit mA mA Type* A A
2.2
2.3
Output power 2, TX_Mode2
(5)
POUT_2
4.0
5.5
7.0
dBm
A
2.4
Supply current 2, TX_Mode2
5, 8 5, 8
IS_P2 IS_P2
7.3
8.8 9.1
mA mA
A A
2.5
Output power 3, TX_Mode2
(5)
POUT_3
11.0
12.5
14.0
dBm
A
2.6
Supply current 3, TX_Mode2
5, 8 5, 8
IS_P3 IS_P3
20.2
23.5 24.5
mA mA
A A
2.7
Tamb = -40C to +125C Output Power Variation VS = 1.9V to 3.6V for full temperature and Pout = POUT_x + POUT supply voltage range (can be applied to all power levels) Crystal Oscillator (XTO) Maximum series resistance RM of XTAL after start-up C0 < 2.0 pF
(5)
POUT
-4.0
+1.5
dB
B
3 3.1
6, 7
RM_MAX CM 2 4.0
170
fF
D
3.2
Motional capacitance of Recommended values XTAL C0 < 2.0 pF CM = 4.0 fF RM = 20 CLOAD = 9 pF V(XTO2) - V(XTO1) V(XTO1)
6, 7
15
D
3.3
Stabilized Amplitude XTAL
6, 7 VppXTO21 VppXTO1 640 320
mVpp
A
3.4
1.0 < C0 < 2.0 pF RM < 170 Pulling of fXTO versus temperature and supply CLOAD = 9 pF 4 fF < CM < 10 fF change CM < 15 fF
6, 7
fRF
-3 -5
+3 +5
ppm
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: (Pin Number) in brackets mean they are measured matched to 50 according to Figure 4-2 on page 8 with component values and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
19
9128C-RKE-10/08
10. Electrical Characteristics (Continued)
VS = 1.9V to 3.6V Tamb = -40C to +125C, CLK_ON = "High"; DIV_CNTRL = "Low", CLOAD_CLK = 10 pF. fXTO = 13.0000 MHz, fCLK = 1.625 MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with CM = 4.0 fF, C0 = 1.5 pF, CLOAD = 9 pF and RM 170. Typical values are given at VS = 3.0V and Tamb = 25C No. Parameters 3.5 DC voltage after XTAL amplitude stable Test Conditions V(XTO2) - V(XTO1) XTO running This value is important for crystal oscillator start-up behavior C0 < 2.0 pF, 8 pF < CLOAD < 10 pF FXTAL = 13.000 MHz 11.0 MHz < FXTAL < 14.8 MHz Recommended values for proper start-up and low current consumption Quality NPO CLOAD = (C4 + CXTO1) x (C5 + CXTO2) / (C4 + C5 + CXTO1 + CXTO2) CLoad_nom = 9 pF (inc. PCB) The PCB Capacitance of about 1 pF has to be added Time between EN = "High" and XTO_RDY = "High" C0 < 2.0 pF, 4 fF < CM < 15 fF C0 < 2.0 pF, 2 fF < CM < 15 fF RM < 170 11.0 MHz < FXTAL < 14.8 MHz Pin 6, 7 Symbol VDC_XTO Min. Typ. 40 Max. Unit mV Type* C
3.6
Negative real part of XTO impedance at begin of start-up
6, 7
RXTO12_START
-1500
-2200
B
-1300
3.7
External Capacitors C4, C5
6, 7
C4 C5
-5%
15
+5%
pF
D
3.8
Pin Capacitance XTO1 and XTO2
6, 7
CXTO1 CXTO2
-15% -15%
2 2
+15% +15%
pF
C
3.9
Crystal oscillator start-up time
6, 7, 1
TXTO
0.20 0.32
0.3 0.5
ms
B
3.10 3.11 4 4.1
Required for stable operation of Maximum shunt capacitance C0 of XTAL XTO, CLoad > 7. 5 pF Oscillator frequency XTO Fractional-N-PLL Frequency range of RF S434_N315 = "LOW" frequency S434_N315 = "HIGH" Time between XTO_RDY= "High" and Register Locking time of the PLL programmed till PLL is locked fXTO = 13.0000 MHz other fXTO PLL loop bandwidth In Loop phase noise PLL Out of Loop Phase noise (VCO) Unity gain loop frequency of synthesizer 25 kHz distance to carrier At 1 MHz At 36 MHz 433.92 MHz and 315 MHz other frequencies
6, 7 6, 7
C0_MAX fXTO 11.0 300 367
1.5 13.0000
3.0
pF MHz
D C
14.8 368 450 98.46
5
fRF
MHz
A
s
B
4.2
1, 5
TPLL
1280/ f XTO 140 280 -83 -91 -122 380 -76 -84 -115 kHz dBc/Hz dBc/Hz dBc/Hz B A A C
4.3 4.4 4.5
5 5 5
fLoop_PLL LPLL Lat1M Lat36M
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: (Pin Number) in brackets mean they are measured matched to 50 according to Figure 4-2 on page 8 with component values and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
20
ATA5749 [Preliminary]
9128C-RKE-10/08
ATA5749 [Preliminary]
10. Electrical Characteristics (Continued)
VS = 1.9V to 3.6V Tamb = -40C to +125C, CLK_ON = "High"; DIV_CNTRL = "Low", CLOAD_CLK = 10 pF. fXTO = 13.0000 MHz, fCLK = 1.625 MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with CM = 4.0 fF, C0 = 1.5 pF, CLOAD = 9 pF and RM 170. Typical values are given at VS = 3.0V and Tamb = 25C No. Parameters FSK modulation frequency Test Conditions Duty cycle of the modulation signal = 50%, (this corresponds to 40 kBit/s Manchester coding and 80 kBit/s NRZ coding) Duty cycle of the modulation signal = 50%, (this corresponds to 40 kBit/s Manchester coding and 80 kBit/s NRZ coding) At fRF fXTO / 8 At fRF fXTO / 4 At fRF fXTO DIV_CNTRL = "High" At fRF fXTO / 4 At fRF fXTO CLK_ON = "Low" At f0 fXTO ASK_NFSK = "High" TX_Mode_2 FREQ[0:14] = 3730, FSEP[0:7] = 101 S434_N315 = "Low" fRF 3.00 MHz fRF 6.00 MHz FREQ[0:14] = 14342, FSEP[0:7] = 101 S434_N315 = "High" fRF 3.159 MHz fRF 9,840MHz fXTO = 13.0000 MHz other fXTO see Table 3-1 on page 4 Pin Symbol Min. Typ. Max. Unit Type*
4.6
2, 5
FMOD_FSK
0
40
kHz
B
4.7
ASK modulation frequency
2, 5
FMOD_ASK
0
40
kHz
B
4.8
Spurious emission
5
Spur
-47 -47 -60 -47 -58 -60
dBc
B
4.9
Spurious emission
5
Spur
dBc
B
4.10 Spurious emission
5
Spur
dBc
B
4.11 Fractional Spurious
5
Spur
-50 -50
dBc
B
-50 -50 0.396 5 fdev f XTO / 32768 793 101.16 f XTO / 128.5 Hz A kHz A
FSK frequency 4.12 deviation
4.13 Frequency resolution
fXTO = 13.0000 MHz other fXTO
fPLL
f XTO / 16384
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: (Pin Number) in brackets mean they are measured matched to 50 according to Figure 4-2 on page 8 with component values and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
21
9128C-RKE-10/08
11. Timing Characteristics (ATA5749)
VS = 1.9V to 3.6V, Tamb = -40C to +125C. Typical values are given at VS = 3.0V and Tamb = 25C. All parameters are referred to GND (pin 9). Parameters where crystal relevant parameters are important correspond to a crystal with CM = 4.0 fF, C0 = 1.5 pF, CLOAD = 9 pF and RM 170 unless otherwise specified. No. Parameters 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 EN set-up time to rising edge of SCK SDIN_TXDIN set-up time to falling edge of EN SDIN_TXDIN set-up time to rising edge of SCK SDIN_TXDIN hold time from rising edge of SCK SCK Cycle time SCK high time period SCK low time period EN low time period with SDIN_TXDIN = "High" for register reset Clock output frequency (CMOS microcontroller compatible) fXTO = 13.000 MHz DIV_CNTRL = "High" (fCLK = fXTO / 4) DIV_CNTRL = "Low" (fCLK = fXTO / 8) Cload 20 pF, DIV_CNTRL = "Low" (fclk = fXTO / 8) "High" = 0.8 x VS, "Low" = 0.2 x VS, fCLK < 1.625 MHz Cload 10 pF, DIV_CNTRL = "High" (fclk = fXTO / 4) "High" = 0.8 x VS, "Low" = 0.2 x VS, fCLK < 3.25 MHz Cload 20 pF, DIV_CNTRL = "Low" (fclk = fXTO / 8) "High" = 0.8 x VS, "Low" = 0.2 x VS, fCLK < 1.85 MHz Cload 10 pF, DIV_CNTRL = "High" (fclk = fXTO / 4) "High" = 0.8 x VS, "Low" = 0.2 x VS, fCLK < 3.7 MHz Test Conditions Pin 1, 10 2, 10 2, 3 2, 3 3 3 3 2, 10 Symbol TEN_setup TSDIN_TXDIN
_setup
Min. 10 125 10 10 500 200 200 10
Typ.
Max.
Unit s ns ns ns ns ns ns us
Type* C C C C C C C C
TSetup THold TSCK_Cycle TSCK_High TSCK_Low TEN_Reset
3.25 1 fCLK 1.625 MHz A
1.9
1.10
Clock output minimum "High" and "Low" time
1
TCLKLH
125
220
ns
A
1.11
Clock output minimum "High" and "Low" time
1
TCLKLH
62.5
110
ns
A
1.12
Clock output minimum "High" and "Low" time
1
TCLKLH
125
180
ns
C
1.13
Clock output minimum "High" and "Low" time
1
TCLKLH
62.6
90
ns
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
22
ATA5749 [Preliminary]
9128C-RKE-10/08
ATA5749 [Preliminary]
12. Digital Port Characteristics
VS = 1.9V to 3.6V, Tamb = 40C to +125C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25C, all inputs are Schmitt trigger interfaces. No. Parameters 1.1 SDIN_TXDIN Test Conditions "Low" level input voltage "High" level input voltage Internal pull-down resistor "Low" level input voltage "High" level input voltage Internal pull-down resistor "Low" level input voltage "High" level input voltage Internal pull-down resistor Pin Symbol VII Vih RPDN VII Vih RPDN VII Vih RPDN Min. 0 VS - 0.25 160 0 VS - 0.25 160 0 VS - 0.25 160 Typ. Max. 0.25 VS 380 0.25 VS 380 0.25 VS 380 Unit V V k V V k V V k Type* A
250
1.2
SCK
A
250
1.3
EN input
A
250
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
23
9128C-RKE-10/08
13. Ordering Information
Extended Type Number ATA5749-6DQ Package MSOP10 Remarks -
14. Package Information
Package: TSSOP 10 (acc. to JEDEC Standard MO-187) Dimensions in mm Not indicated tolerances 0.05
1.1 max
0.850.1
30.1
30.1
0.5 nom. 4 x 0.5 = 2 nom. 10 9 8 7 6
3.80.3 4.90.1
technical drawings according to DIN specifications
Drawing-No.: 6.543-5095.01-4 12345 Issue: 3; 16.09.05
24
ATA5749 [Preliminary]
9128C-RKE-10/08
0.15
0.25
ATA5749 [Preliminary]
15. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 9128C-RKE-10/08 History * Features on page 1 changed * Section 8 "Absolute Maximum Ratings" on page 17 changed * Section 12 "Digital Port Characteristics" on page 23 changed * * * * * * * * * Put datasheet in the newest template Features on page 1 changed Section 1 "Description" on page 1 changed Figure 1-1 "Block Diagram" on page 2 changed Section 3.1 "Fractional-N PLL" on page 4 changed Section 3.4 "Clock Driver" on page 6 changed Figure 4-1 "Typical Application Circuit" on page 7 changed Figure 4-2 "Output Power Measurement Circuit" on page 8 changed Section 10 "Electrical Characteristics" numbers 4.2, 4.12 and 4.13 on pages 20 to 21 changed
9128B-RKE-08/08
25
9128C-RKE-10/08
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9128C-RKE-10/08

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