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R8A66120FFA
4M-bit x 2 MULTIPLE FIELD MEMORY Description
RJJ03FXXXREJ03F0161-0170 Rev.1.70 May.16.2008
R8A66120FFA is high-speed field memory with two FIFO (First In First Out) memories of 4M-bit, which uses high-performance silicon gate process technology.
Features
*Total memory Capacity 8Mega-bit *High speed operation cycle time 10.0ns(Min.) fmax = 100MHz output access time 6.0ns(Max.) *Output hold time 1.0ns(Min.) *Supply voltage 3.3 0.3V *Variable length delay bit *Synchronous write/read operation *3 states output *Package PLQP0048KB-A (48P6Q-A) ( 48pins 7x7mm body LQFP )
Application
W-CDMA base station, Digital PPC, Digital TV,VTR and so on.
Mode Descriptions
1K-word = 1024-words
1024K-word 4bit bus I/F
DA<3:0> CKA WRESA WEA DB<3:0> CKB WRESB WEB
4 1024K-w X 4-bit FIFO 4 1024K-w X 4-bit FIFO
4
QA<3:0> RRESA REA
4
QB<3:0> RRESB REB
The 2 pieces of 1024K-word x 4-bit FIFO can be operated completely independently. 2-system individual input 2-system individual output
Pin Configuration (Top view)
Outline: PLQP0048KB-A (48P6Q-A)
REJ03F0161-0170 Rev.1.70 May.16.2008 page 1 of 14
R8A66120FFA Block Diagram
Data input DA<3:0> DB<3:0>
INPUT BUFFER Clock inputs Mode setting input MODE MODE CONTROL CIRCUIT CKA CKB
WRITE CONTROL CIRCUIT
READ CONTROL CIRCUIT
Write control inputs for A-system WRESA WEA
MEMORY ARRAY 256K-word x 16-bit 256K-word x 16-bit
Read control inputs for A-system RRESA REA
READ ADDRESS COUNTER
WRITE ADDRESS COUNTER
Write control inputs for B-system WRESB WEB
Read control inputs for B-system RRESB REB
Power on reset input POR Test setting input TEST<2:1> MODE CONTROL CIRCUIT
Vcc GND
OUTPUT BUFFER
QA<3:0> Data output
QB<3:0>
REJ03F0161-0170 Rev.1.70 May.16.2008 page 2 of 14
R8A66120FFA
Pin Function Description
Pin name (*1) CKx WEx Name Clock input Write enable input Input/ Output Input Input Number of pin(s) 2 2 Function They are clock inputs. They are write enable control inputs. When they are "L", a write enable status is provided. They are reset inputs to initialize a write address counter of internal FIFO. When they are "L", a write reset status is provided. They are read enable control inputs. When they are "L", a read enable status is provided. They are reset inputs to initialize a read address counter of internal FIFO. When they are "L", a read reset status is provided. They are data input bus. They are data output bus. This is a pin for setting operation mode. MODE should be fixed at "L". They are pins for test. TEST<2:1> should be fixed at "L". This is a power on reset input. They are 3.3 V power supply pins. They are ground pins.
WRESx
Write reset input
Input
2
REx
Read enable input
Input
2
RRESx
Read reset input
Input
2
Dx<3:0> Qx<3:0> MODE TEST<2:1> POR Vcc GND
Data input Data output Mode setting input Test setting input Power on reset input Power supply pin Ground pin
Input Output Input Input Input -
8 8 1 2 1 9 9
*Note1: X of the pin name shows A or B. A = A-system, B = B-system.
Mode pin Setting
In normal operation mode. It should be fixed on "L".
Pin Name MODE L H
Operation MODE Normal operation Out of a guarantee
Operation Description
4 DA<3:0> CKA WRESA WEA 4 DB<3:0> CKB WRESB WEB 1024K-w X 4-bit FIFO(B) 4 QB<3:0> 1024K-w X 4-bit FIFO(A) 4 QA<3:0> R8A66120FFA can be controlled two pieces of 1024K-word x 4-bit FIFO completely independently. Taking FIFO (A) as an example, the operation of FIFO memory is described as follows. The operation of FIFO (B) is the same as that of FIFO (A). When write enable input WEA is "L", the contents of data input DA<3:0> are written into FIFO (A) in synchronization with the rising of clock input CKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", this IC disable to write data into FIFO (A) and the write address counter of FIFO (A) is not incremented. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized. When read enable input REA is "L", the contents of FIFO (A) are outputted to data output QA<3:0> in synchronization with the rising of clock input CKA. At this time, the read address counter of FIFO (A) is incremented. When REA is "H", this IC disable to read data from FIFO (A) and the read address counter of FIFO (A) is not incremented. Also QA<3:0> become high impedance state. When read reset input RRESA is "L", the read address counter of FIFO (A) is initialized.
RRESA REA
RRESB REB
REJ03F0161-0170 Rev.1.70 May.16.2008 page 3 of 14
R8A66120FFA
Electrical Characteristics
Absolute Maximum Ratings (Ta = 0 ~ 70oC, unless otherwise noted)
Symbol Vcc VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature Ratings -0.3 ~ +3.8 A value based on GND -0.3 ~ Vcc+0.3 -0.3 ~ Vcc+0.3 Ta = 70 C 550 -55 ~ +150 Conditions Unit V V V mW C
Recommended Operating Conditions
Symbol Parameter Vcc VI VO Topr Supply voltage Input voltage Output voltage Operating ambient temperature Test conditions A value based on GND Min. 3.0 0 0 0 Limits Typ. 3.3 Max. 3.6 Vcc Vcc 70 Unit V V V C
DC Characteristics (Ta = 0 ~ 70oC, Vcc = 3.3 + 0.3V, GND = 0V, unless otherwise noted)
Symbol Parameter VIH VIL VOH VOL IIH IIL IOZH IOZL Icc "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current "L" input current Off state "H" output current Off state "L" output current Operating mean current dissipation Input capacitance Off state output capacitance Test conditions A value based on GND IOH = -4mA IOL = 4mA VI = Vcc VI = GND VO = Vcc VO = GND Vcc = 3.3 0.3 V VI : Repeat "H" and "L" VO : Output open tCK = 10.0ns (f = 100MHz) f = 1MHz f = 1MHz Min. 0.8xVcc Vcc0.4 0.4 10 -10 10 -10 150 Limits Typ. Max. 0.2 x Vcc Unit V V V V uA uA uA uA mA
CI CO
10 15
pF pF
REJ03F0161-0170 Rev.1.70 May.16.2008 page 4 of 14
R8A66120FFA
Power On
After power-on this IC, some circuits of internal FIFO should be initialized by the following procedures (1), (2). Also, when the supply voltage (Vcc) drops below the operation voltage range(3.0 to 3.6V) during operating and so this is powered on again, they should be initialized by the same procedures. (1)After 1msec or more has passed under the following conditions (i), (ii) and (iii), please input the signal of "L" to "H" to POR pin for power on reset. After of that, POR pin should be fixed at "H". (i) :Vcc reaches to the operation voltage range. (ii) :The clock signal is inputted to CK pin (iii) :POR pin is fixed at "L". (2)After POR pin is fixed at "H", write reset and read reset operations should be provided with 100 cycles or more respectively. There is no problem in these reset operations, if total reset cycles reach to 100 or more even if those are discontinuous.
Pin nam e Vcc
3.0V 3.6V GND
Vcc
Vcc CK GND 1msec or more
Vcc POR GND 100 cycles or more of continuous or discontinuous reset operation Vcc GND
WRES RRES
REJ03F0161-0170 Rev.1.70 May.16.2008 page 5 of 14
R8A66120FFA
Timing Requirements (Ta = 0 ~ 70oC,Vcc = 3.3 + 0.3V, GND = 0V, unless otherwise noted)
Symbol tCK tCKH tCKL tDS tDH tWRESS tWRESH tRRESS tRRESH tWES tWEH tRES tREH tr, tf Parameter Clock (CK) cycle CK "H" pulse w idth CK "L" pulse w idth Input data setup time to CK Input data hold time to CK Write reset setup time to CK Write reset hold time to CK Read reset setup time to CK Read reset hold time to CK Write enable setup time to CK Write enable hold time to CK Read enable setup time to CK Read enable hold time to CK Input pulse rise / fall time Limits Min. 10 4 4 4 0 4 0 4 0 4 0 4 0 3 ns Typ. Max. 200 Unit
Switching Characteristics (Ta = 0 ~ 70oC, Vcc = 3.3 + 0.3V, GND = 0V, unless otherwise noted)
Symbol tAC tOH tOEN tODIS Parameter Output access time to CK Output hold time to CK Output enable time to CK Output disable time to CK 1 1 1 6 6 Limits Min. Typ. Max. 6 ns Unit
REJ03F0161-0170 Rev.1.70 May.16.2008 page 6 of 14
R8A66120FFA
Switching Characteristics Measurement Circuit
Vcc
RL=1K
SW1 Qn Qn SW2
CL=10pF: tAC, tOH
RL=1K
CL=3pF: tOEN, tODIS
Parameter tODIS(LZ) tODIS(HZ) tOEN(ZL) tOEN(ZH)
SW1 Close Open Close Open
SW2 Open Close Open Close
Input pulse level Input pulse rise/fall time Decision voltage input Decision voltage output
: 0 ~ Vcc : 1 ns : 1/2 Vcc : 1/2 Vcc (However, tODIS(HZ) is judged with 90% of the output amplitude, while tODIS(LZ) is judged with 10% of the output amplitude. )
The load capacitance CL includes the floating capacitance of connections and a input capacitance of a probe.
tODIS and tOEN Measurement Conditions
VIH
CK
1/2 Vcc
1/2 Vcc VIL
VIH
RE
VIL
tODIS(HZ) tOEN(ZH)
Qn
90% 1/2 Vcc
VOH
tOEN(ZL) tODIS(LZ)
Qn
10%
1/2 Vcc VOL
REJ03F0161-0170 Rev.1.70 May.16.2008 page 7 of 14
R8A66120FFA
Operating Timing
Write Cycle
n cycle CK n+1 cycle n+2 cycle
Disable cycle
n+3 cycle
n+4 cycle
tCK
tCKH
tCKL
tWEH tWES
tWEH
tWES
WE
tDS tDH
tDS tDH
Dn
(n)
(n+1)
(n+2)
(n+3)
(n+4)
In case of WRES = "H"
Write Reset Cycle
n-1 cycle n cycle
Reset cycle
0 cycle
1 cycle
CK
tCK
tWRESH t WRESS
tWRESH tWRESS
WRES
tDS tDH
tDS tDH
Dn
(n-1)
(n)
(0)
(1)
In case of WE = "L"
Write Reset and Write Enable Combination Cycle
n cycle n+1 cycle n+2 cycle Disable cycle 0 cycle 1 cycle
CK
tCK
tCKH
tCKL
tWEH tWES
tWEH tWES
WE
tWRESH tWRESS tWRESH tWRESS
WRES
tDS tDH
Dn
tDS tDH (n+1) (n+2) (0) (1)
(n)
Note: There is no timing restriction of WE to WRES. REJ03F0161-0170 Rev.1.70 May.16.2008 page 8 of 14
R8A66120FFA
Read Cycle
n cycle n+1 cycle n+2 cycle
Disable time
n+3 cycle
n+4 cycle
CK
tCK
tCKH
tCKL
tREH
tRES
tREH
tRES
RE
tAC
tODIS HIGH-Z
tOEN
Qn
(n) tOH
(n+1)
(n+2) tOH
(n+3)
(n+4)
In case of RRES = "H"
Read Reset Cycle
n-1 cycle n cycle
Reset cycle
0 cycle
1 cycle
CK
tCK
tRRESH tRRESS
t RRESH tRRESS
RRES
tAC
Qn
tAC
tAC
(n-1) tOH
(n) tOH
(0) tOH
(1)
In case of RE = "L"
Read Reset and Read Enable Combination Cycle
n cycle CK n+1cycle n+2cycle
Disable cycle
0 cycle
1 cycle
tCK
tCKH
tCKL
tREH tRES
tREH
tRES
RE
t RRESH tRRESS tRRESH tRRESS
RRES
tAC
Qn
tAC (n) tOH (n+1)
tODIS (n+2) tOH
HIGH-Z
tOEN
tAC (0) tOH (1)
Note: There is no timing restriction of RE to RRES. REJ03F0161-0170 Rev.1.70 May.16.2008 page 9 of 14
R8A66120FFA
Caution When Write Cycle and Read Cycle Approach Each Other
The interval m between write cycle and a read cycle should be secured more than 256 cycles when the write cycle goes ahead of the read cycle on the following conditions, that is to say the interval less than 255 cycles is forbidden. WRES, RRES="H"; WE, RE="L", and * Both write side and read side are activated continuously. When once this restriction to the interval isn't fulfilled, writing data is guaranteed, but reading data isn't guaranteed not only for the cycles when it isn't fulfilled but also for the following 256 cycles after it is fulfilled again. In this 256 cycles, read disable and read reset cycles are not counted. But the following condition is an exception to the restriction to forbid the intervals less than 255 cycles. * Either write side or read side is temporarily stopped owing to reset cycles (WRES or RRES="L") or disable cycles (WE or RE ="H"). Note: Also, when the address counter is incremented up to the last cycle of 1-line and then returned to 0 cycle, the interval m between write and read cycles should be secured more than 256 cycles taking account that they are cyclic and serial lines.
m255 WRES,RRES=HWE,RE=L
256
256
255
254
254
254
255
256
256
256
"m", the interval between a write cycle and a read cycle Write side Read side
n+256 cycle n cycle
n+257 cycle n+1 cycle
Disable cycle n+2 cycle n+3 cycle
n+258 cycle n+4 cycle
n+259 cycle n+5 cycle
n+260 cycle
n+261 cycle
n+262 cycle n+6 cycle
n+263 cycle n+7 cycle
Disable cycle
CK
WE
D
(n+256)
(n+257)
(n+258)
(n+259)
(n+260)
(n+261)
(n+262)
(n+263)
RE HIGH-Z
Q
(n)
(n+1)
(n+2)
(n+3)
invalid
The data on forbidden cycles are not guaranteed
invalid
The data are defined because it's on write disable cycles
The data of 256 cycles after the forbidden cycles are not guaranteed
In the case of read cycle goes ahead of the write cycle or write cycle and read cycle are accorded. It's exceptions of the restriction on forbid the intervals less than 255 cycles.
Caution of The State of Clock Stopping
Stopping of clock signal of this IC is forbidden during operating of it. "Stopping of clock signal" mean that CK is fixed at "L" or "H" for more than tck(Max)(=200ns). When this restriction to tck isn't fulfilled, all writing data before stopping of clock signal isn't defined. Once the clock signal stopped, 1 cycle or more of both write reset cycles and read reset cycles should be secured to operate again.
the state of clock stopping 1 cycle or more of both write reset cycles and read reset cycles are needed for continuation.
tCK
CK
tCK(Max)
WRES RRES
REJ03F0161-0170 Rev.1.70 May.16.2008 page 10 of 14
R8A66120FFA
Variable Length Delay bits
The 1-line length (cycle number) of R8A66120FFA is 1,048,576-cycle.
1-line Delay
In read cycles, an output data is read out at the (first) rising edge of CK (i.e. the start of the cycle ) . In write cycles, an input data is written at the (second) rising edge of CK (i.e. the end of the cycle ) . So 1-line delay can be made easily according to the control method of the following figure.
Reset cycle
0 cycle
1 cycle
2 cycle
1048574 cycle
1048575 cycle
1048576 (0') cycle 0 cycle
1048577 (1') 1048578 (2') Write side cycle cycle 1 cycle 2 cycle
Read side
CK
WRES RRES
Dn
(0)
(1)
(2)
(1048573)
(1048574)
(1048575)
(0')
(1')
(2')
1048576 cycle
Qn
(0)
(1)
(2)
WE, RE"L"
N-bit Delay 1 (Reset at cycles corresponding to delay length)
Reset cycle 0 cycle 1 cycle 2 cycle n-1 cycle Reset cycle 0' cycle 0 cycle 1' cycle 1 cycle 2' cycle 2 cycle
Write side Read side
CK
WRES RRES
Dn
(0)
(1)
(2)
(n-2)
(n-1)
(0')
(1')
(2')
Delay length n
Qn
(0)
(1)
(2)
1048576 in 256 WE, RE"L" Note: Take care of the restriction to a interval between a write cycle and a read cycle (ref. page10).
REJ03F0161-0170 Rev.1.70 May.16.2008 page 11 of 14
R8A66120FFA
N-bit Delay 2 (Sliding timings of WRES and RRES at cycles corresponding to delay length)
Reset cycle 0 cycle 1 cycle 2 cycle n-1 cycle Reset cycle n cycle 0 cycle n+1 cycle 1 cycle n+2 cycle 2 cycle n+3 cycle 3 cycle
Write side Read side
CK
WRES
RRES
Dn
(0)
(1)
(2)
(n-2)
(n-1)
(n)
(n+1)
(n+2)
(n+3)
Delay length n
Qn
(0)
(1)
(2)
(3)
1048576 256 WE, RE"L"
N-bit Delay 3 (Sliding address by disabling RE for cycles corresponding to delay length)
Reset cycle 0 cycle 1 cycle 2 cycle n-1 cycle n cycle 0 cycle n+1 cycle 1 cycle n+2 cycle 2 cycle n+3 cycle Write side 3 cycle Read side
CK
WRES RRES
RE
Dn
(0)
(1)
(2)
(n-2)
(n-1)
(n)
(n+1)
(n+2)
(n+3)
Delay length n
Qn
HIGH-Z
(0)
(1)
(2)
(3)
1048576 WE="L"
n
256
REJ03F0161-0170 Rev.1.70 May.16.2008 page 12 of 14
R8A66120FFA
Reading shortest a data written at n cycle on write-side
In order to read out a written data, CK should be inputted for 256 cycles and more after the data is written. In following figure, an example is shown of reading out the data written at the rising edge of CK (*1) at n cycle on write-side. Output data becomes invalid when this restriction isn't fulfilled. Also, take care of the restriction to the interval between a write cycle and a read cycle (ref. page10).
256 cycles or more
n-1 cycle n cycle n+1 cycle n+253 cycle n-2 cycle n+254 cycle n-1 cycle n+255 cycle Disable cycle n+256 cycle n cycle n+257 cycle n+1 cycle n+258 cycle n+2 cycle
Write side Read side
CK
1
Dn
(n-1)
(n)
(n+1)
(n+253)
(n+254)
(n+255)
(n+256)
(n+257)
(n+258)
RE
HIGH-Z Qn
invalid invalid (n) (n+1) (n+2)
Reading longest a data written at n cycle on write-side : 1-line Delay
Output Q of n cycle<1>* can be read out until n cycle<1>* on read-side and n cycle<2>* on write-side overlap each other.
n cycle1* n cycle0*
0 cycle2* 0 cycle1*
n cycle2* n cycle1*
Write side Read side
CK
Dn
(n-1)<1>*
(n)<1>*
(0)<2>*
(n-1)<2>*
(n)<2>*
Qn
(n-1)<0>*
(n)<0>*
(0)<1>*
(n-1)<1>*
(n)<1>*
<0>* , <1>* and <2>* indicate a line number.
REJ03F0161-0170 Rev.1.70 May.16.2008 page 13 of 14
R8A66120FFA
Package Outline
JEITA Package Code P-LQFP48-7x7-0.50
RENESAS Code PLQP0048KB-A
Previous Code 48P6Q-A
MASS[Typ.] 0.2g
HD
*1
D
36
25 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
E HE
37
24
c1
*2
c
Reference Symbol
Dimension in Millimeters
Terminal cross section 48
ZE
13
1 ZD Index mark
12
A2
F
A
A1
L L1
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
Min 6.9 6.9 8.8 8.8 0 0.17 0.09 0
y e
*3
bp
Detail F x
0.35
Nom Max 7.0 7.1 7.0 7.1 1.4 9.0 9.2 9.0 9.2 1.7 0.1 0.2 0.22 0.27 0.20 0.145 0.20 0.125 8 0.5 0.08 0.10 0.75 0.75 0.5 0.65 1.0
All trademarks and registered trademarks are the property of their respective owners.
REJ03F0161-0170 Rev.1.70 May.16.2008 page 14 of 14
c
R8A66120FFA
REJ03F0161-0170 Rev.1.70 May.16.2008 page 15 of 14

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