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| DS2252T DS2252T Secure Microcontroller Module FEATURES PACKAGE OUTLINE * 8051 compatible microcontroller for secure/sensitive applications - 32K, 64K, or 128K bytes of nonvolatile SRAM for program and/or data storage - In-system programming via on-chip serial port - Capable of modifying its own program or data memory in the end system 1 20 21 40 * Firmware Security Features: - - - - - - Memory stored in encrypted form Encryption using on-chip 64-bit key Automatic true random key generator SDI Self Destruct Input Improved security over previous generations Protects memory contents from piracy 40-Pin SIMM DESCRIPTION The DS2252T is an 8051 compatible microcontroller based on nonvolatile RAM technology. It is designed for systems that need to protect memory contents from disclosure. This includes key data, sensitive algorithms, and proprietary information of all types. Like other members of the Secure Microcontroller family, it provides full compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NVRAM instead of ROM, the user can program, then reprogram the microcontroller while in-system. This allows frequent changing of sensitive processes with minimal effort. The DS2252T provides an array of mechanisms to prevent an attacker from examining the memory. It is designed to resist all levels of threat including observation, analysis, and physical attack. As a result, a massive effort would be required to obtain any information about memory contents. Furthermore, the "Soft" nature of the DS2252T allows frequent modification of secure information. This minimizes that value of any information that is obtained. * Crashproof Operation - Maintains all nonvolatile resources for over 10 years in the absence of power - Power-fail Reset - Early Warning Power-fail Interrupt - Watchdog Timer - Precision reference for power monitor * Fully 8051 Compatible - - - - 128 bytes scratchpad RAM Two timer/counters On-chip serial port 32 parallel I/O port pins * Permanently powered real time clock ECopyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. 121395 1/14 DS2252T Using a security system based on the DS5002FP, the DS2252T protects the memory contents from disclosure. It loads program memory via its serial port and encrypts it in real-time prior to storing it in SRAM. Once encrypted, the RAM contents and the program flow are unintelligible. The real data exists only inside the processor chip after being decrypted. Any attempt to discover the on-chip data, encryption keys, etc., results in its destruction. Extensive use of nonvolatile lithium backed technology create a microcontroller that retains data for over 10 years at room temperature, but which can be erased instantly if tampered with. The DS2252T even interfaces directly to external tamper protection hardware. The DS2252T provides a permanently powered real time lock with interrupts for time stamp and date. It keeps time to one hundredth of a second using its on- board 32 KHz crystal. Like other Secure Microcontrollers in the family, the DS2252T provides crashproof operation in portable systems or systems with unreliable power. These features include the ability to save the operating state, Power-fail Reset, Power-fail Interrupt, and Watchdog Timer. All nonvolatile memory and resources are maintained for over 10 years at room temperature in the absence of power. A user loads programs into the DS2252T via its on-chip Serial Bootstrap Loader. This function supervises the loading of software into NVRAM, validates it, then becomes transparent to the user. It also manages the loading of new encryption keys automatically. Software is stored in on-board CMOS SRAM. Using its internal Partitioning, the DS2252T can divide a common RAM into user selectable program and data segments. This Partition can be selected at program loading time, but can be modified anytime later. The microcontroller will decode memory access to the SRAM, access memory via its Byte-wide bus and write-protect the memory portion designated as program (ROM). A detailed summary of the security features is provided in the User's Guide section of the Secure Microcontroller data book. An overview is also available in the DS5002FP data sheet. ORDERING INFORMATION PART NUMBER DS2252T-32-16 DS2252T-64-16 DS2252T-128-16 RAM SIZE 32K bytes 64K bytes 128K bytes MAX CRYSTAL SPEED 16 MHz 16 MHz 16 MHz TIMEKEEPING? Yes Yes Yes Operating information is contained in the User's Guide section of the Secure Microcontroller Data Book. This data sheet provides ordering information, pinout, and electrical specifications. 121395 2/14 DS2252T DS2252T BLOCK DIAGRAM Figure 1 DS2252T +3V VCC VCCO RST ALE XTAL1 XTAL2 GND DS5002FP PROG SDI BYTE-WIDE ADDRESS BUS P0.0-0.7 P1.0-1.7 P2.0-2.7 P3.0-3.7 P3.2 IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII BYTE-WIDE DATA BUS CE1 R/W CE2 PE1 INTP 32K OR 128K SRAM IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII 32K SRAM (-64 only) DS1283 REAL TIME CLOCK 121395 3/14 DS2252T PIN ASSIGNMENT 1 2 3 4 5 6 7 8 9 10 P1.0 VCC P1.1 P0.0 P1.2 P0.1 P1.3 P0.2 P1.4 P0.3 11 12 13 14 15 16 17 18 19 20 P1.5 P0.4 P1.6 P0.5 P1.7 P0.6 RST P0.7 P3.0 RXD SDI 21 22 23 24 25 26 27 28 29 30 P3.1 TXD ALE P3.2 INT0 PROG P3.3 INT1 P2.7 P3.4 T0 P2.6 P3.5 T1 P2.5 31 32 33 34 35 36 37 38 39 40 P3.6 WR P2.4 P3.7 RD P2.3 XTAL2 P2.2 XTAL1 P2.1 GND P2.0 PIN DESCRIPTION PIN DESCRIPTION 4, 6, 8, 10, P0.0 - P0.7. General purpose I/O Port 0. This port is open-drain and can not drive a logic 1. 12, 14, 16, 18 It requires external pull-ups. Port 0 is also the multiplexed Expanded Address/Data bus. When used in this mode, it does not require pull-ups. 1, 3, 5, 7, 9, 11, 13, 15 40, 38, 36, 34, 32, 30, 28, 26 19 21 23 25 27 29 31 33 17 P1.0 - P1.7. General purpose I/O Port 1. P2.0 - P2.7. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address bus. P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on board UART. This pin should NOT be connected directly to a PC COM port. P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on board UART. This pin should NOT be connected directly to a PC COM port. P3.2 INT0. General purpose I/O port pin 3.2. Also serves as the active low External Interrupt 0. This pin is also connected to the INTP output of the DS1283 Real Time Clock. P3.3 INT1. General purpose I/O port pin 3.3. Also serves as the active low External Interrupt 1. P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input. P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input. P3.6 WR. General purpose I/O port pin. Also serves as the write strobe for Expanded bus operation. P3.7 RD. General purpose I/O port pin. Also serves as the read strobe for Expanded bus operation. RST - Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin is pulled down internally, can be left unconnected if not used. An RC power-on reset circuit is not needed and is NOT recommended. ALE - Address Latch Enable. Used to de-multiplex the multiplexed Expanded Address/Data bus on Port 0. This pin is normally connected to the clock input on a '373 type transparent latch. 22 121395 4/14 DS2252T PIN 35, 37 39 2 24 DESCRIPTION XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output. GND - Logic ground. VCC - +5V. PROG - Invokes the Bootstrap loader on a falling edge. This signal should be debounced so that only one edge is detected. If connected to ground, the microcontroller will enter Bootstrap loading on power up. This signal is pulled up internally. SDI - Self Destruct Input. A logic 1 applied to this input causes a hardware unlock. This involves the destruction of Encryption Keys, Vector RAM, and the momentary removal of power from VCCO. This pin should be grounded if not used. 20 INSTRUCTION SET The DS2252T executes an instruction set that is object code compatible with the industry standard 8051 microcontroller. As a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the DS2252T. A complete description of the instruction set and operation are provided in the User's Guide section of the Secure Microcontroller Data Book. MEMORY ORGANIZATION Figure 2 illustrates the memory map accessed by the DS2252T. The entire 64K of program and 64K of data are available to the Byte-wide bus. This preserves the I/O ports for application use. An alternate configuration allows dynamic Partitioning of a 64K space as shown in Figure 3. Any data area not mapped into the NVRAM is reached via the Expanded bus on Ports 0 and 2. Off- board program memory is not available for security reasons. Selecting PES=1 provides access to the Real- time Clock as shown in Figure 4. These selections are made using Special Function Registers. The memory map and its controls are covered in detail in the User's Guide section of the Secure Microcontroller Data Book. 121395 5/14 DS2252T DS2252T MEMORY MAP IN NON-PARTITIONABLE MODE (PM=1) Figure 2 PROGRAM MEMORY DATA MEMORY (MOVX) 64K FFFFh NVRAM PROGRAM 0000h DS2252T MEMORY MAP IN PARTITIONABLE MODE (PM=0) Figure 3 PROGRAM MEMORY PARTITION NVRAM PROGRAM 0000h NOTE: PARTITIONABLE MODE IS NOT SUPPORTED ON THE 128KB VERSION OF THE DS2252T. LEGEND: = NVRAM MEMORY = EXPANDED BUS (PORTS 0 AND 2) 121395 6/14 EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE II II EEEEE EEEEE EEEEE IIIII EEEEE IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII FFFFh EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE NVRAM DATA DATA MEMORY (MOVX) NVRAM DATA = NOT AVAILABLE EEEEEE EEEEEE EEEEEE EEEEEE EEEEEE EEEEEE EEEEEE EEEEEE EEEEEE EEEEEE EEEEEE EEEEEE EE EE DS2252T DS2252T MEMORY MAP WITH (PES=1) Figure 4 PROGRAM MEMORY DATA MEMORY (MOVX) 64K FFFFh C000h PARTITION 8000h NVRAM PROGRAM 4000h 0000h NOT ACCESSIBLE POWER MANAGEMENT The DS2252T monitors VCC to provide Power-fail Reset, early warning Power-fail Interrupt, and switch over to lithium backup. It uses an internal band-gap reference in determining the switch points. These are called VPFW, VCCMIN, and VLI respectively. When VCC drops below VPFW, the DS2252T will perform an interrupt vector to location 2Bh if the power fail warning was enabled. Full processor operation continues regardless. When power falls further to VCCMIN, the DS2252T invokes a reset state. No further code execution will be performed unless power rises back above VCCMIN. All decoded chip enables and the R/W signal go to an inactive (logic 1) state. VCC is still the power source at this time. When VCC drops further to below VLI, internal circuitry will switch to the built-in lithium cell for power. The majority of internal circuits will be disabled and the remaining nonvolatile states will be retained. The User's Guide has more information on this topic. The trip points VCCMIN and VPFW are listed in the electrical specifications. IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII REAL-TIME CLOCK IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII 16K II II 121395 7/14 DS2252T ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C -40C to +70C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC CHARACTERISTICS PARAMETER Input Low Voltage Input High Voltage Input High Voltage (RST, XTAL1, PROG) Output Low Voltage @ IOL=1.6 mA (Ports 1, 2, 3) Output Low Voltage @ IOL=3.2 mA (Ports 0, ALE) Output High Voltage @ IOH=-80 A (Ports 1, 2, 3) Output High Voltage @ IOH=-400 A (Ports 0, ALE) Input Low Current VIN=0.45V (Ports 1, 2, 3) Transition Current; 1 to 0 VIN=2.0V (Ports 1, 2, 3) Input Leakage Current 0.45 MAX +0.8 VCC+0.3 VCC+0.3 0.45 0.45 UNITS V V V V V V V -50 -500 10 150 4.50 4.25 45 7.0 80 10 4.25 4.65 0.4 VCC 3.5 60 V V V K 1 1, 2 1, 2 A A A K V V mA mA A pF V 1 1 4 5 6 7 1 NOTES 1 1 1 1 1 1 1 121395 8/14 DS2252T AC CHARACTERISTICS PARAMETER SDI Pulse Reject SDI Pulse Accept SYMBOL tSPR tSPA 10 MIN TYP (tA = 0C to70C; VCC=0V to 5V) MAX 2 UNITS s s NOTES 3 3 AC CHARACTERISTICS EXPANDED BUS MODE TIMING SPECIFICATIONS # 1 2 3 4 14 15 16 PARAMETER Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low RD Pulse Width WR Pulse Width RD Low to Valid Data In @12 MHz @16 MHz Data Hold after RD High Data Float after RD High ALE Low to Valid Data In @12 MHz @16 MHz Valid Addr. to Valid Data In @12 MHz @16 MHz ALE Low to RD or WR Low Address Valid to RD or WR Low Data Valid to WR Going Low Data Valid to WR High @12 MHz @16 MHz Data Valid after WR High RD Low to Address Float RD or WR High to ALE High SYMBOL 1/tCLK tALPW tAVALL tAVAAV tRDPW tWRPW tRDLDV tRDHDV tRDHDZ tALLVD tAVDV tALLRDL tAVRDL tDVWRL tDVWRH tWRHDV tRDLAZ tRDHALH (tA = 0C to70C; VCC = 5V + 10%) MIN 1.0 2tCLK-40 tCLK-40 tCLK-35 6tCLK-100 6tCLK-100 5tCLK-165 5tCLK-105 0 2tCLK-70 8tCLK-150 8tCLK-90 9tCLK-165 9tCLK-105 3tCLK-50 4tCLK-130 tCLK-60 7tCLK-150 7tCLK-90 tCLK-50 0 tCLK-40 tCLK+50 3tCLK+50 MAX 16 (-16) UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 17 18 19 20 21 22 23 24 25 26 27 121395 9/14 DS2252T EXPANDED DATA MEMORY READ CYCLE 2 27 ALE 19 21 RD 14 16 18 3 4 26 17 A7-A0 (PCL) INSTR IN PORT 0 A7-A0 (Rn OR DPL) DATA IN 22 20 PORT 2 P2.7-P2.0 OR A15-A8 FROM DPH A15-A8 FROM PCH EXPANDED DATA MEMORY WRITE CYCLE 27 ALE 21 15 WR 23 3 4 24 25 PORT 0 A7-A0 (Rn OR DPL) DATA OUT A7-A0 (PCL) INSTR IN 22 PORT 2 P2.7-P2.0 OR A15-A8 FROM DPH A15-A8 FROM PCH 121395 10/14 DS2252T AC CHARACTERISTICS (cont'd) EXTERNAL CLOCK DRIVE # 28 PARAMETER External Clock High Time @12 MHz @16 MHz External Clock Low Time @12 MHz @16 MHz External Clock Rise Time @12 MHz @16 MHz External Clock Fall Time @12 MHz @16 MHz SYMBOL tCLKHPW tCLKLPW tCLKR tCLKF (tA = 0C to70C; VCC = 5V + 10%) MIN 20 15 20 15 20 15 20 15 MAX UNITS ns ns ns ns ns ns ns ns 29 30 31 EXTERNAL CLOCK TIMING 28 29 30 31 1 AC CHARACTERISTICS (cont'd) POWER CYCLING TIMING # 32 33 34 PARAMETER Slew Rate from VCCMIN to VLI Crystal Start up Time Power On Reset Delay SYMBOL tF tCSU tPOR (tA = 0C to70C; VCC = 5V + 10%) MIN 130 (note 8) 21504 tCLK MAX UNITS s 121395 11/14 DS2252T POWER CYCLE TIMING VCC VPFW VCCMIN VLI 32 INTERRUPT SERVICE ROUTINE 33 CLOCK OSC 34 INTERNAL RESET LITHIUM CURRENT AC CHARACTERISTICS (cont'd) SERIAL PORT TIMING - MODE 0 # 35 36 37 38 39 PARAMETER Serial Port Clock Cycle Time Output Data Setup to Rising Clock Edge Output Data Hold after Rising Clock Edge Clock Rising Edge to Input Data Valid Input Data Hold after Rising Clock Edge SYMBOL tSPCLK tDOCH tCHDO tCHDV tCHDIV (tA = 0C to70C; VCC = 5V + 10%) MIN 12tCLK 10tCLK-133 2tCLK-117 10tCLK-133 0 MAX UNITS s ns ns ns ns 121395 12/14 DS2252T SERIAL PORT TIMING - MODE 0 INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE 35 CLOCK 36 37 DATA OUT WRITE TO SBUF REGISTER 38 INPUT DATA VALID CLEAR RI VALID VALID VALID VALID VALID VALID SET RI 0 1 2 3 4 5 6 7 SET TI 39 NOTES: 1. All voltage referenced to ground. 2. SDI should be taken to a logic high when VCC=+5V, and to approximately 3V when VCC<3V. 3. SDI is deglitched to prevent accidental destruction. The pulse must be longer than tSPR to pass the deglitcher, but SDI is not guaranteed unless it is longer than tSPA. 4. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF=10 ns, VIL = 0.5V; XTAL2 disconnected; RST = PORT0 = VCC. 5. Idle mode IIDLE is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; PORT0 = VCC, RST = VSS. 6. Stop mode ISTOP is measured with all output pins disconnected; PORT0 = VCC; XTAL2 not connected; RST = XTAL1 = VSS. 7. Pin capacitance is measured with a test frequency - 1 MHz, tA = 25C. 8. Crystal start-up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user should check with the crystal vendor for a worst case specification on this time. 121395 13/14 DS2252T PACKAGE DRAWING P (SIDE B) (SIDE A) O N A U3 U1B U1A U2 J (SIDE B) C M C L D E G I I H K L F PKG DIM A B C D E F G H I J K L M N O P MIN 2.645 2.379 0.995 0.395 0.245 40-PIN MAX 2.655 2.389 1.005 0.405 0.255 0.050 BSC 0.075 0.245 0.085 0.255 0.950 BSC 0.120 1.320 1.445 0.057 - - - 0.130 1.330 1.455 0.067 0.300 0.165 0.054 121395 14/14 |
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