View ATSAM2553_4322346.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* Interfaces Directly to Instrument Hardware
- Keyboard Velocity Scanner (up to 264 keys, 64 s Time Accuracy, Log Time Scale) - Switches Scanner (up to 176 switches) - LED Display Controller (up to 88 LEDs) - Sliders Scanner (Built-in ADC, up to 16 Sliders) - LCD Display (8-bit Interface) Crisp Musical Response - 49 MHz Built-in 16-bit Microcontroller - Interface with Keyboard/Switches through Built-in Shared Memory High Quality Sound - 64-slot Digital Sound Synthesizer/Processor - Multi-algorithm: PCM with Dynamic LP Filter, FM, Delay Lines for Effects, Equalizer, Surround, Digital Audio-in Processing, etc. - Compatible with ATSAM97XX Sounds and Firmware. - 48 kHz Sampling Rate - Up to 32 Mega x 16 ROM/RAM for FIrmware, Orchestrations and PCM Data - Up to 4 Channels Audio-out, 2 Channels Audio-in Top Technology - 128-lead LQFP Space-saving Package - Single 12.2880 MHz Crystal Operation, Built-in Pll Minimizes RFI Available Soundbanks for GM or High Quality Piano - CleanWave 1-Mbyte and 4-Mbyte Sample Sets (Free License) - High Quality Piano & Strings 2-Mbyte Sample Set - Other Sample Sets Available Under Special Licensing Conditions Quick Time to Market - Enhanced P16 Processor with C Compiler - Proven Reliable Synthesis Drivers - In-circuit Emulation with SamVS-C Debugger for Easy Prototype Development - Built-in External Flash Programming Algorithm, Allows Onboard Flash Programming. - All Existing ATSAM97xx and ATSAMA2xxx Tools Available for Sound and Soundbank Development
*
*
Sound Synthesis ATSAM2553 Integrated Digital Musical Instrument
*
*
*
1. Description
The ATSAM2553 integrates into a single chip a SAM core (64-slots DSP + 16-bit processor), a 32K x 16 RAM, an LCD display interface and a scanner allowing direct connection to velocity sensitive keyboards, switches, LEDs and sliders. With addition of a single external ROM or Flash and a stereo DAC, a complete low cost musical instrument can be built, including reverb and chorus effects, parametric equalizer, surround effects, orchestrations, pitch bend, wheel controller, without compromising on sound quality. The ATSAM2553 is housed in a standard 128-lead LQFP package.
6399A-DRMSD-13-Oct-08
Figure 1-1.
Typical Application
ROM * * * * * * Keyboards Switches Leds LCD display Sliders Midi in/out
ATSAM2553
DAC
2. Main Features
The ATSAM2553 provides a new generation of integrated solutions for electronic musical instruments. The ATSAM2553 includes all key circuitry into a single silicon chip: sound synthesizer/processor, 16-bit control processor, interface with keyboards, switches, sliders, LEDs, LCD display, etc. The synthesis/sound processing core of the ATSAM2553 is taken from the SAM97xx series, whose quality has already been demonstrated through dozens of different musical products: E.Pianos, home keyboards, professional keyboards, classical organs, sound expanders. The maximum polyphony is 64 voices without effects. A typical application will be 38-voice polyphony with reverb, chorus, 4-band equalizer and surround. The ATSAM2553 is directly compatible with most available musical keyboards. This includes configuration options for spring or rubber type contacts, common anode or common cathode type matrix. A 64 s timing accuracy for velocity detection provides a very reliable dynamic response even with low cost unweighted keyboards. The time between contacts is coded with 256 steps on a logarithmic time scale, then converted by software to a 128-step MIDI scale according to the type of keyboard and a selected keyboard sensitivity. The ATSAM2553 can handle directly up to 176 switches. Switches, organized in matrix form, require only a serial diode. Up to 88 LEDs can be directly controlled by the ATSAM2553 in a time multiplexed way. Additional LEDs can be connected through additional external shift registers using the GPIO lines (general purpose I/O) of the ATSAM2553. The built-in analog to digital converter of the ATSAM2553 allows connecting continuous controllers like pitch-bend wheel, modulation, volume sliders, tempo sliders, etc. Up to 16 sliders can be connected. The ATSAM2553 can be directly connected to most LCD displays through an 8-bit dedicated data bus and 3 control signals. Configuration options allow the ATSAM2553 to cover a wide range of musical products, from the lowest cost keyboard to the high range digital piano, thanks to flexible memory and I/O organization: built-in 64K bytes RAM, up to 64M bytes external memory for firmware, orchestrations and PCM data. The external memory can be ROM, RAM or FLASH. Memory types can be mixed, but for most applications there is no need for external RAM memory as the built-in 64K bytes
2
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
RAM is enough to handle firmware variables and reverb delay lines. External flash memory can be programmed on-board from a host processor through the ATSAM2553. The ATSAM2553 operates from a single 12.2880 MHz crystal. A built-in PLL raises the frequency to 49.152 MHz for internal processing. This allows to minimize radio frequency interference (RFI), making it easier to comply with FCC, CSA, CE standards. A power-down feature is also included which can be controlled externally (PDWN pin). This makes the ATSAM2553 very suitable for battery operated instruments. The ATSAM2553 has been designed with final instrument quick time to market in mind. The ATSAM2553 product development program includes key features to minimize product development efforts: * C compiler for built-in P16 processor * Specialized debug interface, allowing on-target software development with a source code debugger. * Standard sound generation/processing firmware * Standard orchestration firmware * Windows tools for sounds, soundbanks and orchestrations developments * Standard soundbanks * Strong technical support available directly from Dream(R)
3
6399A-DRMSD-13-Oct-08
3. ATSAM2553 Internal Architecture
Figure 3-1. Internal Architecture
DACLK DABDx DAAD CLBD WSBD RUN 32k x 16 SRAM VCCBAT
64 Slots DSP with Algorithm s in RAM P16 Proces s or 256x16 RAM 512x16 ROM
Memory Manager Unit
MIDI UART 3 x Tim ers Control & Status regs
A0-A24 A0-A23 D0-D15 D0-D15 RD/, WR/ RD/, WR/ CSx/ CSx/ XIO/ XIOx/
DEBUG/
MIDI IN/OUT MIDI IN/OUT P0-3 GPIO0 -4 KBDIO/ KBD|IO/ ROW0-3 ROW0-2 BR0-10 MK0-10 VA33 VREFP AGND VREFN VIN VIN
X1,X2 LFT RESET/ PDWN/
128 11 304 x 16 Scanning RAM
Clock & PLL
Keyboards Switches Sliders LEDs Scanning I/F
8 bit ADC 10-bit ADC
LCD dis play Interface
DB0-DB7 DB0-DB7 RS RS R/W RW E ENB
The highly integrated architecture of the ATSAM2553 combines a specialized high-performance RISC-based digital signal processor (DSP) and a general purpose 16-bit CISC-based control processor (P16). An on-chip memory management unit (MMU) allows the DSP and the control processor to share an internal 32K x 16 RAM as well as external ROM and/or RAM memory devices. An intelligent peripheral I/O interface function handles other I/O interfaces, such as the on-chip MIDI UART and 3 timers, with minimum intervention from the control processor. A keyboard/switches/sliders/LEDs autonomous scanning interface handles the specific music instrument peripherals, including accurate keyboard velocity detection and communicates with the control processor through a dedicated 304x11 dual port RAM. An LCD display interface allows direct connection to common LCD displays
4
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
3.1 DSP Engine
The DSP engine operates on a frame-timing basis with the frame subdivided into 64 process slots. Each process is itself divided into 16 micro-instructions known as "algorithm". Up to 32 DSP algorithms can be stored on-chip in the Alg RAM memory, allowing the device to be programmed for a number of audio signal generation/processing applications. The DSP engine is capable of generating 64 simultaneous voices using algorithms such as wavetable synthesis with interpolation, alternate loop and 24dB resonant filtering for each voice. Slots may be linked together (ML RAM) to allow implementation of more complex synthesis algorithms. A typical musical instrument application will use a little more than half the capacity of the DSP engine for synthesis, thus providing state of the art 38 voices synthesis polyphony. The remaining processing power may be used for typical functions like reverberation, chorus, surround effect, equalizer, etc. Frequently accessed DSP parameter data are stored into 5 banks of on-chip RAM memory. Sample data or delay lines, which are accessed relatively infrequently, are stored in external ROM, or into the built-in 32K x 16 RAM. The combination of localized micro-program memory and localized parameter data allows micro-instructions to execute in 20.3 ns (49 MIPS). Separate busses from each of the on-chip parameter RAM memory banks allow highly parallel data movement to increase the effectiveness of each micro-instruction. With this architecture, a single micro-instruction can accomplish up to 6 simultaneous operations (add, multiply, load, store, etc.), providing a potential throughput of 294 million operations per second (MOPS).
3.2
Enhanced P16 Control Processor and I/O Functions
The Enhanced P16 control processor is the new version of the P16 processor with added instructions allowing C compiling. The P16 is a general-purpose 16-bit CISC processor core which runs from external memory. A debug ROM is included on-chip for easy development of firmware directly on the target system. This ROM also contains the necessary code to directly program externally connected flash memory. The P16 includes 256 words of local RAM data memory for use as registers, scratchpad data and stack. The P16 control processor writes to the parameter RAM blocks within the DSP core in order to control the synthesis process. In a typical application, the P16 control processor parses and interprets incoming commands from the MIDI UART or from the scanning interface and then controls the DSP by writing into the parameter RAM banks in the DSP core. Slowly changing synthesis functions, such as LFOs, are implemented in the P16 control processor by periodically updating the DSP parameter RAM variables. The P16 control processor interfaces with other peripheral devices, such as the system control and status registers, the on-chip MIDI UART, the on-chip timers and the scanning interface through specialized "intelligent" peripheral I/O logic. This I/O logic automates many of the system I/O transfers to minimize the amount of overhead processing required from the P16.
3.3
Memory Management Unit (MMU)
The Memory Management Unit (MMU) block allows external ROM and/or RAM memory resources to be shared between the synthesis/DSP and the P16 control processor. This allows a single ROM device to serve as sample memory storage for the DSP and as program storage for the P16 control processor. An internal 32K x 16 RAM is also connected to the MMU, allowing RAM resources to be shared between the DSP for delay lines and the P16 for program data.
5
6399A-DRMSD-13-Oct-08
3.4
Keyboards/Switches/Sliders/LEDs Scanning Interface
The scanning interface consists of hardwired logic. It time multiplexes keyboard, switches and LEDs connections therefore minimizing the amount of wiring required. It communicates with the P16 through an 304 x 11 dual port RAM and a few control registers. When a new incoming event is detected, such as key-on, key-off or switch change, the scanning interface will notify the P16 by indicating the type of event. The P16 then simply reads the dual port RAM to get the corresponding parameter, such as velocity or switch status. Conversely, the P16 simply writes into the dual port RAM the led states to be displayed and the scanning interface will then take care of time multiplexing the display. The scanning interface uses an unique key velocity detect scheme with a pseudo-logarithmic time scale. This allows velocities to be accurately detected, even when keyboard keys are pressed very softly. Finally a built-in 10-bit analog to digital converter (ADC) allows the connection of up to 16 continuous controllers through external analog multiplexers such as the 4051.
3.5
LCD Display Interface
The LCD display interface uses a dedicated bidirectional data bus (DB0-DB7) an Instruction/data control RS, a read write signal R/W and an enable signal ENB. Built-in features are included to accommodate even the slowest LCD displays.
3.6
Flash Programming
The ATSAM2553 enables programming Flash memories in three different ways: * Blank Flash programming is done by the debug interface. This mode is very slow and should be reserved for the initial boot sector programming. * Program update. All the Flash content can be re-programmed. The ATSAM2553 cannot play music during the Flash erase and programming. A specific firmware is used to program Flash with the DSP * Parameters update, e.g. in keyboard applications, backup parameter and sequencer song. If the Flash enables concurrent read during program/erase, it is possible to backup parameters in the upper memory plane while the p firmware is running on the lower plane. The ATSAM2553 cannot play music during the parameter backup because sound samples are stored in both memory planes.
3.7
Flash Features
* 3.3v or 5v * Access time: 90 ns (for 12.288 MHz crystal) * Dual plane with concurrent read while program/erase recommended for parameters backup.
6
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
4. Pin Description
5VT indicates a 5 volt tolerant Input or I/O pin.
4.1
Pins by Function
Table 4-1.
Pin Name GND
Power Supply
Pin# 1, 14, 33, 48, 65, 85, 97, 98, 116 16 18, 32, 40, 49, 64, 84, 96, 115, 128 Type PWR Function DIGITAL GROUND All pins should be connected to a ground plane ANALOG GROUND for the ADC. Should be connected to a clean analog ground. POWER SUPPLY, 3.3V 10% All pins should be connected to a VD33 plane Power for the internal PLL, +1.8V nominal (1.8V 10%). These pins can be connected to the output of the regulator OUTVC18 (pin 41). A 100 nF decoupling capacitor should be connected between this pin and PLL ground (pin98) Analog power for the ADC, +3.3V nominal (3,3V 10%).
AGND
PWR
VD33
PWR
VD18
100
PWR
VA33
17
PWR
Power supply decoupling note: like all high speed HCMOS ICs, proper decoupling is mandatory for reliable operation and RFI reduction. The recommended decoupling is 100 nF at each corner of the IC with an additional 10 FT bulk capacitor close to the X1, X2 pins.
Table 4-2.
Pin Name MIDI-IN MIDI-OUT
Serial MIDI
Pin# 127 126 Type IN 5VT OUT Function Serial MIDI IN. This pin has a built-in pull up Serial MIDI OUT.
Table 4-3.
Pin Name WA0-WA24 WD0-WD15 WOE WWE
External PCM ROM/RAM/IO
Pin# 42-47,5055,66-78 21-31,34-38 94 95 Type OUT I/O 5VT OUT OUT OUT OUT Function External memory I/O Address, up to 32 Mega x 16 for direct ROM/RAM connection. External memory I/O data. Data is read (input) when RD is low, written (output) when WR is low. External ROM/RAM peripherals output enable. External RAM peripherals write enable. Programmable chip selects. Can be configured to handle several ROMs or mixed RAM/ROM/Flash. External peripheral chip select. XIO maps its peripheral into 4k bytes address space for optional further decoding.
WCS0 -WCS1 92,93 XIO 20
7
6399A-DRMSD-13-Oct-08
Table 4-4.
Pin Name KBDIO
Keyboard, Switches, LEDs, Sliders, Scanning
Pin# 19 Type OUT Function If 1 BR[0-10] & MK[0-10] hold keyboard contact input data. If 0 BR[0-10] holds switch status input, MK[0-10] holds led data output. Row select: keyboard, switches/LEDs, external slider analog multiplexer (4051) channel select. Sixteen rows combined with eleven BR/MK columns allow to control 176 keys, 176 switches, 88 leds and 16 sliders. The programmable bit P0 can be programmed to be used as ROW4. This allows to use keyboards with matrix other than 8*11 (e.g. 22*4) or multiple keyboards up to 264 keys. Kbd contact 1/switch status. When KBDIO =1 then BR[0-10] holds the keyboard key-off or first contact status. This can be configured as normally close (spring type), normally open (rubber type), common anode or common cathode contact diodes. When KBDIO = 0 then BR[0-10] holds the switch status from ROW[0-4]. Kbd contact 2/LED data. When KBDIO = 1 then MK[0-10] holds the keyboard key-on or second contact status. This can be configured as common anode or common cathode contact diodes. When KBDIO = 0 then MK[0-10] holds the LED data from ROW[0-4] Slider analog input. Ranges from AGND to VA33. Should hold the ROW[0-3] slider voltage. Multiple sliders should be connected through external analog multiplexer(s) like 4051.
ROW0-ROW3
56-59
OUT
BR0-BR10
104-114
IN 5VT
MK0-MK10
79-83,86-91
I/O 5VT
VIN
15
ANA
The following signals are controlled by firmware, therefore their timing relationships is determined by firmware only. Table 4-5.
Pin Name RS RW ENB DB0-DB7
LCD Display Interface
Pin# 5 4 3 6-13 Type OUT OUT OUT I/O 5VT Function Select Instruction (LOW) or Data (HIGH) Select Write (LOW) or Read (HIGH) Enable, active high Bi-directional data bus
8
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
The ATSAM2553 connects to a variety of stereo DACs or CODECs from 16 to 20 bits, with Japanese or I2S format. When Japanese format is used, only 16 bits are supported without external circuitry Table 4-6.
Pin Name CKOUT DABD0DABD1 DAAD CLBD WSBD
Digital Audio Group
Pin# 120 123,124 125 121 122 Type OUT OUT IN 5VT OUT OUT Function Master clock for / DAC (256 x Fs) Serial data for 2 stereo output channels. Serial data for 1 stereo input channel Digital audio bit clock Digital audio left/right select
Table 4-7.
Pin Name P0-P3
Miscellaneous Group
Pin# 60-63 Type I/O 5VT Function General purpose programmable I/O pins. P0 pin can be used as general purpose I/O or as ROW4 function. These pins have a built-in pull down. Debug clock, should be connected to VD33 under normal operation. If DBCLK is found low just after RESET, then the internal ROM debugger/Flash programmer is started. Debug data, allows serial communication for debug/Flash programming. This pin has a built-in pull down. Debug ack, toggled each time a bit is received/sent on DBDATA. Reset input, active low. This is a Schmitt trigger input, allowing direct connection of a RC network. Power down, active low. When power down is active, WCS0, WCS1, XIO, WWE, WOE address and data lines are floated. All other outputs are set to 0. The crystal oscillator is stopped, OUTVC18 is set to 0 and 1.8V supply voltage is removed from the core. To exit from power down, PDWN must be set to VD33, then RESET applied. When unused this pin must be connected to VD33. 3.3V to 1.8 V regulator output. The built-in regulator gives 1.8V for internal use (core supply). PLL supply pin VD18 could also be connected to this pin. Decoupling capacitors 470 pF in parallel with 2.2 or 4.7 F must be connected between OUTVC18 and GND. 12.288 MHz (nominal) crystal connection. An external clock can also be used at X1. Test pins, should be grounded.
DBCLK
117
IN 5VT
DBDATA DBACK RESET
119 118 103
I/O 5VT OUT IN 5VT
PDWN
39
IN
OUTVC18
41
PWR
X1-X2 TEST0TEST1
101,102 2,99
IN
9
6399A-DRMSD-13-Oct-08
4.2
Pinout by Pin Number 128-lead LQFP Package
Pinout by Pin#
Name GND TEST0 ENB RW RS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 GND VIN AGND VA33 VD33 KBDIO XIO WD0 WD1 WD2 WD3 WD4 WD5 WD6 WD7 WD8 WD9 WD10 VD33 Pin# 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name GND WD11 WD12 WD13 WD14 WD15 PDWN VD33 OUTVC18 WA0 WA1 WA2 WA3 WA4 WA5 GND VD33 WA6 WA7 WA8 WA9 WA10 WA11 ROW0 ROW1 ROW2 ROW3 P0 P1 P2 P3 VD33 Pin# 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Name GND WA12 WA13 WA14 WA15 WA16 WA17 WA18 WA19 WA20 WA21 WA22 WA23 WA24 MK0 MK1 MK2 MK3 MK4 VD33 GND MK5 MK6 MK7 MK8 MK9 MK10 WCS0 WCS1 WOE WWE VD33 Pin# 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Name GND GND TEST1 VD18 X1 X2 RESET BR0 BR1 BR2 BR3 BR4 BR5 BR6 BR7 BR8 BR9 BR10 VD33 GND DBCLK DBACK DBDATA CKOUT CLBD WSBD DABD0 DABD1 DAAD MIDI_OUT MIDI_IN VD33
Table 4-8.
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
10
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
5. Marking
Figure 5-1. ATSAM2553 Marking
FRANCE
SAM2553
YYWW 58A66C XXXXXXXXX
PIN 1
11
6399A-DRMSD-13-Oct-08
6. Mechanical Dimensions 128-lead LQFP Package
Figure 6-1. Mechanical Dimensions
12
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
7. Electrical Characteristics
7.1 Absolute Maximum Ratings(*)
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All voltages with respect to 0V, GND = 0V.
Temperature under bias................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on any 5 volt tolerant pin .......................... -0.3 to 5.5V Voltage on any non 5 volt tolerant pin ........ -0.3 to VD33 + 0.3V Supply Voltage.......................................................................... VD33 ......................................................................-0.3V to 3.6V VD18 .........................................................................-0.3V to 2V VA33 ......................................................................-0.3V to 3.6V Maximum IOL per I/O pin............................................... 10 mA Maximum IOH per I/O pin .............................................. 10 mA Maximum Output current from OUTVC18 pin (max duration = 1sec) IREGO ........................................................................... 70 mA
13
6399A-DRMSD-13-Oct-08
7.2
Recommended Operating Conditions
Recommended Operating Conditions
Parameter Supply voltage Supply voltage (PLL) Supply voltage (PLL) OUTVC18 output current Operating ambient temperature Min 3 1.65 3 -25 Typ 3.3 1.8 3.3 30 70 Max 3.6 1.95 3.6 Unit V V V mA C
Table 7-1.
Symbol VD33 VD18 VA33 IREGO TA
7.3
DC Characteristics
DC Characteristics (TA = 25C, VD33 = 3.3V 10%, VD18 = 1.8V 10%)
Parameter Low level input voltage High level input voltage on non-5VT pins High level input voltage on 5VT pins Low level output voltage IOL=4mA High level output voltage IOH=4mA Power supply current at (crystal freq.=12.288 MHz) Min -0.3 2 2 VD33-0.4 Typ 0.7 36 Power down supply current Pull-up or Pull-down resistor 8 0.6 13 25 Max 0.8 3.6 5.5 0.4 Unit V V V V V mA mA mA kOhm
Table 7-2.
Symbol VIL VIH VIH VOL VOH ID18 ID33 - Rud
14
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
8. Timings
All timings conditions: VD33=3.3V, VD18=1.8V, TA=25C, all outputs except X2, have load capacitance = 30 pF. All timings refer to tck, which is the internal master clock period. The internal master clock frequency is 4 times the frequency at pin X1. Therefore tck=txtal/4. The sampling rate is given by 1/(tck*1024). The maximum crystal frequency/clock frequency at X1 is 12.288 MHz (48 KHz sampling rate).
8.1
Crystal Frequency Selection Considerations
There is a trade-off between the crystal frequency and the support of widely available external ROM/Flash components. Table 8-1 allows to select the best fit for a given application;
Table 8-1.
Crystal Frequency Selection Chart
Xtal (MHz) 12.288 11.2896 9.60 8.00 tck (ns) 20.35 22.14 26.04 31.25 ROM tA (ns) 92 101 120 146 Comments Recommended for current designs.
Sample Rate (kHz) 48 44.1 37.5 31.25
Using 12.288 MHz crystal frequency allows to use widely available ROM/Flash with 90 ns access time, while providing state of the art 48 kHz sampling rate.
15
6399A-DRMSD-13-Oct-08
8.2
Scanning (Keyboard, Switches, LEDs, Sliders
Scanning (Keyboard, Switches, LEDs, Sliders
Figure 8-1.
tkbd tsclk SCLK KBDIO/ ROW BR[0-10] tka tkd MK[0-10]
tio
tioa tiod
tka tkd
tiog
tioh
All timings relative to 12.288 MHz crystal between X1 and X2. Table 8-2.
Symbol Tkbd Tio Tsclk Tka tkd tioa tiod tiog tioh
Timing Parameters
Parameter Keyboard access (KBDIO high time) Switches/leds access (KBDIO low time) Internal scanning clock period Keyboard valid from rising KBDIO Break (contact1) and make (contact2) data from Keyboard floating from rising KBDIO Switch data valid from falling KBDIO Switch data floating from falling KBDIO LED data MK guard time LED data floating from rising KBDIO 3.7 27 0 1.2 Min Typ 1.3 3.9 325 1.1 1.5 3.6 4 163 82 Max Unit s s ns s s s s ns ns
16
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
8.3 External ROM/Flash, RAM, I/O Read Timing
External ROM/Flash, RAM, I/O Read Timing
tRC
Figure 8-2.
WCS0/ WCS1/ XIO/ WA0WA24
tCSOE
tPOE WOE/ tOE WD0WD15 tACE tDF
Table 8-3.
Symbol tRC tCSOE tPOE tACE tOE tDF
Timing Parameters
Parameter Read cycle time Chip select low / address valid to WOE/ low Output enable pulse width Chip select/address access time Output enable access time Chip select or WOE/ high to input data Hi-Z Min 5*tck 2*tck-5 5*tck-5 3*tck-5 0 Typ 3*tck Max 6*tck 3*tck+5 2*tck-5 Unit ns ns ns ns ns ns
17
6399A-DRMSD-13-Oct-08
8.4
External Flash, RAM, I/O Write Timing
External Flash, RAM, I/O Write Timing
Figure 8-3.
WCS0/ WCS1/ XIO/ WA0WA24
tRC
tCSOE
tPOE WOE/ tOE WD0WD15 tACE tDF
Table 8-4.
Symbol tWC tCSWE tWP tDW tDH
Timing Parameters
Parameter Write cycle time Write enable low from CS/ or Address or WOE/ Write pulse width Data out setup time Data out hold time Min 5*tck 2*tck-10 4*tck-10 10 Typ 4*tck Max 6*tck Unit ns ns ns ns ns
18
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
8.5 Digital Audio
Digital Audio
Figure 8-4.
tcw WSBD CLBD DABD0 DABD1 DAAD
tcw
tclbd
tsod
tsod
Table 8-5.
Symbol tcw tsod tclbd
Timing Parameters
Parameter CLBD rising to WSBD change DABD valid prior/after CLBD rising CLBD cycle time Min 8*tck-10 8*tck-10 Typ 16*tck Max Unit ns ns ns
Figure 8-5.
Digital Audio Frame Format
WSBD (I2S) WSBD (Japanese) CLBD
DABD0 DABD1 DAAD
MSB
LSB (16bits)
LSB (20bits) LSB (18bits)
MSB
19
6399A-DRMSD-13-Oct-08
9. Recommended Crystal Compensation
Figure 9-1. Recommend Crystal Compensation
10. Recommended Board Layout
Like all HCMOS high integration ICs, following simple rules of board layout is mandatory for reliable operations: * GND, VD33, VD18 distribution, decouplings All GND, AGND, VD33, VD18, VA33 pins should be connected. A GND plane is strongly recommended below the ATSAM2553. The board GND + VD33 planes could be in grid form to minimize EMI. Recommended VD18 decoupling is 0.1F, close to the VD18 pin and 470pF in parallel with 2.2 or 4.7F, close to OUTVC18 pin. VD33 requires 0.1 F at each corner of the IC with an additional 10 FT capacitor that should be placed close to the crystal. * Crystal The paths between the crystal, the crystal compensation capacitors and the ATSAM2553 should be short and shielded. The ground return from the compensation capacitors should be the GND plane from ATSAM2553. * Busses Parallel layout from DB0-DB7 and WA0-WA24/WD0-WD15 should be avoided. The DB0-DB7 bus is an asynchronous type bus. Even on short distances, it can induce pulses on WA0WA24/WD0-WD15 which can corrupt address and/or data on these busses. A ground plane should be implemented below the DB0-DB7 bus. A ground plane should be implemented below the WA0-WA24/WD0-WD15 bus, which connects both to the ROM/Flash grounds and to the ATSAM2553. * Analog section A specific AGND ground plane should be provided, which connects by a single trace to the GND ground. No digital signals should cross the AGND plane. Refer to the CODEC vendor recommended layout for correct implementation of the analog section
20
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
11. Typical Keyboard, Switches, LEDs, Sliders Connection
21
6399A-DRMSD-13-Oct-08
12. Overview of Operations
Note: the reader should be familiar with the ATSAM97xx series operation. Refer to the ATSAM9707 product development kit "prgdvkit.pdf" document. This chapter describes operations and registers specific to the ATSAM2553.
12.1
Memory Mapping
Size (in word) 256 768 32M - 1K 32K 4K 4K 216K 32M - 256K
Address Low 000:0000 000:0100 000:0400 200:0000 200:8000 200:9000 200:A000 204:0000
Address High 000:00FF 000:03FF 1FF:FFFF 200:7FFF 200:8FFF 200:9FFF 203:FFFF 3FF:FFFF
Access ATSAM97xx standard routine ROM Built in debug ROM External ROM/Flash (WCS0/) Built in SRAM External memory page XIO (XIO/) Not used Not used External SRAM (WCS1)
12.2
I/O Mapping
Write 0-9 0A 0B 0C - 0E 0F
Read 0-9 0A X 0C - 0E 0F Standard ATSAM97xx I/O (Refer to prgdvkit.pdf) LCD port Keyboard config Scanning port ADD0-2 GPIO Control/Status
12.3
LCD Interface
The ATSAM2553 can be directly connected to most LCD displays. The ATSAM2553 provides an 8-bit data bus, DB0-DB7 and 3 output control pins RS, RW, ENB. All the LCD pins are controlled by I/O Access ADD 0AH. The IO reads only the 8-bit data bus. The IO writes into the 11-bit LCD_Reg:
LCD_Reg[7:0] LCD_Reg[8] LCD_Reg[9] LCD_Reg[10] DB[7:0] RS RW ENB
22
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
IO Access Write Write Read Read
IO Data IOD[10:0] (IOD[9]=0) IOD[10:0] (IOD[9]=1) xx xxx, LCD_D[7:0]
LCD_Reg[10] IOD[10:0] LCD_Reg[9]=0 IOD[10:0] LCD_Reg[9]=1 LCD_Reg[9]=0 LCD_Reg[9]=1
DB[7:0] IOD[7:0] output LCD_D[7:0] input LCD_Reg[7:0] output LCD_D[7:0] input
RW 0 1 0 1
Comments Set LCD in write mode Set LCD in read mode Invalid read from LCD in write mode Read from LCD
12.4
Keyboard Configuration Register
The configuration register allows dealing with a variety of keyboards. This write only 6-bit register is mapped at the address OBH in the I/O space. Reg[0] = contact type Reg[1] = diode wiring 0 for rubber type contact 1 for spring type contact 0 for common anode wiring 1 for common cathode wiring The default configuration (power-up) is common anode (Reg[1]=0) and rubber contact (Reg[0]=0) which corresponds to most popular keyboards. Reg[3:2] = Scanning clock divider. (Default 00).
Reg[3:2]} 00 01 10 11 Divide Factor 1 2 4 Not Used
Reg[5:4] = Scanning matrix. (Default 00).
Reg[5:4]} 00 01 10 11 Scanning Matrix Row[2:0] Row[3:0] Row[4:0] Not Used
23
6399A-DRMSD-13-Oct-08
12.5
Scanning Interface
The ATSAM2553 has built-in specialized hardware which allows the following functions: * Scanning of up to 264 keys from an external keyboard, with key-on and key-off velocity measurement (time between contacts) * Scanning of up to 176 switches * Time multiplex control of up to 88 LEDs * Analog to digital conversion of up to 16 analog sources The P16 interfaces with the scanning using a 3 addresses port located at 0CH to 0EH in the I/O mapping. This port enables access to the keyboard RAM. This 304 x 11 RAM is mapped as follows:
* Key Page 0
00H 00H
* Key Page 1
00H
* Key Page 2
Key velocity and status for MK0/BR0 at row [2:0] Key velocity and status for MK1/BR1 at row [2:0] Key velocity and status for MK2/BR2 at row [2:0] Key velocity and status for MK3/BR3 at row [2:0] Key velocity and status for MK4/BR4 at row [2:0] Key velocity and status for MK5/BR5 at row [2:0] Key velocity and status for MK6/BR6 at row [2:0] Key velocity and status for MK7/BR7 at row [2:0] Key velocity and status for MK8/BR8 at row [2:0] Key velocity and status for MK9/BR9 at row [2:0] Key velocity and status for MK10/BR10 at row [2:0]
08H
Key velocity and status for MK0/BR0 at row [2:0] Key velocity and status for MK1/BR1 at row [2:0] Key velocity and status for MK2/BR2 at row [2:0] Key velocity and status for MK3/BR3 at row [2:0] Key velocity and status for MK4/BR4 at row [2:0] Key velocity and status for MK5/BR5 at row [2:0] Key velocity and status for MK6/BR6 at row [2:0] Key velocity and status for MK7/BR7 at row [2:0] Key velocity and status for MK8/BR8 at row [2:0] Key velocity and status for MK9/BR9 at row [2:0] Key velocity and status for MK10/BR10 at row LED data
08H
Key velocity and status for MK0/BR0 at row [2:0] Key velocity and status for MK1/BR1 at row [2:0] Key velocity and status for MK2/BR2 at row [2:0] Key velocity and status for MK3/BR3 at row [2:0] Key velocity and status for MK4/BR4 at row [2:0] Key velocity and status for MK5/BR5 at row [2:0] Key velocity and status for MK6/BR6 at row [2:0] Key velocity and status for MK7/BR7 at row [2:0] Key velocity and status for MK8/BR8 at row [2:0] Key velocity and status for MK9/BR9 at row [2:0] Key velocity and status for MK10/BR10 at row [2:0]
08H
10H
10H
10H
18H
18H
18H
20H
20H
20H
28H
28H
28H
30H
30H
30H
38H
38H
38H
40H
40H
40H
48H
48H
48H
50H
50H
50H
58H
58H
58H
60H
SWITCH data
70H
ADC data
7FH
24
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
Note: There are three possible values for Key page. 0: Value sampled at Row4 = 0, Row3 = 0 1: Value sampled at Row4 = 0, Row3 = 1 2: Value sampled at Row4 = 1, Row3 = 0 3: Not used. 12.5.1 KBD Status (I/O add OCH Read-only) * D[7] KRQ flag = 1 indicates that a key-on or key-off has been detected and that the P16 service is requested. This flag is automatically cleared by a write to data H for the detected key. * D[6:0] specify which keyboard key is requesting the service, valid only if KRQ flag = 1. Key nb range from 0 to 87. * D[9:8] specify the Key page 12.5.2 RAM Add (I/O add OCH Write-only) * D[6:0] RAM address * D[7] don't care * D[9:8] Key page
Key Page Value: 0,1,2 Don't-care Don't-care Don't-care Add 00H to 57H 58H to 5FH 60H to 6FH 70H to 7FH Index 8*i+row[2:0] row[2:0] row[3:0] row[3:0] Content Key velocity and status Led data Switch status ADC value
"i" refers to the Mki or Bri signal number which ranges from 0 to 10. For example, the information regarding the key at row 2, column MK5/BR5, will be found at RAM address 8*5+2=42. The scanning hardware cycles the row[2:0] signals from 0 to 7 to the output pins in 41.6 s (5.2 s per row). 12.5.3 RAM Data (I/O add ODH Read/Write) Data[10:0] I/O add ODH, Data[10:0] Data[15:11] don't care
Scanning RAM data format:
Bit-> Key velocity & status LED data Switch data ADC status 10 SRQ MK10 BR10 X 9 ON MK9 BR9 X 8 BUSY MK8 BR8 X MK7 BR7 MK6 BR6 MK5 BR5 MK4 BR4 7 6 5 4 VEL MK3 BR3 MK2 BR2 MK1 BR1 MK0 BR0 3 2 1 0
ADC DATA
25
6399A-DRMSD-13-Oct-08
Key velocity & Status: * SRQ: If 1, indicates that the velocity detection is completed and that this key requests attention from the P16. In this case BUSY = 0, ON and VEL hold valid information. * ON: 1 indicates key-on, 0 indicates key-off. Valid only if SRQ = 1. * BUSY: Used internally by the scanning hardware, indicates "velocity detection in progress".
* VEL: From 0 to 255, valid only if SRQ = 1, indicates the time between contacts. Time is depending on Scanning divider and Scanning matrix configuration. Time = TimeCount x 2Scanning divider x (1 + Scanning matrix) - 0 < VEL < 128: TimeCount = VEL x 41.6 s. - 128 < VEL < 192: TimeCount = 128 x 41.6 s + (VEL - 128) x 2 x 41.6s. - 192 < VEL < 224: TimeCount = 2 x 128 x 41.6 s + (VEL - 192) x 4 x 41.6s. - 224 < VEL < 240: TimeCount = 3 x 128 x 41.6 s + (VEL - 224) x 8 x 41.6s. - 240 < VEL < 255: TimeCount = 4 x 128 x 41.6 s + (VEL - 240) x 16 x 41.6s. * LED data: The P16 should write to these locations the MK information which should appear to the MK[10:0] pins at row[2:0] time. * Switch data: These locations hold the BR information read from the BR[10:0] pins at row[3:0] time. * ADC data: These locations represent the analog voltage at VIN pin at row[3:0] time, from 0 (VIN = AGND) to 03FFH (VIN = VA33). ADC data are sampled with 10-bit precision and the result is stored on 8 bits.
12.6
GPIO
P[3:1] are controlled by the ATSAM97xx config and control/status registers (refer to prgdvkit.pdf). P0 in normal mode is controlled by the ATSAM97xx config and control/status registers (refer to prgdvkit.pdf). The ATSAM2553 additional GPIO control/status register controls P0 normal and alternate mode. The GPIO register is located at address 0xF in the I/O mapping.
Data bit number 7 6 5 4 3 2 1 0 Write x x x P0 Alt x DBDATA OUT DBACK DBDATA Output Enable Read x x x P0 Alt DBCLK DBDATA IN DBACK status DBCLK
26
ATSAM2553
6399A-DRMSD-13-Oct-08
ATSAM2553
PO:
Normal Input SAM2553_config_Reg[0] (I/O add0) SAM2553_GPIO_Reg[4] (I/O addF) 0 x Normal Output 1 0 Alternate Output 1 1
In alternate output mode, GPIO0 = Row4.
27
6399A-DRMSD-13-Oct-08
13. Revision History
Change Request Ref
Document Ref. 6399A
Comments First issue.
28
ATSAM2553
6399A-DRMSD-13-Oct-08
Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com www.atmel.com/Dream Literature Requests www.atmel.com/literature Technical Support info@dream.fr Atmel techincal support Sales Contacts www.atmel.com/contacts/
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
(c) 2008 Atmel Corporation. All rights reserved. Atmel(R), Atmel logo and combinations thereof, Dream (R) and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
6399A-DRMSD-13-Oct-08

▲Up To Search▲

Price & Availability of ATSAM2553

	To Download ATSAM2553 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .