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ADVANCE
128Mb: x32 DDR SDRAM
DOUBLE DATA RATE (DDR) SDRAM
FEATURES
* VDD = +2.5V 0.125V, VDDQ = +2.5V 0.125V * Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture * Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle * Reduced and matched output drive options * Differential clock inputs (CK and CK#) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; centeraligned with data for WRITEs * DLL to align DQ and DQS transitions with CK * Four internal banks for concurrent operation * Data mask (DM) for masking write data * Programmable burst lengths: 2, 4, 8, or full page * 32ms, 4,096-cycle auto refresh * Auto precharge option * Auto Refresh and Self Refresh Modes * 2.5V I/O (SSTL_2 compatible) * DQS per byte on the FBGA package * 1.8V VDDQ option for FBGA package * tRAS lockout
MT46V4M32 - 1 Meg x 32 x 4 banks
For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/dramds
PIN ASSIGNMENT (TOP VIEW) 100-Pin TQFP
DQ2 VSSQ DQ1 DQ0 VDD VDDQ DQS NC \ RFU VSSQ DNU NC NC NC NC VDDQ VSS DQ31 DQ30 VSSQ DQ29
10099 98 97 96 95 94 93 9291 90 89 88 87 86 8584 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 3940 41 42 43 44 45 4647 48 49 50
DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DM0 DM2 WE# CAS# RAS# CS# BA0 BA1
DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ VREF DM3 DM1 CK CK# CKE NC/MCL A8/AP
OPTIONS
* Configuration 4 Meg x 32 (1 Meg x 32 x 4 banks) * IO Voltage 2.5V VDDQ 1.8V VDDQ * Plastic Packages 100-pin TQFP (0.65mm lead pitch) 12mm x 12mm FBGA * Timing - Cycle Time 300 MHz @ CL = 5 250 MHz @ CL = 4 200 MHz @ CL = 3
Part Number Example:
MARKING
4M32 None V1 LG FK -331 -4 1 -5
Configuration Refresh Count Row Addressing Bank Addressing Column Addressing
KEY TIMING PARAMETERS
SPEED GRADE -33 -4 -5 CL = 51 CLOCK RATE CL = 41 CL = 31 DATA-OUT ACCESS WINDOW2 WINDOW DQS-DQ SKEW
Note: 1. -4 and -33 speed grades are only available in the FBGA package
MT46V4M32V1FK-33
128Mb (x32) DDR SDRAM PART NUMBER
PART NUMBER MT46V4M32LG
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
300 MHz 250 MHz 0.685ns 250 MHz 200 MHz 0.950ns 200 MHz 1.400ns
A0 A1 A2 A3 VDD A10 A11 NC NC NC NC NC NC NC A9 VSS A4 A5 A6 A7
4 Meg x 32 1 Meg x 32 x 4 banks 4K 4K (A0-A11) 4 (BA0, BA1) 256 (A0-A7)
0.6ns +0.40ns 0.7ns +0.45ns 0.7ns +0.45ns
ARCHITECTURE 4 Meg x 32
1. CL = CAS (Read) Latency 2. Minimum clock rate @ max CL
1
(c)2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.
ADVANCE
128Mb: x32 DDR SDRAM
GENERAL DESCRIPTION
The 128Mb (x32) DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728- bits. It is internally configured as a quadbank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2nprefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM effectively consists of a single 2n-bit wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The 128Mb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, 8, or full page locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class I compatible.
NOTE: 1. The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. 2. Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise.
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
ADVANCE
128Mb: x32 DDR SDRAM
TABLE OF CONTENTS
Functional Block Diagram - 4 Meg x 32 ..................... Pin Descriptions .......................................................... 4 5 Write to Precharge - Uninterrupting ............. Write to Precharge - Interrupting .................. Write to Precharge - Odd, Interrupting ......... Precharge ................................................................ Power-Down ........................................................... Truth Table 2 (CKE) ...................................................... Truth Table 3 (Current State, Same Bank) ........................ Truth Table 4 (Current State, Different Bank) .................. Operating Conditions Absolute Maximum Ratings ....................................... DC Electrical Characteristics and Operating Conditions ............................................................... AC Input Operating Conditions ................................ Clock Input Operating Conditions ........................... DC Electrical Characteristics and Operating Conditions, 1.8V Option ....................................... AC Input Operating Conditions, 1.8V Option ......... Clock Input Operating Conditions, 1.8V Option .... Capacitance .................................................................. IDD Specifications and Conditions ................................ Electrical Characteristics and Recommended AC Operating Conditions ..................................... Notes ............................................................................. Derating Data Valid Window ..................................... Voltage and Timing Waveforms Impedance Match Output .................................... Reduced Output Drive Characteristics .............. Output Timing - tDQSQ and tQH ......................... Output Timing - tAC and tDQSCK ....................... Input Timing .......................................................... Input Voltage .......................................................... Initialize and Load Mode Registers ..................... Power-Down Mode ................................................ Auto Refresh Mode ................................................ Self Refresh Mode .................................................. Reads Bank Read - Without Auto Precharge ............ Bank Read - With Auto Precharge .................. Writes Bank Write - Without Auto Precharge ........... Bank Write - With Auto Precharge ................. Write - DM Operation ...................................... 100-pin TQFP dimensions .......................................... FBGA Package .............................................................. 32 33 34 35 35 36 37 39
Functional Description ............................................... 7 Initialization ........................................................... 7 Register Definition ................................................ 7 Mode Register ................................................... 7 Burst Length ................................................. 8 Burst Type .................................................... 9 Read Latency ............................................... 9 Operating Mode .......................................... 9 Extended Mode Register ................................. 10 DLL Enable/Disable .................................. 10 Commands ................................................................... Truth Table 1 (Commands) ............................................ Truth Table 1A (DM Operation) ...................................... Deselect ................................................................... No Operation (NOP) .............................................. Load Mode Register ............................................... Active ....................................................................... Read ....................................................................... Write ....................................................................... Precharge ................................................................ Auto Precharge ....................................................... Burst Terminate ..................................................... Auto Refresh ........................................................... Self Refresh ............................................................. Operation ..................................................................... Bank/Row Activation ............................................. Reads ....................................................................... Read Burst ......................................................... Consecutive Read Bursts ................................ Nonconsecutive Read Bursts ......................... Random Read Accesses ................................... Terminating a Read Burst ............................... Read to Write ..................................................... Read to Precharge ............................................ Writes ....................................................................... Write Burst ......................................................... Consecutive Write to Write ............................... Nonconsecutive Write to Write ........................ Random Write Cycles ...................................... Write to Read - Uninterrupting ...................... Write to Read - Interrupting ........................... Write to Read - Odd, Interrupting .................. 11 11 11 12 12 12 12 12 12 12 12 12 13 13 14 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 30 31
41 41 41 42 43 43 43 44 44 45 46 47 50 51 52 54 54 55 56 57 58 59 60 61 62 63 64 65 66
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
ADVANCE
128Mb: x32 DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM 4 Meg x 32
CKE CK# CK CS# WE# CAS# RAS#
COMMAND DECODE
CONTROL LOGIC BANK3 BANK2 BANK1
MODE REGISTERS
REFRESH 12 COUNTER
13 12
ROWADDRESS MUX
12
BANK0 ROWADDRESS LATCH & DECODER
4096
BANK0 MEMORY ARRAY (4096 x 256 x 64)
32 64 READ LATCH MUX 32 DQS GENERATOR CA0 32
CLK
DATA
DLL
SENSE AMPLIFIERS 8,192
DRVRS 1 DQ0 DQ31, DM0 DM3 DQS 4 MASK 4 4 4 8 32 64 32 32 32 32 RCVRS 4
2 A0-A11, BA0, BA1 ADDRESS REGISTER BANK CONTROL LOGIC
I/O GATING DM MASK LOGIC
CA0 64
DQS
14
2
256 (x64)
64
WRITE FIFO & DRIVERS clk out
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH 7
1
clk in DATA
8
CLK
INPUT REGISTERS
1
CA0
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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ADVANCE
128Mb: x32 DDR SDRAM
PIN DESCRIPTIONS
TQFP PIN NUMBERS 55, 54 SYMBOL CK, CK# TYPE Input DESCRIPTION Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A8) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A8 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A8 LOW, bank selected by BA0, BA1) or all banks (A8 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Data Input/Output: Data Input/Output: Data Input/Output: Data Input/Output: Data Strobe: Output with read data, input with write data. DQS is edge-aligned with read data, centered in write data. It is used to capture data.
53
CKE
Input
28
CS#
Input
27, 26, 25 23, 56, 24, 57
RAS#, CAS#, Input WE# DM0-DM3 Input
29, 30 31-34, 47-51, 45, 36, 37
BA0, BA1 A0-A11
Input Input
97, 98, 100, 1, 3, 4, 6, 7 DQ0-7 60, 61, 63, 64, 68, 69, 71, 72 DQ8-15 9, 10, 12, 13, 17, 18, 20, 21 DQ16-23 74, 75, 77, 78, 80, 81, 83, 84 DQ24-31 94 DQS
I/O I/O I/O I/O I/O
(continued on next page)
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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ADVANCE
128Mb: x32 DDR SDRAM
PIN DESCRIPTIONS (continued)
TQFP PIN NUMBERS SYMBOL TYPE - - DESCRIPTION No Connect: These pins should be left unconnected. Do Not Use: Must float to minimize noise. Reserved for Future Use No Connect: Not internally connected. Must Connect LOW (for compatibility with SGRAM devices). DQ Power Supply: +2.5V 0.125V. Isolated on the die for improved noise immunity. 1.8V option DQ Ground. Isolated on the die for improved noise immunity. Power Supply: +2.5V 0.125V. Ground. SSTL_2 reference voltage. 38, 39, 40, 41, 42, 43, 44 NC 87, 88, 90 91 DNU 93 NC/RFU 52 NC (MCL) 2, 8, 14, 22, 59, 67, 73, 79, 86, 95 5, 11, 19, 62, 70, 76, 82, 92, 99 15, 35, 65, 96 16, 46, 66, 85 58 VDDQ VSSQ VDD VSS VREF
Supply Supply Supply Supply Supply
NOTE: 1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins deemed to be of importance.
FBGA BALLOUT
1 A B C D E F G H J K L M DQS0 DQ4 DQ6 DQ7 2 DM0 VDDQ DQ5 VDDQ 3 VSSQ NC VSSQ VDD 4 DQ3 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS BA1 A0 5 DQ2 DQ1 VSSQ VSSQ 6 DQ0 7 8 9 10 VSSQ NC VSSQ VDD 11 DM3 12 DQS3
DQ31 DQ29 DQ28
VDDQ VDDQ DQ30 VDDQ VDD VSS VDD VSS VSSQ VSSQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ
3
VDDQ DQ27 DQ26 DQ25 VDDQ DQ24
DQ17 DQ16 VDDQ DQ19 DQ18 VDDQ DQS2 DM2 NC
VSS/1 VSS/1 VSS/1 VSS/1 VSS/1 VSS/1 VSS/1 VSS/1 VSS/1 VSS/1 VSS/1 VSS/1 VSS/1 VSS/1 VSS/1 VSS/1 VSS A10 A2 A1 VSS VDD A11 A3 VSS VDD A9 A4 VSS RFU A5 A6
VDDQ DQ15 DQ14 VDDQ DQ13 DQ12 NC DM1 DQS1
DQ21 DQ20 VDDQ DQ22 DQ23 VDDQ CAS# RAS# CS# WE# NC NC VDD NC BA0
VDDQ DQ11 DQ10 VDDQ VDD DQ9 NC CK# CKE DQ8 NC
DSF/MCL
VSS RFU A7
2
CK A8/AP
VREF
NOTE: 1. This package uses 4 DQS lines
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
ADVANCE
128Mb: x32 DDR SDRAM
FUNCTIONAL DESCRIPTION
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. The 128Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2nprefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Once the 200s delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) is recommended by JEDEC specification but is not required by the Micron device. Following these requirements, the DDR SDRAM is ready for normal operation once a value has been written in to the DRAM and it has been refreshed correctly. Read accesses to the DRAM prior to it being written in to the DRAM must be assumed to be unknown and unrepeatable.
REGISTER DEFINITION
MODE REGISTER The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 1. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A11 specify the operating mode.
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD and VDDQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VDDQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200s delay prior to applying an executable command.
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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ADVANCE
128Mb: x32 DDR SDRAM
Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Full page burst is supported in sequential mode only. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely se-
Table 1 Burst Definition
Order of Accesses Within a Burst Burst Length Starting Column Address A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 Cn+3, Cn+4... ...Cn-1, Cn... Cn, Cn-1, Cn-2 Cn-3, Cn-4... ...Cn+1, Cn... 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported
2 A1 0 0 1 1 A2 A1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
4
Figure 1 Mode Register Definition
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
8
876543210 13 12 11 10 9 Operating Mode 0* 0* CAS Latency BT Burst Length
Mode Register (Mx)
Full Page (256)
n = A0 - A7, A0 = 0
* M13 and M12 (BA0 and BA1) must be 0, 0 to select the base mode register (vs. the extended mode register).
Burst Length M2 M1 M0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M3 = 0 Reserved 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved
n = A0 - A7, A0 = 1
Not supported
NOTE:
M3 0 1
Burst Type Sequential Interleaved
M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 3 4 5 Reserved Reserved
1. For a burst length of two, A1-A7 select the block of two burst; A0 selects the starting column within the block. 2. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block. 3. For a burst length of eight, A3-A7 select the block of eight burst; A0-A2 select the starting column within the block. 4. For a full-page burst, the full row is selected and A0-A7 select the starting column. A0 also selects the direction of the burst (incrementing if A0 = 0, decrementing if A0 = 1). 5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
M11 M10 M9 M8 M7 0 0 0 0 0 0 0 1 0 0 -
M6-M0 Valid Valid -
Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
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128Mb: x32 DDR SDRAM
lected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.
Table 2 CAS Latency
ALLOWABLE OPERATING FREQUENCY (MHz) SPEED -33 -4 -5 CL = 5 300 - - CL = 4 250 250 - CL = 3 - 200 200
Figure 2 CAS Latency
T0 CK# CK COMMAND T1 T2 T2n T3 T3n
READ
NOP
NOP
NOP
CL = 2 DQS
Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, 3, 4 or 5 clocks, as shown in Figure 2. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 2 indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A11 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER
DQ
CK# CK COMMAND
T0
T1
T2
T3
T3n
READ
NOP
NOP
NOP
CL = 3 DQS
DQ Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ TRANSITIONING DATA DON'T CARE
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
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128Mb: x32 DDR SDRAM
SET command with bits A7 and A9-A11 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A11 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. EXTENDED MODE REGISTER The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable. These functions are controlled via the bits shown in Figure 3. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. Although not required by the Micron device, the enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. Although not required by Micron, JEDEC recommends a LOAD MODE REGISTER command be issued to the mode register (BA0/BA1 both LOW) to reset the DLL. Output Drive Strength The reduced drive strength for all outputs are specified to be SSTL2, Class I. The x32 supports both reduced and matched impedance drive strengths. This option is intended for the support of the lighter load and/or point-topoint environments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class I drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. The DLL must be reset any time the clock frequency is changed followed by 200 clock cycles.
Figure 3 Extended Mode Register Definition
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 2 11 01 RFU
8
7
6
DS
5
4
RFU
3 2
2
1
0
DS DLL
Extended Mode Register (Ex)
E0 0 1 E6 0 0 1 1 E1 0 1 0 1
DLL Enable Disable Drive Strength Reserved Half Reserved Matched
NOTE: 1. E13 and E12 (BA0 and BA1) must be 1, 0 to select the Extended Mode Register (vs. the base Mode Register). 2. Reserved for future use. Set values to 0.
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Commands
Truth Table 1 provides a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables appear following the Operation section; these tables provide current state/next state information.
TRUTH TABLE 1 - COMMANDS
(Note: 1) NAME (FUNCTION) DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER CS# RAS# CAS# WE# H L L L L L L L L X H L H H H L L L X H H L L H H L L X H H H L L L H L ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code NOTES 9 9 3 4 4 8 5 6, 7 2
TRUTH TABLE 1A - DM OPERATION
NAME (FUNCTION) Write Enable Write Inhibit DM L H DQs Valid X NOTES 10 10
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 provide the opcode to be written to the selected mode register. 3. BA0-BA1 provide bank address and A0-A11provide row address. 4. BA0-BA1 provide bank address; A0-A7provide column address; A8 HIGH enables the auto precharge feature (nonpersistent), and A8 LOW disables the auto precharge feature. 5. A8 LOW: BA0-BA1 determine which bank is precharged. A8 HIGH: all banks are precharged and BA0-BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask write data; provided coincident with the corresponding data.
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DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (CS# LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode registers are loaded via inputs A0-A11. See mode register descriptions in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. AUTO PRECHARGE Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A8 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This "earliest valid stage" is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRASmin, as described for each burst type in the Operation section of this data sheet. The user must not issue another command to the same bank until the precharge time (tRP) is completed. BURST TERMINATE The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet.
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AUTO REFRESH AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS#-BEFORERAS# (CBR) REFRESH in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during an AUTO REFRESH command. The 128 Mb x32 DDR SDRAM requires AUTO REFRESH cycles at an average interval of 7.8s (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 18 x 7.8s (140.4s). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates. This is a JEDEC requirement that is NOT required for Micron's 128Mb x32 DDR device. SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are "Don't Care" during SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
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Operations
BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated, as shown in Figure 4. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 15ns with a 166 MHz clock (6ns period) results in 2.5 clocks rounded to 3. This is reflected in Figure 5, which covers any case where 2 < tRCD (MIN)/tCK 3. (Figure 5 also shows the same case for tRCD; the same procedure is used to convert other specification limits from time units to clock cycles). A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
Figure 4 Activating a Specific Row in a Specific Bank
CK# CK CKE CS# HIGH
RAS#
CAS#
WE#
A0-A11
RA
BA0,1
BA
RA = Row Address BA = Bank Address
Figure 5 Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK 3
T0 CK# CK COMMAND
ACT NOP NOP ACT NOP NOP RD/WR NOP
T1
T2
T3
T4
T5
T6
T7
A0-A11
Row
Row
Col
BA0, BA1
Bank x
Bank y
Bank y
tRRD
tRCD
DON T CARE
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READs READ bursts are initiated with a READ command, as shown in Figure 6. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of CK and CK#). Figure 7 shows general timing for each possible CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last dataout element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A detailed explanation of tDQSQ (valid dataout skew), tQH (data-out window hold), the valid data window are depicted in Figure 27. A detailed explanation of tDQSCK (DQS transition skew to CK) and tAC (data-out transition skew to CK) is depicted in Figure 28. Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles after the first READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 8. A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive read data is shown for illustration in Figure 9. Full-speed random read accesses within a page (or pages) can be performed as shown in Figure 10.
Figure 6 READ Command
CK# CK CKE CS# HIGH
RAS# CAS#
WE# A0-A7 A9, A10, A11
EN AP CA
A8
DIS AP
BA0,1
BA
CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge DON T CARE
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Figure 7 READ Burst
T0 CK# CK COMMAND T1 T2 T2n T3 T3n T4 T5
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank a, Col n
CL = 2 DQS
DQ
DO n
T0 CK# CK COMMAND
T1
T2
T3
T3n
T4
T5
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank a, Col n
CL = 3 DQS
DQ
DO n
DON T CARE
TRANSITIONING DATA
NOTE: 1. DO n = data-out from column n. 2. Burst length = 4. 3. Three subsequent elements of data-out appear in the programmed order following DO n. 4. Shown with nominal tAC, tDQSCK, and tDQSQ.
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Figure 8 Consecutive READ Bursts
T0 CK# CK COMMAND T1 T2 T2n T3 T3n T4 T4n T5 T5n
READ
NOP
READ
NOP
NOP
NOP
ADDRESS
Bank, Col n
Bank, Col b
CL = 2 DQS
DQ
DO n
DO b
T0 CK# CK COMMAND
T1
T2
T3
T3n
T4
T4n
T5
T5n
READ
NOP
READ
NOP
NOP
NOP
ADDRESS
Bank, Col n
Bank, Col b
CL = 3 DQS
DQ
DO n
DO b
DON T CARE NOTE: 1. 2. 3. 4. 5. 6.
TRANSITIONING DATA
DO n (or b) = data-out from column n (or column b). Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first). Three subsequent elements of data-out appear in the programmed order following DO n. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b. Shown with nominal tAC, tDQSCK, and tDQSQ. Example applies only when READ commands are issued to same device.
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Figure 9 Nonconsecutive READ Bursts
T0 CK# CK COMMAND T1 T2 T2n T3 T3n T4 T5 T5n T6
READ
NOP
NOP
READ
NOP
NOP
NOP
ADDRESS
Bank, Col n
Bank, Col b
CL = 2 DQS
DQ
DO n
DO b
T0 CK# CK COMMAND
T1
T2
T3
T3n
T4
T5
T5n
T6
READ
NOP
NOP
READ
NOP
NOP
NOP
ADDRESS
Bank, Col n
Bank, Col b
CL = 3 DQS
DQ
DO n
DO b
DON T CARE NOTE: 1. 2. 3. 4. 5. 6.
TRANSITIONING DATA
DO n (or b) = data-out from column n (or column b). Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first). Three subsequent elements of data-out appear in the programmed order following DO n. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b. Shown with nominal tAC, tDQSCK, and tDQSQ. Example applies when READ commands are issued to different devices or nonconsecutive READs.
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Figure 10 Random READ Accesses
T0 CK# CK COMMAND T1 T2 T2n T3 T3n T4 T4n T5 T5n
READ
READ
READ
READ
NOP
NOP
ADDRESS
Bank, Col n
Bank, Col x
Bank, Col b
Bank, Col g
CL = 2 DQS
DQ
DO n
DO n'
DO x
DO x'
DO b
DO b'
DO g
T0 CK# CK COMMAND
T1
T2
T3
T3n
T4
T4n
T5
T5n
READ
READ
READ
READ
NOP
NOP
ADDRESS
Bank, Col n
Bank, Col x
Bank, Col b
Bank, Col g
CL = 3 DQS
DQ
DO n
DO n'
DO x
DO x'
DO b
DO b'
DON T CARE NOTE: 1. 2. 3. 4. 5.
TRANSITIONING DATA
DO n (or x or b or g) = data-out from column n (or column x or column b or column g). Burst length = 2 or 4 or 8 (if 4 or 8, the following burst interrupts the previous). n' or x' or b' or g' indicates the next data-out following DO n or DO x or DO b or DO g, respectively. READs are to an active row in any bank. Shown with nominal tAC, tDQSCK, and tDQSQ.
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READs (continued) Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 11. The BURST TERMINATE latency is equal to the READ (CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure 12. The tDQSS (MIN) case is shown; the tDQSS (MAX) case has a longer bus idle time. (tDQSS [MIN] and tDQSS [MAX] are defined in the section on WRITEs.) A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto precharge was not activated. The PRECHARGE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 13. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data elements.
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Figure 11 Terminating a READ Burst
T0 CK# CK COMMAND
BST5
T1
T2
T2n
T3
T4
T5
READ
NOP
NOP
NOP
NOP
ADDRESS
Bank a, Col n
CL = 2 DQS
DQ
DO n
T0 CK# CK COMMAND
T1
T2
T3
T4
T5
READ
BST5
NOP
NOP
NOP
NOP
ADDRESS
Bank a, Col n
CL = 3 DQS
DQ
DO n
DON T CARE NOTE: 1. 2. 3. 4. 5.
TRANSITIONING DATA
DO n = data-out from column n. Burst length = 4. Subsequent element of data-out appears in the programmed order following DO n. Shown with nominal tAC, tDQSCK, and tDQSQ. BST = BURST TERMINATE command.
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Figure 12 READ to WRITE
T0 CK# CK COMMAND
BST7
T1
T2
T2n
T3
T4
T4n
T5
T5n
READ
NOP
WRITE
NOP
NOP
ADDRESS
Bank, Col n
Bank, Col b
tDQSS
CL = 2 DQS DQ DM
DO n
(MIN)
DI b
T0 CK# CK COMMAND
T1
T2
T3
T4
T5
T5n
READ
BST7
NOP
NOP
WRITE
NOP
ADDRESS
Bank a, Col n
Bank, Col b
tDQSS
CL = 3 DQS DQ DM
DO n
(MIN)
DI b
DI b
DON T CARE
TRANSITIONING DATA
NOTE: 1. DO n = data-out from column n. 2. DI b = data-in from column b. 3. Burst length = 4 in the cases shown (applies for bursts of 8 and full page as well; if the burst length is 2, the BST command shown can be NOP). 4. One subsequent element of data-out appears in the programmed order following DO n. 5. Data-in elements are applied following DI b in the programmed order. 6. Shown with nominal tAC, tDQSCK, and tDQSQ. 7. BST = BURST TERMINATE command.
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Figure 13 READ to PRECHARGE
T0 CK# CK COMMAND6 T1 T2 T2n T3 T3n T4 T5
READ
NOP
PRE
NOP
NOP
ACT
ADDRESS
Bank a, Col n
Bank a, (a or all)
Bank a, Row
CL = 2 DQS
tRP
DQ
DO n
T0 CK# CK COMMAND6
T1
T2
T3
T3n
T4
T5
T6
READ
NOP
PRE
NOP
NOP
ACT
NOP
ADDRESS
Bank a, Col n
Bank a, (a or all)
Bank a, Row
CL = 3 DQS
tRP
DQ
DO n
DON T CARE NOTE: 1. 2. 3. 4. 5. 6.
TRANSITIONING DATA
DO n = data-out from column n. Burst length = 4, or an interrupted burst of 8 or full page. Three subsequent elements of data-out appear in the programmed order following DO n. Shown with nominal tAC, tDQSCK, and tDQSQ. READ to PRECHARGE equals two clocks, which allows two data pairs of data-out. PRE = PRECHARGE command; ACT = ACTIVE command.
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 14. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble. The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one clock cycle). All of the WRITE diagrams show the nominal case, and where the two extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Figure 15 shows the nominal case and the extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored. Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any positive edge of clock following the previous WRITE command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued x cycles after the first WRITE command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). Figure 16 shows concatenated bursts of 4. An example of nonconsecutive WRITEs is shown in Figure 17. Full-speed random write accesses within a page or pages can be performed as shown in Figure 18. Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without truncating the WRITE burst, tWTR should be met as shown in Figure 19. Data for any WRITE burst may be truncated by a subsequent READ command, as shown in Figure 20. Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in should be masked with DM as shown in Figure 21.
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Figure 14 WRITE Command
CK# CK CKE CS# RAS# CAS# HIGH
WE#
A0-A7 A9, A10, A11
CA
EN AP
A8
DIS AP
BA0,1
BA
CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge DON T CARE
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, tWR should be met as shown in Figure 22. Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figures 23 and 24. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data-in should be masked with DM as shown in Figures 23 and 24. After the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
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Figure 15 WRITE Burst
T0 CK# CK COMMAND
WRITE NOP NOP NOP
T1
T2
T2n
T3
ADDRESS
tDQSS (NOM)
Bank a, Col b
tDQSS
DQS DQ DM
DI b
tDQSS (MIN)
tDQSS
DQS DQ DM
DI b
tDQSS (MAX)
tDQSS
DQS DQ DM
DI b
DON T CARE
TRANSITIONING DATA
NOTE: 1. DI b = data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. An uninterrupted burst of 4 is shown. 4. A8 is LOW with the WRITE command (auto precharge is disabled).
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Figure 16 Consecutive WRITE to WRITE
T0 CK# CK COMMAND T1 T2 T2n T3 T3n T4 T4n T5
WRITE
NOP
WRITE
NOP
NOP
NOP
ADDRESS
Bank, Col b tDQSS (NOM)
Bank, Col n
DQS DQ DM
DI b DI n
DON T CARE NOTE: 1. 2. 3. 4. 5.
TRANSITIONING DATA
DI b, etc. = data-in for column b, etc. Three subsequent elements of data-in are applied in the programmed order following DI b. Three subsequent elements of data-in are applied in the programmed order following DI n. An uninterrupted burst of 4 is shown. Each WRITE command may be to any bank.
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Figure 17 Nonconsecutive WRITE to WRITE
T0 CK# CK COMMAND T1 T2 T2n T3 T4 T4n T5 T5n
WRITE
NOP
NOP
WRITE
NOP
NOP
ADDRESS
Bank, Col b tDQSS (NOM)
Bank, Col n
DQS DQ DM
DI b DI n
DON T CARE NOTE: 1. 2. 3. 4. 5.
TRANSITIONING DATA
DI b, etc. = data-in for column b, etc. Three subsequent elements of data-in are applied in the programmed order following DI b. Three subsequent elements of data-in are applied in the programmed order following DI n. An uninterrupted burst of 4 is shown. Each WRITE command may be to any bank.
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Figure 18 Random WRITE Cycles
T0 CK# CK COMMAND T1 T1n T2 T2n T3 T3n T4 T4n T5 T5n
WRITE
WRITE
WRITE
WRITE
WRITE
NOP
ADDRESS
Bank, Col b
Bank, Col x
Bank, Col n
Bank, Col a
Bank, Col g
tDQSS (NOM)
DQS DQ DM
DI b DI b' DI x DI x' DI n DI n' DI a DI a' DI g DI g'
DON'T CARE NOTE: 1. 2. 3. 4.
TRANSITIONING DATA
DI b, etc. = data-in for column b, etc. b', etc. = the next data-in following DI b, etc., according to the programmed burst order. Programmed burst length = 2. For 4, or 8 the burst is terminated. Each WRITE command may be to any bank.
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Figure 19 WRITE to READ - Uninterrupting
T0 CK# CK COMMAND T1 T1n T2 T2n T3 T4 T5 T6 T6n
WRITE
NOP
NOP
NOP tWTR
READ
NOP
NOP
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
Bank a, Col n
CL = 2
DQS DQ DM
DI b DI n
tDQSS (MIN)
tDQSS
CL = 2
DQS DQ DM
DI b DI n
tDQSS (MAX)
tDQSS
CL = 2
DQS DQ DM
DI b DI n
DON T CARE NOTE: 1. 2. 3. 4. 5.
TRANSITIONING DATA
DI b = data-in for column b. Three subsequent elements of data-in are applied in the programmed order following DI b. An uninterrupted burst of 4 is shown. tWTR is referenced from the first positive CK edge after the last data-in pair. The READ and WRITE commands are to the same bank. However, the READ and WRITE commands may be to different devices, in which case tWTR is not required and the READ command could be applied earlier. 6. A8 is LOW with the WRITE command (auto precharge is disabled).
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Figure 20 WRITE to READ - Interrupting
T0 CK# CK COMMAND T1 T1n T2 T2n T3 T4 T5 T5n T6 T6n
WRITE
NOP
NOP tWTR
READ
NOP
NOP
NOP
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
Bank a, Col n
CL = 2
DQS DQ DM
DI b DI n
tDQSS (MIN)
tDQSS
CL = 2
DQS DQ DM
DI b DI n
tDQSS (MAX)
tDQSS
CL = 2
DQS DQ DM
DI b DI n
DON T CARE NOTE: 1. 2. 3. 4. 5. 6. 7.
TRANSITIONING DATA
DI b = data-in for column b. An interrupted burst of 4 or 8 is shown; two data elements are written. One subsequent element of data-in is applied in the programmed order following DI b. tWTR is referenced from the first positive CK edge after the last data-in pair. A8 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T2 and T2n (nominal case) to register DM. If the burst of 8 was used, DM would not be required at T3-T4n because the READ command would mask the last two data elements.
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Figure 21 WRITE to READ - Odd Number of Data, Interrupting
T0 CK# CK COMMAND T1 T1n T2 T2n T3 T4 T5 T5n T6 T6n
WRITE
NOP
NOP tWTR
READ
NOP
NOP
NOP
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
Bank a, Col n
CL = 2
DQS DQ DM
DI b DI n
tDQSS (MIN)
tDQSS
CL = 2
DQS DQ DM
DI b DI n
tDQSS (MAX)
tDQSS
CL = 2
DQS DQ DM
DI b DI n
DON T CARE NOTE: 1. 2. 3. 4. 5. 6.
TRANSITIONING DATA
DI b = data-in for column b. An interrupted burst of 4 is shown; one data element is written. tWTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements). A8 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T1n, T2, and T2n (nominal case) to register DM. If the burst of 8 was used, DM would not be required at T3-T4n because the READ command would mask the last four data elements.
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Figure 22 WRITE to PRECHARGE - Uninterrupting
T0 CK# CK COMMAND
PRE7 tRP Bank, (a or all)
T1
T1n
T2
T2n
T3
T4
T5
T6
WRITE
NOP
NOP
NOP tWR
NOP
NOP
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
DQS DQ DM
DI b
tDQSS (MIN)
tDQSS
DQS DQ DM
DI b
tDQSS (MAX)
tDQSS
DQS DQ DM
DI b
DON T CARE NOTE: 1. 2. 3. 4. 5.
TRANSITIONING DATA
DI b = data-in for column b. Three subsequent elements of data-in are applied in the programmed order following DI b. An uninterrupted burst of 4 is shown. tWR is referenced from the first positive CK edge after the last data-in pair. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE and WRITE commands may be to different devices, in which case tWR is not required and the PRECHARGE command could be applied earlier. 6. A8 is LOW with the WRITE command (auto precharge is disabled). 7. PRE = PRECHARGE command.
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Figure 23 WRITE to Precharge - Interrupting
T0 CK# CK COMMAND
PRE9
T1
T1n
T2
T2n
T3
T4
T5
T6
WRITE
NOP
NOP tWR
NOP
NOP tRP
NOP
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
Bank, (a or all)
DQS DQ DM
DI b
tDQSS (MIN)
tDQSS
DQS DQ DM
DI b
tDQSS (MAX)
tDQSS
DQS DQ DM
DI b
DON T CARE NOTE: 1. 2. 3. 4. 5. 6. 7. 8.
TRANSITIONING DATA
DI b = data-in for column b. Subsequent element of data-in is applied in the programmed order following DI b. An interrupted burst of 4 is shown; two data elements are written. tWR is referenced from the first positive CK edge after the last data-in pair. The PRECHARGE and WRITE commands are to the same bank. A8 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T2 and T2n (nominal case) to register DM. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE command would mask the last two data elements. 9. PRE = PRECHARGE command.
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Figure 24 WRITE to PRECHARGE - Odd Number of Data, Interrupting
T0 CK# CK COMMAND
PRE9
T1
T1n
T2
T2n
T3
T4
T5
T6
WRITE
NOP
NOP tWR
NOP
NOP tRP
NOP
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
Bank, (a or all)
DQS DQ DM
DI b
tDQSS (MIN)
tDQSS
DQS DQ DM
DI b
tDQSS (MAX)
tDQSS
DQS DQ DM
DI b
DON T CARE NOTE: 1. 2. 3. 4. 5. 6. 7. 8.
TRANSITIONING DATA
DI b = data-in for column b. Subsequent element of data-in is applied in the programmed order following DI b. An interrupted burst of 4 is shown; one data elements are written. tWR is referenced from the first positive CK edge after the last data-in pair. The PRECHARGE and WRITE commands are to the same bank. A8 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T1n, T2, and T2n (nominal case) to register DM. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE command would mask the last two data elements. 9. PRE = PRECHARGE command.
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PRECHARGE The PRECHARGE command (Figure 25) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. POWER-DOWN (CKE NOT ACTIVE) Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress: from the issuing of a READ or WRITE command until completion of the burst. For READs, a burst completion is defined when the Read Postamble is satisfied; For WRITEs, a burst completion is defined when the Write Postamble is satisfied. Power-down (Figure 26) is entered when CKE is registered LOW. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK# and CKE. For maximum power savings, the user has the option of disabling the DLL prior to entering power-down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles (approximately 2s) must occur before a READ command can be issued. However, powerdown duration is limited by the refresh requirements of the device, so in most applications, the self-refresh mode is preferred over the DLL-disabled power-down mode. While in power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR SDRAM, while all other input signals are "Don't Care." The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later.
Figure 25 PRECHARGE Command
CK# CK CKE CS# HIGH
RAS#
CAS#
WE#
A0-A7, A9-A11
ALL BANKS
A8
ONE BANK
BA0,1
BA
BA = Bank Address (if A8 is LOW; otherwise Don t Care )
Figure 26 Power-Down
T0 CK# CK
tIS
T1
T2 ( (
Ta0
Ta1
Ta2
)) (( ))
tIS
CKE
(( ))
COMMAND
VALID
NOP
(( )) (( ))
NOP
NOP
VALID
No READ/WRITE access in progress
Enter power-down mode
Exit power-down mode DON'T CARE
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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TRUTH TABLE 2 - CKE
(Notes: 1-4) CKEn-1 CKEn L L H L H L CURRENT STATE Power-Down Self Refresh Power-Down Self Refresh All Banks Idle Bank(s) Active All Banks Idle H
NOTE: 1. 2. 3. 4. 5.
COMMAND n X X DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP AUTO REFRESH See Truth Table 3
ACTION n Maintain Power-Down Maintain Self Refresh Exit Power-Down Exit Self Refresh Precharge Power-Down Entry Active Power-Down Entry Self Refresh Entry
NOTES
5
H
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge n. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. All states and sequences not shown are illegal or reserved. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 200 clock cycles is needed before applying a READ command for the DLL to lock.
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TRUTH TABLE 3 - CURRENT STATE BANK n - COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any H L L Idle L L L Row Active Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled)
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the "row active" state. Read w/AutoPrecharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/AutoPrecharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
COMMAND/ACTION DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) ACTIVE (select and activate row) AUTO REFRESH LOAD MODE REGISTER READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE (truncate READ burst, start PRECHARGE) BURST TERMINATE READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE (truncate WRITE burst, start PRECHARGE)
NOTES
X H L L L H H L H H L H H H L
X H H L L L L H L L H H L L H
X H H H L H L L H L L L H L L
7 7 10 10 8 10 10, 12 8 9 10, 11 10 8, 11
L L L L L L L L L
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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NOTE (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the DDR SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. All states and sequences not shown are illegal or reserved. Not bank-specific; requires that all banks are idle, and bursts are not in progress. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Requires appropriate DM masking. 12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command. 6. 7. 8. 9. 10.
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TRUTH TABLE 4 - CURRENT STATE BANK n - COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle Row Activating, Active, or Precharging Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled) Read (With AutoPrecharge) Write (With AutoPrecharge) H L X L L L L L L L L L L L L L L L L L L L L X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H X H X H H L L H H L L H H L L H H L L H H L L COMMAND/ACTION DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE 7 7 7 7, 9 7, 8 7 7 7, 9 7 7 NOTES
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
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NOTE (continued): 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See following text Write with Auto Precharge Enabled: See following text 3a. The read with auto precharge enabled or WRITE with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends,with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. This device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. In either case, all other related limitations apply (e.g., contention between read data and write data must be avoided). 3b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is summarized below. From Command WRITE w/AP To Command READ or READ w/AP WRITE or WRITE w/AP PRECHARGE ACTIVE READ or READ w/AP WRITE or WRITE w/AP PRECHARGE ACTIVE Minimum delay (with concurrent auto precharge) [1 + (BL/2)] tCK + tWTR (BL/2) tCK 1 tCK 1 tCK (BL/2) * tCK [CLRU + (BL/2)] tCK 1 tCK 1 tCK
READ w/AP
CLRU = CAS Latency (CL) rounded up to the next integer BL=BustLength 4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. Requires appropriate DM masking. 9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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128Mb: x32 DDR SDRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to VSS ............................................ -1V to +3.6V Voltage on VDDQ Supply Relative to VSS ............................................ -1V to +3.6V Voltage on VREF and Inputs Relative to VSS ............................................ -1V to +3.6V Voltage on I/O Pins Relative to VSS ............................... -0.5V to VDDQ +0.5V Operating Temperature, TA (ambient) ... 0C to +70C Storage Temperature (plastic) ............ -55C to +150C Power Dissipation ........................................................ 2W Short Circuit Output Current ................................. 50mA *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1-5, 16, 40; notes appear on pages 46-49) (0C TA +70C; VDD = +2.5V 0.125V, VDDQ = +2.5V 0.125V) PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Clock Input Voltage Level; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK# INPUT LEAKAGE CURRENT Any input 0V VIN VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS: Impedance Match High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF,maximum VTT) OUTPUT LEVELS: Reduced drive option High Current (VOUT = VDDQ-0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF,maximum VTT) SYMBOL VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN VID VIX II IOZ MIN 2.375 2.375 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 1.15 -2 -5 MAX 2.625 2.625 0.51 x VDDQ VREF + 0.04 VDD + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 1.35 2 5 UNITS NOTES V V V V V V V V V A A 8 9 40 6 7 28 28
IOH IOL IOHR IOLR
-4 4 -9 9
- - - -
mA mA mA mA
37, 39
38, 39
AC INPUT OPERATING CONDITIONS
(Notes: 1-5, 14, 16, 40; notes appear on pages 46-49) (0C TA +70C; VDD = +2.5V 0.125V, VDDQ = +2.5V 0.125V) PARAMETER/CONDITION Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK#
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
SYMBOL VIH(AC) VIL(AC) VID(AC) VIX(AC)
MIN VREF + 0.310 - 0.7 0.5xVDDQ-0.2
MAX - VREF - 0.310 VDDQ + 0.6 0.5xVDDQ+0.2
UNITS V V V V
NOTES 14, 28, 39 14, 28, 39 8 9
41
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CLOCK INPUT OPERATING CONDITIONS
(Notes: 1-5, 15, 16, 30; notes appear on pages 46-49) (0C TA + 70C; VDD = +2.5V 0.125V, VDDQ = +2.5V 0.125V) PARAMETER/CONDITION Clock Input Mid-Point Voltage; CK and CK# Clock Input Voltage Level; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK# SYMBOL VMP(DC) VIN(DC) VID(DC) VID(AC) VIX(AC) MIN 1.15 -0.3 0.36 0.7 0.5 x VDDQ - 0.2 MAX 1.35 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 x VDDQ + 0.2 UNITS V V V V V NOTES 6, 9 6 6, 8 8 9
Figure 27 SSTL_2 Clock Input
2.80V
CK# Maximum Clock Level
5
1.45V 1.25V 1.05V
X
VMP (DC)
1
VIX (AC)
2
VID (DC) 4 VID (AC)
3
X
CK
- 0.30V
Minimum Clock Level
5
NOTE:
1. This provides a minimum of 1.15V to a maximum of 1.35V, and is always half of VDDQ. 2. CK and CK# must cross in this region. 3. CK and CK# must meet at least VID(DC) min when static and is centered around VMP(DC) 4. CK and CK# must have a minimum 700mv peak to peak swing. 5. CK or CK# may not be more positive than VDDQ + 0.3V or more negative than Vss - 0.3V. 6. For AC operation, all DC clock requirements must also be satisfied. 7. Numbers in diagram reflect nominal values.
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS FOR 1.8V OPTION
(Notes: 1-5, 16, 40; notes appear on pages 46-49) (0C TA +70C; VDD = +2.5V 0.125V, VDDQ = +1.8V 0.125V) PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Clock Input Voltage Level; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK# INPUT LEAKAGE CURRENT Any input 0V VIN VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS: Impedance Match High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF,maximum VTT) OUTPUT LEVELS: Reduced drive option High Current (VOUT = VDDQ-0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF,maximum VTT) SYMBOL VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN VID VIX II IOZ MIN 2.375 1.67 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 0.8 -2 -5 MAX 2.625 1.925 0.51 x VDDQ VREF + 0.04 VDD + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 1.0 2 5 UNITS NOTES V V V V V V V V V A A 8 9 40 6 7 28 28
IOH IOL IOHR IOLR
-4 4 -9 9
- - - -
mA mA mA mA
37, 39
38, 39
AC INPUT OPERATING CONDITIONS FOR 1.8V OPTION
(Notes: 1-5, 14, 16, 40; notes appear on pages 46-49) (0C TA +70C; VDD = +2.5V 0.125V, VDDQ = +1.8V 0.125V) PARAMETER/CONDITION Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK# SYMBOL VIH(AC) VIL(AC) VID(AC) VIX(AC) MIN VREF + 0.310 - 0.7 0.5xVDDQ-0.2 MAX - VREF - 0.310 VDDQ + 0.6 0.5xVDDQ+0.2 UNITS V V V V NOTES 14, 28, 39 14, 28, 39 8 9
CLOCK INPUT OPERATING CONDITIONS FOR 1.8V OPTION
(Notes: 1-5, 15, 16, 30; notes appear on pages 46-49) (0C TA + 70C; VDD = +2.5V 0.125V, VDDQ = +1.8V 0.125V) PARAMETER/CONDITION Clock Input Mid-Point Voltage; CK and CK# Clock Input Voltage Level; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK# SYMBOL VMP(DC) VIN(DC) VID(DC) VID(AC) VIX(AC) MIN 0.8 -0.3 0.36 0.7 0.5 x VDDQ - 0.2 MAX 1.0 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 x VDDQ + 0.2 UNITS V V V V V NOTES 6, 9 6 6, 8 8 9
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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CAPACITANCE
(Note: 13) PARAMETER Delta Input/Output Capacitance: DQs, DQS, DM Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE SYMBOL DCIO DCI1 DCI2 CIO CI1 CI2 CI3 TQFP Package MIN - - - 4.0 2.0 2.0 2.0 MAX 0.50 0.50 0.25 5.0 3.0 3.0 3.0 FBGA Package MIN - - - 3.0 2.0 2.0 2.0 MAX 0.50 0.50 0.50 5.0 3.0 3.0 3.0 UNITS NOTES pF pF pF pF pF pF pF 24 29 29
IDD SPECIFICATIONS AND CONDITIONS
(Notes: 1-5, 10, 12, 14, 40; notes on pages 46-49) (0C TA +70C; VDDQ = +2.5V 0.125V, VDD = +2.5V 0.125V) MAX PARAMETER/CONDITION OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cyle; Address and control inputs changing once per clock cycle; OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK MIN; CKE = LOW; IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle AUTO REFRESH CURRENT SELF REFRESH CURRENT: CKE 0.2V
tRFC tRFC
SYMBOL IDD0
-33
-4
-5
UNITS NOTES mA 22
TBD
TBD
TBD
IDD1
TBD
TBD
TBD
mA
22
IDD2P IDD2N
TBD TBD
TBD TBD
TBD TBD
mA mA
32
IDD3P IDD3N
TBD TBD
TBD TBD
TBD TBD
mA mA
32 22
IDD4R
TBD
TBD
TBD
mA
IDD4W
TBD
TBD
TBD
mA
= tRFC (MIN) = 7.8s
IDD5a IDD5b IDD6
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
mA mA mA
22 27 11
Standard
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1-5,14-17,33,40; notes on pages 46-49) (0C TA +70C; VDDQ = +2.5V 0.125V, VDD = +2.5V 0.125V)
AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time -33 -4 -5 SYMBOL MIN MAX MIN MAX MIN MAX tAC -0.6 +0.6 -0.7 +0.7 -0.7 +0.7 tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK(5) 3.3 8 tCK(4) 4 8 4 8 tCK(3) 5 8 5 8 tCK(2) 8 8 tDAL 6 6 6 tDH 0.45 0.45 0.45 tDS 0.45 0.45 0.45 tDIPW 1.25 1.25 1.25 tDQSCK -0.6 +0.6 -0.7 +0.7 -0.7 +0.7 tDQSH 0.4 0.4 0.4 tDQSL 0.4 0.4 0.4 tDQSQ 0.4 0.45 0.45 tDQSS 0.8 1.2 0.8 1.2 0.8 1.2 tDSS 0.25 0.25 0.25 tDSH 0.25 0.25 0.25 tHP tCH,tCL tCH,tCL tCH,tCL tHZ -0.5 -0.5 -0.5 tLZ -0.5 -0.5 -0.5 tIH 0.9 0.9 0.9 t IS 0.9 0.9 0.9 tIPW 2 2 2 tMRD 2 2 2 tPDIX 1 tCK 1 tCK 1 tCK
tQH tRAS tRC tRFC tREFC tREFI tRCDR tRCDW tRP tRPRE tRPST tRRD tVTD tWPRE tWPRES tWPST tWR tWTR tXSNR tXSRD
CL = 5 CL = 4 CL = 3 CL = 2 Auto precharge write recovery plus precharge time DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time Address and control input setup time Address and control input pulse width LOAD MODE REGISTER command cycle time Power-Down Recovery Time DQ-DQS hold, DQS to first DQ to go non-valid, per access ACTIVE to PRECHARGE command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period REFRESH to REFRESH command interval Average periodic refresh interval ACTIVE to READ delay ACTIVE to WRITE delay PRECHARGE command period DQS Read preamble DQS Read postamble ACTIVE bank a to ACTIVE bank b command Terminating voltage delay to VDD DQS Write preamble DQS Write preamble setup time DQS Write postamble Write recovery time Internal WRITE to READ command delay Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command Data valid output window
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
UNITS ns tCK tCK ns ns ns ns tCK ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns tCK ns ns ns ns ns s s ns ns ns tCK tCK tCK ns tCK ns tCK tCK tCK ns tCK ns
NOTES 30 30
26, 31 26, 31 31
25, 26
34 18 18 14 14
25, 26 34 25, 26 34 35
+ t IS tHP
+ t IS tHP
+ t IS tHP
-0.4ns -0.4ns -0.4ns 40 120,000 40 120,000 40 120,000 56 56 58 62 62 62 NA NA NA 7.8 7.8 7.8 16 16 20 10 10 10 16 16 20 0.9 1.1 0.9 1.1 0.9 1.1 0.4 0.6 0.4 0.6 0.4 0.6 3 3 2 0.25 0 0.4 0.6 3 1 66 200 tQH-tDQSQ 0.25 0 0.4 0.6 3 1 66 200 tQH-tDQSQ 0.25 0 0.4 0.6 2 1 66 200 tQH-tDQSQ
23 23
42
20, 21 19
na
25
45
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NOTES
1. 2. All voltages referenced to VSS. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. Outputs measured with equivalent load:
VTT Output (VOUT), Reduced Drive) 50 Reference Point 20pF Output (VOUT), Impedance Match Reference Point 10pF
3.
4.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 10. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 5 for -33, CL = 4 for 4, and CL = 3 for -5. Outputs are open during IDD measurments. 11. Enables on-chip refresh and address counters. 12. IDD specifications are tested after the device is properly initialized.
13. This parameter is sampled. VDD = +2.5V 0.125V, VDDQ = +2.5V 0.125V, VREF = VSS, f = 100 MHz, TA = 25C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 14. Command/Address input slew rate = 1V/ns. If the slew rate is less than 0.3V/ns, timing is no longer referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points.If the slew rate exceeds 3V/ns, functionality is uncertain. 15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. 17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 18. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 22. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS MAX for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 23. The refresh period 32ms. This equates to an average refresh rate of 7.8s.
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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NOTES (continued)
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 25. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, andtQH [tHP - 0.4ns (-3), tHP - 0.4ns (-4) or tHP 0.5ns (-4)]. The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. Referenced to each output group: DQS with DQ0DQ31 27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 28. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid level. The inputs require the AC value to be achieved during signal transition edge and the driver should achieve the same slew rate through the AC values. 29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device.. 30. CK and CK# input slew rate must be 1V/ns. 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing is no longer referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points. 32. Vdd must not vary more than 4% if CKE is not active while any bank is active. 33. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK/ inputs, collectively during bank active.
DERATING DATA VALID WINDOW (tQH - tDQSQ)
1.8 -33 @ tCK = 3.3ns t -4 @ tCK = 4ns 1.6 1.500 1.475 1.4 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 -5 @ tCK = 5ns
t
t
ns
1.2
1.150
1.130
1.110
1.090
1.070
1.050
1.030
1.010 0.990 0.970 0.950
1.0
0.850 0.8
0.834
0.817
0.801
0.784
0.768
0.751
0.735
0.718
0.702
0.685
0.6
0.4 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 Clock Duty Cycle 47/53 46.5/54.5 46/54 45.5/55.5 45/55
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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128Mb: x32 DDR SDRAM
NOTES (continued)
35. READs and WRITEs with autoprecharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. 36. Impedance Matched Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figures A b)The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figures A . c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figures B. d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figures B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current will not exceed 1.7, for device drain-to-source voltages from 0 to VDDQ/2. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 30%, for device drain-to-source voltages from 0 to VDDQ/2. 37. Reduced Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figures C and D. b)The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figures C and D. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figures C and D.
Figure A Pull-Down Characteristics
30
-45
Figure B Pull-Up Characteristics
-40
25
Max Min Nominal Low Nominal High
-35
Max Min Nominal Low Nominal High
20
-30
Iout(mA)
-25
15
Iout(mA)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-20
10
-15
-10
5
-5
0
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Vout (V)
Vout (V)
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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128Mb: x32 DDR SDRAM
NOTES (continued)
d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of FiguresC and C. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current will not exceed 1.7, for device drain-to-source voltages from 0 to VDDQ/2. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 30%, for device drain-to-source voltages from 0 to VDDQ/2. 38. The voltage levels used are derived from the refernced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 39. VIH overshoot: VIH (MAX) = VDDQ+1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 40. All speed grades support CL 2, 3, 4, and 5 but only the speed grades listed in the AC timing tables are tested. 41. The DLL must be reset when changing the frequency. 42. VDD and VDDQ must track each other.
Figure C Pull-Down
80 70 60 50
Iout(mA)
Nominal Low Nominal High MIN MAX
Figure D Pull-Up
-120
Nominal Low Nominal High MIN MAX
-100
-80
Iout(mA)
40 30 20
-60
-40
-20
10 0 0.0 0.5 1.0
Vout (V)
0
1.5
2.0
2.5
0.0
0.5
1.0 Vout (V)
1.5
2.0
2.5
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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128Mb: x32 DDR SDRAM
IMPEDANCE MATCH OUTPUT DRIVE CHARACTERISTICS
VOLTAGE (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA) NOMINAL NOMINAL NOMINAL NOMINAL LOW HIGH MINIMUM MAXIMUM LOW HIGH MINIMUM MAXIMUM 3.4 4.98 -1.18 -2.56 6.34 9.0 11.4 13.5 15.3 16.9 18.3 19.4 20.3 21.0 21.6 22.1 22.5 22.9 23.2 23.5 23.8 24.0 9.52 13.7 17.6 21.3 24.7 27.8 30.6 33.2 35.5 37.4 39.1 40.6 41.7 42.7 43.5 44.1 44.7 45.2 -2.33 -3.64 -5.08 -6.64 -8.3 -10.0 -11.8 -13.7 -15.6 -17.5 -19.5 -21.5 -23.6 -25.6 -27.7 .29.8 -31.9 .34.1 -4.99 -7.5 -10.1 -12.7 -15.3 -18.0 -20.7 -23.4 -26.1 -28.9 -31.6 -34.4 -37.1 -39.9 -42.6 -45.3 -48.1 -50.8
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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ADVANCE
128Mb: x32 DDR SDRAM
REDUCED OUTPUT DRIVE CHARACTERISTICS
VOLTAGE (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA) NOMINAL NOMINAL NOMINAL NOMINAL LOW HIGH MINIMUM MAXIMUM LOW HIGH MINIMUM MAXIMUM 3.3 3.7 2.5 4.8 -3.3 -4.1 -2.5 -4.9 6.6 9.8 13.0 16.1 18.7 21.3 23.6 25.6 27.7 29.2 30.3 31.3 32.0 32.5 32.7 32.9 33.2 33.5 33.8 33.9 34.2 34.5 34.6 34.9 7.3 10.9 14.4 17.8 21.1 23.9 26.9 29.8 32.6 35.2 37.7 40.1 42.4 44.4 46.4 48.1 49.8 51.5 52.5 53.5 54.5 55.0 55.5 56.0 5.0 7.4 10.0 12.4 14.9 17.4 19.9 21.4 23.0 24.2 25.0 25.4 25.6 25.8 25.9 26.2 26.4 26.5 26.7 26.8 26.9 27.0 27.0 27.1 9.4 14.0 18.3 22.6 26.7 30.7 34.1 37.7 41.2 44.5 47.7 50.7 53.5 56.0 58.6 60.6 62.6 64.6 66.6 68.3 69.9 71.5 72.9 74.1 -6.6 -9.8 -12.9 -16.1 -18.5 -20.5 -22.2 -23.6 -24.8 -25.8 -26.6 -27.0 -27.2 -27.4 -27.5 -27.6 -27.7 -27.8 -27.9 -28.0 -28.1 -28.2 -28.2 -28.3 -7.8 -11.4 -14.9 -18.4 -21.9 -25.3 -28.7 -32.1 -35.4 -38.6 -41.9 -45.2 -48.4 -51.6 -54.7 -57.8 -60.7 -64.1 -67.0 -69.8 -72.7 -75.6 -78.4 -81.3 -5.0 -7.4 -10.0 -12.4 -14.9 -17.4 -19.5 -20.6 -20.9 -21.1 -21.2 -21.3 -21.4 -21.5 -21.6 -21.7 -21.8 -21.8 -21.9 -21.9 -22.0 -22.0 -22.1 -22.2 -9.7 -14.5 -19.2 -23.9 -28.4 -32.9 -37.3 -41.7 -46.0 -50.2 -54.3 -58.4 -62.4 -66.4 -70.4 -73.8 -77.8 -81.3 -84.7 -88.1 -91.6 -95.0 -97.9 -101.3
NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions.
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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Data Output Timing -
T1
tDQSQ, tQH
Figure 28a and Data Valid Window for TQFP Package
T2 T2n T3 T3n T4
CK# CK
tHP4 tHP4 tDQSQ2 tHP4 tDQSQ2 tHP4 tHP4 tDQSQ2 tHP4 tDQSQ2
DQS1
DQ (Last data valid) DQ6 DQ6 DQ6 DQ6 DQ6 DQ6 DQ (First data no longer valid)6
tQH3 tQH3 tQH3 tQH3
DQ (Last data valid)6 DQ (First data no longer valid)6
T2 T2
T2n T2n
T3 T3
T3n T3n
All DQs and DQS, collectively5 Earliest signal transition Latest signal transition
T2
T2n
T3
T3n
Data Valid window
Data Valid window
Data Valid window
Data Valid window
NOTE: 1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an "early DQS," at T3 is a "nominal DQS," and at T3n is a "late DQS." 2. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid transition of DQs . 3. tQH is derived from tHP: tQH = tHP 4. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active. 5. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ. 6. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, DQ8, DQ9, DQ10, DQ11, DQ13, DQ14, DQ15, DQ16, DQ17, DQ18, DQ19 DQ20, DQ21, DQ22, DQ23, DQ24, DQ25, DQ26, DQ27, DQ28, DQ29, DQ30, or DQ31.
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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128Mb: x32 DDR SDRAM
Data Output Timing -
CK# CK
T1 T2 T2n
tDQSQ, tQH
T3 T3n T4
Figure 28b and Data Valid Window for FBGA Package
CK# CK
T1 T2 T2n T3 T3n T4
tHP5
tHP5 tDQSQ3
tHP5
tHP5 tDQSQ3
tHP5 tDQSQ3
tHP5 tDQSQ3
tHP5
tHP5 tDQSQ3
tHP5
tHP5 tDQSQ3
tHP5 tDQSQ3
tHP5 tDQSQ3
DQS0 DQ (Last data valid)2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ (First data no longer valid)2
tQH4 tQH4 tQH4 tQH4
DQS21 DQ (Last data valid)8 DQ8 DQ8 DQ8 DQ8 DQ8 DQ8 DQ (First data no longer valid)8
tQH4 tQH4 tQH4 tQH4
DQS0 (DQ0 - DQ7)
DQS2 (DQ16 - DQ23)
DQ (Last data valid)2 DQ (First data no longer valid)2 DQ0 - DQ7 and DQS0, collectively6
T2 T2 T2
T2n T2n T2n
T3 T3 T3
T3n T3n T3n
DQ (Last data valid)8 DQ (First data no longer valid)8 DQ16 - DQ23 and DQS2, collectively6
T2 T2 T2
T2n T2n T2n
T3 T3 T3
T3n T3n T3n
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
DQS11 DQ (Last data valid)7
UDQS1 DQ (Last data valid)9 DQ9 DQ9 DQ9 DQ9 DQ9 DQ9 DQ (First data no longer valid)9
tQH4 tQH4 tQH4 tQH4
DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ (First data no longer valid)7
tQH4 tQH4 tQH4 tQH4
DQS1 (DQ8 - DQ15)
DQS3 (DQ24 - DQ31)
DQ (Last data valid)7 DQ (First data no longer valid)7 DQ8 - DQ15 and DQS1, collectively6
T2 T2 T2 Data Valid window
T2n T2n T2n Data Valid window
T3 T3 T3
T3n T3n T3n
DQ (Last data valid)9 DQ (First data no longer valid)9
T2 T2 T2 Data Valid window
T2n T2n T2n Data Valid window
T3 T3 T3
T3n T3n T3n
DQ24 - DQ31 and DQS3, collectively6
Data Valid Data Valid window window
Data Valid Data Valid window window
NOTE: 1. DQs transitioning after DQS transition define tDQSQ window. LDQS defines the lower byte and UDQS defines the upper byte. 2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7. 3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid transition of DQs .
4. tQH is derived from tHP: tQH = tHP - tQHS. 5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active. 6. The data valid window is derived for each DQS transition and is tQH minus tDQSQ. 7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15. 8. DQ16, DQ17, DQ18, D19, DQ20, DQ21, DQ22, or DQ23. 9. DQ24, DQ25, DQ26, D26, DQ28, DQ29, DQ30, or DQ31.
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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Figure 29 Data Output Timing - tAC and tDQSCK
T07 CK# CK tLZ(MIN) tRPRE DQS, or LDQS/UDQS2 DQ (Last data valid) DQ (First data valid) All DQs collectively3 tLZ(MIN) T2 T2 T2 T2n T2n T2n T3 T3 T3 T3n T3n T3n T4 T4 T4 T4n T4n T4n T5 T5 T5 T5n T5n T5n tDQSCK1(MAX) tDQSCK1(MIN) tDQSCK1(MAX) tHZ(MAX) tDQSCK1(MIN) tRPST T1 T2 T2n T3 T3n T4 T4n T5 T5n T6
NOTE: 1. 2. 3. 4. 5. 6. 7.
tHZ(MAX) tDQSCK is the DQS output window relative to CK and is the long term component of DQS skew. DQs transitioning after DQS transition define tDQSQ window. All DQs must transition by tDQSQ after DQS transitions, regardless of tAC. tAC is the DQ output window relative to CK, and is the long term component of DQ skew. tLZ(MIN) and tAC(MIN) are the first valid signal transition. tHZ(MAX ,and tAC(MAX) are the latest valid signal transition. READ command with CL = 2 issued at T0.
tAC4(MIN)
tAC4(MAX)
Figure 30 Data Input Timing
T0 CK# CK tDQSS DQS tWPRES DQ DM tDS tDH DON T CARE TRANSITIONING DATA tWPRE DI b tDQSL tDQSH tWPST tDSH1 tDSS2 tDSH1 tDSS2 T1 T1n T2 T2n T3
NOTE: 1. tDSH(MIN) generally occurs during tDQSS(MIN). 2. tDSS(MIN) generally occurs during tDQSS(MAX).
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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128Mb: x32 DDR SDRAM
Figure 31 Input Voltage Waveform
VDDQ (2.3V minimum)
1 VOH(MIN) (1.670V for SSTL2 termination) System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation) 1.560V VIHAC
1.400V
VIHDC
1.300V 1.275V 1.250V 1.225V 1.200V
VREF VREF VREF VREF
+AC Noise +DC Error -DC Error -AC Noise
1.100V
VILDC
0.940V VINAC - Provides margin between VOL (MAX) and VILAC VOL (MAX) (0.83V2 for SSTL2 termination)
VILAC
VSSQ
NOTE: 1. VOH (MIN) with test load is 1.927V 2. VOL (MAX) with test load is 0.373V 3. Numbers in diagram reflect nomimal values utilizing circuit below.
VTT 25 25 Reference Point
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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ADVANCE
128Mb: x32 DDR SDRAM
INITIALIZE AND LOAD MODE REGISTERS
VDD
(( )) (( ))
VDDQ VTT1 VREF
tVTD
(( )) (( ))
T0 CK# CK
(( )) (( ))
T1
(( )) (( tCK ) )
Ta0
(( )) (( ))
Tb0
(( )) (( ))
Tc0
(( )) (( ))
Td0
(( )) (( ))
Te0
(( )) (( ))
Tf0
tCH tIS tIH
tCL
LVCMOS CKE LOW LEVEL
(( ))
(( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
tIS
6 COMMAND66
tIH PRE
(( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( ))
NOP
LMR
LMR
PRE
AR
AR
ACT5
DM
tIS A0-A7, A9-A11
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
tIH
(( )) (( )) (( )) (( )) (( )) (( ))
CODE
CODE
(( )) (( )) ( ( ALL BANKS )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
RA
ALL BANKS
tIS
(( )) (( )) (( )) (( ))
tIH
CODE
A8
CODE
RA
tIS
tIH
tIS
tIH
BA0 = L, BA1 = L
(( )) (( ))
tIS
tIH
BA0, BA1
BA0 = H, BA1 = L
BA
DQS DQ
High-Z High-Z
(( )) (( ))
(( )) (( ))
(( )) (( ))
(( )) (( ))
(( )) (( ))
(( )) (( ))
T = 200 s
tRP
Power-up: VDD and CK stable
tMRD Load Extended Mode Register
tMRD
tRP
tRFC
tRFC5
200 cycles of CK3 Load Mode Register2 DON T CARE
NOTE:
1. VTT is not applied directly to the device; however, tVTD must be greater than or equal to zero to avoid device latch-up. 2. Although not required by the Micron device, JEDEC specifies resetting the DLL with A8 = H. 3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued. 4. The two AUTO REFRESH commands at Tc0 and Td0 may be applied after the LOAD MODE REGISTER (LMR) command at Ta0. 5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank. 6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address
TIMING PARAMETERS
-33 SYMBOL tCH
tCL tCK (5) tCK (4) tCK (3)
-4 MIN 0.45 0.45 4 5 MAX 0.55 0.55 8 8 MIN 0.45 0.45 5
-5 MAX 0.55 0.55 8 UNITS tCK
tCK
MIN 0.45 0.45 3 4 -
MAX 0.55 0.55 8 8 -
SYMBOL tIH
tIS tMRD tRFC tRP tVTD
MIN 0.9 0.9 2 62 16 0
-33 MAX
-4 MIN 0.9 0.9 2 62 16 0 MAX MIN 0.9 0.9 2 62 20 0
-5 MAX UNITS ns ns
tCK
ns ns ns
ns ns ns
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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ADVANCE
128Mb: x32 DDR SDRAM
POWER-DOWN MODE
T0 CK# CK
tIS tIH tCK tIS
(( ))
T1
T2
tCH
tCL
(( )) (( ))
Ta0
Ta1
Ta2
tIS
tPDIX
CKE
tIS tIH NOP
COMMAND
VALID1 tIS tIH
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
NOP
NOP
VALID
ADDR
VALID
VALID
DQS
DQ
DM
Enter 2 Power-Down Mode
Exit Power-Down Mode DON T CARE
NOTE: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at least one row is already active), then the power-down mode shown is active power-down. 2. No column accesses are allowed to be in progress at the time power-down is entered.
TIMING PARAMETERS
-33 SYMBOL tCH
tCL tCK (5) tCK (4)
-4 MIN 0.45 0.45 4 MAX 0.55 0.55 8 MIN 0.45 0.45 -
-5 MAX 0.55 0.55 UNITS tCK
tCK
-33 SYMBOL tCK (3)
tIH tIS tPDIX
-4 MIN 0.9 0.9 1 tCK + tIS MAX MIN 5 0.9 0.9 1 tCK + tIS
-5 MAX 8 UNITS ns ns ns ns
MIN 0.45 0.45 3.3 4
MAX 0.55 0.55 8 8
MIN 0.9 0.9 1 tCK + tIS
MAX -
ns ns
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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ADVANCE
128Mb: x32 DDR SDRAM
AUTO REFRESH MODE
T0 CK# CK
tIS tIH tCK tCH VALID tIS tIH PRE NOP 2 NOP 2 AR tCL
T1
T2
T3
T4
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
Ta0
Ta1
(( )) (( )) (( )) (( ))
Tb0
Tb1
Tb2
CKE
VALID
COMMAND1
NOP 2
NOP 2
AR 5
(( )) (( )) (( )) (( ))
(( )) (( ))
NOP2
NOP2
ACT
A0-A7, A9-A11
ALL BANKS
RA
A81
ONE BANK
(( )) (( ))
RA
tIS
tIH
BA0, BA11
Bank(s) 3
(( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
BA
DQS4
DQ4
DM4
tRP
tRFC
tRFC 5
DON T CARE NOTE: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address. 2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. 3. Don t Care if A8 is HIGH at this point; A8 must be HIGH if more than one bank is active (i.e., must precharge all active banks). 4. DM, DQ and DQS signals are all Don t Care /High-Z for operations shown. 5. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.
TIMING PARAMETERS
-33 MAX 0.55 0.55 8 8 -4 MIN 0.45 0.45 4 MAX 0.55 0.55 8 MIN 0.45 0.45 -5 MAX 0.55 0.55 UNITS
tCK tCK
-33 SYMBOL tCK (3) tIH
tIS tRFC tRP
-4 MIN 0.9 0.9 62 16 MAX MIN 5 0.9 0.9 62 20
-5 MAX 8 UNITS ns ns ns ns ns
SYMBOL
tCH tCL tCK (5) tCK (4)
MIN 0.45 0.45 3.3 4
MIN 0.9 0.9 62 16
MAX -
ns ns
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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ADVANCE
128Mb: x32 DDR SDRAM
SELF REFRESH MODE
T0 CK# CK1
tIS tCH tIH tCL tIS
(( ))
T1
(( )) (( ))
Ta0
Ta1
tCK t IS
(( )) (( ))
Tb0
CKE1
tIS tIH AR
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
COMMAND 4
NOP
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
NOP
VALID
tIS
tIH
ADDR
VALID
DQS
DQ
DM
tRP 2
tXSNR/ tXSRD 3
Enter Self Refresh Mode
Exit Self Refresh Mode
DON T CARE
NOTE: 1. 2. 3.
Clock must be stable before exiting self refresh mode. Device must be in the all banks idle state prior to entering self refresh mode. tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK) is required before a READ command can be applied. 4. AR = AUTO REFRESH command.
TIMING PARAMETERS
-33 MAX 0.55 0.55 8 8 -4 MIN 0.45 0.45 4 5 MAX 0.55 0.55 8 8 MIN 0.45 0.45 5 -5 MAX 0.55 0.55 8 UNITS tCK
tCK
SYMBOL tCH
tCL tCK (5) tCK (4) tCK (3)
MIN 0.45 0.45 3.3 4 -
SYMBOL tIH
tIS tRP tXSNR tXSRD
MIN 0.9 0.9 16 66 200
-33 MAX
-4 MIN 0.9 0.9 16 66 200 MAX MIN 0.9 0.9 20 66 200
-5 MAX UNITS ns ns ns ns
tCK
ns ns ns
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
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ADVANCE
128Mb: x32 DDR SDRAM
BANK READ - WITHOUT AUTO PRECHARGE
CK# CK
tIS tIH tCK tCH tCL
T0
T1
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
CKE
tIS tIH ACT tIS tIH Col n RA NOP6 READ2 NOP6 PRE7 NOP6 NOP6 ACT
COMMAND5
NOP6
A0-A7
RA
A9-A11
RA tIS tIH
ALL BANKS
RA
A8
RA tIS tIH
3
ONE BANK
RA
BA0, BA1
Bank x tRCD tRAS7 tRC
Bank x
Bank x4
Bank x
CL = 2
tRP
DM
Case 1: tAC(MIN) and tDQSCK(MIN)
tRPRE
tDQSCK(MIN) tRPST
DQS
tLZ(MIN)
DQ1
DO n tLZ(MIN) tAC(MIN) tHZ(MIN)
Case 2: tAC(MAX) and tDQSCK(MAX)
tRPRE
tDQSCK(MAX) tRPST
DQS
tLZ(MAX)
DQ1
tLZ(MAX)
DO n tAC(MAX) tHZ(MAX)
DON'T CARE NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order. 2. Burst length = 4 in the case shown. 3. Disable auto precharge. 4. "Don't Care" if A8is HIGH at T5. 5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. 6. NOP commands are shown for ease of illustration; other commands may be valid at these times. 7. The PRECHARGE command can only be applied at T5 if tRAS minimum is met.
TRANSITIONING DATA
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
60
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
ADVANCE
128Mb: x32 DDR SDRAM
BANK READ - WITH AUTO PRECHARGE
CK# CK
tIS tIH tCK tCH tCL
T0
T1
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
CKE
tIS tIH ACT tIS tIH Col n RA NOP5 READ2,6 NOP5 NOP5 NOP5 NOP5 ACT
COMMAND4
NOP5
A0-A7
RA
A9-A11
RA 3
RA
A8 IS BA0, BA1
RA
tIS
tIH
RA
IH
Bank x tRCD tRAS6 tRC Bank x
Bank x
CL = 2
tRP
DM
Case 1: tAC(MIN) and tDQSCK(MIN)
tRPRE
tDQSCK(MIN) tRPST
DQS
tLZ(MIN)
DQ1
DO n tLZ(MIN) tAC(MIN) tHZ(MIN)
Case 2: tAC(MAX) and tDQSCK(MAX)
tRPRE
tDQSCK(MAX) tRPST
DQS
tLZ(MAX)
DQ1
tLZ(MAX)
DO n tAC(MAX) tHZ(MAX)
DON'T CARE NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order. 2. Burst length = 4 in the case shown. 3. Enable auto precharge. 4. ACT = ACTIVE, RA = Row Address, BA = Bank Address. 5. NOP commands are shown for ease of illustration; other commands may be valid at these times. 6. The READ command can only be applied at T3 if tRAS minimum is met by T5.
TRANSITIONING DATA
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
61
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
ADVANCE
128Mb: x32 DDR SDRAM
BANK WRITE - WITHOUT AUTO PRECHARGE
CK# CK
tIS tIH
T0
T1
T2
T3
T4
T4n
T5
T5n
T6
T7
T8
tCK
tCH
tCL
CKE
tIS tIH ACT tIS tIH Col n NOP6 WRITE2 NOP6 NOP6 NOP6 NOP6 PRE
COMMAND5
NOP6
A0-A7
RA
A9-A11
RA tIS tIH
ALL BANKS
A8
RA tIS tIH
3
ONE BANK
BA0, BA1
Bank x tRCD tRAS
Bank x tWR
Bank x4
tRP tDQSS (NOM) tDSH7 tDSS8 tDSH7 tDSS8
DQS
tWPRES tWPRE tDQSL tDQSH tWPST
DQ1 DM tDS
DI b
tDH DON'T CARE TRANSITIONING DATA
NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order. 2. Burst length = 4 in the case shown. 3. Disable auto precharge. 4. "Don't Care" if A8 is HIGH at T8. 5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. 6. NOP commands are shown for ease of illustration; other commands may be valid at these times. 7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T4 or T5. 8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T5 or T6.
TIMING PARAMETERS
-33 MAX 0.55 0.55 8 8 -4 MIN 0.45 0.45 4 5 0.45 0.45 0.4 1.2 0.4 0.8 1.2 MAX 0.55 0.55 8 8 MIN 0.45 0.45 5 0.45 0.45 0.4 0.4 0.8 1.2 -5 MAX 0.55 0.55 8 UNITS tCK
tCK
-33 SYMBOL tDSS
tDSH tIH tIS tRAS tRCDW tRP tWPRE tWPRES tWPST tWR
-4 MIN 0.25 0.25 0.9 MAX MIN 0.25 0.25 0.9 120,000 0.9 40 10 20 0.25 0.6 0 0.4 2
-5 MAX UNITS tCK
tCK
SYMBOL tCH
tCL tCK (5) tCK (4) tCK (3) tDH tDS tDQSH tDQSL tDQSS
MIN 0.45 0.45 3.3 4 0.45 0.45 0.4 0.4 0.8
MIN 0.25 0.25 0.9 0.9 40 10 16 0.25 0 0.4 3
MAX
ns ns ns ns ns tCK
tCK tCK
ns 120,000 ns ns ns ns
tCK
120,000
0.9 40 10 16 0.25
0.6
0 0.4 3
0 0.6
ns
tCK tCK
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
62
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
ADVANCE
128Mb: x32 DDR SDRAM
BANK WRITE - WITH AUTO PRECHARGE
CK# CK
tIS tIH
T0
T1
T2
T3
T4
T4n
T5
T5n
T6
T7
T8
tCK
tCH
tCL
CKE
tIS tIH ACT tIS tIH Col n NOP5 WRITE2 NOP5 NOP5 NOP5 NOP5 NOP5
COMMAND4
NOP5
A0-A7
RA
A9-A11
RA 3
A8
tIS
RA tIH
tIS
tIH
BA0, BA1
Bank x tRCD tRAS
Bank x tWR tRP tDQSS (NOM) tDSH6 tDSS7 tDSH6 tDSS7
DQS
tWPRES tWPRE tDQSL tDQSH tWPST
DQ1 DM
tDS
DI b
tDH
DON'T CARE NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order. 2. Burst length = 4 in the case shown. 3. Enable auto precharge. 4. ACT = ACTIVE, RA = Row Address, BA = Bank Address. 5. NOP commands are shown for ease of illustration; other commands may be valid at these times. 6. tDSH is applicable during tDQSS(MIN) and is referenced from CK T4 or T5. 7. tDSS is applicable during tDQSS (MAX) and is referenced from CK T5 or T6.
TRANSITIONING DATA
TIMING PARAMETERS
-33 MAX 0.55 0.55 8 8 -4 MIN 0.45 0.45 4 5 0.45 0.45 0.4 1.2 0.4 0.8 1.2 MAX 0.55 0.55 8 8 MIN 0.45 0.45 5 0.45 0.45 0.4 0.4 0.8 1.2 -5 MAX 0.55 0.55 8 UNITS
tCK tCK
SYMBOL
tCH tCL tCK (5) tCK (4) tCK (3) tDH tDS tDQSH tDQSL tDQSS
MIN 0.45 0.45 3.3 4 0.45 0.45 0.4 0.4 0.8
ns ns ns ns ns tCK
tCK tCK
SYMBOL tDSS tDSH tIH
tIS tRAS tRCDW tRP tWPRE tWPRES tWPST tWR
MIN 0.25 0.25 0.9 0.9 40 10 16 0.25 0 0.4 3
-33 MAX
-4 MIN 0.25 0.25 0.9 0.9 40 10 16 0.25 MAX MIN 0.25 0.25 0.9 0.9 40 10 20 0.25 0.6 0 0.4 2
-5 MAX UNITS tCK tCK ns ns ns ns ns tCK ns 0.6
tCK tCK
120,000
120,000
120,000
0.6
0 0.4 3
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
63
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
ADVANCE
128Mb: x32 DDR SDRAM
WRITE - DM OPERATION
CK# CK
tIS tIH
T0
T1
T2
T3
T4
T4n
T5
T5n
T6
T7
T8
tCK
tCH
tCL
CKE
tIS tIH ACT tIS tIH Col n NOP6 WRITE2 NOP6 NOP6 NOP6 NOP6 PRE
COMMAND5
NOP6
A0-A7
RA
A9-A11
RA tIS tIH
ALL BANKS
A8
RA tIS tIH
3
ONE BANK
BA0, BA1
Bank x tRCD tRAS
Bank x
Bank x4
tWR tRP
tDQSS (NOM) tDSH7 tDSS8 tDSH7 tDSS8
DQS
tWPRES tWPRE tDQSL tDQSH tWPST
DQ1 DM
tDS
DI b
tDH
DON'T CARE NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order. 2. Burst length = 4 in the case shown. 3. Disable auto precharge. 4. "Don't Care" if A8 is HIGH at T8. 5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. 6. NOP commands are shown for ease of illustration; other commands may be valid at these times. 7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T4 or T5. 8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T5 or T6. 9. tDS and tDH are referanced from DQS
TRANSITIONING DATA
TIMING PARAMETERS
-33 MAX 0.55 0.55 8 8 -4 MIN 0.45 0.45 4 5 0.45 0.45 0.4 1.2 0.4 0.8 1.2 MAX 0.55 0.55 8 8 MIN 0.45 0.45 5 0.45 0.45 0.4 0.4 0.8 1.2 -5 MAX 0.55 0.55 8 UNITS
tCK tCK
SYMBOL
tCH tCL tCK (5) tCK (4) tCK (3) tDH tDS tDQSH tDQSL tDQSS
MIN 0.45 0.45 3.3 4 0.45 0.45 0.4 0.4 0.8
ns ns ns ns ns tCK
tCK tCK
SYMBOL tDSS tDSH tIH
tIS tRAS tRCDW tRP tWPRE tWPRES tWPST tWR
MIN 0.25 0.25 0.9 0.9 40 10 16 0.25 0 0.4 3
-33 MAX
-4 MIN 0.25 0.25 0.9 0.9 40 10 16 0.25 MAX MIN 0.25 0.25 0.9 0.9 40 10 20 0.25 0.6 0 0.4 2
-5 MAX UNITS tCK tCK ns ns ns ns ns tCK ns 0.6
tCK tCK
120,000
120,000
120,000
0.6
0 0.4 3
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
64
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
ADVANCE
128Mb: x32 DDR SDRAM
100-PIN PLASTIC TQFP
+0.10 -0.20 20.10 0.10 22.10 0.65 TYP 0.32 +0.06 -0.10 0.625 (TYP) SEE DETAIL A
14.00 0.10 16.00 0.20
PIN #1 ID 0.15
+0.03 -0.02
1.40 0.05 GAGE PLANE
1.60 MAX 0.10 0.10 +0.10 -0.05 0.10 DETAIL A 1.00 TYP 0.60 0.15
NOTE: 1. All dimensions in millimeters 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02
65
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
ADVANCE
128Mb: x32 DDR SDRAM
144-BALL FBGA
.850 .075 .10 C SEATING PLANE C SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 36% Pb, 2% Ag SOLDER BALL PAD: O .33mm SUBSTRATE: PLASTIC LAMINATE ENCAPSULATION MATERIAL: EPOXY NOVOLAC
8.80 144X 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS O 0.40 .80 TYP BALL A12
BALL #1 ID
BALL A1 ID
BALL A1
8.80
C L
12.00 .10 .80 TYP 6.00 .05
4.40 .05
4.40 .05
C L
6.00 .05
1.20 MAX
12.00 .10
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.
128Mb: x32 DDR SDRAM 4M32DDR_B.p65 - Rev. B, Pub. 7/02 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
66

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