 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CY2300 Phase-Aligned Clock Multiplier Features Benefits 4-multiplier configuration Single phase-locked loop architecture Phase Alignment Low jitter, high accuracy outputs Output enable pin 3.3V operation 5V Tolerant input Internal loop filter 8-pin 150-mil SOIC package Commercial Temperature 1/2x, 1x, 1x, 2x Ref 10 MHz to 166.67 MHz operating range (reference input from 20 MHz to 83.33 MHz) All outputs have a consistent phase relationship with each other and the reference input Meets critical timing requirements Enables design flexibility and lower power consumption Supports industry standard design platforms Allows flexibility on Reference input Alleviates the need for external components Industry standard packaging saves on board space Suitable for wide spectrum of applications Logic Block Diagram FBK 1/2xREF REFIN /2 PLL Divider Logic REF REF 2xREF OE Cypress Semiconductor Corporation Document #: 38-07252 Rev. *C * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised September 23, 2008 [+] Feedback CY2300 Pinouts Figure 1. CY2300 - 8-pin SOIC - Top View 1/2xREF GND REFIN REF 1 2 3 4 8 7 6 5 OE VDD 2xREF REF Table 1. Pin Definitions Pin 1 2 3 4 5 6 7 8 GND REFIN REF REF 2xREF VDD OE Signal[1] 1/2xREF Clock output, 1/2x Reference Ground Input Reference frequency, 5V tolerant input Clock output Reference Clock output Reference Clock output, 2x Reference 3.3V Supply Output Enable (weak pull up) Description Functional Description The CY2300 is a 4-output 3.3V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN output frequencies on respective output pins. The part has an on-chip PLL which locks to an input clock presented on the REFIN pin. The input-to-output skew is guaranteed to be less than 200 ps, and output-to-output skew is guaranteed to be less than 200 ps. Multiple CY2300 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 400 ps. The CY2300 is available in commercial temperature range. Maximum Ratings Supply Voltage to Ground Potential................-0.5V to +7.0V DC Input Voltage (Except Ref) .............. -0.5V to VDD + 0.5V DC Input Voltage REF ........................................... -0.5 to 7V Storage Temperature ................................. -65C to +150C Junction Temperature ................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, Fout < 133.33 MHz Load Capacitance,133.33 MHz < Fout < 166.67 MHz Input Capacitance Power up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min 3.0 0 Max 3.6 70 18 12 7 50 Unit V C pF pF pF ms Note 1. Weak pull down on all outputs. Document #: 38-07252 Rev. *C Page 2 of 6 [+] Feedback CY2300 Electrical Characteristics Parameter VIL VIH IIL IIH VOL VOH IDD Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[2] Output HIGH Voltage Supply Current [2] Description Min 2.0 Max 0.8 Unit V V A A V V mA mA mA VIN = 0V VIN = VDD IOL = 8 mA IOH = -8 mA Unloaded outputs, REFIN = 66 MHz Unloaded outputs, REFIN = 33 MHz Unloaded outputs, REFIN = 20 MHz 2.4 100 50 0.4 45 32 18 Switching Characteristics Parameter 1/t1 Name Output Frequency Duty Cycle[3] = t2 / t1 t3 t4 t5 t6 t7 Rise Fall Time[3] Time[3] 18-pF load 12-pF load Measured at VDD/2 Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 from REFIN to any output Measured at VDD/2 on the 1/2xREF pin of devices (pin 1) Measured at Fout=133.33 MHz, loaded outputs, 18-pF load Stable power supply, valid clocks presented on REFIN 40 50 Test Conditions Min 10 Typ. Max 133.33 166.67 60 1.20 1.20 200 200 400 Unit MHz MHz % ns ns ps ps ps Output to Output Skew on rising edges[3] Delay, REFIN Rising Edge to Output Rising Edge[3] Device to Device Skew[3] tJ tLOCK Period Jitter[3] PLL Lock Time[3] 175 1.0 ps ms Switching Waveforms Figure 2. Duty Cycle Timing t1 t2 VDD/2 Notes 2. Parameter is guaranteed by design and characterization. It is not 100% tested in production. 3. All parameters are specified with equally loaded outputs. Document #: 38-07252 Rev. *C Page 3 of 6 [+] Feedback CY2300 Switching Waveforms (continued) Figure 3. All Outputs Rise/Fall Time OUTPUT 2.0V 0.8V t3 2.0V 0.8V t4 3.3V 0V Figure 4. Output-Output Skew VDD/2 OUTPUT OUTPUT t5 VDD/2 Figure 5. Input-Output Propagation Delay VDD/2 REFIN OUTPUT t6 VDD/2 Figure 6. Device-Device Skew VDD/2 1/2xREF, Device1 1/2xREF, Device2 t7 VDD/2 Test Circuits Test Circuit # 1 VDD 0.1 F OUTPUTS CLK OUT C LOAD GND Document #: 38-07252 Rev. *C Page 4 of 6 [+] Feedback CY2300 Ordering Information Ordering Code Pb-Free CY2300SXC CY2300SXCT 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel Commercial Commercial Package Type Operating Range Package Drawing and Dimensions Figure 7. 8-Pin (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG. 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C Document #: 38-07252 Rev. *C Page 5 of 6 [+] Feedback CY2300 Document History Page Document Title: CY2300 Phase-Aligned Clock Multiplier Document Number: 38-07252 REV. ** *A *B *C ECN 110517 121854 246829 2568533 Orig. of Change SZV RBI RGL AESA Submission Date 01/07/02 12/14/02 08/02/04 09/23/08 Description of Change Change from Spec number: 38-01039 to 38-07252 Power up requirements added to Operating Conditions Information Added Lead Free Devices Updated template. Removed Selector Guide. Removed Operating Conditions for CY2300SI Industrial Temperature Devices. Removed Electrical Characteristics for CY2300SI Industrial Temperature Devices. Removed Switching Characteristics for CY2300SI Industrial Temperature Devices. Removed part number CY2300SC, CY2300SC, CY2300SI, CY2300SI, CY2300SXI and CY2300SXIT. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07252 Rev. *C Revised September 23, 2008 Page 6 of 6 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
Price & Availability of CY2300SXC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |