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PD - 95485
AUTOMOTIVE MOSFET
IRF1407PBF
Typical Applications
Integrated Starter Alternator 42 Volts Automotive Electrical Systems Lead-Free
HEXFET(R) Power MOSFET
D
VDSS = 75V
G S
Benefits
Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax
RDS(on) = 0.0078 ID = 130A
Description
Specifically designed for Automotive applications, this Stripe Planar design of HEXFET(R) Power MOSFETs utilizes the lastest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this HEXFET power MOSFET are a 175C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications.
TO-220AB
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting Torque, 6-32 or M3 screw
Max.
130 92 520 330 2.2 20 390 See Fig.12a, 12b, 15, 16 4.6 -55 to + 175 300 (1.6mm from case ) 10 lbf*in (1.1N*m)
Units
A W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RCS RJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient
Typ.
--- 0.50 ---
Max.
0.45 --- 62
Units
C/W
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1
06/30/04
IRF1407PBF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff.
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. 75 --- --- 2.0 74 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. --- 0.09 --- --- --- --- --- --- --- 160 35 54 11 150 150 140 4.5 7.5 5600 890 190 5800 560 1100
Max. --- --- 0.0078 4.0 --- 20 250 200 -200 250 52 81 --- --- --- --- ---
Units V V/C V S A nA
nC
ns
nH --- --- --- --- --- --- ---
pF
Conditions VGS = 0V, ID = 250A Reference to 25C, ID = 1mA VGS = 10V, ID = 78A VDS = 10V, ID = 250A VDS = 25V, ID = 78A VDS = 75V, VGS = 0V VDS = 60V, VGS = 0V, TJ = 150C VGS = 20V VGS = -20V ID = 78A VDS = 60V VGS = 10V VDD = 38V ID = 78A RG = 2.5 VGS = 10V D Between lead, 6mm (0.25in.) G from package and center of die contact S VGS = 0V VDS = 25V = 1.0KHz, See Fig. 5 VGS = 0V, VDS = 1.0V, = 1.0KHz VGS = 0V, VDS = 60V, = 1.0KHz VGS = 0V, VDS = 0V to 60V
Source-Drain Ratings and Characteristics
Min. Typ. Max. Units IS
ISM
VSD trr Qrr ton Notes:
Conditions D MOSFET symbol --- --- 130 showing the A G integral reverse --- --- 520 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 78A, VGS = 0V --- 110 170 ns TJ = 25C, IF = 78A --- 390 590 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11). Starting TJ = 25C, L = 0.13mH RG = 25, IAS = 78A. (See Figure 12). ISD 78A, di/dt 320A/s, VDD V(BR)DSS, TJ 175C Pulse width 400s; duty cycle 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS . Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
2
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IRF1407PBF
1000
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
1000
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
100
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
4.5V
4.5V
10
10
20s PULSE WIDTH Tj = 25C
1 0.1 1 10 100 1 0.1 1
20s PULSE WIDTH Tj = 175C
10 100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.00
3.0
I D = 130A
ID, Drain-to-Source Current ()
T J = 25C
2.5
RDS(on) , Drain-to-Source On Resistance
TJ = 175C
2.0
100.00
(Normalized)
1.5
1.0
0.5
10.00 3.0 5.0 7.0
VDS = 15V 20s PULSE WIDTH
9.0 11.0 13.0
V GS = 10V
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ, Junction Temperature
( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
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3
IRF1407PBF
100000
15
VGS = 0V, f = 1 MHZ Ciss = C + Cgd, C gs ds SHORTED Crss = C gd Coss = C + C ds gd
VGS , Gate-to-Source Voltage (V)
ID = 78A
VDS = 60V VDS = 37V VDS = 15V
12
C, Capacitance(pF)
10000
Ciss
9
1000
Coss
6
3
Crss
100 1 10 100
0 0 40 80 120 160 200
VDS, Drain-to-Source Voltage (V)
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
1000.00
10000 OPERATION IN THIS AREA LIMITED BY R DS(on)
100.00
T J = 175C
10.00 T J = 25C 1.00 VGS = 0V 0.10 0.0 1.0 2.0 3.0 VSD, Source-toDrain Voltage (V)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
100 100sec
10 Tc = 25C Tj = 175C Single Pulse 1 1 10
1msec
10msec 100 1000
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF1407PBF
140
LIMITED BY PACKAGE
120
VDS VGS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
RD
D.U.T.
+
100
I D , Drain Current (A)
-VDD
80
60
40
Fig 10a. Switching Time Test Circuit
VDS 90%
20
0 25 50 75 100 125 150 175
TC , Case Temperature
( C)
Fig 9. Maximum Drain Current vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
1
(Z thJC )
D = 0.50
0.1
0.20 0.10
Thermal Response
0.05 0.02 0.01 0.01 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1. Duty factor D = 2. Peak T 0.001 0.00001 0.0001 0.001 0.01 t1 / t 2 +TC 1
J = P DM x Z thJC
0.1
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRF1407PBF
15V
650
ID TOP 32A 55A 78A
RG
20V
D.U.T
IAS tp
EAS , Single Pulse Avalanche Energy (mJ)
VDS
L
DRIVER
520
BOTTOM
+ V - DD
390
A
0.01
260
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
130
0 25 50 75 100 125 150 175
Starting T , Junction Temperature J
( C)
I AS
Fig 12b. Unclamped Inductive Waveforms
QG
Fig 12c. Maximum Avalanche Energy vs. Drain Current
10 V
QGS VG QGD
VGS(th) Gate threshold Voltage (V)
3.5
3.0
Charge
ID = 250A
2.5
Fig 13a. Basic Gate Charge Waveform
Current Regulator Same Type as D.U.T.
50K 12V .2F .3F
2.0
D.U.T. VGS
3mA
+ V - DS
1.5 -75 -50 -25 0 25 50 75 100 125 150 175 200
T J , Temperature ( C )
IG ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 14. Threshold Voltage vs. Temperature
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IRF1407PBF
1000
Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses
Avalanche Current (A)
100
0.01
0.05
10
0.10
1 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
400
EAR , Avalanche Energy (mJ)
TOP Single Pulse BOTTOM 10% Duty Cycle ID = 78A
300
200
100
0 25 50 75 100 125 150
Starting T J , Junction Temperature (C)
Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 15, 16). t av = Average time in avalanche. 175 D = Duty cycle in avalanche = t av *f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 16. Maximum Avalanche Energy vs. Temperature
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IRF1407PBF
Peak Diode Recovery dv/dt Test Circuit
D.U.T*
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG V GS * dv/dt controlled by RG * ISD controlled by Duty Factor "D" * D.U.T. - Device Under Test
+ V DD
*
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive P.W. Period D=
P.W. Period
[VGS=10V ] ***
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
[VDD]
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
[ISD]
*** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 17. For N-channel HEXFET(R) power MOSFETs
8
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IRF1407PBF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) -A6.47 (.255) 6.10 (.240) -B4.69 (.185) 4.20 (.165) 1.32 (.052) 1.22 (.048) 2.87 (.113) 2.62 (.103)
4 15.24 (.600) 14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045) MIN 1 2 3 LEAD ASSIGNMENTS IGBTs, CoPACK 1 - GATE 2 1- GATE- DRAIN 1- GATE 32- DRAINSOURCE 2- COLLECTOR 3- EMITTER 3- SOURCE 4 - DRAIN
HEXFET
14.09 (.555) 13.47 (.530)
4- DRAIN
4.06 (.160) 3.55 (.140)
4- COLLECTOR
3X 3X 1.40 (.055) 1.15 (.045)
0.93 (.037) 0.69 (.027) M BAM
3X
0.55 (.022) 0.46 (.018)
0.36 (.014)
2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH
2.92 (.115) 2.64 (.104)
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMP LE : T H IS IS AN IR F 1010 L OT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T H E AS S E MB L Y L INE "C" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y LOT CODE PAR T NU MB E R
Note: "P" in assembly line position indicates "Lead-Free"
DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C
Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.06/04
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Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/

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