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IMPORTANT NOTICE
Dear customer, As from August 2nd 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document.
Company name - NXP B.V. is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of each page "(c) NXP B.V. 200x. All rights reserved", shall now read: "(c) ST-NXP Wireless 200x - All rights reserved". Web site - http://www.nxp.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices previously obtained by sending an email to salesaddresses@nxp.com , is now found at http://www.stnwireless.com under Contacts.
If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless
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ISP1562
Hi-Speed USB PCI host controller
Rev. 03 -- 14 November 2008 Product data sheet
1. General description
The ISP1562 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal Serial Bus (USB) host controller. It integrates two Original USB Open Host Controller Interface (OHCI) cores, one Hi-Speed USB Enhanced Host Controller Interface (EHCI) core, and two transceivers that are compliant with Hi-Speed USB and Original USB. The functional parts of the ISP1562 are fully compliant with Universal Serial Bus Specification Rev. 2.0, Open Host Controller Interface Specification for USB Rev. 1.0a, Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0, PCI Local Bus Specification Rev. 2.2, and PCI Bus Power Management Interface Specification Rev. 1.1. Integrated high performance USB transceivers allow the ISP1562 to handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1562 provides two downstream ports, allowing simultaneous connection of USB devices at different speeds. The ISP1562 is fully compatible with various Operating System (OS) drivers, such as Microsoft Windows standard OHCI and EHCI drivers that are present in Windows XP, Windows 2000 and Red Hat Linux. The ISP1562 directly interfaces to any 32-bit, 33 MHz PCI bus. Its PCI pins can source 3.3 V. The PCI interface fully complies with PCI Local Bus Specification Rev. 2.2. The ISP1562 is ideally suited for use in Hi-Speed USB mobile applications and embedded solutions. The ISP1562 uses a 12 MHz crystal.
2. Features
I Complies with Universal Serial Bus Specification Rev. 2.0 I Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) I Two Original USB OHCI cores comply with Open Host Controller Interface Specification for USB Rev. 1.0a I One Hi-Speed USB EHCI core complies with Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 I Supports PCI 32-bit, 33 MHz interface compliant with PCI Local Bus Specification Rev. 2.2, with support for D3cold standby and wake-up modes; all I/O pins are 3.3 V standard I Compliant with PCI Bus Power Management Interface Specification Rev. 1.1 for all hosts (EHCI and OHCI), and supports all power states: D0, D1, D2, D3hot and D3cold
NXP Semiconductors
ISP1562
HS USB PCI host controller
I CLKRUN support for mobile applications, such as internal notebook design I Configurable subsystem ID and subsystem Vendor ID through external EEPROM I Digital and analog power separation for better ElectroMagnetic Interference (EMI) and ElectroStatic Discharge (ESD) protection I Supports hot Plug and Play and remote wake-up of peripherals I Supports individual power switching and individual overcurrent protection for downstream ports I Supports partial dynamic port-routing capability for downstream ports that allows sharing of the same physical downstream ports between the Original USB host controller and the Hi-Speed USB host controller I Uses 12 MHz crystal oscillator to reduce system cost and EMI emissions I Supports dual power supply: PCI Vaux(3V3) and VCC I Operates at +3.3 V power supply input I Low power consumption I Full industrial operating temperature range from -40 C to +85 C I Full-scan design with high fault coverage (93 % to 95 %) ensures high quality I Available in LQFP100 package
3. Applications
I I I I I I Digital consumer appliances Notebook PCI add-on card PC motherboard Set-Top Box (STB) Web appliances
4. Ordering information
Table 1. Ordering information Package Name ISP1562BE LQFP100 Description plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm Version SOT407-1 Type number
ISP1562_3
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Product data sheet
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Product data sheet Rev. 03 -- 14 November 2008
(c) NXP B.V. 2008. All rights reserved. ISP1562_3
5. Block diagram
NXP Semiconductors
SCL PME# PCICLK 32 AD[31:0] 99 7 10, 12 to 15, 20 to 22, 26 to 31, 33, 34, 50 to 54, 56, 57, 59, 62, 63, 65 to 70 23, 35, 48, 60 REQ# GNT# IDSEL 32-bit, 33 MHz PCI bus INTA# FRAME# DEVSEL# IRDY# CLKRUN# PAR PERR# SERR# TRDY# STOP# RST# VCC(I/O) VI(VREG3V3) REG1V8 9 8 24 4 36 39 37 CONFIGURATION FUNCTION 0 42 47 44 45 38 41 5 11, 25, 40, 55, 71 16 18, 43, 58 VOLTAGE REGULATOR VCC(I/O) DETECT XTAL1 XTAL2 74 75 XOSC PLL 86, 93 VDDA_AUX 78 OC1_N PWE1_N 79 83 DM1 85 DP1 POR ATX1 VCC CORE ORIGINAL USB ATX Hi-SPEED USB ATX CORE RESET_N PORT ROUTER CONFIGURATION FUNCTION 1 CONFIGURATION FUNCTION 2 RAM RAM CONFIGURATION SPACE OHCI (FUNCTION 0) PCI SLAVE PCI MASTER 96
SDA 97 77, 98, 100 VCC(I/O)_AUX
GLOBAL CONTROL
PCI CORE
C/BE#[3:0]
VOLTAGE REGULATOR (Vaux)
3
VI(VAUX3V3)
ISP1562
Vaux(1V8) core
2, 73
AUX1V8
OHCI (FUNCTION 1)
EHCI (FUNCTION 2) RAM
81
RREF
1, 17, 46, 61, 72, 80, 82, 84, 89, 91
GNDA
ATX2 ORIGINAL USB ATX Hi-SPEED USB ATX 6, 19, 32, 49, 64, 76, 94, 95
GNDD
HS USB PCI host controller
ISP1562
87 OC2_N
88
90 DM2
92
004aaa507
DP2
PWE2_N
3 of 93
Fig 1.
Block diagram
NXP Semiconductors
ISP1562
HS USB PCI host controller
6. Pinning information
6.1 Pinning
100 VCC(I/O)_AUX 98 VCC(I/O)_AUX 77 VCC(I/O)_AUX
93 VDDA_AUX
86 VDDA_AUX
88 PWE2_N
79 PWE1_N
87 OC2_N
78 OC1_N
95 GNDD
94 GNDD
GNDA AUX1V8 VI(VAUX3V3) INTA# RST# GNDD PCICLK GNT# REQ#
1 2 3 4 5 6 7 8 9
76 GNDD
91 GNDA
89 GNDA
80 GNDA
84 GNDA
82 GNDA
99 PME#
81 RREF
90 DM2
83 DM1
97 SDA
96 SCL
92 DP2
85 DP1
75 XTAL2 74 XTAL1 73 AUX1V8 72 GNDA 71 VCC(I/O) 70 AD[0] 69 AD[1] 68 AD[2] 67 AD[3] 66 AD[4] 65 AD[5] 64 GNDD
AD[31] 10 VCC(I/O) 11 AD[30] 12 AD[29] 13 AD[28] 14 AD[27] 15 VI(VREG3V3) 16 GNDA 17 REG1V8 18 GNDD 19 AD[26] 20 AD[25] 21 AD[24] 22 C/BE#[3] 23 IDSEL 24 VCC(I/O) 25 AD[23] 26 AD[22] 27 AD[21] 28 AD[20] 29 AD[19] 30 AD[18] 31 GNDD 32 AD[17] 33 AD[16] 34 C/BE#[2] 35 FRAME# 36 IRDY# 37 TRDY# 38 DEVSEL# 39 VCC(I/O) 40 STOP# 41 CLKRUN# 42 REG1V8 43 PERR# 44 SERR# 45 GNDA 46 PAR 47 C/BE#[1] 48 GNDD 49 AD[15] 50
ISP1562BE
63 AD[6] 62 AD[7] 61 GNDA 60 C/BE#[0] 59 AD[8] 58 REG1V8 57 AD[9] 56 AD[10] 55 VCC(I/O) 54 AD[11] 53 AD[12] 52 AD[13] 51 AD[14]
004aaa508
Fig 2.
Pin configuration
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 14 November 2008
4 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
6.2 Pin description
Table 2. Symbol[1] GNDA AUX1V8 Pin description Pin 1 2 Type Description analog ground 1.8 V auxiliary output voltage; only for voltage conditioning; cannot be used to supply power to external components; connected to 100 nF and 20 F capacitors 3.3 V auxiliary input voltage; add a 100 nF decoupling capacitor PCI interrupt PCI pad; 3.3 V signaling; open-drain RST# 5 I PCI reset; used to bring PCI-specific registers, sequencers and signals to a consistent state 3.3 V input pad; push-pull; CMOS GNDD PCICLK GNT# REQ# 6 7 8 9 I I/O I/O digital ground PCI system clock; see Table 118 PCI pad; 3.3 V signaling PCI grant; indicates to the agent that access to the bus is granted PCI pad; 3.3 V signaling PCI request; indicates to the arbitrator that the agent wants to use the bus PCI pad; 3.3 V signaling AD[31] VCC(I/O) AD[30] AD[29] AD[28] AD[27] VI(VREG3V3) GNDA REG1V8 10 11 12 13 14 15 16 17 18 I/O I/O I/O I/O I/O bit 31 of multiplexed PCI address and data PCI pad; 3.3 V signaling 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor bit 30 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 29 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 28 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 27 of multiplexed PCI address and data PCI pad; 3.3 V signaling 3.3 V regulator input voltage; add a 100 nF decoupling capacitor analog ground 1.8 V regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; connected to a 100 nF capacitor and a 4.7 F-to-10 F capacitor digital ground bit 26 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[25] AD[24] 21 22 I/O I/O bit 25 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 24 of multiplexed PCI address and data PCI pad; 3.3 V signaling
ISP1562_3 (c) NXP B.V. 2008. All rights reserved.
VI(VAUX3V3) INTA#
3 4
O
GNDD AD[26]
19 20
I/O
Product data sheet
Rev. 03 -- 14 November 2008
5 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
Pin description ...continued Pin 23 24 Type I/O I Description byte 3 of multiplexed PCI bus command and byte enable PCI pad; 3.3 V signaling PCI initialization device select; used as a chip select during configuration read and write transactions PCI pad; 3.3 V signaling 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor bit 23 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 22 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 21 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 20 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 19 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 18 of multiplexed PCI address and data PCI pad; 3.3 V signaling digital ground bit 17 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 16 of multiplexed PCI address and data PCI pad; 3.3 V signaling byte 2 of multiplexed PCI bus command and byte enable PCI pad; 3.3 V signaling PCI cycle frame; driven by the master to indicate the beginning and duration of an access PCI pad; 3.3 V signaling PCI initiator ready; indicates the ability of the initiating agent to complete the current data phase of a transaction PCI pad; 3.3 V signaling PCI target ready; indicates the ability of the target agent to complete the current data phase of a transaction PCI pad; 3.3 V signaling PCI device select; indicates if any device is selected on the bus PCI pad; 3.3 V signaling 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor PCI stop; indicates that the current target is requesting the master to stop the current transaction PCI pad; 3.3 V signaling PCI CLKRUN signal; pull-down to ground through a 10 k resistor PCI pad; 3.3 V signaling; open-drain
Table 2. Symbol[1] C/BE#[3] IDSEL
VCC(I/O) AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] GNDD AD[17] AD[16] C/BE#[2] FRAME#
25 26 27 28 29 30 31 32 33 34 35 36
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
IRDY#
37
I/O
TRDY#
38
I/O
DEVSEL# VCC(I/O) STOP#
39 40 41
I/O I/O
CLKRUN#
42
I/O
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 14 November 2008
6 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
Pin description ...continued Pin 43 Type Description 1.8 V regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; add a 100 nF decoupling capacitor PCI parity error; used to report data parity errors during all PCI transactions, except a special cycle PCI pad; 3.3 V signaling PCI system error; used to report address parity errors and data parity errors on the Special Cycle command, or any other system error in which the result will be catastrophic PCI pad; 3.3 V signaling; open-drain analog ground PCI parity PCI pad; 3.3 V signaling byte 1 of multiplexed PCI bus command and byte enable PCI pad; 3.3 V signaling digital ground bit 15 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 14 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 13 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 12 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 11 of multiplexed PCI address and data PCI pad; 3.3 V signaling 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor bit 10 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 9 of multiplexed PCI address and data PCI pad; 3.3 V signaling 1.8 V regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; add a 100 nF decoupling capacitor bit 8 of multiplexed PCI address and data PCI pad; 3.3 V signaling byte 0 of multiplexed PCI bus command and byte enable PCI pad; 3.3 V signaling analog ground bit 7 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 6 of multiplexed PCI address and data PCI pad; 3.3 V signaling
Table 2. Symbol[1] REG1V8
PERR#
44
I/O
SERR#
45
O
GNDA PAR C/BE#[1] GNDD AD[15] AD[14] AD[13] AD[12] AD[11] VCC(I/O) AD[10] AD[9] REG1V8
46 47 48 49 50 51 52 53 54 55 56 57 58
I/O I/O I/O I/O I/O I/O I/O I/O I/O -
AD[8] C/BE#[0] GNDA AD[7] AD[6]
59 60 61 62 63
I/O I/O I/O I/O
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 14 November 2008
7 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
Pin description ...continued Pin 64 65 66 67 68 69 70 71 72 73 Type I/O I/O I/O I/O I/O I/O Description digital ground bit 5 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 4 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 3 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 2 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 1 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 0 of multiplexed PCI address and data PCI pad; 3.3 V signaling 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor analog ground 1.8 V auxiliary output voltage; only for voltage conditioning; cannot be used to supply power to external components; add a 100 nF decoupling capacitor crystal oscillator input; this can also be a 12 MHz clock input crystal oscillator output (12 MHz); leave open when clock is used digital ground 3.3 V auxiliary supply voltage; used to power pads; add a 100 nF decoupling capacitor overcurrent sense input for the USB downstream port 1 (digital) 3.3 V input pad; push-pull; CMOS power enable for the USB downstream port 1 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain analog ground analog connection for the external resistor (12 k 1 %) analog ground D-; analog connection for the USB downstream port 1; pull-down to ground through a 15 k resistor analog ground D+; analog connection for the USB downstream port 1; pull-down to ground through a 15 k resistor auxiliary analog supply voltage; add a 100 nF decoupling capacitor overcurrent sense input for the USB downstream port 2 (digital) 3.3 V input pad; push-pull; CMOS power enable for the USB downstream port 2 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain analog ground
Table 2. Symbol[1] GNDD AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] VCC(I/O) GNDA AUX1V8
XTAL1 XTAL2 GNDD
74 75 76
AI AO I O AI/O AI/O AI/O I O -
VCC(I/O)_AUX 77 OC1_N PWE1_N GNDA RREF GNDA DM1 GNDA DP1 VDDA_AUX OC2_N PWE2_N GNDA 78 79 80 81 82 83 84 85 86 87 88 89
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 14 November 2008
8 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
Pin description ...continued Pin 90 91 92 93 94 95 96 97 Type AI/O AI/O I/O I/O O Description D-; analog connection for the USB downstream port 2; pull-down to ground through a 15 k resistor analog ground D+; analog connection for the USB downstream port 2; pull-down to ground through a 15 k resistor auxiliary analog supply voltage; add a 100 nF decoupling capacitor digital ground digital ground I2C-bus clock; pull-up to 3.3 V through a 10 k resistor[2] I2C-bus pad; clock signal I2C-bus data; pull-up to 3.3 V through a 10 k resistor[2] I2C-bus pad; data signal 3.3 V auxiliary supply voltage; used to power pads; add a 100 nF decoupling capacitor PCI Power Management Event; used by a device to request a change in the device or system power state PCI pad; 3.3 V signaling; open-drain 3.3 V auxiliary supply voltage; used to power pads; add a 100 nF decoupling capacitor
Table 2. Symbol[1] DM2 GNDA DP2 VDDA_AUX GNDD GNDD SCL SDA
VCC(I/O)_AUX 98 PME# 99
VCC(I/O)_AUX 100
-
[1] [2]
Symbol names ending with # represent active LOW signals for PCI pins, for example: NAME#. Symbol names ending with underscore N represent active LOW signals for USB pins, for example: NAME_N. Connect to ground if I2C-bus is not used.
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 14 November 2008
9 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
7. Functional description
7.1 OHCI host controller
An OHCI host controller per port transfers data to devices at the Original USB defined bit rate of 12 Mbit/s or 1.5 Mbit/s.
7.2 EHCI host controller
The EHCI host controller transfers data to a Hi-Speed USB compliant device at the Hi-Speed USB defined bit rate of 480 Mbit/s. When the EHCI host controller has the ownership of a port, OHCI host controllers are not allowed to modify the port register. All additional port bit definitions required for the enhanced host controller are not visible to the OHCI host controller.
7.3 Dynamic port-routing logic
The port-routing feature allows sharing of the same physical downstream ports between the Original USB host controller and the Hi-Speed USB host controller. This requirement of Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 provides ports that are multiplexed with the ports of the OHCI. The EHCI is responsible for the port-routing switching mechanism. Two register bits are used for ownership switching. During power-on and system reset, the default ownership of all downstream ports is the OHCI. The enhanced Host Controller Driver (HCD) controls the ownership during normal functionality.
7.4 Hi-Speed USB analog transceivers
The Hi-Speed USB analog transceivers directly interface to the USB cables through integrated termination resistors. These transceivers can transmit and receive serial data at all data rates: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s).
7.5 Power management
The ISP1562 provides an advanced power management capability interface that is compliant with PCI Bus Power Management Interface Specification Rev. 1.1. Power is controlled and managed by the interaction between drivers and PCI registers. For a detailed description on power management, see Section 10.
7.6 Phase-Locked Loop (PLL)
A 12 MHz-to-30 MHz and 48 MHz clock multiplier PLL is integrated on-chip. This allows the use of a low-cost 12 MHz crystal, which also minimizes EMI. No external components are required for the PLL to operate.
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
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10 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
7.7 Power-On Reset (POR)
Figure 3 shows a possible curve of VI(VAUX3V3) and VI(VREG3V3) with dips at t2 to t3 and t4 to t5. At t0, POR will start with 1. At t1, the detector passes through the trip level. Another delay will be added before POR drops to 0 to ensure that the length of the generated detector pulse, POR, is large enough to reset asynchronous flip-flops. If the dip is too short (t4 to t5 < 11 s), POR will not react and will stay LOW.
VI(VAUX3V3), VI(VREG3V3) VPOR(trip)
t0
t1
t2
t3
t4
t5 POR
004aab194
VPOR(trip) is typically 0.9 V.
Fig 3.
Power-on reset
7.8 Power supply
Figure 4 shows the ISP1562 power supply connection.
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 14 November 2008
11 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
ISP1562
16 VI(VREG3V3) PCI 3.3 V
100 nF
11, 25, 40, 55, 71
VCC(I/O)
100 nF
PCI 3.3 V
VI(VAUX3V3) 3
100 nF
PCI Vaux(3V3)(1)
VCC(I/O)_AUX 77, 98, 100
100 nF
PCI Vaux(3V3)(1)
VDDA_AUX 86, 93
100 nF
PCI Vaux(3V3)(1)
AUX1V8 2
20 F(2) 100 nF
AUX1V8 73
100 nF
18
REG1V8
4.7 F(2((3) 100 nF
43, 58
REG1V8
100 nF
1, 6, 17, 19, 32, 46, 49, 61, 64, 72, 76, 80, 82, 84, 89, 91, 94, 95
GND
004aaa665
(1) If Vaux(3V3) is not present on PCI, the pin must be connected to PCI 3.3 V. (2) This electrolytic or tantalum capacitor must be of LOW ESR type (0.2 to 2 ). (3) In ISP1562_1 data sheet, the electrolytic or tantalum capacitor value was mentioned as 20 F. This value was reduced to 4.7 F in ISP1562_2. In older designs, if it is not possible to change the capacitor value, it is OK to retain 20 F, and it does not cause any problem. The value was changed to reduce the capacitor size.
Fig 4.
Power supply connection
8. PCI
8.1 PCI interface
The PCI interface has three functions. The first function (#0) and the second function (#1) are for OHCI host controllers, and the third function (#2) is for the EHCI host controller. All functions support both master and target accesses, and share the same PCI interrupt
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
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12 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
signal INTA#. These functions provide memory-mapped, addressable operational registers as required in Open Host Controller Interface Specification for USB Rev. 1.0a and Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. Each function has its own configuration space. The PCI enumerator must allocate the memory address space for each of these functions. Power management is implemented in each PCI function and all power states are provided. This allows the system to achieve low power consumption by switching off the functions that are not required.
8.1.1 PCI configuration space
PCI Local Bus Specification Rev. 2.2 requires that each of the three PCI functions of the ISP1562 provides its own PCI configuration registers, which can vary in size. In addition to the basic PCI configuration header registers, these functions implement capability registers to support power management.
The registers of each of these functions are accessed by the respective driver. Section 8.2 provides a detailed description of various PCI configuration registers.
8.1.2 PCI initiator and target
A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI transactions as a slave. In the ISP1562, two open host controllers and the enhanced host controller function as both initiators or targets of PCI transactions issued by the host CPU. All USB host controllers have their own operational registers that can be accessed by the system driver software. Drivers use these registers to configure the host controller hardware system, issue commands to it, and monitor the status of the current hardware operation. The host controller plays the role of a PCI target. All operational registers of the host controllers are the PCI transaction targets of the CPU. Normal USB transfers require the host controller to access system memory fields, which are allocated by USB HCDs and PCI drivers. The host controller hardware interacts with the HCD by accessing these buffers. The host controller works as an initiator in this case and becomes a PCI master.
8.2 PCI configuration registers
OHCI USB host controllers and the EHCI USB host controller contain two sets of software-accessible hardware registers: PCI configuration registers and memory-mapped host controller registers. A set of configuration registers is implemented for each of the three PCI functions of the ISP1562, see Table 3. Remark: In addition to the normal PCI header, from offset index 00h to 3Fh, implementation-specific registers are defined to support power management and function-specific features.
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
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NXP Semiconductors
ISP1562
HS USB PCI host controller
Table 3. Address
PCI configuration space registers of OHCI1, OHCI2 and EHCI Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Bits 7 to 0 Reset value[1] Func0 OHCI1 Func1 OHCI2 Func2 EHCI 1562 1131h 0210 0000h 0C03 2011h 0080 0000h 0000 0000h
PCI configuration header registers 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h MAX_LAT [7:0] SID[15:0] reserved reserved reserved MIN_GNT [7:0] IP[7:0] RETRY_ TIMEOUT FLADJ[7:0] IL[7:0] TRDY_ TIMEOUT SBRN[7:0] CP[7:0] SVID[15:0] 1561 1131h 0000 0000h 0000 00DCh 0000 0000h 2A01 0100h 0000 8000h 1561 1131h 0000 0000h 0000 00DCh 0000 0000h 2A01 0100h 0000 8000h 1562 1131h 0000 0000h 0000 00DCh 0000 0000h 1002 0100h 0000 8000h reserved 0000 0000h 0000 0000h 0000 0000h reserved DID[15:0] STATUS[15:0] CC[23:0] HT[7:0] LT[7:0] BAR0[31:0] VID[15:0] CMD[15:0] REVID[7:0] CLS[7:0] 1561 1131h 0210 0000h 0C03 1011h 0080 0000h 0000 0000h 1561 1131h 0210 0000h 0C03 1011h 0080 0000h 0000 0000h
reserved
Enhanced host controller-specific PCI registers 60h DCh E0h PORTWAKECAP[15:0] PMC[15:0] DATA[7:0] PMCSR_BSE [7:0] D282 0001h 0007 2020h FE82 0001h 0000 XX00h[2] Power management registers NEXT_ITEM_ CAP_ID[7:0] D282 0001h PTR[7:0] PMCSR[15:0]
0000 XX00h[2] 0000 XX00h[2]
[1] [2]
Reset values that are highlighted (for example, 0) indicate read and write accesses; and reset values that are not highlighted (for example, 0) indicate read-only. See Section 8.2.3.4.
The HCD does not usually interact with the PCI configuration space. The configuration space is used only by the PCI enumerator to identify the USB host controller and assign appropriate system resources by reading the Vendor ID (VID) and the Device ID (DID).
8.2.1 PCI configuration header registers
The enhanced host controller implements normal PCI header register values, except the values for the memory-mapping base address register, serial bus number and device ID. 8.2.1.1 Vendor ID register This read-only register identifies the manufacturer of the device. PCI Special Interest Group (PCI-SIG) assigns valid vendor identifiers to ensure the uniqueness of the identifier. The bit description is shown in Table 4.
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Table 4. VID - Vendor ID register (address 00h) bit description Legend: * reset value Bit 15 to 0 Symbol VID[15:0] Access Value R 1131h* Description Vendor ID: This read-only register value is assigned to NXP Semiconductors by PCI-SIG as 1131h.
8.2.1.2
Device ID register This is a 2-byte read-only register that identifies a particular device. The identifier is allocated by NXP Semiconductors. Table 5 shows the bit description of the register.
Table 5. DID - Device ID register (address 02h) bit description Legend: * reset value Bit 15 to 0 Symbol DID[15:0] Access R Value X*[1] Description Device ID: This register value is defined by NXP Semiconductors to identify the Hi-Speed USB host controller IC product. For the ISP1562, NXP Semiconductors has defined OHCI functions as 1561h, and the EHCI function as 1562h.
[1]
X is 1561h for OHCI1 and OHCI2; X is 1562h for EHCI.
8.2.1.3
Command register This is a 2-byte register that provides coarse control over the ability of a device to generate and respond to PCI cycles. The bit allocation of the Command register is given in Table 6. When logic 0 is written to this register, the device is logically disconnected from the PCI bus for all accesses, except configuration accesses. All devices are required to support this base level of functionality. Individual bits in the Command register may or may not support this base level of functionality.
Table 6. Bit Symbol Reset Access Bit Symbol Reset Access
[1]
CMD - Command register (address 04h) bit allocation 15 0 R/W 7 SCTRL 0 R 14 0 R/W 6 PER 0 R/W 13 reserved[1] 0 R/W 5 VGAPS 0 R 0 R/W 4 MWIE 0 R/W 0 R/W 3 SC 0 R 0 R/W 2 BM 0 R/W 12 11 10 9 FBBE 0 R/W 1 MS 0 R/W 8 SERRE 0 R/W 0 IOS 0 R/W
The reserved bits should always be written with the reset value.
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Table 7. Bit 15 to 10 9
CMD - Command register (address 04h) bit description Symbol reserved FBBE Description Fast Back-to-Back Enable: This bit controls whether a master can do fast back-to-back transactions to various devices. The initialization software must set this bit if all targets are fast back-to-back capable. 0 -- Fast back-to-back transactions are only allowed to the same agent (value after RST#). 1 -- The master is allowed to generate fast back-to-back transactions to different agents.
8
SERRE
SERR# Enable: This bit is an enable bit for the SERR# driver. All devices that have an SERR# pin must implement this bit. Address parity errors are reported only if this bit and the PER bit are logic 1. 0 -- Disable the SERR# driver. 1 -- Enable the SERR# driver.
7
SCTRL
Stepping Control: This bit controls whether a device does address and data stepping. Devices that never do stepping must clear this bit. Devices that always do stepping must set this bit. Devices that can do either, must make this bit read and write, and initialize it to logic 1 after RST#. Parity Error Response: This bit controls the response of a device to parity errors. When the bit is set, the device must take its normal action when a parity error is detected. When the bit is logic 0, the device sets DPE (bit 15 in the Status register) when an error is detected, but does not assert PERR# and continues normal operation. The state of this bit after RST# is logic 0. Devices that check parity must implement this bit. Devices are required to generate parity, even if parity checking is disabled. VGA Palette Snoop: This bit controls how VGA compatible and graphics devices handle accesses to VGA palette registers. 0 -- The device must treat palette write accesses like all other accesses. 1 -- Palette snooping is enabled, that is, the device does not respond to palette register writes and snoops data. VGA compatible devices must implement this bit.
6
PER
5
VGAPS
4
MWIE
Memory Write and Invalidate Enable: This is an enable bit for using the Memory Write and Invalidate command. 0 -- Memory writes must be used instead. State after RST# is logic 0. 1 -- Masters may generate the command. This bit must be implemented by master devices that can generate the Memory Write and Invalidate command.
3
SC
Special Cycles: Controls the action of a device on special cycle operations. 0 -- Causes the device to ignore all special cycle operations. State after RST# is logic 0. 1 -- Allows the device to monitor special cycle operations.
2
BM
Bus Master: Controls the ability of a device to act as a master on the PCI bus. 0 -- Disables the device from generating PCI accesses. State after RST# is logic 0. 1 -- Allows the device to behave as a bus master.
1
MS
Memory Space: Controls the response of a device to memory space accesses. 0 -- Disables the device response. State after RST# is logic 0. 1 -- Allows the device to respond to memory space accesses.
0
IOS
IO Space: Controls the response of a device to I/O space accesses. 0 -- Disables the device response. State after RST# is logic 0. 1 -- Allows the device to respond to I/O space accesses.
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8.2.1.4
Status register The Status register is a 2-byte read-only register used to record status information on PCI bus-related events. For bit allocation, see Table 8.
Table 8. Bit Symbol Reset Access Bit Symbol Reset Access Table 9. Bit 15 14 13 12 11 10 to 9
STATUS - Status register (address 06h) bit allocation 15 DPE 0 R 7 FBBC 0 R 14 SSE 0 R 6 reserved 0 R 13 RMA 0 R 5 66MC 0 R 12 RTA 0 R 4 CL 1 R 0 R 0 R 11 STA 0 R 3 10 0 R 2 reserved 0 R 0 R 9 1 R 1 8 MDPE 0 R 0 DEVSELT[1:0]
STATUS - Status register (address 06h) bit description Symbol DPE SSE RMA RTA STA DEVSELT [1:0] Description Detected Parity Error: This bit must be set by the device whenever it detects a parity error, even if the parity error handling is disabled. Signaled System Error: This bit must be set whenever the device asserts SERR#. Devices that never assert SERR# do not need to implement this bit. Received Master Abort: This bit must be set by a master device whenever its transaction, except for special cycle, is terminated with master abort. All master devices must implement this bit. Received Target Abort: This bit must be set by a master device whenever its transaction is terminated with target abort. All master devices must implement this bit. Signaled Target Abort: This bit must be set by a target device whenever it terminates a transaction with target abort. Devices that never signal target abort do not need to implement this bit. DEVSEL Timing: These bits encode the timing of DEVSEL#. There are three allowable timing to assert DEVSEL#: 00b -- Fast 01b -- Medium 10b -- Slow 11b -- Reserved These bits are read-only and must indicate the slowest time that a device asserts DEVSEL# for any bus command, except Configuration Read and Configuration Write.
8
MDPE
Master Data Parity Error: This bit is implemented by bus masters. It is set when the following three conditions are met:
* * *
7 FBBC
The bus agent asserted PERR# itself, on a read; or observed PERR# asserted, on a write. The agent setting the bit acted as the bus master for the operation in which error occurred. PER (bit 6 in the Command register) is set.
Fast Back-to-Back Capable: This read-only bit indicates whether the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to logic 1, if the device can accept these transactions; and must be set to logic 0 otherwise. -
6
reserved
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Table 9. Bit 5
STATUS - Status register (address 06h) bit description ...continued Symbol 66MC Description 66 MHz Capable: This read-only bit indicates whether this device is capable of running at 66 MHz. 0 -- 33 MHz 1 -- 66 MHz
4
CL
Capabilities List: This read-only bit indicates whether this device implements the pointer for a new capabilities linked list at offset 34h. 0 -- No new capabilities linked list is available. 1 -- The value read at offset 34h is a pointer in configuration space to a linked list of new capabilities.
3 to 0
reserved
-
8.2.1.5
Revision ID register This 1-byte read-only register indicates a device-specific revision identifier. The value is chosen by the vendor. This field is a vendor-defined extension of the device ID. The Revision ID register bit description is given in Table 10.
Table 10. REVID - Revision ID register (address 08h) bit description Legend: * reset value Bit 7 to 0 Symbol Access Value 11h* Description Revision ID: This byte specifies the design revision number of functions. REVID[7:0] R
8.2.1.6
Class Code register Class Code is a 24-bit read-only register used to identify the generic function of the device, and in some cases, a specific register-level programming interface. Table 11 shows the bit allocation of the register. The Class Code register is divided into three byte-size fields. The upper byte is a base class code that broadly classifies the type of function the device performs. The middle byte is a sub-class code that identifies more specifically the function of the device. The lower byte identifies a specific register-level programming interface, if any, so that device-independent software can interact with the device.
Table 11. Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
CC - Class Code register (address 09h) bit allocation 23 22 21 20 BCC[7:0] 0Ch R 15 R 14 R 13 R 12 SCC[7:0] 03h R 7 R 6 R 5 R 4 RLPI[7:0] X[1] R R R R R R R R R 3 R 2 R 1 R 0 R 11 R 10 R 9 R 8 19 18 17 16
X is 10h for OHCI1 and OHCI2; X is 20h for EHCI.
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Table 12. Bit 15 to 8 7 to 0
CC - Class Code register (address 09h) bit description Symbol SCC[7:0] RLPI[7:0] Description Base Class Code: 0Ch is the base class code assigned to this byte. It implies a serial bus controller. Sub-Class Code: 03h is the sub-class code assigned to this byte. It implies the USB host controller. Register-Level Programming Interface: 10h is the programming interface code assigned to OHCI, which is USB 1.1 specification compliant. 20h is the programming interface code assigned to EHCI, which is USB 2.0 specification compliant.
23 to 16 BCC[7:0]
8.2.1.7
CacheLine Size register The CacheLine Size register is a read and write single-byte register that specifies the system CacheLine size in units of DWORDs. This register must be implemented by master devices that can generate the Memory Write and Invalidate command. The value in this register is also used by master devices to determine whether to use Read, Read Line or Read Multiple command to access the memory. Slave devices that want to allow memory bursting using CacheLine-wrap addressing mode must implement this register to know when a burst sequence wraps to the beginning of the CacheLine. This field must be initialized to logic 0 on activation of RST#. Table 13 shows the bit description of the CacheLine Size register.
Table 13. CLS - CacheLine Size register (address 0Ch) bit description Legend: * reset value Bit 7 to 0 Symbol CLS[7:0] Access R/W Value 00h* Description CacheLine Size: This byte identifies the system CacheLine size.
8.2.1.8
Latency Timer register This register specifies, in units of PCI bus clocks, the value of the Latency Timer for the PCI bus master. Table 14 shows the bit description of the Latency Timer register.
Table 14. LT - Latency Timer register (address 0Dh) bit description Legend: * reset value Bit 7 to 0 Symbol LT[7:0] Access R/W Value 00h* Description Latency Timer: This byte identifies the latency timer.
8.2.1.9
Header Type register The Header Type register identifies the layout of the second part of the predefined header, beginning at byte 10h in configuration space. It also identifies whether the device contains multiple functions. For bit allocation, see Table 15.
Table 15. Bit Symbol Reset Access
HT - Header Type register (address 0Eh) bit allocation 7 MFD 1 R 0 R 0 R 0 R 6 5 4 3 HT[6:0] 0 R 0 R 0 R 0 R 2 1 0
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Table 16. Bit 7
HT - Header Type register (address 0Eh) bit description Symbol MFD Description Multi-Function Device: This bit identifies a multifunction device. 0 -- The device has single function. 1 -- The device has multiple functions.
6 to 0
HT[6:0]
Header Type: These bits identify the layout of the part of the predefined header, beginning at byte 10h in configuration space.
8.2.1.10
Base Address register 0 Power-up software must build a consistent address map before booting the machine to an operating system. This means it must determine how much memory is in the system, and how much address space the I/O controllers in the system require. After determining this information, power-up software can map the I/O controllers into reasonable locations and proceed with system boot. To do this mapping in a device-independent manner, base registers for this mapping are placed in the predefined header portion of configuration space. Bit 0 in all Base Address registers is read-only and used to determine whether the register maps into memory or I/O space. Base Address registers that map to memory space must return logic 0 in bit 0. Base Address registers that map to I/O space must return logic 1 in bit 0. The bit description of the BAR0 register is given in Table 17.
Table 17. BAR0 - Base Address register 0 (address 10h) bit description Legend: * reset value Bit 31 to 0 Symbol BAR0[31:0] Access R/W Value 0000 0000h* Description Base Address to Memory-Mapped Host Controller Register Space: The memory size required by OHCI and EHCI are 4 kB and 256 bytes, respectively. Therefore, BAR0[31:12] is assigned to the two OHCI ports, and BAR0[31:8] is assigned to the EHCI port.
8.2.1.11
Subsystem Vendor ID register The Subsystem Vendor ID register is used to uniquely identify the expansion board or subsystem where the PCI device resides. This register allows expansion board vendors to distinguish their boards, even though the boards may have the same vendor ID and device ID. Subsystem vendor IDs are assigned by PCI-SIG to maintain uniqueness. The bit description of the Subsystem Vendor ID register is given in Table 18.
Table 18. SVID - Subsystem Vendor ID register (address 2Ch) bit description Legend: * reset value Bit 15 to 0 Symbol Access Value 1131h* Description Subsystem Vendor ID: 1131h is the subsystem Vendor ID assigned to NXP Semiconductors. SVID[15:0] R
8.2.1.12
Subsystem ID register Subsystem ID values are vendor specific. The bit description of the Subsystem ID register is given in Table 19.
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Table 19. SID - Subsystem ID register (address 2Eh) bit description Legend: * reset value Bit 15 to 0 Symbol SID[15:0] Access R Value X*[1] Description Subsystem ID: For the ISP1562, NXP Semiconductors has defined OHCI functions as 1561h, and the EHCI function as 1562h.
[1]
X is 1561h for OHCI1 and OHCI2; X is 1562h for EHCI.
8.2.1.13
Capabilities Pointer register This register is used to point to a linked list of new capabilities implemented by the device. This register is only valid if CL (bit 4 in the Status register) is set. If implemented, bit 1 and bit 0 are reserved and must be set to 00b. Software must mask these bits off before using this register as a pointer in configuration space to the first entry of a linked list of new capabilities. The bit description of the register is given in Table 20.
Table 20. CP - Capabilities Pointer register (address 34h) bit description Legend: * reset value Bit 7 to 0 Symbol CP[7:0] Access R Value DCh* Description Capabilities Pointer: EHCI efficiently manages power using this register. This Power Management register is allocated at offset DCh. Only one host controller is needed to manage power in the ISP1562.
8.2.1.14
Interrupt Line register This is a 1-byte register used to communicate interrupt line routing information. This register must be implemented by any device or device function that uses an interrupt pin. The interrupt allocation is done by the BIOS. The POST software needs to write the routing information to this register because it initializes and configures the system. The value in this register specifies which input of the system interrupt controller(s) the interrupt pin of the device is connected. This value is used by device drivers and operating systems to determine priority and vector information. Values in this register are system architecture specific. The bit description of the register is given in Table 21.
Table 21. IL - Interrupt Line register (address 3Ch) bit description Legend: * reset value Bit 7 to 0 Symbol IL[7:0] Access R/W Value 00h* Description Interrupt Line: Indicates which IRQ is used to report interrupt from the ISP1562.
8.2.1.15
Interrupt Pin register This 1-byte register is use to specify which interrupt pin the device or device function uses. Devices or functions that do not use the interrupt pin must set this register to logic 0. The bit description is given in Table 22.
Table 22. IP - Interrupt Pin register (address 3Dh) bit description Legend: * reset value Bit 7 to 0 Symbol IP[7:0] Access R Value 01h* Description Interrupt Pin: INTA# is the default interrupt pin used by the ISP1562.
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8.2.1.16
MIN_GNT and MAX_LAT registers The Minimum Grant (MIN_GNT) and Maximum Latency (MAX_LAT) registers are used to specify the desired settings of the device for latency timer values. For both registers, the value specifies a period of time in units of 250 ns. Logic 0 indicates that the device has no major requirements for setting latency timers. The MIN_GNT register bit description is given in Table 23.
Table 23. MIN_GNT - Minimum Grant register (address 3Eh) bit description Legend: * reset value Bit 7 to 0 Symbol Access Value X*[1] Description MIN_GNT: It is used to specify how long a burst period the device needs, assuming a clock rate of 33 MHz. MIN_GNT[7:0] R
[1]
X is 01h for OHCI1 and OHCI2; X is 02h for EHCI.
The MAX_LAT register bit description is given in Table 24.
Table 24. MAX_LAT - Maximum Latency register (address 3Fh) bit description Legend: * reset value Bit 7 to 0 Symbol MAX_LAT[7:0] Access R Value X*[1] Description MAX_LAT: It is used to specify how often the device needs to gain access to the PCI bus.
[1]
X is 2Ah for OHCI1 and OHCI2; X is 10h for EHCI.
8.2.1.17
TRDY_TIMEOUT - TRDY Timeout register This is a read and write register at address 40h. The default and recommended value is 00h, TRDY time-out disabled. This value can, however, be modified. It is an implementation-specific register, and not a standard PCI configuration register. The TRDY timer is 13 bits: the lower 5 bits are fixed as logic 0, and the upper 8 bits are determined by the TRDY Timeout register value. The time-out is calculated by multiplying the 13-bit timer with the PCICLK cycle time. This register determines the maximum TRDY delay, without asserting the UE (Unrecoverable Error) bit. If TRDY is longer than the delay determined by this register value, then the UE bit will be set.
8.2.1.18
RETRY_TIMEOUT - Retry Timeout register The default value of this read and write register is 80h, and is located at address 41h. This value can, however, be modified. Programming this register as 00h means that retry time-out is disabled. This is an implementation-specific register, and not a standard PCI configuration register. The time-out is determined by multiplying the register value with the PCICLK cycle time. This register determines the maximum number of PCI retires before the UE bit is set. If the number of retries is longer than the delay determined by this register value, then the UE bit will be set.
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8.2.2 Enhanced host controller-specific PCI registers
In addition to the PCI configuration header registers, EHCI needs some additional PCI configuration space registers to indicate the serial bus release number, downstream port wake-up event capability, and adjust the USB bus frame length for Start-Of-Frame (SOF). The EHCI-specific PCI registers are given in Table 25.
Table 25. Offset 60h 61h 62h to 63h EHCI-specific PCI registers Register Serial Bus Release Number (SBRN) Frame Length Adjustment (FLADJ) Port Wake Capability (PORTWAKECAP)
8.2.2.1
SBRN register The Serial Bus Release Number (SBRN) register is a 1-byte register, and the bit description is given in Table 26. This register contains the release number of the USB specification with which this USB host controller module is compliant.
Table 26. SBRN - Serial Bus Release Number register (address 60h) bit description Legend: * reset value Bit 7 to 0 Symbol SBRN[7:0] Access R Value 20h* Description Serial Bus Specification Release Number: This register value is to identify Universal Serial Bus Specification Rev. 2.0. All other combinations are reserved.
8.2.2.2
FLADJ register This feature is used to adjust any offset from the clock source that generates the clock that drives the SOF counter. When a new value is written to these six bits, the length of the frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is given in Table 27.
Table 27. Bit Symbol Reset Access
[1]
FLADJ - Frame Length Adjustment register (address 61h) bit allocation 7 reserved[1] 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 6 5 4 3 FLADJ[5:0] 0 R/W 0 R/W 0 R/W 2 1 0
The reserved bits should always be written with the reset value.
Table 28. Bit 7 to 6 5 to 0
FLADJ - Frame Length Adjustment register (address 61h) bit description Symbol reserved FLADJ[5:0] Description Frame Length Timing Value: Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time, number of SOF counter clock periods to generate a SOF microframe length, is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000; see Table 29.
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FLADJ value as a function of SOF cycle time SOF cycle time (480 MHz) 59488 59504 59520 : 59984 60000 : 60480 60496
Table 29. 0 (00h) 1 (01h) 2 (02h) : 31 (1Fh) 32 (20h) : 62 (3Eh) 63 (3Fh)
FLADJ value
8.2.2.3
PORTWAKECAP register Port Wake Capability (PORTWAKECAP) is a 2-byte register used to establish a policy about which ports are for wake events; see Table 30. Bit positions 15 to 1 in the mask correspond to a physical port implemented on the current EHCI controller. Logic 1 in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect or connect, or overcurrent events as wake-up events. This is an information only mask register. The bits in this register do not affect the actual operation of the EHCI host controller. The system-specific policy can be established by BIOS initializing this register to a system-specific value. The system software uses the information in this register when enabling devices and ports for remote wake-up.
Table 30. PORTWAKECAP - Port Wake Capability register (address 62h) bit description Legend: * reset value Bit Symbol Access R/W Value 0007h* Description Port Wake-Up Capability Mask: EHCI does not implement this feature. 15 to 0 PORTWAKE CAP[15:0]
8.2.3 Power management registers
Table 31. Offset Value read from address 34h + 0h Value read from address 34h + 1h Value read from address 34h + 2h Value read from address 34h + 4h Value read from address 34h + 6h Value read from address 34h + 7h Power management registers Register Capability Identifier (CAP_ID) Next Item Pointer (NEXT_ITEM_PTR) Power Management Capabilities (PMC) Power Management Control/Status (PMCSR) Power Management Control/Status PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) Data
8.2.3.1
CAP_ID register The Capability Identifier (CAP_ID) register when read by the system software as 01h indicates that the data structure currently being pointed to is the PCI power management data structure. Each function of a PCI device may have only one item in its capability list with CAP_ID set to 01h. The bit description of the register is given in Table 32.
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Table 32. CAP_ID - Capability Identifier register bit description Address: Value read from address 34h + 0h Legend: * reset value Bit 7 to 0 Symbol CAP_ID[7:0] Access R Value 01h* Description ID: This field when 01h identifies the linked list item as being PCI Power Management registers.
8.2.3.2
NEXT_ITEM_PTR register The Next Item Pointer (NEXT_ITEM_PTR) register describes the location of the next item in the function's capability list. The value given is an offset into the function's PCI configuration space. If the function does not implement any other capabilities defined by the PCI-SIG for inclusion in the capabilities list, or if power management is the last item in the list, then this register must be set to 00h. See Table 33.
Table 33. NEXT_ITEM_PTR - Next Item Pointer register bit description Address: Value read from address 34h + 1h Legend: * reset value Bit 7 to 0 Symbol NEXT_ITEM_ PTR[7:0] Access R Value 00h* Description Next Item Pointer: This field provides an offset into the function's PCI configuration space, pointing to the location of the next item in the function's capability list. If there are no additional items in the capabilities list, this register is set to 00h.
8.2.3.3
PMC register The Power Management Capabilities (PMC) register is a 2-byte register, and the bit allocation is given in Table 34. This register provides information on the capabilities of the function related to power management.
Table 34. PMC - Power Management Capabilities register bit allocation Address: Value read from address 34h + 2h Bit Symbol Reset Access Bit Symbol Reset Access
[1]
15 1 R 7
14 1 R 6
13 PME_S[4:0] X[1] R 5 DSI 0 R
12 1 R 4 reserved 0 R
11 X[1] R 3 PMI 0 R
10 D2_S X[1] R 2 0 R
9 D1_S 1 R 1 VER[2:0] 1 R
8 AUX_C 0 R 0 0 R
AUX_C[1:0] 1 R 0 R
X is 0 for OHCI1 and OHCI2; X is 1 for EHCI.
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Table 35. PMC - Power Management Capabilities register bit description Address: Value read from address 34h + 2h Bit 15 to 11 Symbol PME_S [4:0] Description PME Support: These bits indicate the power states in which the function may assert PME#. Logic 0 for any bit indicates that the function is not capable of asserting the PME# signal while in that power state. PME_S[0] -- PME# can be asserted from D0 PME_S[1] -- PME# can be asserted from D1 PME_S[2] -- PME# can be asserted from D2 PME_S[3] -- PME# can be asserted from D3hot PME_S[4] -- PME# can be asserted from D3cold 10 9 8 to 6 D2_S D1_S AUX_C [2:0] D2_Support: If this bit is logic 1, this function supports the D2 power management state. Functions that do not support D2 must always return logic 0 for this bit. D1_Support: If this bit is logic 1, this function supports the D1 power management state. Functions that do not support D1 must always return logic 0 for this bit. Auxiliary Current: This three-bit field reports the Vaux(3V3) auxiliary current requirements for the PCI function. If the Data register is implemented by this function:
* *
A read from this field needs to return a value of 000b. The Data register takes precedence over this field for Vaux(3V3) current requirement reporting.
If the PME# generation from D3cold is not supported by the function (PMC[15] = 0), this field must return a value of 000b when read. For functions that support PME# from D3cold and do not implement the Data register, bit assignments corresponding to the maximum current required for Vaux(3V3) are: 111b -- 375 mA 110b -- 320 mA 101b -- 270 mA 100b -- 220 mA 011b -- 160 mA 010b -- 100 mA 001b -- 55 mA 000b -- 0 (self-powered) 5 DSI Device Specific Initialization: This bit indicates whether special initialization of this function is required, beyond the standard PCI configuration header, before the generic class device driver can use it. This bit is not used by some operating systems. For example, Microsoft Windows and Windows NT do not use this bit to determine whether to use D3. Instead, it is determined using the capabilities of the driver. Logic 1 indicates that the function requires a device-specific initialization sequence, following transition to D0 uninitialized state. 4 3 reserved PMI PME Clock: 0 -- Indicates that no PCI clock is required for the function to generate PME#. 1 -- Indicates that the function relies on the presence of the PCI clock for the PME# operation. Functions that do not support the PME# generation in any state must return logic 0 for this field. 2 to 0 VER[2:0] Version: A value of 010b indicates that this function complies with PCI Bus Power Management Interface Specification Rev. 1.1.
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HS USB PCI host controller
8.2.3.4
PMCSR register The Power Management Control/Status (PMCSR) register is a 2-byte register used to manage the power management state of the PCI function, as well as to allow and monitor Power Management Events (PMEs). The bit allocation of the register is given in Table 36.
Table 36. PMCSR - Power Management Control/Status register bit allocation Address: Value read from address 34h + 4h Bit Symbol Reset Access Bit Symbol Reset Access
[1] [2]
15 PMES X[1] R/W 7 0 R/W
14 DS[1:0] 0 R 6 0 R/W
13 0 R 5 reserved[2] 0 R/W
12 0 R/W 4 0 R/W
11 D_S[3:0] 0 R/W 3 0 R/W
10 0 R/W 2 0 R/W
9 0 R/W 1 PS[1:0] 0 R/W
8 PMEE X[1] R/W 0 0 R/W
Sticky bit, if the function supports PME# from D3cold, then X is indeterminate at the time of initial operating system boot; X is 0 if the function does not support PME# from D3cold. The reserved bits should always be written with the reset value.
Table 37. PMCSR - Power Management Control/Status register bit description Address: Value read from address 34h + 4h Bit 15 Symbol PMES Description PME Status: This bit is set when the function normally asserts the PME# signal independent of the state of the PMEE bit. Writing logic 1 to this bit clears it and causes the function to stop asserting PME#, if enabled. Writing logic 0 has no effect. This bit defaults to logic 0, if the function does not support the PME# generation from D3cold. If the function supports the PME# generation from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. Data Scale: This two-bit read-only field indicates the scaling factor when interpreting the value of the Data register. The value and meaning of this field vary, depending on which data value is selected by the D_S field. This field is a required component of the Data register (offset 7) and must be implemented, if the Data register is implemented. If the Data register is not implemented, this field must return 00b when PMCSR is read. Data Select: This four-bit field selects the data that is reported through the Data register and the D_S field. This field is a required component of the Data register (offset 7) and must be implemented, if the Data register is implemented. If the Data register is not implemented, this field must return 00b when PMCSR is read. PME Enabled: Logic 1 allows the function to assert PME#. When it is logic 0, PME# assertion is disabled. This bit defaults to logic 0, if the function does not support the PME# generation from D3cold. If the function supports PME# from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. -
14 to 13 DS[1:0]
12 to 9
D_S [3:0]
8
PMEE
7 to 2
reserved
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Table 37. PMCSR - Power Management Control/Status register bit description ...continued Address: Value read from address 34h + 4h Bit 1 to 0 Symbol PS[1:0] Description Power State: This two-bit field is used to determine the current power state of the EHCI function and to set the function into a new power state. The definition of the field values is given as: 00b -- D0 01b -- D1 10b -- D2 11b -- D3hot If the software attempts to write an unsupported, optional state to this field, the write operation must complete normally on the bus; however, data is discarded and no status change occurs.
8.2.3.5
PMCSR_BSE register The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI bridge-specific functionality and is required for all PCI-to-PCI bridges. The bit allocation of this register is given in Table 38.
Table 38. PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit allocation Address: Value read from address 34h + 6h Bit Symbol Reset Access 7 BPCC_EN 0 R 6 B2_B3# 0 R 0 R 0 R 0 R 5 4 3 reserved 0 R 0 R 0 R 2 1 0
Table 39. PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit description Address: Value read from address 34h + 6h Bit 7 Symbol BPCC_EN Description Bus Power/Clock Control Enable: 1 -- Indicates that the bus power or clock control mechanism as defined in Table 40 is enabled. 0 -- Indicates that the bus or power control policies as defined in Table 40 are disabled. When the bus power or clock control mechanism is disabled, the bridge's PMCSR Power State (PS) field cannot be used by the system software to control the power or clock of the bridge's secondary bus. 6 B2_B3# B2/B3 support for D3hot: The state of this bit determines the action that is to occur as a direct result of programming the function to D3hot. 1 -- Indicates that when the bridge function is programmed to D3hot, its secondary bus's PCI clock will be stopped (B2). 0 -- Indicates that when the bridge function is programmed to D3hot, its secondary bus will have its power removed (B3). This bit is only meaningful if bit 7 (BPCC_EN) is logic 1. 5 to 0 reserved Table 40. PCI bus power and clock control Resultant actions by bridge (either direct or indirect) none none
Originating device's Secondary bus bridge PM state PM state D0 D1 B0 B1
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PCI bus power and clock control ...continued Resultant actions by bridge (either direct or indirect) clock stopped on secondary bus clock stopped and PCI VCC removed from secondary bus (B3 only); for definition of B2_B3#, see Table 39 none
Table 40.
Originating device's Secondary bus bridge PM state PM state D2 D3hot D3cold B2 B2, B3 B3
8.2.3.6
Data register The Data register is an optional, 1-byte register that provides a mechanism for the function to report state dependent operating data, such as power consumed or heat dissipated. Table 41 shows the bit description of the register.
Table 41. DATA - Data register bit description Address: Value read from address 34h + 7h Legend: * reset value Bit 7 to 0 Symbol DATA[7:0] Access R Value 00h* Description DATA: This register is used to report the state dependent data requested by the D_S field of the PMCSR register. The value of this register is scaled by the value reported by the DS field of the PMCSR register.
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9. I2C-bus interface
A simple I2C-bus interface is provided in the ISP1562 to read customized vendor ID, product ID and some other configuration bits from an external EEPROM. The I2C-bus interface is for bidirectional communication between ICs using two serial bus wires: SDA (data) and SCL (clock). Both lines are driven by open-drain circuits and must be connected to the positive supply voltage through pull-up resistors when in use; otherwise, they must be connected to ground.
9.1 Protocol
The I2C-bus protocol defines the following conditions:
* * * *
Bus free: both SDA and SCL are HIGH START: a HIGH-to-LOW transition on SDA, while SCL is HIGH STOP: a LOW-to-HIGH transition on SDA, while SCL is HIGH Data valid: after a START condition, data on SDA is stable during the HIGH period of SCL; data on SDA may only change while SCL is LOW
Each device on the I2C-bus has a unique slave address, which the master uses to select a device for access. The master starts a data transfer using a START condition and ends it by generating a STOP condition. Transfers can only be initiated when the bus is free. The receiver must acknowledge each byte by using a LOW level on SDA during the ninth clock pulse on SCL. For detailed information, refer to The I2C-bus Specification Version 2.1.
9.2 Hardware connections
The ISP1562 can be connected to an external EEPROM through the I2C-bus interface. The hardware connections are shown in Figure 5.
Vaux(3V3) Vaux(3V3)
RP
RP
SCL SDA I2C-bus
SCL SDA
A0 A1
24C01 ISP1562
USB HOST EEPROM or equivalent
A2
004aaa509
Fig 5.
EEPROM connection diagram
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The slave address that the ISP1562 uses to access the EEPROM is 101 0000b. Page mode addressing is not supported. Therefore, pins A0, A1 and A2 of the EEPROM must be connected to ground (logic 0).
9.3 Information loading from EEPROM
Figure 6 shows the content of the EEPROM memory. If the EEPROM is not present, the default values of device ID, vendor ID, subsystem VID and subsystem DID assigned to NXP Semiconductors by PCI-SIG will be loaded. For default values, see Table 3.
address
0
subsystem vendor ID (L)
1
subsystem vendor ID (H)
2
subsystem device ID (L) - OHCI
3
subsystem device ID (H) - OHCI
4
subsystem device ID (L) - EHCI
5
subsystem device ID (H) - EHCI
6
reserved - FFh 15h - loads subsystem vendor ID, device ID 1Ah - loads default values defined by NXP Semiconductors
004aaa930
7
signature
L = LOW; H = HIGH.
Fig 6.
Information loading from EEPROM
10. Power management
10.1 PCI bus power states
The PCI bus can be characterized by one of the four power management states: B0, B1, B2 and B3. B0 state (PCI clock = 33 MHz, PCI bus power = on) -- This corresponds to the bus being fully operational. B1 state (PCI clock = intermittent clock operation mode, PCI bus power = on) -- When a PCI bus is in B1, PCI VCC is still applied to all devices on the bus. No bus transactions, however, are allowed to take place on the bus. The B1 state indicates a perpetual idle state on the PCI bus. B2 state (PCI clock = stop, PCI bus power = on) -- PCI VCC is still applied on the bus, but the clock is stopped and held in the LOW state. B3 state (PCI clock = stop, PCI bus power = off) -- PCI VCC is removed from all devices on the PCI bus segment.
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10.2 USB bus states
Reset state -- When the USB bus is in the reset state, the USB system is stopped. Operational state -- When the USB bus is in the active state, the USB system is operating normally. Suspend state -- When the USB bus is in the suspend state, the USB system is stopped. Resume state -- When the USB bus is in the resume state, the USB system is operating normally.
11. USB host controller registers
Each host controller contains a set of on-chip operational registers that are mapped to uncached memory of the system addressable space. This memory space must begin on a DWORD (32-bit) boundary. The size of the allocated space is defined by the initial value in the Base Address register 0. HCDs must interact with these registers to implement USB functionality. After the PCI enumeration driver finishes the PCI device configuration, the new base address of these memory-mapped operational registers is defined in BAR0. The HCD can access these registers by using the address of base address value + offset. Table 42 contains a list of host controller registers.
Table 42. Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h USB host controller registers OHCI register HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA Reset value[1] Func0 OHCI1 0000 0010h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 2EDFh 0000 0000h 0000 0000h 0000 0000h 0000 0628h FF00 0901h Func1 OHCI2 0000 0010h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 2EDFh 0000 0000h 0000 0000h 0000 0000h 0000 0628h FF00 0901h CAPLENGTH/HCIVERSION[2] HCSPARAMS HCCPARAMS HCSP-PORTROUTE1[31:0] HCSP-PORTROUTE2[59:32] reserved reserved reserved USBCMD USBSTS USBINTR FRINDEX reserved PERIODICLISTBASE ASYNCLISTADDR reserved reserved reserved reserved EHCI register Reset value[1] Func2 EHCI 0100 0020h 0000 2192h 0000 0012h 0000 0010h 0000 0000h 0008 0000h 0000 1000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h -
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Table 42. Address 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h
[1] [2]
USB host controller registers ...continued OHCI register HcRhDescriptorB HcRhStatus HcRhPortStatus[1] HcRhPortStatus[2] reserved reserved reserved reserved reserved reserved Reset value[1] Func0 OHCI1 0002 0000h 0000 0000h 0000 0000h Func1 OHCI2 0002 0000h 0000 0000h 0000 0000h reserved reserved reserved reserved reserved CONFIGFLAG PORTSC1 PORTSC2 reserved reserved EHCI register Reset value[1] Func2 EHCI 0000 0000h 0000 0000h 0000 0000h -
Reset values that are highlighted, for example, 0, are the ISP1562 implementation-specific reset values; and reset values that are not highlighted, for example, 0, are compliant with OHCI and EHCI specifications. HCIVERSION is 0100h when subsystem ID and subsystem vendor ID are configured through the external EEPROM or when SCL is pulled down. Otherwise, it is 0095h.
For the OHCI host controller, there are only operational registers for the USB operation. For the enhanced host controller, there are two types of registers: one set of read-only capability registers, and one set of read and write operational registers.
11.1 OHCI USB host controller operational registers
OHCI HCDs must communicate with these registers to implement USB data transfers. Based on their functions, these registers are classified into four partitions:
* * * *
Control and status Memory pointer Frame counter Root hub
11.1.1 HcRevision register
Table 43. HcRevision - Host Controller Revision register bit allocation Address: Content of the base address register + 00h Bit Symbol Reset Access Bit Symbol Reset Access 0 R 0 R 0 R 0 R 0 R 23 0 R 22 0 R 21 0 R 20 reserved 0 R 0 R 0 R 0 R 31 30 29 28 reserved 0 R 19 0 R 18 0 R 17 0 R 16 27 26 25 24
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14 0 R 6 0 R 13 0 R 5 0 R 12 reserved 0 R 4 REV[7:0] 1 R 11 0 R 3 0 R 10 0 R 2 0 R 9 0 R 1 0 R 8 0 R 0 0 R
Bit Symbol Reset Access Bit Symbol Reset Access
15 0 R 7 0 R
Table 44. HcRevision - Host Controller Revision register bit description Address: Content of the base address register + 00h Bit 31 to 8 7 to 0 Symbol Description reserved REV[7:0] Revision: This read-only field contains the BCD representation of the version of the HCI specification that is implemented by this host controller. For example, a value of 11h corresponds to version 1.1. All host controller implementations that are compliant with this specification must have a value of 10h.
11.1.2 HcControl register
This register defines the operating modes for the host controller. All the fields in this register, except for HCFS and RWC, are modified only by the HCD. The bit allocation is given in Table 45.
Table 45. HcControl - Host Controller Control register bit allocation Address: Content of the base address register + 04h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 0 R/W 23 0 R/W 15 0 R/W 7 HCFS[1:0] 0 R/W
30 0 R/W 22 0 R/W 14 0 R/W 6 0 R/W
29 0 R/W 21 0 R/W 13 reserved[1] 0 R/W 5 BLE 0 R/W
28 reserved[1] 0 R/W 20 reserved[1] 0 R/W 12 0 R/W 4 CLE 0 R/W
27 0 R/W 19 0 R/W 11 0 R/W 3 IE 0 R/W
26 0 R/W 18 0 R/W 10 RWE 0 R/W 2 PLE 0 R/W
25 0 R/W 17 0 R/W 9 RWC 0 R/W 1 CBSR[1:0] 0 R/W
24 0 R/W 16 0 R/W 8 IR 0 R/W 0 0 R/W
The reserved bits should always be written with the reset value.
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Table 46. HcControl - Host Controller Control register bit description Address: Content of the base address register + 04h Bit 31 to 11 10 Symbol reserved RWE Description Remote Wake-up Enable: This bit is used by the HCD to enable or disable the remote wake-up feature on detecting upstream resume signaling. When this bit and RD (bit 3) in the HcInterruptStatus register are set, a remote wake-up is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt. Remote Wake-up Connected: This bit indicates whether the host controller supports remote wake-up signaling. If remote wake-up is supported and used by the system, it is the responsibility of the system firmware to set this bit during POST. The host controller clears the bit on a hardware reset but does not alter it on a software reset. Remote wake-up signaling of the host system is host-bus-specific and is not described in this specification. Interrupt Routing: This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. If clear, all interrupts are routed to the normal host bus interrupt mechanism. If set, interrupts are routed to the system management interrupt. The HCD clears this bit on a hardware reset, but it does not alter this bit on a software reset. The HCD uses this bit as a tag to indicate the ownership of the host controller. Host Controller Functional State for USB: 00b -- USBRESET 01b -- USBRESUME 10b -- USBOPERATIONAL 11b -- USBSUSPEND A transition to USBOPERATIONAL from another state causes SOF generation to begin 1 ms later. The HCD may determine whether the host controller has begun sending SOFs by reading SF (bit 2) in HcInterruptStatus. This field may be changed by the host controller only when in the USBSUSPEND state. The host controller may move from the USBSUSPEND state to the USBRESUME state after detecting the resume signaling from a downstream port. The host controller enters USBSUSPEND after a software reset; it enters USBRESET after a hardware reset. The latter also resets the root hub and asserts subsequent reset signaling to downstream ports. 5 BLE Bulk List Enable: This bit is set to enable the processing of the bulk list in the next frame. If cleared by the HCD, processing of the bulk list does not occur after the next SOF. The host controller checks this bit whenever it wants to process the list. When disabled, the HCD may modify the list. If HcBulkCurrentED is pointing to an Endpoint Descriptor (ED) to be removed, the HCD must advance the pointer by updating HcBulkCurrentED before re-enabling processing of the list. Control List Enable: This bit is set to enable the processing of the control list in the next frame. If cleared by the HCD, processing of the control list does not occur after the next SOF. The host controller must check this bit whenever it wants to process the list. When disabled, the HCD may modify the list. If HcControlCurrentED is pointing to an ED to be removed, the HCD must advance the pointer by updating HcControlCurrentED before re-enabling processing of the list. Isochronous Enable: This bit is used by the HCD to enable or disable processing of isochronous EDs. While processing the periodic list in a frame, the host controller checks the status of this bit when it finds an isochronous ED (that is, the Format bit of ED is logic 1; for details, refer to Open Host Controller Interface Specification for USB Rev. 1.0a). If set (enabled), the host controller continues processing the EDs. If cleared (disabled), the host controller halts processing of the periodic list, which now contains only isochronous EDs, and begins processing the bulk or control lists. Setting this bit is guaranteed to take effect in the next frame and not the current frame. Periodic List Enable: This bit is set to enable the processing of the periodic list in the next frame. If cleared by the HCD, processing of the periodic list does not occur after the next SOF. The host controller must check this bit before it starts processing the list.
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9
RWC
8
IR
7 to 6
HCFS [1:0]
4
CLE
3
IE
2
PLE
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Table 46. HcControl - Host Controller Control register bit description ...continued Address: Content of the base address register + 04h Bit 1 to 0 Symbol CBSR [1:0] Description Control Bulk Service Ratio: This specifies the service ratio of control EDs over bulk EDs. Before processing any of the nonperiodic lists, the host controller must compare the ratio specified with its internal count on how many nonempty control EDs are processed, in determining whether to continue serving another control ED or switching to bulk EDs. The internal count must be retained when crossing the frame boundary. After a reset, the HCD is responsible to restore this value. 00b -- 1 : 1 01b -- 2 : 1 10b -- 3 : 1 11b -- 4 : 1
11.1.3 HcCommandStatus register
This register is used by the host controller to receive commands issued by the HCD. It also reflects the current status of the host controller. To the HCD, it appears as a `write to set' register. The host controller must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register. The HCD may issue multiple distinct commands to the host controller without concern for corrupting previously issued commands. The HCD has normal read access to all bits. The SOC[1:0] field (bits 17 and 16 in the HcCommandStatus register) indicates the number of frames with which the host controller has detected the scheduling overrun error. This occurs when the periodic list does not complete before EOF. When a scheduling overrun error is detected, the host controller increments the counter and sets SO (bit 0 in the HcInterruptStatus register). Table 47 shows the bit allocation of the HcCommandStatus register.
Table 47. HcCommandStatus - Host Controller Command Status register bit allocation Address: Content of the base address register + 08h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 0 R/W 23 0 R/W 15 0 R/W 7 0 R/W
30 0 R/W 22 0 R/W 14 0 R/W 6 reserved[1] 0 R/W
29 0 R/W 21 reserved[1] 0 R/W 13 0 R/W 5 0 R/W
28 reserved[1] 0 R/W 20 0 R/W 12 reserved[1] 0 R/W 4 0 R/W
27 0 R/W 19 0 R/W 11 0 R/W 3 OCR 0 R/W
26 0 R/W 18 0 R/W 10 0 R/W 2 BLF 0 R/W
25 0 R/W 17 SOC[1:0] 0 R/W 9 0 R/W 1 CLF 0 R/W
24 0 R/W 16 0 R/W 8 0 R/W 0 HCR 0 R/W
The reserved bits should always be written with the reset value.
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Table 48. HcCommandStatus - Host Controller Command Status register bit description Address: Content of the base address register + 08h Bit 31 to 18 17 to 16 Symbol Description reserved SOC[1:0] Scheduling Overrun Count: The bit is incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. It must be incremented when a scheduling overrun is detected, even if SO (bit 0 in HcInterruptStatus) is already set. This is used by the HCD to monitor any persistent scheduling problems. reserved OCR Ownership Change Request: This bit is set by an OS HCD to request a change of control of the host controller. When set, the host controller must set OC (bit 30 in HcInterruptStatus). After the changeover, this bit is cleared and remains so until the next request from the OS HCD. Bulk List Filled: This bit is used to indicate whether there are any Transfer Descriptors (TDs) on the bulk list. It is set by the HCD whenever it adds a TD to an ED in the bulk list. When the host controller begins to process the head of the bulk list, it checks Bulk-Filled (BF). If BLF is logic 0, the host controller does not need to process the bulk list. If BLF is logic 1, the host controller must start processing the bulk list and set BF to logic 0. If the host controller finds a TD on the list, then the host controller must set BLF to logic 1, causing the bulk list processing to continue. If no TD is found on the bulk list, and if the HCD does not set BLF, then BLF is still logic 0 when the host controller completes processing the bulk list and the bulk list processing stops. Control List Filled: This bit is used to indicate whether there are any TDs on the control list. It is set by the HCD whenever it adds a TD to an ED in the control list. When the host controller begins to process the head of the control list, it checks CLF. If CLF is logic 0, the host controller does not need to process the control list. If Control-Filled (CF) is logic 1, the host controller needs to start processing the control list and set CLF to logic 0. If the host controller finds a TD on the list, then the host controller must set CLF to logic 1, causing the control list processing to continue. If no TD is found on the control list, and if the HCD does not set CLF, then CLF is still logic 0 when the host controller completes processing the control list and the control list processing stops. 0 HCR Host Controller Reset: This bit is set by the HCD to initiate a software reset of the host controller. Regardless of the functional state of the host controller, it moves to the USBSUSPEND state in which most of the operational registers are reset, except those stated otherwise; for example, IR (bit 8) in the HcControl register, and no host bus accesses are allowed. This bit is cleared by the host controller on completing the reset operation. The reset operation must be completed within 10 s. This bit, when set, must not cause a reset to the root hub and no subsequent reset signaling must be asserted to its downstream ports.
15 to 4 3
2
BLF
1
CLF
11.1.4 HcInterruptStatus register
This is a 4-byte register that provides the status of the events that cause hardware interrupts. The bit allocation of the register is given in Table 49. When an event occurs, the host controller sets the corresponding bit in this register. When a bit becomes set, a hardware interrupt is generated, if the interrupt is enabled in the HcInterruptEnable register (see Table 51) and the MIE (Master Interrupt Enable) bit is set. The HCD may clear specific bits in this register by writing logic 1 to the bit positions to be cleared. The HCD may not set any of these bits. The host controller does not clear the bit.
Table 49. HcInterruptStatus - Host Controller Interrupt Status register bit allocation Address: Content of the base address register + 0Ch Bit Symbol Reset Access 31 reserved[1] 0 R/W 30 OC 0 R/W 0 R/W 0 R/W 0 R/W 29 28 27 reserved[1] 0 R/W 0 R/W 0 R/W 26 25 24
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22 0 R/W 14 0 R/W 6 RHSC 0 R/W 21 0 R/W 13 0 R/W 5 FNO 0 R/W 20 reserved[1] 0 R/W 12 reserved[1] 0 R/W 4 UE 0 R/W 19 0 R/W 11 0 R/W 3 RD 0 R/W 18 0 R/W 10 0 R/W 2 SF 0 R/W 17 0 R/W 9 0 R/W 1 WDH 0 R/W 16 0 R/W 8 0 R/W 0 SO 0 R/W
Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
23 0 R/W 15 0 R/W 7 reserved[1] 0 R/W
The reserved bits should always be written with the reset value.
Table 50. HcInterruptStatus - Host Controller Interrupt Status register bit description Address: Content of the base address register + 0Ch Bit 31 30 Symbol reserved OC Description Ownership Change: This bit is set by the host controller when HCD sets OCR (bit 3) in the HcCommandStatus register. This event, when unmasked, will always immediately generate a System Management Interrupt (SMI). This bit is forced to logic 0 when the SMI# pin is not implemented. Root Hub Status Change: This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. Frame Number Overflow: This bit is set when the Most Significant Bit (MSB) of HcFmNumber (bit 15) changes value, or after the HccaFrameNumber is updated. Unrecoverable Error: This bit is set when the host controller detects a system error not related to USB. The host controller must not proceed with any processing nor signaling before the system error is corrected. The HCD clears this bit after the host controller is reset. Resume Detected: This bit is set when the host controller detects that a device on the USB is asserting resume signaling. This bit is set by the transition from no resume signaling to resume signaling. This bit is not set when the HCD sets the USBRESUME state. Start-of-Frame: At the start of each frame, this bit is set by the host controller and an SOF token is generated at the same time. Write-back Done Head: This bit is immediately set after the host controller has written HcDoneHead to HccaDoneHead. Further, updates of HccaDoneHead occur only after this bit is cleared. The HCD must only clear this bit after it has saved the content of HccaDoneHead. Scheduling Overrun: This bit is set when USB schedules for current frame overruns and after the update of HccaFrameNumber. A scheduling overrun increments the SOC[1:0] field (bits 17 to 16 of HcCommandStatus).
29 to 7 6 5 4
reserved RHSC FNO UE
3
RD
2 1
SF WDH
0
SO
11.1.5 HcInterruptEnable register
Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. A hardware interrupt is requested on the host bus if the following conditions occur:
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ISP1562
HS USB PCI host controller
* A bit is set in the HcInterruptStatus register. * The corresponding bit in the HcInterruptEnable register is set. * The MIE (Master Interrupt Enable) bit is set.
Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the current value of this register is returned. The bit allocation is given in Table 51.
Table 51. HcInterruptEnable - Host Controller Interrupt Enable register bit allocation Address: Content of the base address register + 10h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 MIE 0 R/W 23 0 R/W 15 0 R/W 7 reserved[1] 0 R/W
30 OC 0 R/W 22 0 R/W 14 0 R/W 6 RHSC 0 R/W
29 0 R/W 21 0 R/W 13 0 R/W 5 FNO 0 R/W
28 0 R/W 20 reserved[1] 0 R/W 12 reserved[1] 0 R/W 4 UE 0 R/W
27 reserved[1] 0 R/W 19 0 R/W 11 0 R/W 3 RD 0 R/W
26 0 R/W 18 0 R/W 10 0 R/W 2 SF 0 R/W
25 0 R/W 17 0 R/W 9 0 R/W 1 WDH 0 R/W
24 0 R/W 16 0 R/W 8 0 R/W 0 SO 0 R/W
The reserved bits should always be written with the reset value.
Table 52. HcInterruptEnable - Host Controller Interrupt Enable register bit description Address: Content of the base address register + 10h Bit 31 Symbol MIE Description Master Interrupt Enable: 0 -- Ignore 1 -- Enables interrupt generation by events specified in other bits of this register. 30 OC Ownership Change: 0 -- Ignore 1 -- Enables interrupt generation because of ownership change. 29 to 7 reserved -
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HS USB PCI host controller
Table 52. HcInterruptEnable - Host Controller Interrupt Enable register bit description ...continued Address: Content of the base address register + 10h Bit 6 Symbol RHSC Description Root Hub Status Change: 0 -- Ignore 1 -- Enables interrupt generation because of root hub status change. 5 FNO Frame Number Overflow: 0 -- Ignore 1 -- Enables interrupt generation because of frame number overflow. 4 UE Unrecoverable Error: 0 -- Ignore 1 -- Enables interrupt generation because of unrecoverable error. 3 RD Resume Detect: 0 -- Ignore 1 -- Enables interrupt generation because of resume detect. 2 SF Start-of-Frame: 0 -- Ignore 1 -- Enables interrupt generation because of Start-of-Frame. 1 WDH HcDoneHead Write-back: 0 -- Ignore 1 -- Enables interrupt generation because of HcDoneHead write-back. 0 SO Scheduling Overrun: 0 -- Ignore 1 -- Enables interrupt generation because of scheduling overrun.
11.1.6 HcInterruptDisable register
Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register. Therefore, writing logic 1 to a bit in this register clears the corresponding bit in the HcInterruptEnable register, whereas writing logic 0 to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a read, the current value of the HcInterruptEnable register is returned. The register contains 4 bytes, and the bit allocation is given in Table 53.
Table 53. HcInterruptDisable - Host Controller Interrupt Disable register bit allocation Address: Content of the base address register + 14h Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 31 MIE 0 R/W 23 30 OC 0 R/W 22 0 R/W 21 0 R/W 20 reserved[1] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 19 29 28 27 reserved[1] 0 R/W 18 0 R/W 17 0 R/W 16 26 25 24
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HS USB PCI host controller
14 0 R/W 6 RHSC 0 R/W 13 0 R/W 5 FNO 0 R/W 12 reserved[1] 0 R/W 4 UE 0 R/W 11 0 R/W 3 RD 0 R/W 10 0 R/W 2 SF 0 R/W 9 0 R/W 1 WDH 0 R/W 8 0 R/W 0 SO 0 R/W
Bit Symbol Reset Access Bit Symbol Reset Access
[1]
15 0 R/W 7 reserved[1] 0 R/W
The reserved bits should always be written with the reset value.
Table 54. HcInterruptDisable - Host Controller Interrupt Disable register bit description Address: Content of the base address register + 14h Bit 31 Symbol MIE Description Master Interrupt Enable: 0 -- Ignore 1 -- Disables interrupt generation because of events specified in other bits of this register. This field is set after a hardware or software reset. Interrupts are disabled. 30 OC Ownership Change: 0 -- Ignore 1 -- disables interrupt generation because of ownership change. 29 to 7 6 reserved RHSC Root Hub Status Change: 0 -- Ignore 1 -- Disables interrupt generation because of root hub status change. 5 FNO Frame Number Overflow: 0 -- Ignore 1 -- Disables interrupt generation because of frame number overflow. 4 UE Unrecoverable Error: 0 -- Ignore 1 -- Disables interrupt generation because of unrecoverable error. 3 RD Resume Detect: 0 -- Ignore 1 -- Disables interrupt generation because of resume detect. 2 SF Start-of-Frame: 0 -- Ignore 1 -- Disables interrupt generation because of Start-of-Frame. 1 WDH HcDoneHead Write-back: 0 -- Ignore 1 -- Disables interrupt generation because of HcDoneHead write-back. 0 SO Scheduling Overrun: 0 -- Ignore 1 -- Disables interrupt generation because of scheduling overrun.
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HS USB PCI host controller
11.1.7 HcHCCA register
The HcHCCA register contains the physical address of Host Controller Communication Area (HCCA). The bit allocation is given in Table 55. The HCD determines alignment restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA. The alignment is evaluated by examining the number of zeroes in lower order bits. The minimum alignment is 256 bytes; therefore, bits 0 through 7 will always return logic 0 when read. This area is used to hold the control structures and the interrupt table that are accessed by both the host controller and the HCD.
Table 55. HcHCCA - Host Controller Communication Area register bit allocation Address: Content of the base address register + 18h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 0 R/W 23 0 R/W 15 0 R/W 7 0 R/W
30 0 R/W 22 0 R/W 14 0 R/W 6 0 R/W
29 0 R/W 21 0 R/W 13 0 R/W 5 0 R/W
28 0 R/W 20 0 R/W 12 HCCA[7:0] 0 R/W 4 reserved[1] 0 R/W
27 0 R/W 19 0 R/W 11 0 R/W 3 0 R/W
26 0 R/W 18 0 R/W 10 0 R/W 2 0 R/W
25 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W
24 0 R/W 16 0 R/W 8 0 R/W 0 0 R/W
HCCA[23:16]
HCCA[15:8]
The reserved bits should always be written with the reset value.
Table 56. HcHCCA - Host Controller Communication Area register bit description Address: Content of the base address register + 18h Bit 31 to 8 7 to 0 Symbol HCCA[23:0] reserved Description Host Controller Communication Area Base Address: This is the base address of the HCCA. -
11.1.8 HcPeriodCurrentED register
The HcPeriodCurrentED register contains the physical address of the current isochronous or interrupt ED. Table 57 shows the bit allocation of the register.
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Table 57. HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit allocation Address: Content of the base address register + 1Ch Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R 0 R 0 R 7 0 R 6 PCED[3:0] 0 R 0 R 0 R 0 R 0 R 5 0 R 4 0 R 15 0 R 14 0 R 13 0 R 23 0 R 22 0 R 21 31 30 29 28 0 R 20 0 R 12 PCED[11:4] 0 R 3 0 R 2 reserved 0 R 0 R 0 R 1 0 R 0 27 0 R 19 0 R 11 26 0 R 18 0 R 10 25 0 R 17 0 R 9 24 0 R 16 0 R 8 PCED[27:20]
PCED[19:12]
Table 58. HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit description Address: Content of the base address register + 1Ch Bit 31 to 4 Symbol PCED[27:0] Description Period Current ED: This is used by the host controller to point to the head of one of the periodic lists that must be processed in the current frame. The content of this register is updated by the host controller after a periodic ED is processed. The HCD may read the content in determining which ED is being processed at the time of reading. -
3 to 0
reserved
11.1.9 HcControlHeadED register
The HcControlHeadED register contains the physical address of the first ED of the control list. The bit allocation is given in Table 59.
Table 59. HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit allocation Address: Content of the base address register + 20h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
ISP1562_3
31 0 R 23 0 R 15 0 R
30 0 R 22 0 R 14 0 R
29 0 R 21 0 R 13 0 R
28 0 R 20 0 R 12 0 R
27 0 R 19 0 R 11 0 R
26 0 R 18 0 R 10 0 R
25 0 R 17 0 R 9 0 R
24 0 R 16 0 R 8 0 R
43 of 93
CHED[27:20]
CHED[19:12]
CHED[11:4]
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ISP1562
HS USB PCI host controller
6 CHED[3:0] 0 R 5 0 R 4 0 R 3 0 R 2 reserved 0 R 0 R 0 R 1 0
Bit Symbol Reset Access
7 0 R
Table 60. HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit description Address: Content of the base address register + 20h Bit Symbol Description Control Head ED: The host controller traverses the control list, starting with the HcControlHeadED pointer. The content is loaded from HCCA during the initialization of the host controller. 31 to 4 CHED[27:0] 3 to 0 reserved
11.1.10 HcControlCurrentED register
The HcControlCurrentED register contains the physical address of the current ED of the control list. The bit allocation is given in Table 61.
Table 61. HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit allocation Address: Content of the base address register + 24h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R 0 R 0 R 7 0 R 6 CCED[3:0] 0 R 0 R 0 R 0 R 0 R 5 0 R 4 0 R 15 0 R 14 0 R 13 0 R 23 0 R 22 0 R 21 31 30 29 28 0 R 20 0 R 12 CCED[11:4] 0 R 3 0 R 2 reserved 0 R 0 R 0 R 1 0 R 0 27 0 R 19 0 R 11 26 0 R 18 0 R 10 25 0 R 17 0 R 9 24 0 R 16 0 R 8 CCED[27:20]
CCED[19:12]
Table 62. HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit description Address: Content of the base address register + 24h Bit 31 to 4 Symbol CCED[27:0] Description Control Current ED: This pointer is advanced to the next ED after serving the present. The host controller must continue processing the list from where it left off in the last frame. When it reaches the end of the control list, the host controller checks CLF (bit 1 of HcCommandStatus). If set, it copies the content of HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it does nothing. The HCD is allowed to modify this register only when CLE (bit 4 in the HcControl register) is cleared. When set, the HCD only reads the instantaneous value of this register. Initially, this is set to logic 0 to indicate the end of the control list. -
3 to 0
reserved
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11.1.11 HcBulkHeadED register
This register (see Table 63) contains the physical address of the first ED of the bulk list.
Table 63. HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit allocation Address: Content of the base address register + 28h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 0 R/W 23 0 R/W 15 0 R/W 7 0 R/W
30 0 R/W 22 0 R/W 14 0 R/W 6 BHED[3:0] 0 R/W
29 0 R/W 21 0 R/W 13 0 R/W 5 0 R/W
28 0 R/W 20 0 R/W 12 0 R/W 4 0 R/W
27 0 R/W 19 0 R/W 11 0 R/W 3 0 R/W
26 0 R/W 18 0 R/W 10 0 R/W 2 reserved[1] 0 R/W
25 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W
24 0 R/W 16 0 R/W 8 0 R/W 0 0 R/W
BHED[27:20]
BHED[19:12]
BHED[11:4]
The reserved bits should always be written with the reset value.
Table 64. HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit description Address: Content of the base address register + 28h Bit 31 to 4 3 to 0 Symbol Description BHED[27:0] Bulk Head ED: The host controller traverses the bulk list starting with the HcBulkHeadED pointer. The content is loaded from HCCA during the initialization of the host controller. reserved -
11.1.12 HcBulkCurrentED register
This register contains the physical address of the current endpoint of the bulk list. The endpoints are ordered according to their insertion to the list because the bulk list must be served in a round-robin fashion. The bit allocation is given in Table 65.
Table 65. HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit allocation Address: Content of the base address register + 2Ch Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 31 30 29 28 0 R/W 27 0 R/W 26 0 R/W 25 0 R/W 24 0 R/W BCED[27:20]
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HS USB PCI host controller
22 0 R/W 14 0 R/W 6 BCED[3:0] 0 R/W 21 0 R/W 13 0 R/W 5 0 R/W 20 0 R/W 12 0 R/W 4 0 R/W 19 0 R/W 11 0 R/W 3 0 R/W 18 0 R/W 10 0 R/W 2 reserved[1] 0 R/W 0 R/W 0 R/W 17 0 R/W 9 0 R/W 1 16 0 R/W 8 0 R/W 0
Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
23 0 R/W 15 0 R/W 7 0 R/W
BCED[19:12]
BCED[11:4]
The reserved bits should always be written with the reset value.
Table 66. HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit description Address: Content of the base address register + 2Ch Bit Symbol Description 31 to 4 BCED[27:0] Bulk Current ED: This is advanced to the next ED after the host controller has served the current ED. The host controller continues processing the list from where it left off in the last frame. When it reaches the end of the bulk list, the host controller checks CLF (bit 1 of HcCommandStatus). If the CLF bit is not set, nothing is done. If the CLF bit is set, it copies the content of HcBulkHeadED to HcBulkCurrentED and clears the CLF bit. The HCD can modify this register only when BLE (bit 5 in the HcControl register) is cleared. When HcControl is set, the HCD reads the instantaneous value of this register. This is initially set to logic 0 to indicate the end of the bulk list. 3 to 0 reserved -
11.1.13 HcDoneHead register
The HcDoneHead register contains the physical address of the last completed TD that was added to the done queue. In a normal operation, the HCD need not read this register because its content is periodically written to the HCCA. Table 67 shows the bit allocation of the register.
Table 67. HcDoneHead - Host Controller Done Head register bit allocation Address: Content of the base address register + 30h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
ISP1562_3
31 0 R/W 23 0 R/W 15 0 R/W
30 0 R/W 22 0 R/W 14 0 R/W
29 0 R/W 21 0 R/W 13 0 R/W
28 DH[27:20] 0 R/W 20 DH[19:12] 0 R/W 12 DH[11:4] 0 R/W
27 0 R/W 19 0 R/W 11 0 R/W
26 0 R/W 18 0 R/W 10 0 R/W
25 0 R/W 17 0 R/W 9 0 R/W
24 0 R/W 16 0 R/W 8 0 R/W
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HS USB PCI host controller
6 DH[3:0] 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 reserved[1] 0 R/W 0 R/W 0 R/W 1 0
Bit Symbol Reset Access
[1]
7 0 R/W
The reserved bits should always be written with the reset value.
Table 68. HcDoneHead - Host Controller Done Head register bit description Address: Content of the base address register + 30h Bit Symbol Description 31 to 4 DH[27:0] Done Head: When a TD is completed, the host controller writes the content of HcDoneHead to the NextTD field of the TD. The host controller then overwrites the content of HcDoneHead with the address of this TD. This is set to logic 0 whenever the host controller writes the content of this register to HCCA. 3 to 0 reserved -
11.1.14 HcFmInterval register
This register contains a 14-bit value that indicates the bit time interval in a frame, that is, between two consecutive SOFs, and a 15-bit value indicating the full-speed maximum packet size that the host controller may transmit or receive, without causing a scheduling overrun. The HCD may carry out minor adjustment on FI (Frame Interval) by writing a new value over the present at each SOF. This provides the possibility for the host controller to synchronize with an external clocking resource and to adjust any unknown local clock offset. The bit allocation of the register is given in Table 69.
Table 69. HcFmInterval - Host Controller Frame Interval register bit allocation Address: Content of the base address register + 34h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 FIT 0 R/W 23 0 R/W 15 reserved[1] 0 R/W 7 1 R/W
30 0 R/W 22 0 R/W 14 0 R/W 6 1 R/W
29 0 R/W 21 0 R/W 13 1 R/W 5 0 R/W
28 0 R/W 20 0 R/W 12 0 R/W 4 FI[7:0] 1 R/W
27 FSMPS[14:8] 0 R/W 19 0 R/W 11 FI[13:8] 1 R/W 3 1 R/W
26 0 R/W 18 0 R/W 10 1 R/W 2 1 R/W
25 0 R/W 17 0 R/W 9 1 R/W 1 1 R/W
24 0 R/W 16 0 R/W 8 0 R/W 0 1 R/W
FSMPS[7:0]
The reserved bits should always be written with the reset value.
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HS USB PCI host controller
Table 70. HcFmInterval - Host Controller Frame Interval register bit description Address: Content of the base address register + 34h Bit 31 Symbol FIT Description Frame Interval Toggle: The HCD toggles this bit whenever it loads a new value to Frame Interval. FS Largest Data Packet: This field specifies the value that is loaded into the largest data packet counter at the beginning of each frame. The counter value represents the largest amount of data in bits that can be sent or received by the host controller in a single transaction at any given time, without causing a scheduling overrun. The field value is calculated by the HCD. Frame Interval: This specifies the interval between two consecutive SOFs in bit times. The nominal value is set to 11,999. The HCD must store the current value of this field before resetting the host controller to reset this field to its nominal value. The HCD can then restore the stored value on completing the reset sequence.
30 to 16 FSMPS [14:0]
15 to 14 reserved 13 to 0 FI[13:0]
11.1.15 HcFmRemaining register
This register is a 14-bit down counter showing the bit time remaining in the current frame. Table 71 contains the bit allocation of this register.
Table 71. HcFmRemaining - Host Controller Frame Remaining register bit allocation Address: Content of the base address register + 38h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 FRT 0 R/W 23 0 R/W 15 reserved[1] 0 R/W 7 0 R/W
30 0 R/W 22 0 R/W 14 0 R/W 6 0 R/W
29 0 R/W 21 0 R/W 13 0 R/W 5 0 R/W
28 0 R/W 20 reserved[1] 0 R/W 12 0 R/W 4 FR[7:0] 0 R/W
27 reserved[1] 0 R/W 19 0 R/W 11 FR[13:8] 0 R/W 3 0 R/W
26 0 R/W 18 0 R/W 10 0 R/W 2 0 R/W
25 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W
24 0 R/W 16 0 R/W 8 0 R/W 0 0 R/W
The reserved bits should always be written with the reset value.
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Table 72. HcFmRemaining - Host Controller Frame Remaining register bit description Address: Content of the base address register + 38h Bit 31 Symbol FRT Description Frame Remaining Toggle: This bit is loaded from FIT (bit 31 of HcFmInterval) whenever FR[13:0] reaches 0. This bit is used by the HCD for synchronization between FI[13:0] (bits 13 to 0 of HcFmInterval) and FR[13:0]. Frame Remaining: This counter is decremented at each bit time. When it reaches 0, it is reset by loading the FI[13:0] value specified in HcFmInterval at the next bit time boundary. When entering the USBOPERATIONAL state, the host controller reloads the content with FI[13:0] of HcFmInterval and uses the updated value from the next SOF.
30 to 14 13 to 0
reserved FR[13:0]
11.1.16 HcFmNumber register
This register is a 16-bit counter, and the bit allocation is given in Table 73. It provides a timing reference among events happening in the host controller and the HCD. The HCD may use the 16-bit value specified in this register and generate a 32-bit frame number, without requiring frequent access to the register.
Table 73. HcFmNumber - Host Controller Frame Number register bit allocation Address: Content of the base address register + 3Ch Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 0 R/W 23 0 R/W 15 reserved[1] 0 R/W 7 0 R/W
30 0 R/W 22 0 R/W 14 0 R/W 6 0 R/W
29 0 R/W 21 0 R/W 13 0 R/W 5 0 R/W
28 reserved[1] 0 R/W 20 reserved[1] 0 R/W 12 0 R/W 4 FN[7:0] 0 R/W
27 0 R/W 19 0 R/W 11 FN[13:8] 0 R/W 3 0 R/W
26 0 R/W 18 0 R/W 10 0 R/W 2 0 R/W
25 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W
24 0 R/W 16 0 R/W 8 0 R/W 0 0 R/W
The reserved bits should always be written with the reset value.
Table 74. HcFmNumber - Host Controller Frame Number register bit description Address: Content of the base address register + 3Ch Bit 31 to 14 13 to 0 Symbol reserved FN[13:0] Description Frame Number: Incremented when HcFmRemaining is reloaded. It must be rolled over to 0h after FFFFh. Automatically incremented when entering the USBOPERATIONAL state. The content is written to HCCA after the host controller has incremented Frame Number at each frame boundary and sent an SOF but before the host controller reads the first ED in that frame. After writing to HCCA, the host controller sets SF (bit 2 in HcInterruptStatus).
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HS USB PCI host controller
11.1.17 HcPeriodicStart register
This register has a 14-bit programmable value that determines when is the earliest time for the host controller to start processing the periodic list. For bit allocation, see Table 75.
Table 75. HcPeriodicStart - Host Controller Periodic Start register bit allocation Address: Content of the base address register + 40h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 0 R/W 23 0 R/W 15 reserved[1] 0 R/W 7 0 R/W
30 0 R/W 22 0 R/W 14 0 R/W 6 0 R/W
29 0 R/W 21 0 R/W 13 0 R/W 5 0 R/W
28 reserved[1] 0 R/W 20 reserved[1] 0 R/W 12 0 R/W 4 P_S[7:0] 0 R/W
27 0 R/W 19 0 R/W 11 P_S[13:8] 0 R/W 3 0 R/W
26 0 R/W 18 0 R/W 10 0 R/W 2 0 R/W
25 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W
24 0 R/W 16 0 R/W 8 0 R/W 0 0 R/W
The reserved bits should always be written with the reset value.
Table 76. HcPeriodicStart - Host Controller Periodic Start register bit description Address: Content of the base address register + 40h Bit 31 to 14 13 to 0 Symbol reserved P_S[13:0] Description Periodic Start: After a hardware reset, this field is cleared. It is then set by the HCD during the host controller initialization. The value is roughly calculated as 10 % of HcFmInterval. A typical value is 3E67h. When HcFmRemaining reaches the value specified, processing of the periodic lists have priority over control or bulk processing. The host controller, therefore, starts processing the interrupt list after completing the current control or bulk transaction that is in progress.
11.1.18 HcLSThreshold register
This register contains an 11-bit value used by the host controller to determine whether to commit to the transfer of a maximum of 8-byte low-speed packet before EOF. Neither the host controller nor the HCD can change this value. For bit allocation, see Table 77.
Table 77. HcLSThreshold - Host Controller Low-Speed Threshold register bit allocation Address: Content of the base address register + 44h Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 31 30 29 28 reserved[1] 0 R/W 0 R/W 0 R/W 0 R/W 27 26 25 24
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HS USB PCI host controller
22 0 R/W 14 reserved[1] 0 R/W 6 0 R/W 21 0 R/W 13 0 R/W 5 1 R/W 20 reserved[1] 0 R/W 12 0 R/W 4 LST[7:0] 0 R/W 19 0 R/W 11 0 R/W 3 1 R/W 18 0 R/W 10 LST[11:8] 1 R/W 2 0 R/W 1 R/W 1 0 R/W 0 R/W 0 0 R/W 17 0 R/W 9 16 0 R/W 8
Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
23 0 R/W 15 0 R/W 7 0 R/W
The reserved bits should always be written with the reset value.
Table 78. HcLSThreshold - Host Controller Low-Speed Threshold register bit description Address: Content of the base address register + 44h Bit 31 to 12 11 to 0 Symbol reserved LST[11:0] Description Low-Speed Threshold: This field contains a value that is compared to the FR[13:0] field, before initiating a low-speed transaction. The transaction is started only if FR this field. The value is calculated by the HCD, considering the transmission and set-up overhead.
11.1.19 HcRhDescriptorA register
This register is the first of two registers describing the characteristics of the root hub. Reset values are implementation-specific. Table 79 contains the bit allocation of the HcRhDescriptorA register.
Table 79. HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit allocation Address: Content of the base address register + 48h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 15 0 R/W 14 reserved[1] 0 R/W 0 R/W 0 R/W 13 0 R/W 12 NOCP 0 R/W 1 R/W 23 1 R/W 22 1 R/W 21 31 30 29 28 1 R/W 20 reserved[1] 0 R/W 11 OCPM 1 R/W 0 R/W 10 DT 0 R 0 R/W 9 NPS 0 R/W 0 R/W 8 PSM 1 R/W 27 1 R/W 19 26 1 R/W 18 25 1 R/W 17 24 1 R/W 16 POTPGT[7:0]
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HS USB PCI host controller
6 0 R 5 0 R 4 NDP[7:0] 0 R 3 0 R 2 0 R 1 0 R 0 1 R
Bit Symbol Reset Access
[1]
7 0 R
The reserved bits should always be written with the reset value.
Table 80. HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit description Address: Content of the base address register + 48h Bit 31 to 24 Symbol POTPGT [7:0] reserved NOCP Description Power On To Power Good Time: This byte specifies the duration the HCD must wait before accessing a powered-on port of the root hub. It is implementation-specific. The unit of time is 2 ms. The duration is calculated as POTPGT x 2 ms. No Overcurrent Protection: This bit describes how the overcurrent status for root hub ports are reported. When this bit is cleared, the OCPM bit specifies global or per-port reporting. 0 -- Overcurrent status is collectively reported for all downstream ports. 1 -- No overcurrent protection supported. 11 OCPM Overcurrent Protection Mode: This bit describes how the overcurrent status for root hub ports are reported. At reset, this bit reflects the same mode as Power Switching Mode. This bit is valid only if the NOCP bit is cleared. 0 -- Overcurrent status is collectively reported for all downstream ports. 1 -- Overcurrent status is reported on a per-port basis. 10 9 DT NPS Device Type: This bit specifies that the root hub is not a compound device. The root hub is not permitted to be a compound device. This field must always read logic 0. No Power Switching: This bit is used to specify whether power switching is supported or ports are always powered. It is implementation-specific. When this bit is cleared, the PSM bit specifies global or per-port switching. 0 -- Ports are power switched. 1 -- Ports are always powered on when the host controller is powered on. 8 PSM Power Switching Mode: This bit is used to specify how the power switching of root hub ports is controlled. It is implementation-specific. This field is only valid if the NPS field is cleared. 0 -- All ports are powered at the same time. 1 -- Each port is individually powered. This mode allows port power to be controlled by either the global switch or per-port switching. If the PPCM (Port Power Control Mask) bit is set, the port responds only to port power commands (Set/Clear Port Power). If the port mask is cleared, then the port is controlled only by the global power switch (Set/Clear Global Power). 7 to 0 NDP[7:0] Number Downstream Ports: These bits specify the number of downstream ports supported by the root hub. It is implementation-specific. The minimum number of ports is 1. The maximum number of ports supported by OHCI is 15.
23 to 13 12
11.1.20 HcRhDescriptorB register
The HcRhDescriptorB register is the second of two registers describing the characteristics of the root hub. The bit allocation is given in Table 81. These fields are written during initialization to correspond to the system implementation. Reset values are implementation-specific.
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Table 81. HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit allocation Address: Content of the base address register + 4Ch Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 DR[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 DR[15:8] 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 PPCM[7:0] 0 R/W 11 0 R/W 10 1 R/W 9 0 R/W 8 31 30 29 28 27 0 R 19 26 0 R/W 18 25 0 R/W 17 24 0 R/W 16 PPCM[15:8]
Table 82. HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit description Address: Content of the base address register + 4Ch Bit 31 to 16 Symbol PPCM [15:0] Description Port Power Control Mask: Each bit indicates whether a port is affected by a global power control command when Power Switching Mode is set. When set, only the power state of the port is affected by per-port power control (Set/Clear Port Power). When cleared, the port is controlled by the global power switch (Set/Clear Global Power). If the device is configured to global switching mode (Power Switching Mode = 0), this field is not valid. Bit 0 -- Reserved Bit 1 -- Ganged-power mask on port 1 Bit 2 -- Ganged-power mask on port 2 15 to 0 DR[15:0] Device Removable: Each bit is dedicated to a port of the root hub. When cleared, the attached device is removable. When set, the attached device is not removable. Bit 0 -- Reserved Bit 1 -- Device attached to port 1 Bit 2 -- Device attached to port 2
11.1.21 HcRhStatus register
This register is divided into two parts. The lower word of a DWORD represents the Hub Status field, and the upper word represents the Hub Status Change field. Reserved bits must always be written as logic 0. Table 83 shows the bit allocation of the register.
Table 83. HcRhStatus - Host Controller Root Hub Status register bit allocation Address: Content of the base address register + 50h Bit Symbol Reset Access
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31 CRWE 0 R/W
30 0 R/W
29 0 R/W
28 0 R/W
27 reserved[1] 0 R/W
26 0 R/W
25 0 R/W
24 0 R/W
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22 0 R/W 14 0 R/W 6 0 R/W 21 reserved[1] 0 R/W 13 0 R/W 5 reserved[1] 0 R/W 20 0 R/W 12 0 R/W 4 0 R/W 19 0 R/W 11 reserved[1] 0 R/W 3 0 R/W 0 R/W 2 0 R/W 0 R/W 1 OCI 0 R 0 R/W 0 LPS 0 RW 18 0 R/W 10 17 CCIC 0 R/W 9 16 LPSC 0 R/W 8
Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
23 0 R/W 15 DRWE 0 R/W 7 0 R/W
The reserved bits should always be written with the reset value.
Table 84. HcRhStatus - Host Controller Root Hub Status register bit description Address: Content of the base address register + 50h Bit 31 Symbol CRWE Description On write Clear Remote Wake-up Enable: 0 -- No effect 1 -- Clears DRWE (Device Remote Wake-up Enable) 30 to 18 reserved 17 CCIC Overcurrent Indicator Change: This bit is set by hardware when a change has occurred to the OCI bit of this register. 0 -- No effect 1 -- The HCD clears this bit. 16 LPSC On read Local Power Status Change: The root hub does not support the local power status feature. Therefore, this bit is always logic 0. On write Set Global Power: In global power mode (Power Switching Mode = 0), logic 1 is written to this bit to turn on power to all ports (clear Port Power Status). In per-port power mode, it sets Port Power Status only on ports whose Port Power Control Mask bit is not set. Writing logic 0 has no effect. 15 DRWE On read Device Remote Wake-up Enable: This bit enables bit Connect Status Change (CSC) as a resume event, causing a state transition from USBSUSPEND to USBRESUME and setting the Resume Detected interrupt. 0 -- CSC is not a remote wake-up event. 1 -- CSC is a remote wake-up event. On write Set Remote Wake-up Enable: Writing logic 1 sets DRWE (Device Remote Wake-up Enable). Writing logic 0 has no effect. 14 to 2 1 reserved OCI Overcurrent Indicator: This bit reports overcurrent conditions when global reporting is implemented. When set, an overcurrent condition exists. When cleared, all power operations are normal. If the per-port overcurrent protection is implemented, this bit is always logic 0. On read Local Power Status: The root hub does not support the local power status feature. Therefore, this bit is always read as logic 0. On write Clear Global Power: In global power mode (Power Switching Mode = 0), logic 1 is written to this bit to turn off power to all ports (clear Port Power Status). In per-port power mode, it clears Port Power Status only on ports whose Port Power Control Mask bit is not set. Writing logic 0 has no effect.
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11.1.22 HcRhPortStatus[4:1] register
The HcRhPortStatus[4:1] register is used to control and report port events on a per-port basis. NumberofDownstreamPort represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word reflects the port status. The upper word reflects status change bits. Some status bits are implemented with special write behavior. If a transaction, token through handshake, is in progress when a write to change port status occurs, the resulting port status change is postponed until the transaction completes. Always write logic 0 to the reserved bits. The bit allocation of the register is given in Table 85.
Table 85. HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit allocation Address: Content of the base address register + 54h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 0 R/W 23 0 R/W 15 0 R/W 7 0 R/W
30 0 R/W 22 reserved[1] 0 R/W 14 0 R/W 6 reserved[1] 0 R/W
29 0 R/W 21 0 R/W 13 reserved[1] 0 R/W 5 0 R/W
28 reserved[1] 0 R/W 20 PRSC 0 R/W 12 0 R/W 4 PRS 0 R/W
27 0 R/W 19 OCIC 0 R/W 11 0 R/W 3 POCI 0 R/W
26 0 R/W 18 PSSC 0 R/W 10 0 R/W 2 PSS 0 R/W
25 0 R/W 17 PESC 0 R/W 9 LSDA 0 R/W 1 PES 0 R/W
24 0 R/W 16 CSC 0 R/W 8 PPS 0 R/W 0 CCS 0 R/W
The reserved bits should always be written with the reset value.
Table 86. HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description Address: Content of the base address register + 54h Bit 31 to 21 20 Symbol reserved PRSC Description Port Reset Status Change: This bit is set at the end of the 10 ms port reset signal. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- Port reset is not complete. 1 -- Port reset is complete. 19 OCIC Port Overcurrent Indicator Change: This bit is valid only if overcurrent conditions are reported on a per-port basis. This bit is set when the root hub changes the POCI (Port Overcurrent Indicator) bit. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- No change in POCI. 1 -- POCI has changed.
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Table 86. HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description ...continued Address: Content of the base address register + 54h Bit 18 Symbol PSSC Description Port Suspend Status Change: This bit is set when the resume sequence is completed. This sequence includes the 20 ms resume pulse, LS EOP and 3 ms re-synchronization delay. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. This bit is also cleared when Reset Status Change is set. 0 -- Resume is not completed. 1 -- Resume is completed. 17 PESC Port Enable Status Change: This bit is set when hardware events cause the PES (Port Enable Status) bit to be cleared. Changes from the HCD writes do not set this bit. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- No change in PES. 1 -- Change in PES. 16 CSC Connect Status Change: This bit is set whenever a connect or disconnect event occurs. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. If CCS (Current Connect Status) is cleared when a Set Port Reset, Set Port Enable or Set Port Suspend write occurs, this bit is set to force the driver to re-evaluate the connection status because these writes must not occur if the port is disconnected. 0 -- No change in CCS. 1 -- Change in CCS. Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only after a root hub reset to inform the system that the device is attached. 15 to 10 9 reserved LSDA On read Low-Speed Device Attached: This bit indicates the speed of the device attached to this port. When set, a low-speed device is attached to this port. When cleared, a full-speed device is attached to this port. This field is valid only when CCS is set. 0 -- Port is not suspended. 1 -- Port is suspended. On write Clear Port Power: The HCD can clear the PPS (Port Power Status) bit by writing logic 1 to this bit. Writing logic 0 has no effect. 8 PPS On read Port Power Status: This bit reflects the port power status, regardless of the type of power switching implemented. This bit is cleared if an overcurrent condition is detected. The HCD can set this bit by writing Set Port Power or Set Global Power. The HCD can clear this bit by writing Clear Port Power or Clear Global Power. Power Switching Mode and PortPowerControlMask[NDP] determine which power control switches are enabled. In global switching mode (Power Switching Mode = 0), only Set/Clear Global Power controls this bit. In the per-port power switching (Power Switching Mode = 1), if the PortPowerControlMask[NDP] bit for the port is set, only Set/Clear Port Power commands are enabled. If the mask is not set, only Set/Clear Global Power commands are enabled. When port power is disabled, bits CCS (Current Connect Status), PES (Port Enable Status), PSS (Port Suspend Status) and PRS (Port Reset Status) should be reset. 0 -- Port power is off. 1 -- Port power is on. On write Set Port Power: The HCD can write logic 1 to set the PPS (Port Power Status) bit. Writing logic 0 has no effect. Remark: This bit always reads logic 1 if power switching is not supported. 7 to 5 reserved -
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Table 86. HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description ...continued Address: Content of the base address register + 54h Bit 4 Symbol PRS Description On read Port Reset Status: When this bit is set by a write to Set Port Reset, port reset signaling is asserted. When reset is completed and PRSC is set, this bit is cleared. 0 -- Port reset signal is inactive. 1 -- Port reset signal is active. On write Set Port Reset: The HCD can set the port reset signaling by writing logic 1 to this bit. Writing logic 0 has no effect. If CCS is cleared, this write does not set PRS (Port Reset Status) but instead sets CCS. This informs the driver that it attempted to reset a disconnected port. 3 POCI On read Port Overcurrent Indicator: This bit is valid only when the root hub is configured to show overcurrent conditions are reported on a per-port basis. If the per-port overcurrent reporting is not supported, this bit is set to logic 0. If cleared, all power operations are normal for this port. If set, an overcurrent condition exists on this port. 0 -- No overcurrent condition. 1 -- Overcurrent condition detected. On write Clear Suspend Status: The HCD can write logic 1 to initiate a resume. Writing logic 0 has no effect. A resume is initiated only if PSS (Port Suspend Status) is set. 2 PSS On read Port Suspend Status: This bit indicates whether the port is suspended or is in the resume sequence. It is set by a Set Suspend State write and cleared when PSSC (Port Suspend Status Change) is set at the end of the resume interval. This bit is not set if CCS (Current Connect Status) is cleared. This bit is also cleared when PRSC is set at the end of the port reset or when the host controller is placed in the USBRESUME state. If an upstream resume is in progress, it will propagate to the host controller. 0 -- Port is not suspended. 1 -- Port is suspended. On write Set Port Suspend: The HCD can set the PSS (Port Suspend Status) bit by writing logic 1 to this bit. Writing logic 0 has no effect. If CCS is cleared, this write does not set PSS; instead it sets CSS. This informs the driver that it attempted to suspend a disconnected port. 1 PES On read Port Enable Status: This bit indicates whether the port is enabled or disabled. The root hub may clear this bit when an overcurrent condition, disconnect event, switched-off power or operational bus error is detected. This change also causes Port Enabled Status Change to be set. The HCD can set this bit by writing Set Port Enable and clear it by writing Clear Port Enable. This bit cannot be set when CCS (Current Connect Status) is cleared. This bit is also set on completing a port reset when Reset Status Change is set or on completing a port suspend when Suspend Status Change is set. 0 -- Port is disabled. 1 -- Port is enabled. On write Set Port Enable: The HCD can set PES (Port Enable Status) by writing logic 1. Writing logic 0 has no effect. If CCS is cleared, this write does not set PES, but instead sets CSC (Connect Status Change). This informs the driver that it attempted to enable a disconnected port. 0 CCS On read Current Connect Status: This bit reflects the current state of the downstream port. 0 -- No device connected. 1 -- Device connected. On write Clear Port Enable: The HCD can write logic 1 to this bit to clear the PES (Port Enable Status) bit. Writing logic 0 has no effect. The CCS bit is not affected by any write. Remark: This bit always reads logic 1 when the attached device is nonremovable (DeviceRemovable[NDP]).
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11.2 EHCI controller capability registers
Other than the OHCI host controller, there are some registers in EHCI that define the capability of EHCI. The address range of these registers is located before operational registers.
11.2.1 CAPLENGTH/HCIVERSION register
The bit allocation of this 4-byte register is given in Table 87.
CAPLENGTH/HCIVERSION - Capability Length/Host Controller Interface Version Number register bit allocation Address: Content of the base address register + 00h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Table 88. 0 R 0 R 1 R 0 R 7 0 R 6 0 R 5 0 R 4 0 R 0 R 15 0 R 14 0 R 13 0 R 23 0 R 22 0 R 21 31 30 29 28 0 R 20 0 R 12 reserved 0 R 3 0 R 0 R 2 0 R 0 R 1 0 R 0 R 0 0 R 27 0 R 19 0 R 11 26 0 R 18 0 R 10 25 0 R 17 0 R 9 24 1 R 16 0 R 8 HCIVERSION[15:8] Table 87.
HCIVERSION[7:0]
CAPLENGTH[7:0]
CAPLENGTH/HCIVERSION - Capability Length/Host Controller Interface Version Number register bit description Address: Content of the base address register + 00h Bit 31 to 16 15 to 8 7 to 0 Symbol HCIVERSION [15:0] reserved CAPLENGTH [7:0] Description Host Controller Interface Version Number: This field contains a BCD encoded version number of the interface to which the host controller interface conforms. Capability Register Length: This is used as an offset. It is added to the register base to find the beginning of the operational register space.
11.2.2 HCSPARAMS register
The Host Controller Structural Parameters (HCSPARAMS) register is a set of fields that are structural parameters. The bit allocation is given in Table 89.
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Table 89. HCSPARAMS - Host Controller Structural Parameters register bit allocation Address: Content of the base address register + 04h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R 7 PRR 1 R 0 R 0 R 6 reserved 0 R 0 R 15 0 R 14 N_CC[3:0] 1 R 5 0 R 4 PPC 1 R 0 R 0 R 3 0 R 2 0 R 0 R 13 0 R 12 0 R 23 0 R 22 0 R 21 0 R 20 reserved 0 R 11 0 R 10 N_PCC[3:0] 0 R 1 1 R 1 R 0 0 R 0 R 9 0 R 8 31 30 29 28 reserved 0 R 19 0 R 18 0 R 17 0 R 16 27 26 25 24
N_PORTS[3:0]
Table 90. HCSPARAMS - Host Controller Structural Parameters register bit description Address: Content of the base address register + 04h Bit Symbol Description 31 to 16 reserved
15 to 12 N_CC[3:0] Number of Companion Controller: This field indicates the number of companion controllers associated with this Hi-Speed USB host controller. A value of zero in this field indicates there are no companion host controllers. Port-ownership hand-off is not supported. Only high-speed devices are supported on the host controller root ports. A value larger than zero in this field indicates there are companion Original USB host controller(s). Port-ownership hand-offs are supported. 11 to 8 N_PCC [3:0] Number of Ports per Companion Controller: This field indicates the number of ports supported per companion host controller. It is used to indicate the port routing configuration to the system software. For example, if N_PORTS has a value of 6 and N_CC has a value of 2, then N_PCC can have a value of 3. The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, and so on. In the previous example, N_PCC could have been 4, in which case the first four are routed to companion controller 1 and the last two are routed to companion controller 2. The number in this field must be consistent with N_PORTS and N_CC. 7 PRR Port Routing Rules: This field indicates the method used to map ports to companion controllers. 0 -- The first N_PCC ports are routed to the lowest numbered function companion host controller, the next N_PCC ports are routed to the next lowest function companion controller, and so on. 1 -- The port routing is explicitly enumerated by the first N_PORTS elements of the HCSP-PORTROUTE array.
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Table 90. HCSPARAMS - Host Controller Structural Parameters register bit description ...continued Address: Content of the base address register + 04h Bit 6 to 5 4 Symbol reserved PPC Description Port Power Control: This field indicates whether the host controller implementation includes port power control. Logic 1 indicates the port has port power switches. Logic 0 indicates the port does not have port power switches. The value of this field affects the functionality of the Port Power field in each port status and control register.
3 to 0
N_PORTS Number of Ports: This field specifies the number of physical downstream ports implemented on this [3:0] host controller. The value in this field determines how many port registers are addressable in the operational register space. Logic 0 in this field is undefined.
11.2.3 HCCPARAMS register
The Host Controller Capability Parameters (HCCPARAMS) register is a 4-byte register, and the bit allocation is given in Table 91.
Table 91. HCCPARAMS - Host Controller Capability Parameters register bit allocation Address: Content of the base address register + 08h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R 0 R 0 R 7 0 R 6 IST[3:0] 0 R 1 R 0 R 0 R 5 0 R 4 0 R 15 0 R 14 0 R 13 0 R 12 reserved 0 R 3 reserved 0 R 0 R 2 0 R 1 PFLF 1 R 0 R 0 64AC 0 R 0 R 23 0 R 22 0 R 21 0 R 20 reserved 0 R 11 0 R 10 0 R 9 0 R 8 31 30 29 28 reserved 0 R 19 0 R 18 0 R 17 0 R 16 27 26 25 24
Table 92. HCCPARAMS - Host Controller Capability Parameters register bit description Address: Content of the base address register + 08h Bit 31 to 8 7 to 4 Symbol reserved IST[3:0] Description Isochronous Scheduling Threshold: Default = implementation-dependent. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When IST[3] is logic 0, the value of the least significant three bits indicates the number of microframes a host controller can hold a set of isochronous data structures, one or more, before flushing the state. When IST[3] is logic 1, the host software assumes the host controller may cache an isochronous data structure for an entire frame.
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Table 92. HCCPARAMS - Host Controller Capability Parameters register bit description ...continued Address: Content of the base address register + 08h Bit 3 to 2 1 Symbol reserved PFLF Description Programmable Frame List Flag: Default = implementation-dependent. If this bit is cleared, the system software must use a frame list length of 1024 elements with the host controller. The USBCMD register FLS[1:0] (bits 3 and 2) is read-only and must be cleared. If PFLF is set, the system software can specify and use a smaller frame list, and configure the host through the FLS bit. The frame list must always be aligned on a 4 kB page boundary to ensure that the frame list is always physically contiguous. 64-bit Addressing Capability: This field contains the addressing range capability. 0 -- Data structures using 32-bit address memory pointers. 1 -- Data structures using 64-bit address memory pointers.
0
64AC
11.2.4 HCSP-PORTROUTE register
The HCSP-PORTROUTE (Companion Port Route Description) register is an optional read-only field that is valid only if PRR (bit 7 in the HCSPARAMS register) is logic 1. Its address is content of the base address register + 0Ch. This field is a 15-element nibble array, each four bits is one array element. Each array location corresponds one-to-one with a physical port provided by the host controller. For example, PORTROUTE[0] corresponds to the first PORTSC port, PORTROUTE[1] to the second PORTSC port, and so on. The value of each element indicates to which of the companion host controllers this port is routed. Only the first N_PORTS elements have valid information. A value of zero indicates that the port is routed to the lowest numbered function companion host controller. A value of one indicates that the port is routed to the next lowest numbered function companion host controller, and so on.
11.3 Operational registers of enhanced USB host controller
11.3.1 USBCMD register
The USB Command (USBCMD) register indicates the command to be executed by the serial host controller. Writing to this register causes a command to be executed. Table 93 shows the bit allocation.
Table 93. USBCMD - USB Command register bit allocation Address: Content of the base address register + 20h Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 ITC[7:0] 1 R/W 0 R/W 0 R/W 0 R/W 31 30 29 28 reserved[1] 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
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14 0 R/W 6 IAAD 0 R/W 13 0 R/W 5 ASE 0 R/W 12 reserved[1] 0 R/W 4 PSE 0 R/W 0 R/W 11 0 R/W 3 FLS[1:0] 0 R/W 10 0 R/W 2 9 0 R/W 1 HC RESET 0 R/W 8 0 R/W 0 RS 0 R/W
Bit Symbol Reset Access Bit Symbol Reset Access
[1]
15 0 R/W 7 LHCR 0 R/W
The reserved bits should always be written with the reset value.
Table 94. USBCMD - USB Command register bit description Address: Content of the base address register + 20h Bit 31 to 24 23 to 16 Symbol reserved ITC[7:0] Description Interrupt Threshold Control: Default = 08h. This field is used by the system software to select the maximum rate at which the host controller will issue interrupts. If software writes an invalid value to this register, the results are undefined. Valid values are: 00h -- reserved 01h -- 1 microframe 02h -- 2 microframes 04h -- 4 microframes 08h -- 8 microframes (equals 1 ms) 10h -- 16 microframes (equals 2 ms) 20h -- 32 microframes (equals 4 ms) 40h -- 64 microframes (equals 8 ms) Software modifications to this field while HCH (bit 12) in the USBSTS register is zero results in undefined behavior. 15 to 8 7 reserved LHCR Light Host Controller Reset: This control bit is not required. It allows the driver software to reset the EHCI controller, without affecting the state of the ports or the relationship to the companion host controllers. If not implemented, a read of this field will always return zero. If implemented, on read: 0 -- Indicates that the Light Host Controller Reset has completed and it is ready for the host software to re-initialize the host controller. 1 -- Indicates that the Light Host Controller Reset has not yet completed. 6 IAAD Interrupt on Asynchronous Advance Doorbell: This bit is used as a doorbell by software to notify the host controller to issue an interrupt the next time it advances the asynchronous schedule. Software must write logic 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets IAA (bit 5 in the USBSTS register). If IAAE (bit 5 in the USBINTR register) is logic 1, then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to logic 0 after it sets IAA. Software must not set this bit when the asynchronous schedule is inactive because this results in an undefined value.
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Table 94. USBCMD - USB Command register bit description ...continued Address: Content of the base address register + 20h Bit 5 Symbol ASE Description Asynchronous Schedule Enable: Default = 0. This bit controls whether the host controller skips processing the asynchronous schedule. 0 -- Do not process the asynchronous schedule. 1 -- Use the ASYNCLISTADDR register to access the asynchronous schedule. 4 PSE Periodic Schedule Enable: Default = 0. This bit controls whether the host controller skips processing the periodic schedule. 0 -- Do not process the periodic schedule. 1 -- Use the PERIODICLISTBASE register to access the periodic schedule. 3 to 2 FLS[1:0] Frame List Size: Default = 00b. This field is read and write only if PFLF (bit 1) in the HCCPARAMS register is set to logic 1. This field specifies the size of the frame list. The size the frame list controls which bits in the Frame Index register must be used for the frame list current index. 00b -- 1024 elements (4096 bytes) 01b -- 512 elements (2048 bytes) 10b -- 256 elements (1024 bytes) for small environments 11b -- reserved 1 HCRESET Host Controller Reset: This control bit is used by the software to reset the host controller. The effects of this on Root Hub registers are similar to a chip hardware reset. Setting this bit causes the host controller to reset its internal pipelines, timers, counters, state machines, and so on, to their initial values. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. This reset does not affect the PCI Configuration registers. All operational registers, including port registers and port state machines, are set to their initial values. Port ownership reverts to the companion host controller(s). The software must re-initialize the host controller to return it to an operational state. This bit is cleared by the host controller when the reset process is complete. Software cannot terminate the reset process early by writing logic 0 to this register. Software must check that bit HCH is logic 0 before setting this bit. Attempting to reset an actively running host controller results in undefined behavior. Run/Stop: 1 = Run. 0 = Stop. When set, the host controller executes the schedule. The host controller continues execution as long as this bit is set. When this bit is cleared, the host controller completes the current and active transactions in the USB pipeline, and then halts. Bit HCH indicates when the host controller has finished the transaction and has entered the stopped state. Software must check that the HCH bit is logic 1, before setting this bit.
0
RS
11.3.2 USBSTS register
The USB Status (USBSTS) register indicates pending interrupts and various states of the host controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software clears register bits by writing ones to them. The bit allocation is given in Table 95.
Table 95. USBSTS - USB Status register bit allocation Address: Content of the base address register + 24h Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 31 30 29 28 reserved[1] 0 R/W 0 R/W 0 R/W 0 R/W 27 26 25 24
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22 0 R/W 14 21 0 R/W 13 RECL 0 R 5 IAA 0 R/W 0 R 20 reserved[1] 0 R/W 12 HCH 1 R 4 HSE 0 R/W 0 R/W 3 FLR 0 R/W 0 R/W 2 PCD 0 R/W 19 0 R/W 11 18 0 R/W 10 reserved[1] 0 R/W 1 USB ERRINT 0 R/W 0 R/W 0 USBINT 0 R/W 17 0 R/W 9 16 0 R/W 8
Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
23 0 R/W 15 ASS 0 R 7 reserved[1] 0 R/W
PSSTAT 0 R 6
The reserved bits should always be written with the reset value.
Table 96. USBSTS - USB Status register bit description Address: Content of the base address register + 24h Bit 31 to 16 15 Symbol reserved ASS Description Asynchronous Schedule Status: Default = 0. The bit reports the current real status of the asynchronous schedule. If this bit is logic 0, the status of the asynchronous schedule is disabled. If this bit is logic 1, the status of the asynchronous schedule is enabled. The host controller is not required to immediately disable or enable the asynchronous schedule when software changes ASE (bit 5 in the USBCMD register). When this bit and the ASE bit have the same value, the asynchronous schedule is either enabled (1) or disabled (0). Periodic Schedule Status: Default = 0. This bit reports the current status of the periodic schedule. If this bit is logic 0, the status of the periodic schedule is disabled. If this bit is logic 1, the status of the periodic schedule is enabled. The host controller is not required to immediately disable or enable the periodic schedule when software changes PSE (bit 4) in the USBCMD register. When this bit and the PSE bit have the same value, the periodic schedule is either enabled (1) or disabled (0). Reclamation: Default = 0. This is a read-only status bit that is used to detect an empty asynchronous schedule. HC Halted: Default = 1. This bit is logic 0 when RS (bit 0) in the USBCMD register is logic 1. The host controller sets this bit to logic 1 after it has stopped executing because the RS bit is set to logic 0, either by software or by the host controller hardware. For example, on an internal error. Interrupt on Asynchronous Advance: Default = 0. The system software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing logic 1 to IAAD (bit 6) in the USBCMD register. This status bit indicates the assertion of that interrupt source. Host System Error: The host controller sets this bit when a serious error occurs during a host system access, involving the host controller module. In a PCI system, conditions that set this bit include PCI parity error, PCI master abort and PCI target abort. When this error occurs, the host controller clears RS (bit 0 in the USBCMD register) to prevent further execution of the scheduled TDs.
14
PSSTAT
13 12
RECL HCH
11 to 6 5
reserved IAA
4
HSE
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Table 96. USBSTS - USB Status register bit description ...continued Address: Content of the base address register + 24h Bit 3 Symbol FLR Description Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size, as programmed in FLS (bits 3 to 2) of the USBCMD register, is 1024, the Frame Index register rolls over every time bit 13 of the FRINDEX register toggles. Similarly, if the size is 512, the host controller sets this bit to logic 1 every time bit 12 of the FRINDEX register toggles. Port Change Detect: The host controller sets this bit to logic 1 when any port, where PO (bit 13 of PORTSC) is cleared, changes to logic 1, or FPR (bit 6 of PORTSC) changes to logic 1 as a result of a J-K transition detected on a suspended port. This bit is allowed to be maintained in the auxiliary power well. Alternatively, it is also acceptable that, on a D3-to-D0 transition of the EHCI host controller device, this bit is loaded with the logical OR of all the PORTSC change bits, including force port resume, overcurrent change, enable or disable change, and connect status change. USB Error Interrupt: The host controller sets this bit when an error condition occurs because of completing a USB transaction. For example, error counter underflow. If the Transfer Descriptor (TD) on which the error interrupt occurred also had its IOC bit set, both this bit and the USBINT bit are set. For details, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. USB Interrupt: The host controller sets this bit on completing a USB transaction, which results in the retirement of a TD that had its IOC bit set. The host controller also sets this bit when a short packet is detected, that is, the actual number of bytes received was less than the expected number of bytes. For details, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
2
PCD
1
USBERR INT
0
USBINT
11.3.3 USBINTR register
The USB Interrupt Enable (USBINTR) register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this register still appear in USBSTS to allow the software to poll for events. The USBSTS register bit allocation is given in Table 97.
Table 97. USBINTR - USB Interrupt Enable register bit allocation Address: Content of the base address register + 28h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 reserved[1] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 reserved[1] 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 31 30 29 28 reserved[1] 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
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6 5 IAAE 0 R/W 0 R/W 4 HSEE 0 R/W 3 FLRE 0 R/W 2 PCIE 0 R/W 1 USBERR INTE 0 R/W 0 USBINTE 0 R/W
Bit Symbol Reset Access
[1]
7 reserved[1] 0 R/W
The reserved bits should always be written with the reset value.
Table 98. USBINTR - USB Interrupt Enable register bit description Address: Content of the base address register + 28h Bit 31 to 6 5 Symbol reserved IAAE Description Interrupt on Asynchronous Advance Enable: When this bit and IAA (bit 5 in the USBSTS register) are set, the host controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing bit IAA. Host System Error Enable: When this bit and HSE (bit 4 in the USBSTS register) are set, the host controller issues an interrupt. The interrupt is acknowledged by software clearing bit HSE. Frame List Rollover Enable: When this bit and FLR (bit 3 in the USBSTS register) are set, the host controller issues an interrupt. The interrupt is acknowledged by software clearing bit FLR. Port Change Interrupt Enable: When this bit and PCD (bit 2 in the USBSTS register) are set, the host controller issues an interrupt. The interrupt is acknowledged by software clearing bit PCD. USB Error Interrupt Enable: When this bit and USBERRINT (bit 1 in the USBSTS register) are set, the host controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing bit USBERRINT. USB Interrupt Enable: When this bit and USBINT (bit 0 in the USBSTS register) are set, the host controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing bit USBINT.
4 3 2 1
HSEE FLRE PCIE USB ERRINTE USBINTE
0
11.3.4 FRINDEX register
The Frame Index (FRINDEX) register is used by the host controller to index into the periodic frame list. The register updates every 125 s, once each microframe. Bits N to 3 are used to select a particular entry in the periodic frame list during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by the system software in FLS[1:0] (bits 3 to 2) of the USBCMD register. This register must be written as a DWORD. Byte writes produce undefined results. This register cannot be written unless the host controller is in the halted state, as indicated by HCH (bit 12 in the USBSTS register). A write to this register while RS (bit 0 in the USBCMD register) is set produces undefined results. Writes to this register also affect the SOF value. The bit allocation is given in Table 99.
Table 99. FRINDEX - Frame Index register bit allocation Address: Content of the base address register + 2Ch Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 31 30 29 28 reserved[1] 0 R/W 0 R/W 0 R/W 0 R/W 27 26 25 24
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22 0 R/W 14 21 0 R/W 13 0 R/W 5 0 R/W 20 reserved[1] 0 R/W 12 0 R/W 4 0 R/W 19 0 R/W 11 0 R/W 3 0 R/W 18 0 R/W 10 0 R/W 2 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W 16 0 R/W 8 0 R/W 0 0 R/W
Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
23 0 R/W 15 reserved[1] 0 R/W 7 0 R/W
FRINDEX[13:8] 0
R/W 6 0 R/W
FRINDEX[7:0]
The reserved bits should always be written with the reset value.
Table 100. FRINDEX - Frame Index register bit description Address: Content of the base address register + 2Ch Bit 31 to 14 13 to 0 Symbol reserved FRINDEX [13:0] Description Frame Index: Bits in this register are used for the frame number in the SOF packet and as the index into the frame list. The value in this register increments at the end of each time frame. For example, microframe. The bits used for the frame number in the SOF token are taken from bits 13 to 3 of this register. Bits N to 3 are used for the frame list current index. This means that each location of the frame list is accessed eight times, frames or microframes, before moving to the next index. Table 101 illustrates values of N based on the value of FLS[1:0] (bits 3 to 2 in the USBCMD register). Table 101. N based value of FLS[1:0] FLS[1:0] 00b 01b 10b 11b Number elements 1024 512 256 reserved N 12 11 10 -
11.3.5 PERIODICLISTBASE register
The Periodic Frame List Base Address (PERIODLISTBASE) register contains the beginning address of the periodic frame list in the system memory. If the host controller is in 64-bit mode, as indicated by logic 1 in 64AC (bit 0 of the HCCPARAMS register), the most significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT register. For details on the CTRLDSSEGMENT register, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. The system software loads this register before starting the schedule execution by the host controller. The memory structure referenced by this physical memory pointer is assumed as 4 kB aligned. The contents of this register are combined with the FRINDEX register to enable the host controller to step through the periodic frame list in sequence. The bit allocation is given in Table 102.
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Table 102. PERIODICLISTBASE - Periodic Frame List Base Address register bit allocation Address: Content of the base address register + 34h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 0 R/W 23 0 R/W 15 0 R/W 7 0 R/W
30 0 R/W 22 0 R/W 14 BA[3:0] 0 R/W 6 0 R/W
29 0 R/W 21 0 R/W 13 0 R/W 5 0 R/W
28 BA[19:12] 0 R/W 20 BA[11:4] 0 R/W 12 0 R/W 4 reserved[1] 0 R/W
27 0 R/W 19 0 R/W 11 0 R/W 3 0 R/W
26 0 R/W 18 0 R/W 10 reserved[1] 0 R/W 2 0 R/W
25 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W
24 0 R/W 16 0 R/W 8 0 R/W 0 0 R/W
The reserved bits should always be written with the reset value.
Table 103. PERIODICLISTBASE - Periodic Frame List Base Address register bit description Address: Content of the base address register + 34h Bit 31 to 12 11 to 0 Symbol BA[19:0] reserved Description Base Address: These bits correspond to memory address signals 31 to 12, respectively. -
11.3.6 ASYNCLISTADDR register
This 32-bit register contains the address of the next asynchronous queue head to be executed. If the host controller is in 64-bit mode, as indicated by logic 1 in 64AC (bit 0 of the HCCPARAMS register), the most significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT register. For details on the CTRLDSSEGMENT register, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. Bits 4 to 0 of this register always return zeros when read. The memory structure referenced by the physical memory pointer is assumed as 32 bytes (cache aligned). For bit allocation, see Table 104.
Table 104. ASYNCLISTADDR - Current Asynchronous List Address register bit allocation Address: Content of the base address register + 38h Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 31 30 29 28 LPL[26:19] 0 R/W 0 R/W 0 R/W 0 R/W 27 26 25 24
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22 0 R/W 14 0 R/W 6 21 0 R/W 13 0 R/W 5 0 R/W 20 LPL[18:11] 0 R/W 12 LPL[10:3] 0 R/W 4 0 R/W 19 0 R/W 11 0 R/W 3 0 R/W 18 0 R/W 10 0 R/W 2 reserved[1] 0 R/W 0 R/W 0 R/W 17 0 R/W 9 0 R/W 1 16 0 R/W 8 0 R/W 0
Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
23 0 R/W 15 0 R/W 7 0 R/W
LPL[2:0] 0 R/W
The reserved bits should always be written with the reset value.
Table 105. ASYNCLISTADDR - Current Asynchronous List Address register bit description Address: Content of the base address register + 38h Bit 31 to 5 4 to 0 Symbol LPL[26:0] reserved Description Link Pointer List: These bits correspond to memory address signals 31 to 5, respectively. This field may only reference a Queue Head (QH). -
11.3.7 CONFIGFLAG register
The bit allocation of the Configure Flag (CONFIGFLAG) register is given in Table 106.
Table 106. CONFIGFLAG - Configure Flag register bit allocation Address: Content of the base address register + 60h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 0 R/W 23 0 R/W 15 0 R/W 7 0 R/W
30 0 R/W 22 0 R/W 14 0 R/W 6 0 R/W
29 0 R/W 21 0 R/W 13 0 R/W 5 0 R/W
28 reserved[1] 0 R/W 20 reserved[1] 0 R/W 12 reserved[1] 0 R/W 4 reserved[1] 0 R/W
27 0 R/W 19 0 R/W 11 0 R/W 3 0 R/W
26 0 R/W 18 0 R/W 10 0 R/W 2 0 R/W
25 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W
24 0 R/W 16 0 R/W 8 0 R/W 0 CF 0 R/W
The reserved bits should always be written with the reset value.
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Table 107. CONFIGFLAG - Configure Flag register bit description Address: Content of the base address register + 60h Bit 31 to 1 0 Symbol reserved CF Description Configure Flag: The host software sets this bit as the last action in its process of configuring the host controller. This bit controls the default port-routing control logic. 0 -- Port routing control logic default-routes each port to an implementation-dependent classic host controller. 1 -- Port routing control logic default-routes all ports to this host controller.
11.3.8 PORTSC registers 1, 2
The Port Status and Control (PORTSC) register is in the auxiliary power well. It is only reset by hardware when the auxiliary power is initially applied or in response to a host controller reset. The initial conditions of a port are:
* No device connected * Port disabled
If the port has power control, software cannot change the state of the port until it sets port power bits. Software must not attempt to change the state of the port until power is stable on the port; maximum delay is 20 ms from the transition. For bit allocation, see Table 108.
Table 108. PORTSC 1, 2 - Port Status and Control 1, 2 register bit allocation Address: Content of the base address register + 64h + (4 x Port Number - 1) where Port Number is 1, 2 Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
31 0 R/W 23 reserved 0 R/W 15 reserved[1] 0 R/W 7 SUSP 0 R/W
30 0 R/W 22 WKOC_E 0 R/W 14 0 R/W 6 FPR 0 R/W
29 0 R/W 21 WKDS CNNT_E 0 R/W 13 PO 1 R/W 5 OCC 0 R
28 reserved[1] 0 R/W 20 WKCNNT_ E 0 R/W 12 PP 0 R/W 4 OCA 0 R
27 0 R/W 19
26 0 R/W 18 PTC[3:0]
25 0 R/W 17
24 0 R/W 16
0 R/W 11 LS[1:0] 0 R/W 3 PEDC 0 R/W
0 R/W 10 0 R/W 2 PED 0 R/W
0 R/W 9 reserved[1] 0 R/W 1 ECSC 0 R/W
0 R/W 8 PR 0 R 0 ECCS 0 R
The reserved bits should always be written with the reset value.
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Table 109. PORTSC 1, 2 - Port Status and Control 1, 2 register bit description Address: Content of the base address register + 64h + (4 x Port Number - 1) where Port Number is 1, 2 Bit 31 to 23 22 21 20 19 to 16 Symbol reserved WKOC_E WKDS CNNT_E WKCNNT_E PTC[3:0] Description Wake on Overcurrent Enable: Default = 0. Setting this bit enables the port to be sensitive to overcurrent conditions as wake-up events.[1] Wake on Disconnect Enable: Default = 0. Setting this bit enables the port to be sensitive to device disconnects as wake-up events.[1] Wake on Connect Enable: Default = 0. Setting this bit enables the port to be sensitive to device connects as wake-up events.[1] Port Test Control: Default = 0000b. When this field is logic 0, the port is not operating in test mode. A nonzero value indicates that it is operating in test mode and test mode is indicated by the value. The encoding of the test mode bits are: 0000b -- Test mode disabled 0001b -- Test J_STATE 0010b -- Test K_STATE 0011b -- Test SE0_NAK 0100b -- Test packet 0101b -- Test FORCE_ENABLE 0110b to 1111b -- reserved 15 to 14 13 reserved PO Port Owner: Default = 1. This bit unconditionally goes to logic 0 when CF (bit 0) in the CONFIGFLAG register makes logic 0 to logic 1 transition. This bit unconditionally goes to logic 1 when the CF bit is logic 0. The system software uses this field to release ownership of the port to a selected host controller, if the attached device is not a high-speed device. Software writes logic 1 to this bit, if the attached device is not a high-speed device. Logic 1 in this bit means that a companion host controller owns and controls the port. Port Power: The function of this bit depends on the value of PPC (bit 4) in the HCSPARAMS register. If PPC = 0 and PP = 1 -- The host controller does not have port power control switches. Always powered. If PPC = 1 and PP = 1 or 0 -- The host controller has port power control switches. This bit represents the current setting of the switch: logic 0 = off, logic 1 = on. When PP is logic 0, the port is nonfunctional and will not report any status. When an overcurrent condition is detected on a powered port and PPC is logic 1, the PP bit in each affected port may be changed by the host controller from logic 1 to logic 0, removing power from the port. 11 to 10 LS[1:0] Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. These bits are used to detect low-speed USB devices before the port reset and enable sequence. This field is valid only when the Port Enable bit is logic 0, and the Current Connect Status bit is set to logic 1. 00b -- SE0: Not a low-speed device, perform EHCI reset 01b -- K-state: Low-speed device, release ownership of port 10b -- J-state: Not a low-speed device, perform EHCI reset 11b -- Undefined: Not a low-speed device, perform EHCI reset If the PP bit is logic 0, this field is undefined. 9 reserved -
12
PP
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Table 109. PORTSC 1, 2 - Port Status and Control 1, 2 register bit description ...continued Address: Content of the base address register + 64h + (4 x Port Number - 1) where Port Number is 1, 2 Bit 8 Symbol PR Description Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is not in reset. Default = 0. When software sets this bit from logic 0, the bus reset sequence as defined in Universal Serial Bus Specification Rev. 2.0 is started. Software clears this bit to terminate the bus reset sequence. Software must hold this bit at logic 1 until the reset sequence, as specified in Universal Serial Bus Specification Rev. 2.0, is completed. Remark: When software sets this bit, it must also clear the Port Enable bit. Remark: When software clears this bit, there may be a delay before the bit status changes to logic 0 because it will not read logic 0 until the reset is completed. If the port is in high-speed mode after reset is completed, the host controller will automatically enable this port; it can set the Port Enable bit. A host controller must terminate the reset and stabilize the state of the port within 2 ms of software changing this bit from logic 1 to logic 0. For example, if the port detects that the attached device is high-speed during a reset, then the host controller must enable the port within 2 ms of software clearing this bit. HCH (bit 12) in the USBSTS register must be logic 0 before software attempts to use this bit. The host controller may hold Port Reset asserted when the HCH bit is set.[1] 7 SUSP Suspend: Default = 0. Logic 1 means the port is in the suspend state. Logic 0 means the port is not suspended. The PED (Port Enabled) bit and this bit define the port states as follows: PED = 0 and SUSP = X -- Port is disabled. PED = 1 and SUSP = 0 -- Port is enabled. PED = 1 and SUSP = 1 -- Port is suspended. When in the suspend state, downstream propagation of data is blocked on this port, except for the port reset. If a transaction was in progress when this bit was set, blocking occurs at the end of the current transaction. In the suspend state, the port is sensitive to resume detection. The bit status does not change until the port is suspended and there may be a delay in suspending a port, if there is a transaction currently in progress on the USB. Attempts to clear this bit are ignored by the host controller. The host controller will unconditionally set this bit to logic 0 when:
* *
6 FPR
Software changes the FPR (Force Port Resume) bit to logic 0. Software changes the PR (Port Reset) bit to logic 1.
If the host software sets this bit when the Port Enabled bit is logic 0, the results are undefined.[1] Force Port Resume: Logic 1 means resume detected or driven on the port. Logic 0 means no resume (K-state) detected or driven on the port. Default = 0. Software sets this bit to drive the resume signaling. The host controller sets this bit if a J-to-K transition is detected, while the port is in the suspend state. When this bit changes to logic 1 because a J-to-K transition is detected, PCD (bit 2) in the USBSTS register is also set to logic 1. If software sets this bit to logic 1, the host controller must not set the PCD bit. When the EHCI controller owns the port, the resume sequence follows the sequence specified in Universal Serial Bus Specification Rev. 2.0. The resume signaling (full-speed `K') is driven on the port as long as this bit remains set. Software must time the resume and clear this bit after the correct amount of time has elapsed. Clearing this bit causes the port to return to high-speed mode, forcing the bus below the port into a high-speed idle. This bit will remain at logic 1, until the port has switched to the high-speed idle. The host controller must complete this transition within 2 ms of software clearing this bit.[1] Overcurrent Change: Default = 0. This bit is set to logic 1 when there is a change in overcurrent active. Software clears this bit by setting it to logic 1. Overcurrent Active: Default = 0. If set to logic 1, this port has an overcurrent condition. If set to logic 0, this port does not have an overcurrent condition. This bit will automatically change from logic 1 to logic 0 when the overcurrent condition is removed.
5 4
OCC OCA
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Table 109. PORTSC 1, 2 - Port Status and Control 1, 2 register bit description ...continued Address: Content of the base address register + 64h + (4 x Port Number - 1) where Port Number is 1, 2 Bit 3 Symbol PEDC Description Port Enable/Disable Change: Logic 1 means the port enabled or disabled status has changed. Logic 0 means no change. Default = 0. For the root hub, this bit is set only when a port is disabled because of the appropriate conditions existing at the EOF2 point. For definition of port error, refer to Chapter 11 of Universal Serial Bus Specification Rev. 2.0. Software clears this bit by setting it.[1] Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable. Default = 0. Ports can only be enabled by the host controller as a part of the reset and enable sequence. Software cannot enable a port by writing logic 1 to this field. The host controller will only set this bit when the reset sequence determines that the attached device is a high-speed device. Ports can be disabled by either a fault condition or by host software. The bit status does not change until the port state has changed. There may be a delay in disabling or enabling a port because of other host controller and bus events. When the port is disabled, downstream propagation of data is blocked on this port, except for reset.[1] Connect Status Change: Logic 1 means change in ECCS. Logic 0 means no change. Default = 0. This bit indicates a change has occurred in the ECCS of the port. The host controller sets this bit for all changes to the port device connect status, even if the system software has not cleared an existing connect status change. For example, the insertion status changes two times before the system software has cleared the changed condition, hub hardware will be setting an already-set bit, that is, the bit will remain set. Software clears this bit by writing logic 1 to it.[1] Current Connect Status: Logic 1 indicates a device is present on the port. Logic 0 indicates no device is present. Default = 0. This value reflects the current state of the port and may not directly correspond to the event that caused the ECSC bit to be set.[1]
2
PED
1
ECSC
0
ECCS
[1]
These fields read logic 0, if the PP bit is logic 0.
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12. Current consumption
Table 110 shows the current consumption.
Table 110. Current consumption Cumulative current Conditions ISP1562[1] Typ 39 58 76 26 44 62 13 14 14 Unit mA mA mA mA mA mA mA mA mA Total current on pins VCC(I/O)_AUX plus no device connected to the VI(VAUX3V3) plus VDDA_AUX plus one high-speed device connected to the ISP1562 VCC(I/O) plus VI(VREG3V3) two high-speed devices connected to the ISP1562 Auxiliary current on pins VCC(I/O)_AUX plus VI(VAUX3V3) plus VDDA_AUX no device connected to the ISP1562[1] one high-speed device connected to the ISP1562 two high-speed devices connected to the ISP1562 Current on pins VCC(I/O) plus VI(VREG3V3) no device connected to the ISP1562[1] one high-speed device connected to the ISP1562 two high-speed devices connected to the ISP1562
[1]
When one or two full-speed or low-speed power devices are connected, the current consumption is comparable to the current consumption when no high-speed devices are connected. There is a difference of approximately 1 mA.
Table 111 shows the current consumption in S1 and S3 suspend modes.
Table 111. Current consumption: S1 and S3 Power state S1[1] S3[2]
[1] [2] [3]
Typ 20 8[3]
Unit mA mA
S1 represents the system state that will determine the B1 and D1 states. For details, refer to PCI Bus Power Management Interface Specification Rev. 1.1. S3 represents the system state that will determine the B3 and D3 states. For details, refer to PCI Bus Power Management Interface Specification Rev. 1.1. When I2C-bus is present.
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HS USB PCI host controller
13. Limiting values
Table 112. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC(I/O) VI(VREG3V3) VCC(I/O)_AUX VI(VAUX3V3) VDDA_AUX Ilu Vesd Tstg Parameter input/output supply voltage 3.3 V regulator input voltage auxiliary input/output supply voltage 3.3 V auxiliary input voltage auxiliary supply voltage for analog block latch-up current electrostatic discharge voltage storage temperature VI < 0 V or VI > VCC(I/O) all pins (ILI < 1 A) Conditions Min -0.5 -0.5 -0.5 -0.5 -0.5 -4 -40 Max +4.6 +4.6 +4.6 +4.6 +4.6 100 +4 +125 Unit V V V V V mA kV C
14. Recommended operating conditions
Table 113. Recommended operating conditions Symbol VCC(I/O) VI(VREG3V3) VCC(I/O)_AUX VI(VAUX3V3) VDDA_AUX VI(3V3) Tamb Tj Parameter input/output supply voltage 3.3 V regulator input voltage auxiliary input/output supply voltage 3.3 V auxiliary input voltage auxiliary supply voltage for analog block 3.3 V input voltage ambient temperature junction temperature Conditions Min 3.0 3.0 3.0 3.0 3.0 0 -40 -40 Typ 3.3 3.3 3.3 3.3 3.3 Max 3.6 3.6 3.6 3.6 3.6 VCC(I/O) + 0.5 +85 +125 Unit V V V V V V C C
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15. Static characteristics
Table 114. Static characteristics: I2C-bus interface (SDA and SCL) VCC(I/O) = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol VIH VIL Vhys VOL ICC(susp) Parameter HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage suspend supply current IOL = 3 mA Conditions Min 2.1 0 0.15 Typ 1 Max 3.6 0.9 0.4 Unit V V V V A
Table 115. Static characteristics: digital pins VCC(I/O) = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VIH VIL Vhys VOL VOH Parameter HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage HIGH-level output voltage IOL = 3 mA Conditions Min 2.0 0 0.4 2.4 Typ Max 3.6 0.8 0.7 0.4 Unit V V V V V
Table 116. Static characteristics: PCI interface block VCC(I/O) = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VIH VIL VIPU ILI VOH VOL Cin Cclk CIDSEL Parameter HIGH-level input voltage LOW-level input voltage input pull-up voltage input leakage current HIGH-level output voltage LOW-level output voltage input capacitance clock capacitance IDSEL pin capacitance 0 V < VI < VCC(I/O) IO = 500 A IO = 1500 A Conditions Min 2.0 0 2.1 -10 2.7 5 Typ Max 3.6 0.9 +10 0.3 10 12 8 Unit V V V A V V pF pF pF
Table 117. Static characteristics: USB interface block (pins DM1 to DM2 and DP1 to DP2) VDDA_AUX = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VHSSQ Parameter high-speed squelch detection threshold voltage (differential signal amplitude) Conditions squelch detected no squelch detected Min 150 625 Typ Max 100 525 Unit mV mV mV mV Input levels for high-speed
VHSDSC
high-speed disconnect detection disconnect detected threshold voltage (differential disconnect not signal amplitude) detected
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Table 117. Static characteristics: USB interface block (pins DM1 to DM2 and DP1 to DP2) ...continued VDDA_AUX = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VHSCM Parameter high-speed data signaling common mode voltage range (guideline for receiver) high-speed idle level voltage high-speed data signaling HIGH-level voltage high-speed data signaling LOW-level voltage Chirp J level (differential voltage) Chirp K level (differential voltage) HIGH-level input voltage HIGH-level input voltage (floating) for low-/full-speed LOW-level input voltage differential input sensitivity voltage differential common mode voltage range HIGH-level output voltage LOW-level output voltage SE1 output voltage output signal crossover voltage |VDP - VDM| drive Conditions Min -50 Typ Max +500 Unit mV
Output levels for high-speed VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK -10 360 -10 700[1] -900[1] +10 440 +10 1100 -500 mV mV mV mV mV
Input levels for full-speed and low-speed VIH VIHZ VIL VDI VCM 2.0 2.7 0.2 0.8 3.6 0.8 2.5 V V V V V
Output levels for full-speed and low-speed VOH VOL VOSE1 VCRS
[1]
2.8 0 0.8 1.3
-
3.6 0.3 2.0
V V V V
High-speed termination resistor disabled, pull-up resistor connected. Only during reset, when both the hub and the device are capable of high-speed operation.
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16. Dynamic characteristics
Table 118. Dynamic characteristics: system clock timing VCC(I/O) = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol PCI clock fclk(PCI) fclk RS CL VI J tCR tCF
[1] [2]
Parameter PCI clock frequency clock frequency series resistance load capacitance input voltage external clock jitter rise time fall time clock duty cycle
Conditions
Min 31
Typ 12 18 1.8 50
Max 33 100 1.95 50 3 3 -
Unit MHz MHz pF V ppm ns ns %
Crystal oscillator crystal[1]
[2]
1.65 -
External clock input
Suggested values for external capacitors when using a crystal are 22 pF to 27 pF. Recommended accuracy of the clock frequency is 50 ppm for the crystal and oscillator.
Table 119. Dynamic characteristics: I2C-bus interface (SDA and SCL) VCC(I/O) = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol tCF
[1]
Parameter output fall time VIH to VIL
Conditions 10 pF < Cb < 400 pF[1]
Min -
Typ 0
Max 250
Unit ns
The capacitive load for each bus line (Cb) is specified in pF. To meet the specification for VOL and the maximum rise time (300 ns), use an external pull-up resistor with RUP(max) = 850 / Cb k and RUP(min) = (VCC(I/O) - 0.4) / 3 k.
Table 120. Dynamic characteristics: PCI interface block VCC(I/O) = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol SR
[1]
Parameter slew rate
Conditions (rise, fall) standard load[1]
Min 1
Typ -
Max 4
Unit V/ns
Standard load is 10 pF together with a pull-up and pull-down resistor of 10 k.
Table 121. Dynamic characteristics: high-speed source electrical characteristics VDDA_AUX = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VDDA_AUX = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Driver characteristics tHSR tHSF ZHSDRV rise time (10 % to 90 %) fall time (10 % to 90 %) driver output impedance (which also includes the RS serves as high-speed termination) resistor 500 500 40.5 45 49.5 ps ps Conditions Min Typ Max Unit
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Table 121. Dynamic characteristics: high-speed source electrical characteristics ...continued VDDA_AUX = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VDDA_AUX = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Clock timing tHSDRAT tHSFRAM tHSRFI high-speed data rate microframe interval consecutive microframe interval difference 479.76 124.9375 1 480.24 125.0625 four high-speed bit times Mbit/s s ns Conditions Min Typ Max Unit
Table 122. Dynamic characteristics: full-speed source electrical characteristics VDDA_AUX = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tFR tFF tFRFM Parameter rise time fall time differential rise and fall time matching source jitter for differential transition to SE0 transition source SE0 interval of EOP receiver SE0 interval of EOP upstream facing port source low-speed timing jitter for differential transition to SE0 transition source SE0 interval of EOP receiver SE0 interval of EOP width of SE0 interval during differential transition full-speed timing Conditions CL = 50 pF; 10 % to 90 % of |VOH - VOL| CL = 50 pF; 90 % to 10 % of |VOH - VOL| Min 4 4 90 Typ Max 20 20 111.1 Unit ns ns % Driver characteristics
Data timing; see Figure 10 tFDEOP tFEOPT tFEOPR tLDEOP -2 160 82 -40 +5 175 +100 ns ns ns ns
tLEOPT tLEOPR tFST
1.25 670 -
-
1.5 14
s ns ns
Table 123. Dynamic characteristics: low-speed source electrical characteristics VDDA_AUX = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tLR tLF tLRFM Parameter transition time: rise time transition time: fall time rise and fall time matching Conditions Min 75 75 90 Typ Max 300 300 125 Unit ns ns % Driver characteristics
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16.1 Timing
Table 124. PCI clock and IO timing VCC(I/O) = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Tcyc(PCICLK) tHIGH(PCICLK) tLOW(PCICLK) SRPCICLK SRRST# tsu(PCICLK)bs tsu(PCICLK)ptp th(PCICLK) tval(PCICLK)bs tval(PCICLK)ptp tdZ(act) td(act)Z PCI reset timing trst trst-clk
[1]
Parameter PCICLK cycle time PCICLK HIGH time PCICLK LOW time PCICLK slew rate RST# slew rate set-up time to PCICLK (bus signal) set-up time to PCICLK (point-to-point) input hold time from PCICLK PCICLK to signal valid delay (bus signal) PCICLK to signal valid delay (point-to-point) float to active delay active to float delay reset active time after power stable reset active time after CLK stable
Conditions
Min 30 11 11 1 50 7
[1]
Typ -
Max 32 4 11 12 28 -
Unit ns ns ns V/ns mV/ns ns ns ns ns ns ns ns ms s
PCI clock timing; see Figure 7
PCI input timing; see Figure 8 10 0 2
[1]
PCI output timing; see Figure 9
2 2 1 100
REQ# and GNT# are point-to-point signals. GNT# has a set up of 10 ns; REQ# has a set up of 12 ns. All others are bus signals.
Tcyc(PCICLK) tHIGH(PCICLK) 0.6VCC(I/O) 0.5VCC(I/O) 0.4VCC(I/O) 0.3VCC(I/O) 0.2VCC(I/O)
004aaa604
tLOW(PCICLK)
minimum value 0.4VCC(I/O)
Fig 7.
PCI clock
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0.6VCC(I/O) CLK tsu(PCICLK)bs; tsu(PCICLK)ptp 0.4VCC(I/O) 0.2VCC(I/O) th(PCICLK) 0.6VCC(I/O) INPUT DELAY inputs valid 0.4VCC(I/O) 0.2VCC(I/O)
004aaa605
Fig 8.
PCI input timing
0.6VCC(I/O) CLK tval(PCICLK)bs; tval(PCICLK)ptp 0.615VCC(I/O) (falling edge) OUTPUT DELAY 0.285VCC(I/O) (rising edge) 0.4VCC(I/O) 0.2VCC(I/O)
OUTPUT
tdZ(act) td(act)Z
004aaa606
Fig 9.
PCI output timing
tUSBbit +3.3 V crossover point differential data lines crossover point extended
0V differential data to SE0/EOP skew N x tUSBbit + t DEOP source EOP width: t EOPT receiver EOP width: t EOPR
004aaa704
tUSBbit is the bit duration (USB data). tDEOP is the source jitter for differential transition to SE0 transition. Full-speed and low-speed timing symbols have a subscript prefix `F' and `L', respectively.
Fig 10. USB source differential data-to-EOP transition skew and EOP width
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17. Package outline
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
c
y X 75 76 51 50 ZE A
e E HE wM bp pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X L Lp A A2 (A 3)
A1
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7o o 0
16.25 16.25 15.75 15.75
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-02-01 03-02-20
Fig 11. Package outline SOT407-1 (LQFP100)
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18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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18.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 12) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 125 and 126
Table 125. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 235 220 350 220 220
Table 126. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 12.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 12. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
19. Abbreviations
Table 127. Abbreviations Acronym DID DWORD ED EHCI EMI EOF ESD ESR HC HCCA HCD HCI MSB OHCI PCI PCI-SIG PLL PM PMC
ISP1562_3
Description Device ID Double Word Endpoint Descriptor Enhanced Host Controller Interface ElectroMagnetic Interference End-Of-Frame ElectroStatic Discharge Effective Series Resistance Host Controller Host Controller Communication Area Host Controller Driver Host Controller Interface Most Significant Bit Open Host Controller Interface Peripheral Component Interconnect PCI-Special Interest Group Phase-Locked Loop Power Management Power Management Capabilities
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Table 127. Abbreviations ...continued Acronym PME POR POST QH SMI SOF STB TD USB VID Description Power Management Event Power-On Reset Power-On Self Test Queue Head System Management Interrupt Start-Of-Frame Set-Top Box Transfer Descriptor Universal Serial Bus Vendor ID
20. References
[1] [2] [3] [4] [5] [6] Universal Serial Bus Specification -- Rev. 2.0 Open Host Controller Interface Specification for USB -- Rev. 1.0a Enhanced Host Controller Interface Specification for Universal Serial Bus -- Rev. 1.0 PCI Local Bus Specification -- Rev. 2.2 PCI Bus Power Management Interface Specification -- Rev. 1.1 The I2C-bus Specification -- Version 2.1
21. Revision history
Table 128. Revision history Document ID ISP1562_3 Modifications: Release date 20081114 Data sheet status Product data sheet Change notice Supersedes ISP1562_2
* * * *
Updated Figure 3 "Power-on reset". Figure 4 "Power supply connection": added Figure note 3. Table 42 "USB host controller registers": added Table note 2. Table 118 "Dynamic characteristics: system clock timing": removed tW(RESET_N). Product data sheet Product data sheet ISP1562_1 -
ISP1562_2 ISP1562_1 (9397 750 14223)
20070301 20050714
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22. Legal information
22.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
22.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
23. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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24. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 PCI configuration space registers of OHCI1, OHCI2 and EHCI . . . . . . . . . . . . . . . . . . . . . . .14 VID - Vendor ID register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 DID - Device ID register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 CMD - Command register (address 04h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 CMD - Command register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 STATUS - Status register (address 06h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 STATUS - Status register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 REVID - Revision ID register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .18 CC - Class Code register (address 09h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 CC - Class Code register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 CLS - CacheLine Size register (address 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .19 LT - Latency Timer register (address 0Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 HT - Header Type register (address 0Eh) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 HT - Header Type register (address 0Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 BAR0 - Base Address register 0 (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .20 SVID - Subsystem Vendor ID register (address 2Ch) bit description . . . . . . . . . . . . . .20 SID - Subsystem ID register (address 2Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .21 CP - Capabilities Pointer register (address 34h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .21 IL - Interrupt Line register (address 3Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 IP - Interrupt Pin register (address 3Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 MIN_GNT - Minimum Grant register (address 3Eh) bit description . . . . . . . . . . . . . . . . . . . . .22 MAX_LAT - Maximum Latency register (address 3Fh) bit description . . . . . . . . . . . . . .22 EHCI-specific PCI registers . . . . . . . . . . . . . . .23 SBRN - Serial Bus Release Number register (address 60h) bit description . . . . . . . . . . . . . . 23 Table 27. FLADJ - Frame Length Adjustment register (address 61h) bit allocation . . . . . . . . . . . . . . . 23 Table 28. FLADJ - Frame Length Adjustment register (address 61h) bit description . . . . . . . . . . . . . . 23 Table 29. FLADJ value as a function of SOF cycle time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 30. PORTWAKECAP - Port Wake Capability register (address 62h) bit description . . . . . . . 24 Table 31. Power management registers . . . . . . . . . . . . . 24 Table 32. CAP_ID - Capability Identifier register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 33. NEXT_ITEM_PTR - Next Item Pointer register bit description . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 34. PMC - Power Management Capabilities register bit allocation . . . . . . . . . . . . . . . . . . . . 25 Table 35. PMC - Power Management Capabilities register bit description . . . . . . . . . . . . . . . . . . . 26 Table 36. PMCSR - Power Management Control/Status register bit allocation . . . . . . . . 27 Table 37. PMCSR - Power Management Control/Status register bit description . . . . . . . 27 Table 38. PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit allocation . . . . 28 Table 39. PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit description . . . 28 Table 40. PCI bus power and clock control . . . . . . . . . . . 28 Table 41. DATA - Data register bit description . . . . . . . . . 29 Table 42. USB host controller registers . . . . . . . . . . . . . 32 Table 43. HcRevision - Host Controller Revision register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 44. HcRevision - Host Controller Revision register bit description . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 45. HcControl - Host Controller Control register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 46. HcControl - Host Controller Control register bit description . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 47. HcCommandStatus - Host Controller Command Status register bit allocation . . . . . 36 Table 48. HcCommandStatus - Host Controller Command Status register bit description . . . . 37 Table 49. HcInterruptStatus - Host Controller Interrupt Status register bit allocation . . . . . . . 37 Table 50. HcInterruptStatus - Host Controller Interrupt Status register bit description . . . . . . 38 Table 51. HcInterruptEnable - Host Controller Interrupt Enable register bit allocation . . . . . . . 39 Table 52. HcInterruptEnable - Host Controller
continued >>
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 14 November 2008
88 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
Table 74. HcFmNumber - Host Controller Frame Number register bit description . . . . . . . . . . . . 49 Table 75. HcPeriodicStart - Host Controller Periodic Start register bit allocation . . . . . . . . . . . . . . . 50 Table 76. HcPeriodicStart - Host Controller Periodic Start register bit description . . . . . . . . . . . . . . 50 Table 77. HcLSThreshold - Host Controller Low-Speed Threshold register bit allocation . . . . . . . . . . . 50 Table 78. HcLSThreshold - Host Controller Low-Speed Threshold register bit description . . . . . . . . . . 51 Table 79. HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit allocation . . . . . . . . . 51 Table 80. HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit description . . . . . . . . 52 Table 81. HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit allocation . . . . . . . . . 53 Table 82. HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit description . . . . . . . . 53 Table 83. HcRhStatus - Host Controller Root Hub Status register bit allocation . . . . . . . . . . . . . . 53 Table 84. HcRhStatus - Host Controller Root Hub Status register bit description . . . . . . . . . . . . . 54 Table 85. HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit allocation . . . 55 Table 86. HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description . . 55 Table 87. CAPLENGTH/HCIVERSION - Capability Length/Host Controller Interface Version Number register bit allocation . . . . . . . . . . . . . 58 Table 88. CAPLENGTH/HCIVERSION - Capability Length/Host Controller Interface Version Number register bit description . . . . . . . . . . . . 58 Table 89. HCSPARAMS - Host Controller Structural Parameters register bit allocation . . . . . . . . . . 59 Table 90. HCSPARAMS - Host Controller Structural Parameters register bit description . . . . . . . . . 59 Table 91. HCCPARAMS - Host Controller Capability Parameters register bit allocation . . . . . . . . . . 60 Table 92. HCCPARAMS - Host Controller Capability Parameters register bit description . . . . . . . . . 60 Table 93. USBCMD - USB Command register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 94. USBCMD - USB Command register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 95. USBSTS - USB Status register bit allocation . 63 Table 96. USBSTS - USB Status register bit description 64 Table 97. USBINTR - USB Interrupt Enable register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 98. USBINTR - USB Interrupt Enable register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 99. FRINDEX - Frame Index register bit allocation 66
Interrupt Enable register bit description . . . . . .39 Table 53. HcInterruptDisable - Host Controller Interrupt Disable register bit allocation . . . . . .40 Table 54. HcInterruptDisable - Host Controller Interrupt Disable register bit description . . . . .41 Table 55. HcHCCA - Host Controller Communication Area register bit allocation . . . . . . . . . . . . . . . .42 Table 56. HcHCCA - Host Controller Communication Area register bit description . . . . . . . . . . . . . . .42 Table 57. HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Table 58. HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit description . . . . . . . . . . . . . . . . . . . . . . . . .43 Table 59. HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Table 60. HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 61. HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 62. HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit description . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 63. HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit allocation . . . .45 Table 64. HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit description . . .45 Table 65. HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Table 66. HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Table 67. HcDoneHead - Host Controller Done Head register bit allocation . . . . . . . . . . . . . . . . . . . .46 Table 68. HcDoneHead - Host Controller Done Head register bit description . . . . . . . . . . . . . . . . . . .47 Table 69. HcFmInterval - Host Controller Frame Interval register bit allocation . . . . . . . . . . . . . .47 Table 70. HcFmInterval - Host Controller Frame Interval register bit description . . . . . . . . . . . . .48 Table 71. HcFmRemaining - Host Controller Frame Remaining register bit allocation . . . . . . . . . . .48 Table 72. HcFmRemaining - Host Controller Frame Remaining register bit description . . . . . . . . . .49 Table 73. HcFmNumber - Host Controller Frame Number register bit allocation . . . . . . . . . . . . .49
continued >>
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 14 November 2008
89 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
Table 100.FRINDEX - Frame Index register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Table 101.N based value of FLS[1:0] . . . . . . . . . . . . . . . .67 Table 102.PERIODICLISTBASE - Periodic Frame List Base Address register bit allocation . . . . . . . .68 Table 103.PERIODICLISTBASE - Periodic Frame List Base Address register bit description . . . . . . .68 Table 104.ASYNCLISTADDR - Current Asynchronous List Address register bit allocation . . . . . . . . . .68 Table 105.ASYNCLISTADDR - Current Asynchronous List Address register bit description . . . . . . . . .69 Table 106.CONFIGFLAG - Configure Flag register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Table 107.CONFIGFLAG - Configure Flag register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Table 108.PORTSC 1, 2 - Port Status and Control 1, 2 register bit allocation . . . . . . . . . . . . . . . . . . . .70 Table 109.PORTSC 1, 2 - Port Status and Control 1, 2 register bit description . . . . . . . . . . . . . . . . . . .71 Table 110.Current consumption . . . . . . . . . . . . . . . . . . . .74 Table 111.Current consumption: S1 and S3 . . . . . . . . . . .74 Table 112.Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .75 Table 113.Recommended operating conditions . . . . . . . .75 Table 114.Static characteristics: I2C-bus interface (SDA and SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Table 115.Static characteristics: digital pins . . . . . . . . . . .76 Table 116.Static characteristics: PCI interface block . . . .76 Table 117.Static characteristics: USB interface block (pins DM1 to DM2 and DP1 to DP2) . . . . . . . .76 Table 118.Dynamic characteristics: system clock timing .78 Table 119.Dynamic characteristics: I2C-bus interface (SDA and SCL) . . . . . . . . . . . . . . . . . . . . . . . .78 Table 120.Dynamic characteristics: PCI interface block . .78 Table 121.Dynamic characteristics: high-speed source electrical characteristics . . . . . . . . . . . . . . . . .78 Table 122.Dynamic characteristics: full-speed source electrical characteristics . . . . . . . . . . . . . . . . .79 Table 123.Dynamic characteristics: low-speed source electrical characteristics . . . . . . . . . . . . . . . . .79 Table 124.PCI clock and IO timing . . . . . . . . . . . . . . . . . .80 Table 125.SnPb eutectic process (from J-STD-020C) . . .84 Table 126.Lead-free process (from J-STD-020C) . . . . . .84 Table 127.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 128.Revision history . . . . . . . . . . . . . . . . . . . . . . . .86
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 14 November 2008
90 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
25. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4 Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . .11 Power supply connection . . . . . . . . . . . . . . . . . . .12 EEPROM connection diagram . . . . . . . . . . . . . . .30 Information loading from EEPROM . . . . . . . . . . .31 PCI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 PCI input timing . . . . . . . . . . . . . . . . . . . . . . . . . .81 PCI output timing . . . . . . . . . . . . . . . . . . . . . . . . .81 USB source differential data-to-EOP transition skew and EOP width . . . . . . . . . . . . . . . . . . . . . .81 Fig 11. Package outline SOT407-1 (LQFP100) . . . . . . . .82 Fig 12. Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 14 November 2008
91 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
26. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . 10 7.1 OHCI host controller . . . . . . . . . . . . . . . . . . . . 10 7.2 EHCI host controller . . . . . . . . . . . . . . . . . . . . 10 7.3 Dynamic port-routing logic . . . . . . . . . . . . . . . 10 7.4 Hi-Speed USB analog transceivers . . . . . . . . 10 7.5 Power management . . . . . . . . . . . . . . . . . . . . 10 7.6 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . 10 7.7 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 11 7.8 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.1 PCI interface . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.1.1 PCI configuration space . . . . . . . . . . . . . . . . . 13 8.1.2 PCI initiator and target . . . . . . . . . . . . . . . . . . 13 8.2 PCI configuration registers . . . . . . . . . . . . . . . 13 8.2.1 PCI configuration header registers . . . . . . . . . 14 8.2.1.1 Vendor ID register. . . . . . . . . . . . . . . . . . . . . . 14 8.2.1.2 Device ID register . . . . . . . . . . . . . . . . . . . . . . 15 8.2.1.3 Command register . . . . . . . . . . . . . . . . . . . . . 15 8.2.1.4 Status register. . . . . . . . . . . . . . . . . . . . . . . . . 17 8.2.1.5 Revision ID register . . . . . . . . . . . . . . . . . . . . 18 8.2.1.6 Class Code register . . . . . . . . . . . . . . . . . . . . 18 8.2.1.7 CacheLine Size register . . . . . . . . . . . . . . . . . 19 8.2.1.8 Latency Timer register . . . . . . . . . . . . . . . . . . 19 8.2.1.9 Header Type register . . . . . . . . . . . . . . . . . . . 19 8.2.1.10 Base Address register 0 . . . . . . . . . . . . . . . . . 20 8.2.1.11 Subsystem Vendor ID register . . . . . . . . . . . . 20 8.2.1.12 Subsystem ID register . . . . . . . . . . . . . . . . . . 20 8.2.1.13 Capabilities Pointer register . . . . . . . . . . . . . . 21 8.2.1.14 Interrupt Line register . . . . . . . . . . . . . . . . . . . 21 8.2.1.15 Interrupt Pin register . . . . . . . . . . . . . . . . . . . . 21 8.2.1.16 MIN_GNT and MAX_LAT registers. . . . . . . . . 22 8.2.1.17 TRDY_TIMEOUT - TRDY Timeout register . . 22 8.2.1.18 RETRY_TIMEOUT - Retry Timeout register. . 22 8.2.2 Enhanced host controller-specific PCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2.2.1 SBRN register. . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2.2.2 FLADJ register . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2.2.3 PORTWAKECAP register . . . . . . . . . . . . . . . . 24 8.2.3 Power management registers. . . . . . . . . . . . . 8.2.3.1 CAP_ID register . . . . . . . . . . . . . . . . . . . . . . . 8.2.3.2 NEXT_ITEM_PTR register. . . . . . . . . . . . . . . 8.2.3.3 PMC register . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3.4 PMCSR register . . . . . . . . . . . . . . . . . . . . . . . 8.2.3.5 PMCSR_BSE register . . . . . . . . . . . . . . . . . . 8.2.3.6 Data register. . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 9.1 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Hardware connections . . . . . . . . . . . . . . . . . . 9.3 Information loading from EEPROM . . . . . . . . 10 Power management. . . . . . . . . . . . . . . . . . . . . 10.1 PCI bus power states . . . . . . . . . . . . . . . . . . . 10.2 USB bus states . . . . . . . . . . . . . . . . . . . . . . . 11 USB host controller registers. . . . . . . . . . . . . 11.1 OHCI USB host controller operational registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 HcRevision register . . . . . . . . . . . . . . . . . . . . 11.1.2 HcControl register . . . . . . . . . . . . . . . . . . . . . 11.1.3 HcCommandStatus register . . . . . . . . . . . . . . 11.1.4 HcInterruptStatus register . . . . . . . . . . . . . . . 11.1.5 HcInterruptEnable register . . . . . . . . . . . . . . . 11.1.6 HcInterruptDisable register . . . . . . . . . . . . . . 11.1.7 HcHCCA register . . . . . . . . . . . . . . . . . . . . . . 11.1.8 HcPeriodCurrentED register. . . . . . . . . . . . . . 11.1.9 HcControlHeadED register. . . . . . . . . . . . . . . 11.1.10 HcControlCurrentED register . . . . . . . . . . . . . 11.1.11 HcBulkHeadED register . . . . . . . . . . . . . . . . . 11.1.12 HcBulkCurrentED register . . . . . . . . . . . . . . . 11.1.13 HcDoneHead register. . . . . . . . . . . . . . . . . . . 11.1.14 HcFmInterval register. . . . . . . . . . . . . . . . . . . 11.1.15 HcFmRemaining register . . . . . . . . . . . . . . . . 11.1.16 HcFmNumber register . . . . . . . . . . . . . . . . . . 11.1.17 HcPeriodicStart register . . . . . . . . . . . . . . . . . 11.1.18 HcLSThreshold register . . . . . . . . . . . . . . . . . 11.1.19 HcRhDescriptorA register . . . . . . . . . . . . . . . 11.1.20 HcRhDescriptorB register . . . . . . . . . . . . . . . 11.1.21 HcRhStatus register . . . . . . . . . . . . . . . . . . . . 11.1.22 HcRhPortStatus[4:1] register . . . . . . . . . . . . . 11.2 EHCI controller capability registers . . . . . . . . 11.2.1 CAPLENGTH/HCIVERSION register. . . . . . . 11.2.2 HCSPARAMS register . . . . . . . . . . . . . . . . . . 11.2.3 HCCPARAMS register . . . . . . . . . . . . . . . . . . 11.2.4 HCSP-PORTROUTE register. . . . . . . . . . . . . 11.3 Operational registers of enhanced USB host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1 USBCMD register. . . . . . . . . . . . . . . . . . . . . . 24 24 25 25 27 28 29 30 30 30 31 31 31 32 32 33 33 34 36 37 38 40 42 42 43 44 45 45 46 47 48 49 50 50 51 52 53 55 58 58 58 60 61 61 61
continued >>
ISP1562_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 14 November 2008
92 of 93
NXP Semiconductors
ISP1562
HS USB PCI host controller
63 65 66 67 68 69 70 74 75 75 76 78 80 82 83 83 83 83 84 85 86 86 87 87 87 87 87 87 88 91 92
11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 12 13 14 15 16 16.1 17 18 18.1 18.2 18.3 18.4 19 20 21 22 22.1 22.2 22.3 22.4 23 24 25 26
USBSTS register . . . . . . . . . . . . . . . . . . . . . . USBINTR register . . . . . . . . . . . . . . . . . . . . . . FRINDEX register . . . . . . . . . . . . . . . . . . . . . . PERIODICLISTBASE register . . . . . . . . . . . . ASYNCLISTADDR register . . . . . . . . . . . . . . . CONFIGFLAG register . . . . . . . . . . . . . . . . . . PORTSC registers 1, 2 . . . . . . . . . . . . . . . . . . Current consumption . . . . . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions. . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering . . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 November 2008 Document identifier: ISP1562_3

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