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Ordering number : ENA0608A
Monolithic Digital IC
LB11850V
Overview
For Fan Motor Single-Phase Full-Wave Pre-Driver with Speed Control Function
The LB11850V is a single-phase bipolar fan motor driver with speed control function that works with a speed feedback signal. A highly efficient, quiet and low power consumption motor driver circuit, with a high speed accuracy and large variable speed can be implemented by adding a small number of external components. This pre-driver is optimal for driving large scale fan motors (with large air volume and large current) such as those used in servers and consumer products.
Functions and features
* Pre-driver for single-phase full-wave drive PMOS-NMOS is used as an external power TR, enabling high-efficiency and low-power-consumption drive by means of the low-saturation output and single-phase full-wave drive. * On-chip speed control circuit The speed control (closed loop control) using a speed feedback signal makes it possible to achieve higher speed accuracy and lower speed fluctuations when supply voltage fluctuates or load fluctuates, compared with an openloop control system. Separately excited upper direct PWM control method is used as the variable-speed control system. * External PWM input or analog voltage input enabling variable speed control The speed control input signal is compatible with PWM duty ratio or analog voltages. * On-chip soft start circuit * Lowest speed setting pin The lowest speed can be set with the external resistor. * Current limiter circuit incorporated Chopper type current limit at start or lock. * Reactive current cut circuit incorporated Reactive current before phase change is cut to enable silent and low-consumption drive. * Constraint protection and automatic reset functions incorporated * FG (speed detection), RD (lock detection) output * Constant-voltage output pin for hall bias
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32207 MS IM 20070301-S00002 / D0606 MH IM 20060619-S00001 No.A0608-1/14
LB11850V
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter VCC maximum supply voltage OUTN pin maximum output current OUTP pin maximum sink current OUT pin output withstand voltage HB maximum output current CTL, C pin withstand voltage CVI, LIM pin withstand voltage RD/FD output pin output withstand voltage RD/FG output current 5VREG pin maximum output current Allowable power dissipation Operating temperature range Storage temperature range Symbol VCC max IOUTN max IOUTP max VOUT max HB CTL, C max CVI, LIM max FG max FG max I5VREG max Pd max Topr Tstg Mounted on a specified board * Conditions Ratings 18 20 20 18 10 7 7 19 10 10 0.9 -30 to +95 -55 to +150 Unit V mA mA V mA V V V mA mA W C C
Note *1: Mounted on a specified board: 114.3mmx76.1mmx1.6mm, glass epoxy. Note *2: Tj max = 150C. Use the device in a condition that the chip temperature does not exceed Tj = 150C during operation.
Recommended Operating Ranges at Ta = 25C
Parameter VCC supply voltage 1 VCC supply voltage 2 CTL input voltage range LIM input voltage range VCI input voltage range Hall input common phase input voltage range Symbol VCC1 VCC2 VCTL VLIM VCVI VICM VCC pin When VCC-5VREG shorted Conditions Ratings 5.5 to 16 4.5 to 5.5 0 to 5VREG 0 to 5VREG 0 to 5VREG 0.2 to 3 Unit V V V V V V
Electrical Characteristics at Ta = 25C, VCC = 12V, unless otherwise specified
Parameter Circuit current Symbol ICC1 ICC2 5VREG voltage HB voltage Current limiter voltage CPWM pin H level voltage CPWM pin L level voltage CPWM pin charge current CPWM pin discharge current CPWM oscillation frequency CT pin H level voltage CT pin L level voltage CT pin charge current CT pin discharge current CT pin charge/discharge current ratio OUTN pin output H voltage OUTN pin output L voltage OUTP pin output L voltage 5VREG VHB VLIM VCRH VCRL ICPWM1 ICPWM2 FPWM VCTH VCTL ICT1 ICT2 RCT VONH VONL VOPL VCT = 2V VCT = 2V ICT1/ICT2 IO = 10mA IO = 10mA IO = 10mA VCPWM = 0.5V VCPWM = 3.5V C = 220pF 2.8 0.9 1.6 0.16 8 Conditions min During drive During lock protection I5VREG = 5mA IHB = 5mA 4.8 1.05 190 2.8 0.9 24 21 Ratings typ 12 12 5.0 1.20 210 3.0 1.1 30 27 30 3.0 1.1 2.0 0.20 10 VCC-0.85 0.9 0.5 3.2 1.3 2.5 0.25 12 VCC-1.0 1.0 0.65 max 15 15 5.2 1.35 230 3.2 1.3 36 33 mA mA V V mV V V A A kHz V V A A times V V V unit
Continued on next page.
No.A0608-2/14
LB11850V
Continued from preceding page.
Parameter Hall input sensitivity FG output L voltage FG pin leak current RD output L voltage RD pin leak current EO pin output H voltage EO pin output L voltage RC pin output H voltage RC pin output L voltage RC pin clamp voltage CTL pin input H voltage CTL pin input L voltage CTL pin input open voltage CTL pin H input H current CTL pin L input L current C pin output H voltage C pin output L voltage LIM pin input bias current LIM pin common phase input voltage range SOFT pin charge current SOFT pin operating voltage range CVI pin input bias current CVI pin common phase input voltage range CVO pin output H level voltage Output L level voltage Symbol VHN VFGL IFGL VRDL IRDL VEOH VEOL VRCH VRCL VRCCLP VCTLH VCTLL VCTLO ICTLH ICTLL VCH VCL IBLIM VILIM ICSOFT VISOFT IB(VCI) VIVCI VOH(VCO) VOL(VCO) VFGIN = 5VREG VFGIN = 0V Conditions min IN+, IN- difference voltage (including offset and hysteresis) IFG = 5mA VFG = 19V IRD = 5mA VRD = 19V IEO1 = -0.2mA IEO1 = 0.2mA 3.2 0.7 1.3 2.0 0 VREG-0.5 -10 -120 VREG-0.3 1.8 -1 2.0 1.0 2.0 -1 2.0 VREG-0.35 1.8 VREG-0.2 2.0 2.2 1.3 0 -90 VREG-0.1 2.0 2.2 1 VREG 1.6 VREG 2 VREG VREG-1.2 VREG-0.8 0.8 3.45 0.8 1.5 1.1 3.7 1.05 1.7 VREG 1.0 VREG 10 0.15 0.15 030 30 0.30 30 A A V A V V V V V V V V A A V V A V A V A V V V Ratings typ 15 max 25 mV unit
Package Dimensions
unit : mm (typ) 3175C
1.2
Pd max -- Ta
7.8
Allowable power dissipation, Pd max -- W
Mounted on a specified board: 114.3x76.1x1.6mm3,glass epoxy
1.0 0.9 0.8
24
13
5.6
7.6
0.6
0.5
1 0.65 (0.33) 0.22
12 0.15
0.4
0.2
(1.3)
1.5max
0 -30
0
30
60
9095
120
Ambient temperature, Ta -- C
0.1
SANYO : SSOP24(275mil)
No.A0608-3/14
LB11850V
Pin Assignment
OUT2P OUT2N VCC SENCE CVI CVO CTL RC SOFT
1 2 3 4 5 6
24 OUT1P 23 OUT1N 22 SGND 21 5VREG 20 C 19 EO
LB11850V
7 8 9 18 EI 17 LIM 16 CT 15 IN+ 14 HB 13 INTop view
CPWM 10 FG 11 RD 12
Truth Table
Lock protection CPWM = H
INH L H L IN+ L H L H H CT L OUT1P L OFF OFF OFF OUT1N L H L H OUT2P OFF L OFF OFF OUT2N H L H L FG L OFF L OFF Mode OUT12 drive OUT21 drive Lock protection
Speed control CT = L
EO L CPWM H INH L H L H L IN+ L H L H OUT1P L OFF OFF OFF OUT1N L H L H OUT2P OFF L OFF OFF OUT2N H L H L Mode OUT12 drive OUT21 drive Regeneration mode
No.A0608-4/14
FG
RD
CT
VCC Discharge circuit
Block Diagram
VCC
Thermal shat down
VREG
OUT1N
5VREG OUT1P EDEG FG
RC
1shotmulti
LIM CONTROL CIRCUIT
OUT2N
LB11850V
SOFT
VREF
CVI
OUT2P
CVO 5VREG
C
CTL
CTL signal EI EO IN+
CTL
HallBias HB HALL IN-
Oscillation
ILB01797
CPWM
SENSE
GND
No.A0608-5/14
LB11850V
Sample Application Circuit
*3
1F/25V Rp=1k
(1)
(3)
(2) 100
(4)
RF
1F/25V
*2
RFG/RRD= 10k to 100k VCC FG *8 RC RD *7 SENSE LIM OUT1P OUT1N (1) (2) (3) (4) *9
5VREG
LB11850V
SOFT CVI CVO
OUT2P OUT2N HB IN*4
H
C CTLsignal CTL EI EO SGND *1
IN+ CT
*5
CT=1F
CPWM *6
CP=220pF 30kHz
No.A0608-6/14
LB11850V
Description of Pre-driver Block
*1: SGND is connected to the control circuit power supply system. *2: For the signal-side power stabilization capacitor, the capacitance of more than 0.1F is used. Connect the capacitor between VCC and GND with the thick pattern and along the shortest route. *3: For the power-side power stabilization capacitor, the capacitance of more than 0.1F is used. Connect the capacitor between power-side power supply and GND with the thick pattern and along the shortest route. *4: Hall signal input pins Wiring needs to be short to prevent carrying noise. If noise is carried, insert a capacitor between IN+ and IN-. The Hall input circuit is a comparator having a hysteresis of 15mV. It has a 30mV (input signal difference voltage) soft switch zone. It is recommended that the Hall input level is 100mV (p-p) at the minimum. *5: This is the pin to connect capacitor for generating the PWM basic frequency Use of CP = 220pF produces oscillation at the frequency of 30kHz which serves as the PWM basic frequency. Since this pin is also used for the current limiter reset signal, the capacitor must be connected without fail even when no speed control is implemented. *6: This is the pin to connect capacitor for lock detection Constant-current charging and constant-current discharging circuits are incorporated. When the pin voltage becomes 3.0V, the safety lock is applied, and when it lowers to 1.0V, the lock protection is reset. Connect this pin to GND when it is not in use (when lock protection is not required). *7: This is the pin for current limiter detection When the pin voltage exceeds 0.21V, current limiting is applied, and the low-side regeneration mode is established. Connect this pin to GND when it is not in use. *8: Lock detection pin This is the open collector output, which outputs "L" during rotation and "H" at stop. This pin is left open when it is not in use. *10: Speed detection pin. This is the open collector output, which can detect the rotation speed using the FG output according to the phase change. This pin is left open when it is not in use.
No.A0608-7/14
LB11850V
Description of Speed Control Block
1) Speed control diagram
The speed slope is determined by the constant of the RC pin. (RPM) CR time constant large CR time constant small
Rotation speed
Minimum speed
Determined by LIM pin voltage
0%
Small CTL signal (PWMDUTY) Large Large EO pin voltage (V) Small Minimum speed setting rotation Variable speed
100%
Full speed ON Duty large
ON-Duty small CTL pin
5VREG LIM voltage EO pin EO voltage 0V
2) Timing at startup (soft start)
VCC pin
CTL pin
Stop
Full speed Soft start The slope changes according to the capacitance of SOFT pin. (Large Large slope)
SOFT pin
Stop
Full speed
No.A0608-8/14
LB11850V
3) Additional description of operations The LB11850 forms a feedback loop inside the IC so that the FG period (motor speed) corresponding to the control voltage is established by inputting the duty pulse.
LB11850V
FG Speed control block CTL signal CTL Closed Feed-back Loop Pre-driver block
CONTROL SIGNAL
The operation inside the IC is as follows. Pulse signals are created from the edges of the FG signals as shown in the figure below, and a waveform with a pulse width which is determined by the CR time constants and which uses these edges as a reference is generated by a one-shot multivibrator. These pulse waveforms are integrated and the duty ratio of the pre-driver output is controlled as a control voltage.
FG
EDGE pulse
RC pin
Slope due to CR time constant
1 shot output
TRC(s) = 1.15RC
Furthermore, by changing the pulse width as determined by the CR time constant, the VCTL versus speed slope can be changed as shown in the speed control diagram of the previous section. However, since the pulses used are determined by the CR time constant, the variations in CR are output as-is as the speed control error.
No.A0608-9/14
LB11850V
4) Procedure for calculating constants The slope shown in the speed control diagram is determined by the constant of the RC pin.
(RPM) Motor at maximum speed
0%
CTL Duty(%)
100%
(1) Obtain FG signal frequency fFG (Hz) of the maximum speed of the motor. (With FG2 pulses per rotation) fFG (Hz) = 2 rpm/60 .... <1> (2) Obtain the time constant which is connected to the RC pin. (Have "DUTY" (example: 100% = 1.0, 60% = 0.6) serve as the CTL duty ratio at which the maximum speed is to be obtained.) RxC = DUTY/(3.3x1.1xfFG) .... <2> (3) Obtain the resistance and capacitance of the capacitor. Based on the discharge capacity of the RC pin, the capacitance of the capacitor which can be used is 0.01 to 0.015F. Therefore, find the appropriate resistance using equation <3> or <4> below from the result of <2> above. R = (RxC)/0.01F .... <3> R = (RxC)/0.015F .... <4> The temperature characteristics of the curve are determined by the temperature characteristics of the capacitor of the RC pin. When temperature-caused fluctuations in the speed are to be minimized, use a capacitor with good temperature characteristics.
No.A0608-10/14
LB11850V
These pins determine the position of the slope origin. (When the origin point is at (0%, 0 rpm), CVO and CVI are shorted.) (1) Movement along the X-axis (resistance divided between CVO and GND)
(RPM) Motor at maximum speed
Move in the direction of the X-axis
0%
CTL Duty(%)
100%
(Example) In the case where the characteristics change from ones with the origin point (0%, 0 rpm) to ones where the speed at a duty ratio of 30% becomes the speed at 0%: First, obtain the input voltage of the CVI pin required at 0%. CVI = 5-(3xduty ratio) = 5-(3x0.3) = 5-0.9 = 4.1V Next, obtain the resistances at which the voltage becomes 4.1V by dividing the resistance between CVO and GND when CVO is 5V. The ratio of CVO-CVI: CVI-GND is 0.9V: 4.1V = 1: 4.5. Based on the above, the resistance is 20k between CVO and CVI and 91k between CVI and GND. Furthermore, the slope changes. (In the case of the example given, since the resistance ratio is 1: 4.5, the slope is now 4.5/5.5 = 0.8 times what it was originally.) If necessary, change the resistance of the RC pin, and adjust the slope.
LIM SOFT CVI R4 CVO VREF
R5
C CTL CTL
No.A0608-11/14
LB11850V
(2) Movement along the Y-axis (resistance divided between CVO and VCC)
(RPM) Motor at maximum speed
Move in the direction of the Y-axis
0%
CTL Duty(%)
100%
(Example) In the case where the characteristics change from ones with the origin point (0%, 0 rpm) to ones where the speed at a duty ratio of 25% becomes 0 rpm: First, obtain the CVO pin voltage required for the CVI voltage to be 5V at 25%. CVO = 5-(3xduty ratio) = 5-(3x0.25) = 5-0.75 = 4.25V With CVO = 4.25V, find the resistances at which CVI = 5V. The ratio of CVO-CVI: CVI-GND is 0.75V: 7V = 1: 9.3 Based on the above, the resistance is 20k between CVO and CVI and 180k between CVI and VCC. (Due to the current capacity of the CVO pin, the total resistance must be set to 100k or more.) Furthermore, the slope changes. (In the case of the example given, since the resistance ratio is 1: 9.3, the slope is now 9.3/10.3 = 0.9 times what it was originally.) If necessary, change the resistance of the RC pin, and adjust the slope.
VCC LIM VREF R5 R4 SOFT CVI CVO
C CTL CTL
No.A0608-12/14
LB11850V
The minimum speed is determined by the voltage of the LIM pin.
(RPM) Maximum speed 10000
8000
6000
4000 Minimum speed setup
2000
0% 5V
CTL Duty(%) CVO pin voltage (V)
100% 2V
(1) Obtain the ratio of the minimum speed required to the maximum speed. Ra = Minimum speed/maximum speed .... <1> In the example shown in the figure above, Ra = minimum speed/maximum speed = 3000/10000 = 0.3. (2) Obtain the product of the duty ratio at which the maximum speed is obtained and the value in equation <1>. Ca = Duty ratio at maximum speedxRa .... <2> In this example, Ca = duty ratio at maximum speedxRa = 0.8x0.3 = 0.24. (3) Obtain the required LIM pin voltage. LIM = 5-(3xCa) .... <3> In this example, LIM = 5-(3xCa) = 5-(3x0.24) 4.3V. (4) Divide the resistance of 5VREG, and generate the LIM voltage. In this example, the voltage is 4.3V so the resistance ratio is 1: 6. The resistance is 10k between 5VREG and LIM and 62k between LIM and GND.
5VREG
LIM SOFT CVI VREF
No.A0608-13/14
LB11850V
In order to connect a capacitor capable of smoothing the pin voltage to the C pin, the correlation given in the following equation must be satisfied when f (Hz) serves as the input signal frequency of the CTL pin. (R is contained inside the IC, and is 180k (typ.).) 1/f = t < CR The higher the capacitance of the capacitor is, the slower the response to changes in the input signal is.
5VREG CTL pin input inverted waveform (same frequency) C pin CTL pin CTL circuit 180k VREF circuit Connect a capacitor capable of smoothing the pin voltage 1/f = t < CR
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This catalog provides information as of March, 2007. Specifications and information herein are subject to change without notice.
PS No.A0608-14/14

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