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EM77950
BB Controller
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
October 2007
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2007 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 308 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. 3F, SSMEC Bldg., Gaoxin S. Ave. I Shenzhen Hi-tech Industrial Park (South Area), Shenzhen CHINA 518057 Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (USA) P.O. Box 601 Cupertino, CA 95015 USA Tel: +1 408 366-8225 Fax: +1 408 366-8225
Shanghai: Elan Microelectronics Shanghai, Ltd. #23, Zone 115, Lane 572, Bibo Rd. Zhangjiang Hi-Tech Park Shanghai, CHINA 201203 Tel: +86 21 5080-3866 Fax: +86 21 5080-4600
Contents
Contents
1 2 General Description ................................................................................................ 1 Features ................................................................................................................... 1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 4 5 6 Core..................................................................................................................1 Oscillators/System Clocks ................................................................................2 Input and Output (I/O) Pins ...............................................................................2 Timers and Counters ........................................................................................2 Interrupt Sources and Features ........................................................................2 Baseband (BB) .................................................................................................3 Serial Peripheral Interface (SPI) .......................................................................3 Pulse Width Modulation (PWM) ........................................................................3
2.9 Analog to Digital Converter (ADC) ....................................................................3 Pins Assignment ..................................................................................................... 4 Pin Description ........................................................................................................ 6 Block Diagram ......................................................................................................... 9 Memory .................................................................................................................. 10 6.1 Program Memory ............................................................................................10 6.2 RAM-Register ................................................................................................ 11 Function Description............................................................................................. 25 7.1 Special Purpose Registers..............................................................................25
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 7.1.14 7.1.15 7.1.16 7.1.17 7.1.18 7.1.19 Accumulator - ACC .........................................................................................25 Indirect Addressing Contents - IAC0 and IAC1 ...............................................25 High Byte Program Counter HPC and Low Byte Program Counter LPC .........25 Status Register - SR .......................................................................................26 RAM Bank Selector - RAMBS0 and RAMBS1 ................................................26 ROM Page Selector - ROMPS .......................................................................27 Indirect Addressing Pointers - IAP0 and IAP1 ................................................27 Indirect Address Pointer Direction Control Register - IAPDR..........................27 Table Look-up Pointer - LTBL and HTBL ........................................................28 Stack Pointer - STKPTR .................................................................................28 Repeat Counter - RPTC .................................................................................28 Prescaler Counter - PRC................................................................................28 Real Time Clock Counter - RTCC...................................................................28 Interrupt Flag Register - INTF.........................................................................28 Key Wake-up Flag Register - KWUAIF & KWUBIF.........................................29 I/O Port Registers - PTA ~ PTF.......................................................................29 16-bit Free Run Counter (FRC) - LFRC HFRC & LFRCB ...............................29 Serial Peripheral Interface Read Register - SPIRB.........................................29 Serial Peripheral Interface Write Register - SPIWB ........................................29
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Product Specification (V1.0) 10.09.2007
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Contents
7.1.20 7.1.21 7.1.22 7.1.23 7.1.24 7.1.25 7.1.26 7.1.27
ADC Converting Value - ADDATA...................................................................29 PWM Duty - DT0L/DT0H & DT1L/DT1H.........................................................29 PWM Period - PRD0L/PRD0H & PRD1L/PRD1H...........................................29 PWM Duty Latch - DL0L/DL0H & DL1L/DL1H ................................................30 BB Address Register - RFAAR .......................................................................30 BB Data Buffer Register - RFDB.....................................................................30 BB Data Read/Write Control Register - RFACR .............................................30 BB Interrupt Flag Register - RFINTF ..............................................................30
7.2 7.3
Dual Port Register ..........................................................................................31 System Status, Control and Configuration Registers....................................... 31
7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.3.13 7.3.14 7.3.15 Peripherals Enable Control - PRIE .................................................................31 Interrupts Enable Control - INTE ....................................................................31 Key Wake-up Enable Control - KWUAIE & KWUBIE ......................................32 External Interrupts Edge Control - EINTED ....................................................32 Serial Peripheral Serial (SPI) Enable Control Register - SPIC........................33 I/O Control Registers - IOCA~IOCF................................................................33 Pull-up Resistance Control Registers for Ports A~F - PUCA~PUCF...............34 Open Drain Control Registers of Port B/Port C - ODCB/ODCC ......................34 Timer Clock Counter Controller - TCCC .........................................................34 Free Run Counter Controller - FRCC .............................................................35 Watchdog Timer Controller - WDTC ...............................................................35 ADC Analog Input Pin Select - ADCAIS .........................................................36 ADC Configuration Register - ADCCR............................................................36 PWM Control Register - PWMCR ...................................................................37 BB Interrupt Control Register - RFINTE..........................................................37
8
7.4 Code Option (ROM-0x2FFF)........................................................................... 38 Baseband (BB)....................................................................................................... 39 8.1 BB: Standard Interface for the RFW102 Series ...............................................39
8.1.1 8.1.2 8.1.3 8.1.4 Features ..........................................................................................................39 Description ......................................................................................................39 I/O and Package Description...........................................................................40 BB Architecture ...............................................................................................42 Reset...............................................................................................................42 Power Saving Modes ......................................................................................42 8.2.2.1 Power-Down Mode ...........................................................................42 8.2.2.2 Idle Mode..........................................................................................43 Preamble Correlation ......................................................................................43 Refresh Bit ......................................................................................................44 Bit Structure.....................................................................................................44 CRC ................................................................................................................45
8.2
BB Description ................................................................................................42
8.2.1 8.2.2
8.2.3 8.2.4 8.2.5 8.2.6
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Product Specification (V1.0) 10.09.2007
Contents
RX FIFO ..........................................................................................................46 TX FIFO ..........................................................................................................47 Interrupt Driver ................................................................................................47 Packet Size .....................................................................................................49 NET_ID and NODE_ID Filters .........................................................................49 Carrier-Sense..................................................................................................50 8.2.12.1 RFWaves Carrier-Sense Algorithm ...................................................50 8.2.13 Receiver Reference Capacitor Discharge .......................................................51 8.2.14 Changing BB Configuration .............................................................................52 8.2.15 Input Synchronizer ..........................................................................................52
8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12
8.3
Register Description ....................................................................................... 52
8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 8.3.14 8.3.15 8.3.16 Bit Length Register (BLR) ...............................................................................53 Preamble Low Register (PRE-L) .....................................................................53 Preamble High Register (PRE-H)....................................................................53 Packet Parameter Register (PPR)...................................................................53 System Control Register1 (SCR1)...................................................................55 System Control Register 2 (SCR2)..................................................................55 System Control Register 3 (SCR3)..................................................................57 System Control Register 4 (SCR4).................................................................58 Transmit FIFO Status Register (TFSR)............................................................59 Receive FIFO Status Register (RFSR) ............................................................59 Location Control Register (LCR) .....................................................................59 Node Identity Register (BIR)............................................................................60 Net Identity Register (NIR) ..............................................................................60 System Status Register (SSR) ........................................................................61 Packet Size Register (PSR) ............................................................................62 Carrier Sense Register (CSR) .........................................................................62 Interrupt Enable Register (IER) .......................................................................63 Interrupt Identification Register (IIR)................................................................64
8.4
Interrupt Registers ..........................................................................................63
8.4.1 8.4.2
8.5 8.6
List of BB Register Mapping............................................................................ 65 MCU BB Control Registers ............................................................................. 65
8.6.1 8.6.2 Control Registers List ......................................................................................65 BB Control Example ........................................................................................66
9
Direction Serial Peripheral Interface (SPI) ........................................................... 68 9.1 9.2 9.3 9.4 9.5 Introduction.....................................................................................................68 Features .........................................................................................................68 Block Diagram ................................................................................................ 68 Transceiver Timing..........................................................................................69 Related Registers with SPI .............................................................................69
Product Specification (V1.0) 10.09.2007
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Contents
9.6
Function Description ....................................................................................... 70
9.6.1 9.6.2 Block Diagram Description ..............................................................................70 Signal & Pin Description..................................................................................70
10
Analog to Digital Converter (ADC)....................................................................... 71 10.1 ADC Control Registers....................................................................................72 10.2 Programming Steps/Considerations................................................................ 74 Dual Pulse Width Modulations (PWM0 and PWM1)............................................. 75 11.1 Overview.........................................................................................................75 11.2 PWM Control Registers .................................................................................. 76 11.3 PWM Programming Procedures/Steps............................................................ 78 Interrupts................................................................................................................ 78 12.1 Introduction.....................................................................................................78 Circuitry of Input and Output Pins ....................................................................... 80 13.1 Introduction.....................................................................................................80 Timer/Counter System .......................................................................................... 80 14.1 Introduction.....................................................................................................80 14.2 Time Clock Counter (TCC).............................................................................. 80
14.2.1 Block Diagram of TCC.....................................................................................80 14.2.2 TCC Control Registers ....................................................................................81 14.2.3 TCC Programming Procedures/Steps .............................................................81
11
12 13 14
14.3 Free Run Counter ...........................................................................................82
14.3.1 Block Diagram of FRC.....................................................................................82 14.3.2 FRC Control Registers ....................................................................................82 14.3.3 FRC Programming Procedures/Steps .............................................................83
15
Reset and Wake up................................................................................................ 83 15.1 Reset ..............................................................................................................83 15.2 The Status of RST, T, and P of the STATUS Register...................................... 83 15.3 System Set-up Time (SST) ............................................................................. 84 15.4 Wake-up Procedure on Power-on Reset......................................................... 85 Oscillators.............................................................................................................. 85 16.1 Introduction.....................................................................................................85 16.2 Clock Signal Distribution ................................................................................. 85 16.3 PLL Oscillator ................................................................................................. 86 16.4 Selected PLL Oscillation out ........................................................................... 86 Low-Power Mode ................................................................................................... 86 17.1 Introduction.....................................................................................................86 17.2 Green Mode....................................................................................................87 17.3 Sleep Mode .................................................................................................... 87
16
17
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Product Specification (V1.0) 10.09.2007
Contents
18 19
Instruction Description ......................................................................................... 88 18.1 Instruction Set Summary.................................................................................88 Electrical Specification ......................................................................................... 90 19.1 Absolute Maximum Ratings ............................................................................90 19.2 DC Electrical Characteristic ............................................................................ 90 19.3 Voltage Detector Electrical Characteristic .......................................................91 19.4 AC Electrical Characteristic............................................................................. 91
19.4.1 MCU................................................................................................................91 19.4.2 BB ...................................................................................................................92
20
Application Circuit................................................................................................. 93
APPENDIX
A B
Package Type......................................................................................................... 94 Package Information ............................................................................................. 94
Specification Revision History
Doc. Version 1.0 Revision Description Initial released version Date 2007/10/09
Product Specification (V1.0) 10.09.2007
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Contents
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Product Specification (V1.0) 10.09.2007
EM77950
BB Controller
1
General Description
The EM77950 from ELAN Electronics is a low-cost and high performance 8-bit CMOS advance RISC architecture microcontroller device. It has an on-chip 1-Mbps RF driver module/Base Band (BB), Serial Peripheral Interface (SPI), dual Pulse Width Modulation (PWM) with 16-bit resolution, an 8-bit Timer Clock Counter (TCC) and a 16-bit Free Run Timer, multi-channel Analog to Digital Converter (ADC) with 8-bit resolution, Key Wake-up function (KWU), Power-on Reset (POR), Watchdog Timer (WDT), and power saving Sleep Mode. All these features combine to ensure applications require the least external components, hence, not only reduce system cost, but also have the advantage of low power consumption and enhanced device reliability. The 52-pin EM77950 is available in a very cost-effective version that provides a single chip solution in designing wireless products.
2
Features
2.1 Core
Operating Voltage Range: 2.2V ~ 3.6V DC (ADC reference volt 3V) Operating Temperature Range: 0C ~ 70C Operating Frequency Range: DC ~ 48MHz (1 clock/cycle)
* * *
6MHz external clock source 6/12/24/48 MHz to Core clock 6/12/24/48 MHz to clock
Internal Memory
* *
12K x 16 bits of on-chip Program ROM 896 x 8 bits of on-chip Register (SRAM)
Watchdog Timer (WDT) 32 level stacks for both CALL and interrupt subroutine Internal Power-on Reset (POR) function Code protection function available All single cycle (1 clock) instruction except for conditional branches which are two or three cycles. Direct, indirect and relative addressing modes Low power, high speed CMOS technology
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
*1
EM77950
BB Controller
Power consumption: < 4 mA @ 3.3V, 6 MHz < 60 A @ 3.0V, (RC = 32.768 kHz) < 1 A standby current 52/44-pin QFP package
2.2 Oscillators/System Clocks
Three oscillator options:
* *
Crystal/Resonate oscillator of high frequency PLL oscillator: 6MHz, 12 MHz, 24 MHz, and 48 MHz (External crystal should be 6 MHz) External RC oscillator Sleep mode Green mode Normal mode
*
Three modes of system clocks:
* * *
Internal RC oscillator for Power-on Reset (POR) and Watchdog Timer (WDT)
2.3 Input and Output (I/O) Pins
40 I/O pins max. Pull-up resistor options Key Wake-up function Open drain output options
2.4 Timers and Counters
Programmable 8-bit real Time Clock/Counter (TCC) with prescaler and overflow interrupt 16-bit Free Run Counter (FRC) with overflow interrupt
2.5 Interrupt Sources and Features
Hardware priority check Different interrupt vectors Interrupts
* * * * * * *
Key Wake-up function External pin interrupt 16-bit Free Run Counter Overflow TCC (time-base) overflow; Read Buffer Full Interrupt in Serial Peripheral Interface (SPI) An analog to digital converting (ADC) complete One period of Pulse Width Modulation (PWM) complete
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
2*
EM77950
BB Controller
*
Base Band (BB) function interrupts: CSD: carrier sense detection TX_AE: TX_FIFO almost full RX_AF: RX_FIFO almost full TX_ EMPTY: finish a transmitting a package RX_OF: RX_FIFO overflow LINK_DIS: zero counter capacitor discharge mechanism LOCK_OUT: finish receiving a package LOCK_IN: start receiving a package
2.6 Baseband (BB)
Serial to Parallel conversion of RFW102 interface Parallel interface to RFW102 modem Serial to Parallel conversion of RFW102 interface Input FIFO (RX_FIFO) Output FIFO (TX_FIFO) Preamble Correlation Packet Address Filter (Network and unique) CRC calculation Inter-RFWAVES networks Carrier-sense Discharge of RFW-102 reference capacitor Compensate for clock drifts between the transmitting EM77950 and the receiving EM77950 up to 1000ppm. Hence, the EM77950 requires low performance crystal. Interrupt Driver - connected to the EM77950's internal interrupt and informs the EM77950 about BB events.
2.7 Serial Peripheral Interface (SPI)
Either MSB or LBS can be transmitted/received first Both Master and Slave modes available
2.8 Pulse Width Modulation (PWM)
Dual Pulse Width Modulation (PWM) with 16-bit resolution
2.9 Analog to Digital Converter (ADC)
16 multi-channel Analog to Digital Converter with 8-bit resolution
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
*3
EM77950
BB Controller
3
Pins Assignment
PC5/PWM1 PD4/ADC4 PD3/ADC3 PD2/ADC2 PD1/ADC1 PD0/ADC0 PC4/INT1 PC3/INT0 28 PC2/SCK 27 26 25 24 23 22 PC1/SD0 PC0/SDI DVSS RFIO TXRX RF_ACT DVDD PB7/KW U7 PB6/KW U6 PB5/KW U5 PB4/KW U4 PB3/KW U3 PB2/KW U2 21 20 19 18 17 16 15 14 1 PF0/OSCO2 2 PF1 3 PA0/KWU8 4 PA1/KWU9 5 PA2/KWUA 6 PA3/KWUB 7 /RST 8 PA4 9 PA5 10 PA6 11 PA7/PWM0 12 PB0/KWU0 13 PB1/KWU1
OSCO1 32
AVSS
39 PD5/ADC5 PD6/ADC6 PD7/ADC7 Vref PE0/ADC8 PE1/ADC9 PE2/ADCA PE3/ADCB PE4/ADCC PE5/ADCD PE6/ADCE PE7/ADCF AVDD 40 41 42 43 44 45 46 47 48 49 50 51 52
38
37
36
35
34
OSCI
33
PLCC 31
30
29
EM77950A
Fig. 3-1 Pin Configuration of EM77950A
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Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
EM77950
BB Controller
PC5/PWM1
PD1/ADC1
PD2/ADC2
PD0/ADC0
PC4/INT1
PC3/INT0 24
AVSS
OSCO1
33 P D 3/A D C 3 P D 4/A D C 4 P D 5/A D C 5 P D 6/A D C 6 P D 7/A D C 7 V re f P E 0/A D C 8 P E 1/A D C 9 P E 2 /A D C A P E 3 /A D C B AVDD 34 35 36 37 38 39 40 41 42 43 44 1 PF0/OSCO2
32
31
30
29
OSCI
28
27
PLCC
26
25
23 22 21 20 19 18 P C 1/S D 0 P C 0/S D I DVSS R F IO TX R X R F _A C T DVDD P B 3/K W U 3 P B 2/K W U 2 P B 1/K W U 1 P B 0/K W U 0
E M 7 7 9 5 0B
PC2/SCK 17 16 15 14 13 12 11 PA7/PWM0
2 PF1
3 PA0/KWU8
4 PA1/KWU9
5 PA2/KWUA
6 PA3/KWUB
7 /RST
8 PA4
9 PA5
10 PA6
Fig. 3-2 Pins Configuration of EM77950B
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
*5
EM77950
BB Controller
4
Pin Description
The Table below shows the corresponding relationship between the pad and pins of EM77950A
Pin # 1 2 3~6 7 8~10 11 Symbol PTF0/OSCO2 PF1 KWU8~B, PA0~3 /RST PTA4~6 PWM0/PTA7 Type I/O I/O I/O - I/O I/O I/O - - - - -
Schmitt Pull High Open Trigger /50K Drain
Function Description Pin 0 of Port F Selected PLL clock out Pin 1 of Port F Pins 0~3 of Port A (default). Key Wake-up 8~B Reset pin Pins 4~6 of Port A. Pin 7 of Port A. PWM0 output Pins 0~7 of Port B (default). Key Wake-up 0~7 Power supply for digital circuit. The power source value should be within the range of the operating voltage. BB/RF Active Transceiver modes control Transceiver to/from RF modem Ground Pin for Digital circuit Data in of SPI Pin 0 of Port C Data out of SPI Pin 1 of Port C Clock of SPI Pin 2 of Port C External interrupt Pin 0 Pin 3 of Port C External interrupt Pin 1 Pin 4 of Port C Pin 5 of Port C. PWM1 output External capacitor for PLL circuit Output of crystal oscillator Input of crystal oscillator Ground Pin for Analog circuit
-
-
- - - - - -
12~19 PB0 ~ PB7
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
DVDD RF_ACT TXRX RFIO DVSS SDI/PTC0 SDO/PTC1 SCK/PTC2 EINT0/ PTC3 EINT1/ PTC4 PWM1/PTC5 PLLC OSCO1 OSCI AVSS
- O O I/O - I/O I/O I/O I/O I/O I/O - O I -
- - - - - - - - - - - -
- - - - - - - - -
- - - - - - - - -
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Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
EM77950
BB Controller
Pin # 35~42 43
Symbol PTD0~7, ADC0~7 VREF
Type I/O I I/O
Schmitt Pull High Open Trigger /50K Drain
Function Description Pins 0~7 of Port D Inputs 0~7 of ADC Reference voltage for ADC Pins 0~7 of Port E Inputs 8~F of ADC Power supply for analog circuit. The power source value should be within the range of the operating voltage.
- - -
-
- - -
PTE0~7, 44~51 ADC8~F 52 AVDD
-
-
-
-
The Table below shows the corresponding relationship between the pad and pins of EM77950B
Pin # 1 2 3~6 7 8~10 11 Symbol PTF0/OSCO2 PF1 KWU8~B, PA0~3 /RST PTA4~6 PWM0/PTA7 Type I/O I/O I/O - I/O I/O
Schmitt Pull High Open Trigger /50K Drain
Function Description Pin 0 of Port F Selected PLL clock out Pin 1 of Port F Pins 0~3 of Port A (default) Key Wake-up 8~B Reset pin Pins 4~6 of Port A Pin 7 of Port A. PWM0 output Pins 0~3 of Port B (default) Key Wake-up 0~7 Power supply for digital circuit. The power source value should be within the range of the operating voltage. BB/RF Active Transceiver modes control Transceiver to/from RF modem Ground Pin for Digital circuit Data in of SPI Pin 0 of Port C Data out of SPI Pin 1 of Port C
- - - - -
-
- - - - - -
12~15 PB0 ~ PB3
I/O
-
16 17 18 19 20 21
DVDD RF_ACT TXRX RFIO DVSS SDI/PTC0
- O O I/O - I/O
- - - - -
- - - - -
- - - - -
22
SDO/PTC1
I/O
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
*7
EM77950
BB Controller
Pin # 23
Symbol SCK/PTC2
Type I/O
Schmitt Pull High Open Trigger /50K Drain
Function Description Clock of SPI Pin 2 of Port C External interrupt Pin 0 Pin 3 of Port C External interrupt Pin 1 Pin 4 of Port C Pin 5 of Port C PWM1 output External capacitor for PLL circuit Output of crystal oscillator Input of crystal oscillator Pins 0~7 of Port D Inputs 0~7 of ADC Reference voltage for ADC Pins 0~3 of Port E Inputs 8~B of ADC Power supply for analog circuit. The power source value should be within the range of the operating voltage.
24
EINT0/ PTC3
I/O
-
25
EINT1/ PTC4
I/O
-
26 27 28 29 31~38 39 40~43
PWM1/PTC5 PLLC OSCO1 OSCI PTD0~7, ADC0~7 VREF PTE0~3, ADC8~B
I/O - O I I/O I I/O
- - - - - - -
- - - -
- - - - - -
44
AVDD
-
-
-
-
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Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
EM77950
BB Controller
5
Block Diagram
WMOSCS0 WMOSCS1
6/12/24 MHz
OSCI OSCO1
LX OSC PLL OSC SLEEP 1 0
GREEN
ADC
CPU
Base Band
FRC
TCC
SPI
M U X
OSC02
PLLDIV
WDTCE
PPSCL0 PPSCL1 PPSCL2
OSCS0 OSCS1
Internal RC OSC.
M U X
Watchdog Controller
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
*9
EM77950
BB Controller
6
Memory
6.1 Program Memory
The EM77950 has a 14-bit program counter (PC). The space of program memory, which is partitioned into 2 pages can address up to 12K. One page has 8K in length, and the other is 4K. Fig. 6-1 depicts the profile of the program memory and stack. The initial address is 0x0000. The table of interrupt-vectors starts from 0x10 to 0x80 with every other eight-address space.
HPC A13 A12 A11 A10 A9 A8
LPC A7~A0
INT CALL Stack 0 RET RETL RETI Stack 1
PS0 0 1
Address 0000 ~ 1 FFF 2000 ~ 2FFF
Page 0 1 Stack 1E Stack 1F ACC2 SR2 RAMBS02 ROMPS2 ACC1 SR1 RAMBS01 ROMPS1 ACC0 SR0 RAMBS00 ROMPS0
Addr 0000
Vector Reset
0010 Key Wake-up 0020 0028 TCCOF FRCOF
Fig. 6-1 Configuration of Program Memory (ROM) for EM77950
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Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
EM77950
BB Controller
6.2 RAM-Register
A total of 896 accessible bytes of data memory are available for the EM77950. By function, they are classified into general purpose registers, system control/configuration registers, specific purpose registers, Baseband (BB) control/status registers, SPI control/status registers, timer/counter registers, and IO port status/control registers. All of the mentioned registers except I/O ports and their related control registers are implemented as static RAM. The RAM configurations are shown in Fig. 6-2.
00 System, Configuration, Clock, IO port Registers 30 31 General purpose registers 3F 40
000
010
011
100
101
110
80 Peripherals, and Interrupts Control registers 9A 9B
280
380
480
580
680
Dual Port Register
General purpose Registers Of Bank 0 FF
General purpose Registers Of Bank 2
General purpose Registers Of Bank 3
General purpose Registers Of Bank 4
General purpose Registers Of Bank 5
General purpose Registers Of Bank 6
7F
2FF
3FF
4FF
5FF
6FF
Fig. 6-2 of Data Memory (RAM) Configuration
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
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EM77950
BB Controller
The table is a summary of all registers except general purpose registers.
Addr Name Reset Type Full Name Bit Name 0x00 IAC0 Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x01 HPC Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x02 LPC Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x03 SR Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name RAMBS Read / Write (R/W) 0x04 0 Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0x05 ROMPS Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int RST R/W 0 P P PCF R/W 0 0 PC7 R 0 0 IAC07 R/W 0 0 P R/W 0 0 P Bit 7 Bit 6 IAC06 Bit 5 IAC05 R/W 0 0 P Bit 4 IAC04 R/W 0 0 P Bit 3 IAC03 R/W 0 0 P Bit 2 IAC02 R/W 0 0 P Bit 1 IAC01 R/W 0 0 P Bit 0 IAC00 R/W 0 0 P
Indirect Addressing Register contents
Most Significant Byte of Programming Counter PC6 R 0 0 PC5 R 0 0 PC4 R 0 0 PC3 R 0 0 PC2 R 0 0 PC1 R 0 0 PC0 R 0 0
Jump to corresponding interrupt vector or continue to execute next instruction Least Significant Byte of Programming Counter PCE R/W 0 0 PCD R/W 0 0 PCC R/W 0 0 PCB R/W 0 0 PCA R/W 0 0 PC9 R/W 0 0 PC8 R/W 0 0
Jump to corresponding interrupt vector or continue to execute next instruction Status Register T R/W 1 T T P R/W 1 T T Z R/W U P P DC R/W U P P C R/W U P P
RAM Bank Selector 0 RBS02 RBS01 RBS00 R 0 0 P R 0 0 P R 0 0 P
ROM Page Selector RPS0 R/W 0 0 P
12 *
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
EM77950
BB Controller
Addr
Name
Reset Type Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indirect Addressing Pointer 0 IAP07 R/W 0 0 P IAP06 R/W 0 0 P IAP05 R/W 0 0 P IAP04 R/W 0 0 P IAP03 R/W 0 0 P IAP02 R/W 0 0 P IAP01 R/W 0 0 P IAP00 R/W 0 0 P
0x06
IAP0
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
RAM Bank Selector 1 RBS12 R/W 0 0 P RBS11 R/W 0 0 P RBS10 R/W 0 0 P
0x07 RAMBS1
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Indirect Addressing Pointer 1 IAP17 R/W 0 0 P IAP16 R/W 0 0 P IAP15 R/W 0 0 P IAP14 R/W 0 0 P IAP13 R/W 0 0 P IAP12 R/W 0 0 P IAP11 R/W 0 0 P IAP10 R/W 0 0 P
0x08
IAP1
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Indirect Addressing Contents 1 IAC17 R/W 0 0 P IAC16 R/W 0 0 P IAC15 R/W 0 0 P IAC14 R/W 0 0 P IAC13 R/W 0 0 P IAC12 R/W 0 0 P IAC11 R/W 0 0 P IAC10 R/W 0 0 P
0x09
IAC1
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Indirect Address Pointer Direction Control Register IAP1_D IAP0_D IAP1_D_E IAP0_D_E
0x0A
IAPDR
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
R/W 0 0 P
R/W 0 0 P
R/W 0 0 P
R/W 0 0 P
Least Significant Byte of Table Look-up TBL7 R/W 0 0 P TBL6 R/W 0 0 P TBL5 R/W 0 0 P TBL4 R/W 0 0 P TBL3 R/W 0 0 P TBL2 R/W 0 0 P TBL1 R/W 0 0 P TBL0 R/W 0 0 P
0x0B
LTBL
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
* 13
EM77950
BB Controller
Addr
Name
Reset Type Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Most Significant Byte of Table Look-up TBLF R/W 0 0 P TBLE R/W 0 0 P TBLD R/W 0 0 P TBLC R/W 0 0 P TBLB R/W 0 0 P TBLA R/W 0 0 P TBL9 R/W 0 0 P TBL8 R/W 0 0 P
0x0C
HTBL
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Stack Pointer STKPT7 STKPT6 STKPT5 STKPT4 STKPT3 STKPT2 STKPT1 STKPT0 R 1 1 P R 1 1 P R 1 1 P R 1 1 P R 1 1 P R 1 1 P R 1 1 P R 1 1 P
0x0D STKPTR
Repeat Pointer RPTC7 RPTC6 RPTC5 RPTC4 RPTC3 RPTC2 RPTC1 RPTC0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x0E
RPTC
Prescaler Counter PRC7 R/W 0 0 0 PRC6 R/W 0 0 0 PRC5 R/W 0 0 0 PRC4 R/W 0 0 0 PRC3 R/W 0 0 0 PRC2 R/W 0 0 0 PRC1 R/W 0 0 0 PRC0 R/W 0 0 0
0x0F
PRC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Time Clock/Counter TCC7 R/W 0 0 0 TCC6 R/W 0 0 0 TCC5 R/W 0 0 0 TCC4 R/W 0 0 0 TCC3 R/W 0 0 0 TCC2 R/W 0 0 0 TCC1 R/W 0 0 0 TCC0 R/W 0 0 0
0x10
TCC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Interrupt Flag ADIF R/W 0 0 P RBFIF PWM1IF PWM0IF EINT1F EINT0F TCCOF FRCOF R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x11
INTF
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int
14 *
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
EM77950
BB Controller
Addr
Name
Reset Type Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A Key Wake up Interrupt Flag KWUBIF KWUAIF KWU9IF KWU8IF R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x12 KWUAIF
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Port B Key Wake up Interrupt Flag KWU7IF KWU6IF KWU5IF KWU4IF KWU3IF KWU2IF KWU1IF KWU0IF R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x13 KWUBIF
General Purpose I/O port, Port A PTA7 R/W U U P PTA6 R/W U U P PTA5 R/W U U P PTA4 R/W U U P PTA3 R/W U U P PTA2 R/W U U P PTA1 R/W U U P PTA0 R/W U U P
0x14
PTA
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
General Purpose I/O port, Port B PTB7 R/W U U P PTB6 R/W U U P PTB5 R/W U U P PTB4 R/W U U P PTB3 R/W U U P PTB2 R/W U U P PTB1 R/W U U P PTB0 R/W U U P
0x15
PTB
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
General Purpose I/O port, Port C PTC5 R/W U U P PTC4 R/W U U P PTC3 R/W U U P PTC2 R/W U U P PTC1 R/W U U P PTC0 R/W U U P
0x16
PTC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
General Purpose I/O port, Port D PTD7 R/W U U P PTD6 R/W U U P PTD5 R/W U U P PTD4 R/W U U P PTD3 R/W U U P PTD2 R/W U U P PTD1 R/W U U P PTD0 R/W U U P
0x17
PTD
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
* 15
EM77950
BB Controller
Addr
Name
Reset Type Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
General Purpose I/O port, Port E PTE7 R/W U U P PTE6 R/W U U P PTE5 R/W U U P PTE4 R/W U U P PTE3 R/W U U P PTE2 R/W U U P PTE1 R/W U U P PTE0 R/W U U P
0x18
PTE
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
General Purpose I/O port, Port F PTF1 R/W U U P PTF0 R/W U U P
0x19
PTF
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Least significant Byte of 16-bit Free Run Counter FRC7 R 0 0 0 FRC6 R 0 0 0 FRC5 R 0 0 0 FRC4 R 0 0 0 FRC3 R 0 0 0 FRC2 R 0 0 0 FRC1 R 0 0 0 FRC0 R 0 0 0
0x1A
LFRC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Most significant Byte of 16-bit Free Run Counter FRCF R/W 0 0 0 FRCE R/W 0 0 0 FRCD R/W 0 0 0 FRCC R/W 0 0 0 FRCB R/W 0 0 0 FRCA R/W 0 0 0 FRC9 R/W 0 0 0 FRC8 R/W 0 0 0
0x1B
HFRC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Least significant Byte Buffer of 16-bit Free Run Counter FRCB7 R/W 0 0 0 FRCB6 R/W 0 0 0 FRCB5 FRCB4 FRCB3 FRCB2 FRCB1 FRCB0 R/W 0 0 0 R/W 0 0 0 R/W 0 0 0 R/W 0 0 0 R/W 0 0 0 R/W 0 0 0
0x1C LFRCB
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Serial Peripheral Interface Read Register SPIR7 R/W 0 0 P SPIR6 R/W 0 0 P SPIR5 R/W 0 0 P SPIR4 R/W 0 0 P SPIR3 R/W 0 0 P SPIR2 R/W 0 0 P SPIR1 R/W 0 0 P SPIR0 R/W 0 0 P
0x1D
SPIRB
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int
16 *
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
EM77950
BB Controller
Addr
Name
Reset Type Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Serial Peripheral Interface Write Register SPIW7 R/W 0 0 P SPIW6 R/W 0 0 P SPIW5 R/W 0 0 P SPIW4 R/W 0 0 P SPIW3 R/W 0 0 P SPIW2 R/W 0 0 P SPIW1 R/W 0 0 P SPIW0 R/W 0 0 P
0x1E SPIWB
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Converting Value of ADC ADD7 R/W 0 0 P ADD6 R/W 0 0 P ADD5 R/W 0 0 P ADD4 R/W 0 0 P ADD3 R/W 0 0 P ADD2 R/W 0 0 P ADD1 R/W 0 0 P ADD0 R/W 0 0 P
0x1F ADDATA
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
-
-
-
-
-
-
0x20
NC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Duty of PWM0-Low Byte DT07 R 0 0 P DT06 R 0 0 P DT05 R 0 0 P DT04 R 0 0 P DT03 R 0 0 P DT02 R 0 0 P DT01 R 0 0 P DT00 R 0 0 P
0x21
DT0L
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Duty of PWM0-High Byte DT0F R 0 0 P DT0E R 0 0 P DT0D R 0 0 P DT0C R 0 0 P DT0B R 0 0 P DT0A R 0 0 P DT09 R 0 0 P DT08 R 0 0 P
0x22
DT0H
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Period of PWM0- Low Byte PRD07 R/W 0 0 P PRD06 R/W 0 0 P PRD05 PRD04 R/W 0 0 P R/W 0 0 P PRD03 R/W 0 0 P PRD02 R/W 0 0 P PRD01 R/W 0 0 P PRD00 R/W 0 0 P
0x23
PRD0L
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
* 17
EM77950
BB Controller
Addr
Name
Reset Type Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Period of PWM0- High Byte PRD0F PRD0E PRD0D PRD0C PRD0B PRD0A PRD09 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P PRD08 R/W 0 0 P
0x24 PRD0H
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Duty Latch of PWM0-Low Byte DL07 R/W 0 0 P DL06 R/W 0 0 P DL05 R/W 0 0 P DL04 R/W 0 0 P DL03 R/W 0 0 P DL02 R/W 0 0 P DL01 R/W 0 0 P DL00 R/W 0 0 P
0x25
DL0L
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Duty Latch of PWM0-High Byte DL0F R/W 0 0 P DL0E R/W 0 0 P DL0D R/W 0 0 P DL0C R/W 0 0 P DL0B R/W 0 0 P DL0A R/W 0 0 P DL019 R/W 0 0 P DL08 R/W 0 0 P
0x26
DL0H
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Duty of PWM1-Low Byte DT17 R 0 0 P DT16 R 0 0 P DT15 R 0 0 P DT14 R 0 0 P DT13 R 0 0 P DT12 R 0 0 P DT11 R 0 0 P DT10 R 0 0 P
0x27
DT1L
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Duty of PWM1-High Byte DT1F R 0 0 P DT1E R/ 0 0 P DT1D R 0 0 P DT1C R 0 0 P DT1B R 0 0 P DT1A R 0 0 P DT19 R 0 0 P DT18 R 0 0 P
0x28
DT1H
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Period of PWM1- Low Byte PRD17 R/W 0 0 P PRD16 R/W 0 0 P PRD15 R/W 0 0 P PRD14 R/W 0 0 P PRD13 R/W 0 0 P PRD12 R/W 0 0 P PRD1 R/W 0 0 P PRD10 R/W 0 0 P
0x29 PRD1L
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int
18 *
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
EM77950
BB Controller
Addr
Name
Reset Type Full Name Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Period of PWM1- High Byte PRD1F PRD1E PRD1D PRD1C PRD1B PRD1A PRD19 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P PRD18 R/W 0 0 P
0x2A PRD1H
Duty Latch of PWM1-Low Byte DL17 R/W 0 0 P DL16 R/W 0 0 P DL15 R/W 0 0 P DL14 R/W 0 0 P DL13 R/W 0 0 P DL12 R/W 0 0 P DL11 R/W 0 0 P DL10 R/W 0 0 P
0x2B
DL1L
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Duty Latch of PWM1-High Byte DL1F R/W 0 0 P DL1E R/W 0 0 P DL1D R/W 0 0 P DL1C R/W 0 0 P DL1B R/W 0 0 P DL1A R/W 0 0 P DL19 R/W 0 0 P DL18 R/W 0 0 P
0x2C
DL1H
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
BB Address Register AAR4 R/W 0 0 P AAR3 R/W 0 0 P AAAR2 R/W 0 0 P AAR1 R/W 0 0 P AAR0 R/W 0 0 P
0x2D RFAAR
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
BB Data Buffer RFDB7 RFDB6 RFDB5 RFDB4 RFDB3 RFDB2 RFDB1 RFDB0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x2E
RFDB
BB Data Read/Write Control Register RRST R/W 0 0 P RFRD R/W 1 1 P RFWR R/W 1 1 P
0x2F RFACR
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
* 19
EM77950
BB Controller
Addr
Name
Reset Type Full Name Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BB Interrupt Flag Register CSDF TX_AEF RX_AFF TX_EMPTYF RX_OFF LINK_DISF LOCK_OUTF LOCK_INF R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x30 RFINTF
Dual Port Registers (64 in total) DPR7 R/W x x P DPR6 R/W x x P DPR5 R/W x x P DPR4 R/W x x P DPR3 R/W x x P DPR2 R/W x x P DPR1 R/W x x P DPR0 R/W x x P
0x40 ~ 0x7F DPR
Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Peripheral Function Enable SPIE R/W 0 0 P BBE R/W 0 0 P ADE R/W 0 0 P PWM1E PWM0E R/W 0 0 P R/W 0 0 P TCCE R/W 0 0 P FRCE R/W 0 0 P
0x80
PRIE
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Interrupt Enable Control Register GIE R/W 0 0 P RBFIE PWM1IE PWM0IE EINT1E EINT0E R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P TCCOE FRCOE R/W 0 0 P R/W 0 0 P
0x81
INTE
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Port A Key Wake up Interrupt Enable Control Register KWUBE KWUAE
KWU9E KWU8E R/W 0 0 P R/W 0 0 P
0x82 KWUAIE
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int
R/W 0 0 P
R/W 0 0 P
Port B Key Wake up Interrupt Enable Control Register
KWU7E KWU6E KWU5E
KWU4E KWU3E KWU2E KWU1E KWU0E R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x83 KWUBIE
R/W 0 0 P
R/W 0 0 P
R/W 0 0 P
20 *
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
EM77950
BB Controller
Addr
Name
Reset Type Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
External Interrupt Edge Control EINT1ED EINT0ED
0x84 EINTED
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
SPI_RBF
R/W 0 0 P
R/W 0 0 P
Serial Peripheral Serial (SPI) Enable Control Register CES R/W 0 0 P SBR2 R/W 0 0 P SBR1 R/W 0 0 0 SBR0 R/W 0 0 0 SDID R/W 0 0 0 SDOD R/W 0 0 0 SPIS R/W 0 0 0 R/W 0 0 P
0x85
SPIC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
I/O Control of Port A IOCA7 R/W 1 1 P IOCA6 R/W 1 1 P IOCA5 IOCA4 IOCA3 IOCA2 R/W 1 1 P R/W 1 1 P R/W 1 1 P R/W 1 1 P IOCA1 R/W 1 1 P IOCA0 R/W 1 1 P
0x86
IOCA
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
I/O Control of Port B IOCB7 R/W 1 1 P IOCB5 R/W 1 1 P IOCB5 IOCB4 IOCB3 IOCB2 R/W 1 1 P R/W 1 1 P R/W 1 1 P R/W 1 1 P IOCB1 R/W 1 1 P IOCB0 R/W 1 1 P
0x87
IOCB
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
I/O Control of Port C IOCC5 IOCC4 IOCC3 IOCC2 R/W 1 1 P R/W 1 1 P R/W 1 1 P R/W 1 1 P IOCC1 R/W 1 1 P IOCC0 R/W 1 1 P
0x88
IOCC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
I/O Control of Port D IOCD7 R/W 1 1 P IOCD6 R/W 1 1 P IOCD5 IOCD4 IOCD3 IOCD2 R/W 1 1 P R/W 1 1 P R/W 1 1 P R/W 1 1 P IOCD1 R/W 1 1 P IOCD0 R/W 1 1 P
0x89
IOCD
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
* 21
EM77950
BB Controller
Addr
Name
Reset Type Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I/O Control of Port E IOCE7 IOCE6 R/W 1 1 P R/W 1 1 P IOCE5 R/W 1 1 P IOCE4 R/W 1 1 P IOCE3 R/W 1 1 P IOCE2 R/W 1 1 P IOCE1 R/W 1 1 P IOCE0 R/W 1 1 P
0x8A
IOCE
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
I/O Control of Port F IOCF1 R/W 1 1 P IOCF0 R/W 1 1 P
0x8B
IOCF
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Pull-up Control of Port A PUCA7 PUCA6 PUCA5 R/W 0 0 P R/W 0 0 P R/W 0 0 P PUCA4 R/W 0 0 P PUCA3 PUCA2 R/W 0 0 P R/W 0 0 P PUCA1 R/W 0 0 P PUCA0 R/W 0 0 P
0x8C
PUCA
Pull-up Control of Port B PUCB7 PUCB6 PUCB5 R/W 0 0 P R/W 0 0 P R/W 0 0 P PUCB4 R/W 0 0 P PUCB3 PUCB2 PUCB1 R/W 0 0 P R/W 0 0 P R/W 0 0 P PUCB0 R/W 0 0 P
0x8D
PUCB
Pull-up Control of Port C PUCC5 R/W 0 0 P PUCC4 PUCC3 PUCC2 R/W 0 0 P R/W 0 0 P R/W 0 0 P PUCC1 R/W 0 0 P PUCC0 R/W 0 0 P
0x8E
PUCC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int
Pull-up Control of Port D PUCD7 PUCD6 PUCD5 R/W 0 0 P R/W 0 0 P R/W 0 0 P PUCD4 PUCD3 PUCD2 R/W 0 0 P R/W 0 0 P R/W 0 0 P PUCD1 R/W 0 0 P PUCD0 R/W 0 0 P
0x8F
PUCD
22 *
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
EM77950
BB Controller
Addr
Name
Reset Type Full Name Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pull-up Control of Port E PUCE7 PUCE6 PUCE5 PUCE2 PUCE3 PUCE2 PUCE1 PUCE0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x90
PUCE
Pull-up Control of Port F PUCF1 PUCF0 R/W 0 0 P R/W 0 0 P
0x91
PUCF
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Open Drain Control of Port B OPCB7 OPCB6 OPCB5 OPCB4 OPCB3 OPCB2 OPCB1 OPCB0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 0 R/W 0 0 0 R/W 0 0 0
0x92
ODCB
Time Clock/Counter Control TCCS0 R/W 0 0 P PS2 R/W 0 0 P PS1 R/W 0 0 P PS0 R/W 0 0 P
0x93
TCCC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
Free Run Counter Control OSCO2E OSCO2SL1 OSCO2SL0 PPSCL2 PPSCL1 PPSCL0 FRCCS
0x94
FRCC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
R/W 0 0 P
R/W 0 0 P
R/W 0 0 P
R/W 0 0 P
R/W 0 0 P
R/W 0 0 P
R/W 0 0 P
Watchdog Timer Control GREEN R/W 0 0 0 WDTCE R/W 0 0 P RAT2 R/W 0 0 P RAT1 R/W 0 0 P RAT0 R/W 0 0 P
0x95
WDTC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
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Addr
Name
Reset Type Full Name Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC Analog Input Pin Select IMS2 R/W 0 0 P IMS1 R/W 0 0 P IMS0 R/W 0 0 P CKR2 R/W 0 0 P CKR1 R/W 0 0 P CKR0 R/W 0 0 P
0x96 ADCAIS
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
ADC Configuration Register
ADRUN ADIE
-
-
AIPS3
AIPS2
AIPS1
AIPS0
0x97 ADCCR
Read / Write (R/W) R/W Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0 0 P
R/W 0 0 P
R/W 0 0 P
R/W 0 0 P
R/W 0 0 P
R/W 0 0 P
PWM Control Register S_PWM1 S_PWM0
-
-
0x98 PWMCR
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int Full Name Bit Name
R/W 0 0 P
R/W 0 0 P
BB Interrupt Enable Control Register CSDE TX_AEE RX_AFE TX_EMPTYE RX_OFE LINK_DISE LOCK_OUTE LOCK_INE R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x99 RFINTE
Read / Write (R/W) R/W Power-on /RESET and WDT Wake-up from Int Full Name Bit Name 0 0 P
Open Drain Control of Port C OPCC5 R/W 0 0 P OPCC4 R/W 0 0 P OPCC3 OPCC2 OPCC1 OPCC0 R/W 0 0 P R/W 0 0 P R/W 0 0 P R/W 0 0 P
0x9A
ODCC
Read / Write (R/W) Power-on /RESET and WDT Wake-up from Int
24 *
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
EM77950
BB Controller
7
Function Description
7.1 Special Purpose Registers
The special purpose registers are function-oriented registers used by the CPU to access memory, record execution results, and carry out the desired operation. The functions of the registers related to the core are described in the following subsections
7.1.1 Accumulator - ACC
Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register.
7.1.2 Indirect Addressing Contents - IAC0 (0x00), and IAC1 (0x09)
The contents of R0 and R9 are implemented as indirect addressing pointers if any instruction uses R6 and R8 as registers.
7.1.3 High Byte Program Counter HPC (0x01) and Low Byte Program Counter LPC (0x02)
Program Counter (PC) is composed of registers HPC and LPC. PC and the hardware stacks are 14 bits wide. The structure is depicted in Fig. 6-1. Generates 12K x 16 on-chip ROM addresses to the corresponding program memory (ROM).
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All the bits of PC are set "0"s as a reset condition occurs. "RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2, A" allows the loading of an address from the "A" register to the lower 8 bits of the PC, and the high byte (A8~A14) of the PC remain unchanged. "ADD R2, A" & "TBL" allows a corresponding address / offset be added to the current PC.
7.1.4 Status Register - SR (0x03)
Bit 7 Bit 6 Bit 5 RST Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 C
Bit 0 (C): Carry flag. This bit indicates that a carry out of ALU occurred during the last arithmetic operation. This bit is also affected during bit test, branch instruction and bit shifts. Bit 1 (DC): Auxiliary carry flag. This bit is set during ADD and ADC operations to indicate that a carry occurred between Bit 3 and Bit 4. Bit 2 (Z): Zero flag. Set to "1" if the result of the last arithmetic, data or logic operation is zero. Bit 3 (P): Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4 (T): Time-out bit. Set to 1 by the "SLEP" command and the "WDTC" command, or during power up and reset to 0 by WDT timeout. Bit 5 (RST): Set if the CPU wakes up by keying Wake-up pins. Reset if the chip wakes up from other ways. Bits 6 and 7 are reserved.
7.1.5 RAM Bank Selector - RAMBS0 (0x04), and RAMBS1 (0x07)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAMBSX2 RAMBSX1 RAMBSX0
As depicted in Fig. 6-2, there are seven available banks in the MCU. Each of them have 128 registers and can be accessed by defining the bits, RAMBSX0 ~ RAMBSX2, as shown below.
26 *
Product Specification (V1.0) 10.09.2007
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BB Controller
RAMBSX (0x04/0x07) 000 010 011 100 101 110
Bank 0 2 3 4 5 6
7.1.6 ROM Page Selector - ROMPS (0x05)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RPS0
As depicted in Fig. 6-1, there are two available pages in MCU. The first page has 8Kx16 ROM size and the second page has 4Kx16 ROM size. Both of them can be accessed by defining the bits, RPS0, as shown below. As depicted in Fig. 6-1, there are two available pages in the MCU. Each page has 12Kx16 ROM size and can be accessed by defining the bits, RPS0, as shown below.
RPS0 0 1 Page (Address) 0 (0x0000~0x1FFF) 1 (0x2000~0x2FFF)
7.1.7 Indirect Addressing Pointers - IAP0 (0x06), and IAP1 (0x08)
Both R6 and R8 are not physically implemented registers. They are useful as indirect addressing pointers. Any instruction using R6/R4 and R8/R7 as registers actually access data pointed by R0 and R9 individually.
7.1.8 Indirect Address Pointer Direction Control Register - IAPDR (0x0A)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 IAP1_D Bit 2 IAP0_D Bit 1 Bit 0 IAP1_D_E IAP0_D_E
Bit 0/1 (IAP0_D_E/IAP1_D_E) Indirect addressing pointer0/1 direction function enable bit. 0: Disable 1: Enable Bit 2/3 (IAP0_D/IAP1_D) Indirect addressing pointer0/1 direction control bit. 0: Minus direction 1: Plus direction
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7.1.9 Table Look-up Pointer - LTBL (0x0B), and HTBL (0x0C)
The maximum length of a table is 64K, and can be accessed through registers LTBL and HTBL. HTBL is the high byte of the pointer, whereas LTBL is the low byte.
7.1.10 Stack Pointer - STKPTR (0x0D)
Register RD indicates how many stacks the current free run program uses. It is a read only register.
7.1.11 Repeat Counter - RPTC (0x0E)
The RE register is used to set how many times the "RPT" instruction is going to read the table.
7.1.12 Prescaler Counter - PRC (0x0F)
Prescaler counter for TCC.
7.1.13 Real Time Clock Counter - RTCC (0x10)
TCC counter.
7.1.14 Interrupt Flag Register - INTF (0x11)
Bit 7 ADIF Bit 6 RBFIF Bit 5 PWM1IF Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF
Bit 0 (FRCOF): FRC Overflow interrupt. Set as the contents of the FRC counter change from 0xFFFF to 0x0000, reset by software. Bit 1 (TCCOF): TCC Overflow interrupt. Set as the contents of the TCC counter change from 0xFF to 0x00, reset by software. Bits 2 ~ 3 (EINT0F & EINTIF): External input pin interrupt flag. Interrupt occurs at a defined edge of the external input pin, reset by software. Bits 4 ~ 5 (PWM0IF & PWM1IF): PWM interrupt flag. Interrupt occurs when TMRX is equal to PRDX, reset by software. Bit 6 (RBFIF): SPI receiving buffer full Interrupt flag. Interrupt occurs when an 8-bit data is received, reset by software. Bit 7 (ADIF): ADC conversion complete interrupt flag. Each bit can function independently regardless whether its related interrupt mask bit is enabled or not.
28 *
Product Specification (V1.0) 10.09.2007
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BB Controller
7.1.15 Key Wake-up Flag Register - KWUAIF (0x12) & KWUBIF (0x13)
KWUAIF: Port A Key Wake-up Interrupt Flag
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 KWUBIF Bit 2 KWUAIF Bit 1 KWU9IF Bit 0 KWU8IF
KWUBIF: Port B Key Wake-up Interrupt Flag
Bit 7 KWU7IF Bit 6 KWU6IF Bit 5 KWU5IF Bit 4 KWU4IF Bit 3 KWU3IF Bit 2 KWU2IF Bit 1 KWU1IF Bit 0 KWU0IF
7.1.16 I/O Port Registers - PTA ~ PTF (0x14 ~ 0x19)
PTX can be operated by related instructions, as any other general purpose registers. That is, PTX is an 8-bit, bidirectional, general purpose port. Its corresponding I/O control bit determines the data direction of a PTX pin.
7.1.17 16-bit Free Run Counter (FRC) - LFRC (0x1A), HFRC (0x1B) & LFRCB (0x1C)
R1A is 16-bit FRC low byte; R1B is high byte; R1C is low byte buffer.
7.1.18 Serial Peripheral Interface Read Register - SPIRB (0x1D)
Register R1D indicates SPI received data.
7.1.19 Serial Peripheral Interface Write Register - SPIWB (0x1E)
Register R1E indicates SPI transmitted data.
7.1.20 ADC Converting Value - ADDATA (0x1F)
ADDATA: Converting Value of ADC.
Bit 7 ADD7 Bit 6 ADD6 Bit 5 ADD5 Bit 4 ADD4 Bit 3 ADD3 Bit 2 ADD2 Bit 1 ADD1 Bit 0 ADD0
7.1.21 PWM Duty - DT0L (0x21)/DT0H (0x22) & DT1L (0x27) / DT1H (0x28)
R22 : R21 16-bit PWM0 output duty cycle. R28 : R27 16-bit PWM1 output duty cycle.
7.1.22 PWM Period - PRD0L (0x23)/PRD0H (0x24) & PRD1L (0x29)/PRD1H (0x2A)
R24 : R23 16-bit PWM0 output period cycle. R2A : R29 16-bit PWM1 output period cycle.
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
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7.1.23 PWM Duty Latch - DL0L (0x25)/DL0H (0x26) & DL1L (0x2B)/DL1H (0x2C)
R26 : R25 16-bit PWM0 output duty cycle buffer. R2C : R2B 16-bit PWM1 output duty cycle buffer.
7.1.24 BB Address Register - RFAAR (0x2D)
Register R2D indicates BB indirect RAM address.
7.1.25 BB Data Buffer Register - RFDB (0x2E)
Register R2E indicates BB indirect RAM data.
7.1.26 BB Data Read/Write Control Register - RFACR (0x2F)
Register R2F indicates BB RAM access control.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 RRST Bit 1 RFRD Bit 0 RFWR
Bit 0 (RFWR): Write BB register. Bit 1 (RFRD): Read BB register Bit 2 (RRST): BB S/W reset. Bit 3 ~ Bit 7: reserved
7.1.27 BB Interrupt Flag Register - RFINTF (0x30)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CSDF TX_AEF RX_AFF
TX_ EMPTYF RX_OFF LINK_ DISF LOCK_OUTF LOCK_ INF
Bit 0 (LOCK_INF): This bit reflects the LOCK IN flag interrupt. Bit 1 (LOCK_OUTF): This bit reflects the LOCK OUT flag interrupt. Bit 2 (LINK_DISF): This interrupt is invoked by the zero counter capacitor discharge mechanism. Bit 3 (RX_OFF): This bit reflects the RX FIFO full flag interrupt. Bit 4 (TX_EMPTYF): This bit reflects the TX EMPTY flag interrupt. Bit 5 (RX_AFF): This bit reflects the RX FIFO almost full flag interrupt. Bit 6 (TX_AEF): This bit reflects the TX FIFO almost empty flag interrupt. Bit 7 (CSDF): This flag indicates that a carrier-sense interrupt has occurred.
30 *
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
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BB Controller
7.2 Dual Port Register (0x40 ~ 0x7F)
R 40 ~ R7F are dual port registers.
7.3 System Status, Control and Configuration Registers
These registers are function-oriented registers used by the CPU to record, enable or disable the peripheral modules, interrupts, and the operation clock modes.
7.3.1
Bit 7 SPIE
Peripherals Enable Control - PRIE (0x80)
Bit 6 Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE
Bit 0 (FRCE): Free Run Counter 0 (FRC0) Enable bit. Bit 1 (TCCE): Timer Clock/Counter (TCC) Enable bit. Bit 2 (PWM0E): PWM0 function Enable bit. Bit 3 (PWM1E): PWM1 function Enable bit. Bit 4 (ADE): ADC Enable bit. Bit 5 (BBE): Base Band (BB) Enable bit. Bit 7 (SPIE): Serial Peripheral Interface Enable bit. 0: disable function 1: enable function
7.3.2
Bit 7 GIE
Interrupts Enable Control - INTE (0x81)
Bit 6 RBFIE Bit 5 PWM1IE Bit 4 PWM0IE Bit 3 EINT1E Bit 2 EINT0E Bit 1 TCCOE Bit 0 FRCOE
Bit 0 (FRC0OE): Free Run Counter (FRC) Overflow interrupt enable bit. Bit 1 (TCCOE): TCC (TCC) Overflow interrupt enable bit. Bit 2 (EINT0E): External pin (EINT0) interrupt enable bit. Bit 3 (EINT1E): External pin (EINT1) interrupt enable bit. Bits 4 (PWM0IE): PWM0 period complete enable bit. Bits 5 (PWM1IE): PWM1 period complete enable bit. Bit 6 (RBFIE): SPI Read Buffer Full (EINT) interrupt enable bit. 0: disable function interrupt 1: enable function interrupt
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BB Controller
Bit 7 (GIE): Global interrupt control bit. Global interrupt is enabled by the ENI and RETI instructions and is disabled by the DISI instruction. 0: disable Global interrupt function 1: enable Global interrupt function
7.3.3 Key Wake-up Enable Control - KWUAIE (0x82) & KWUBIE (0x83)
KWUAIE: Port A Key Wake-up Interrupt Enable Control Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 KWUBE Bit 2 KWUAE Bit 1 KWU9E Bit 0 KWU8E
Bit 0 ~bit 3 (KWU8E ~ KWUBE): Enable or disable the PTA0 ~ PTA3 Key Wake-up function. 0: disable key wake-up function 1: enable key wake-up function KWUBIE: Port B Key Wake-up Interrupt Enable Control Register
Bit 7 KWU7E Bit 6 KWU6E Bit 5 KWU5E Bit 4 KWU4E Bit 3 KWU3E Bit 2 KWU2E Bit 1 KWU1E Bit 0 KWU0E
Bit 0 ~bit 7 (KWU0 ~ KWU7): Enable or disable the PTB0 ~ PTB7 Key Wake Up function. 0: disable key wake-up function 1: enable key wake-up function
7.3.4 External Interrupts Edge Control - EINTED (0x84)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EINT1ED EINT0ED
Bit 0 (EINT0ED): Define which edge as an interrupt source for EINT0. Bit 1 (EINT1ED): Define which edge as an interrupt source for EINT1. 0: Falling Edge 1: Rising Edge Bit 2 ~ Bit 7 reserved
32 *
Product Specification (V1.0) 10.09.2007
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BB Controller
7.3.5 Serial Peripheral Serial (SPI) Enable Control Register - SPIC (0x85)
Bit 7 SPI_RBF Bit 6 CES Bit 5 SBR2 Bit 4 SBR1 Bit 3 SBR0 Bit 2 SDID Bit 1 SDOD Bit 0 SPIS
Bit 0 (SPIS): SPI start. Bit 1 (SDOD): SPI data shift out direction. 0: Most significant bit (MSB) transmitted first 1: Least significant bit (LSB) transmitted first Bit 2 (SDID): SPI data shift in direction. 0: Most significant bit (MSB) received first 1: Least significant bit (LSB) received first Bit 3 ~ 5 (SBR0 ~ SBR2): Configure the transmission mode and the clock rate.
SBR2 (Bit5) 0 0 0 0 1 1 1 1 SBR1 (Bit4) 0 0 1 1 0 0 1 1 SBR0 (Bit3) 0 1 0 1 0 1 0 1 Mode Master Master Master Master Master Slave N/A N/A Baud Rate Fosc/2 Fosc/4 Fosc/8 Fosc/16 Fosc/32 N/A N/A N/A
Bit 6 (CES): Clock edge select bit. 0 : Data shifts out on a rising edge, and shifts in on a falling edge. Data is held during a low level 1 : Data shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level Bit 7 (SPI_RBF): SPI read buffer full flag.
7.3.6 I/O Control Registers - IOCA~IOCF (0x86~0x8B)
IOCX is used to determine the data direction of its corresponding I/O port bit. 0 : configure a selected I/O pin as output 1 : configure a selected I/O pin as input The only four least significant bits of port F, and the only five least significant bits of port C are available.
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7.3.7 Pull-up Resistance Control Registers for Ports A~F - PUCA~PUCF (0x8C ~ 0x91)
Each bit of PUCX is used to control the pull-up resistors attached to its corresponding pin respectively. The theoretical value of the resistor is 64 K. However, due to process variation, 35% variation in resistance must be taken into consideration. PUCX:
Bit 7 PUCX7 Bit 6 PUCX6 Bit 5 PUCX5 Bit 4 PUCX4 Bit 3 PUCX3 Bit 2 PUCX2 Bit 1 PUCX1 Bit 0 PUCX0
0 : Pull-up Resistors disconnected 1 : Pull-up Resistors attached
7.3.8 Open Drain Control Registers of Port B/Port C - ODCB/ODCC (0x92/0x9A)
ODCB/ODCC: Open drain control of Port B/Port C.
Bit 7 OPCX7 Bit 6 OPCX6 Bit 5 OPCX5 Bit 4 OPCX4 Bit 3 OPCX3 Bit 2 OPCX2 Bit 1 OPCX1 Bit 0 OPCX0
0 : Open drain disable 1 : Open drain enable
7.3.9 Timer Clock Counter Controller - TCCC (0x93)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TCCS0 Bit 2 PSR2 Bit 1 PSR1 Bit 0 PSR0
Bit 0 ~ 2 (PSR0 ~ PSR2): Prescaler for TCC.
PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 Clock Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3 (TCCS0): Clock Source Select.
TCCS0 0 1 Clock Source Selected PLL Clock Source Selected IRC Clock Source
Bits 4 ~ 7 are reserved.
34 * Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
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BB Controller
7.3.10 Free Run Counter Controller - FRCC (0x94)
Bit 7 Bit 6 Bit 5 Bit 4 OSCO2SL0 Bit 3 PPSCL2 Bit 2 PPSCL1 Bit 1 PPSCL0 Bit 0 FRCCS OSCO2E OSCO2SL1
Bit 0 (FRCCS): Clock Source Select.
FRCCS 0 1 Clock Source Selected PLL Clock Source Selected IRC Clock Source
Bits 1 ~ 3 (PSR0 ~ PSR2): Prescaler for the OSCO2 clock output.
PPSCL2 0 0 0 0 1 1 1 1 PPSCL1 0 0 1 1 0 0 1 1 PPSCL0 0 1 0 1 0 1 0 1 Clock Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 4 and Bit 5 (OSCO2SL0 and OSCO1SL1): System Clock Frequency Select Control Bits
OSCO2SL0 0 0 1 1 OSCO2SL1 0 1 0 1 Output Frequency (MHz) 6 12 24 48
Bit 6 (OSCO2E): OSCO2 output function mask. . 0: OSCO2 disabled, function as pin PF0; 1: OSCO2 enabled. Bit 7 Reserved.
7.3.11 Watchdog Timer Controller - WDTC (0x95)
Bit 7 GREEN Bit 6 Bit 5 Bit 4 WDTCE Bit 3 Bit 2 RAT2 Bit 1 RAT1 Bit 0 RAT0
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Bit 0 ~ 2 (RAT0 ~ RAT2): Prescaler of WDT.
RAT2 0 0 0 0 1 1 1 1 RAT1 0 0 1 1 0 0 1 1 RAT0 0 1 0 1 0 1 0 1 Clock Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 4 (WDTCE): Enable the WDT Counter 0 : WDT disabled; 1 : WDT enabled. Bits 7 (GREEN): for the reason of power saving, the system clock can be changed to internal RC mode. 1 : Green Mode 0 : Normal Mode Bits 3, 5 and 6 are reserved.
7.3.12 ADC Analog Input Pin Select - ADCAIS (0x96)
Bit 7 Bit 6 Bit 5 Bit 4 IMS2 Bit 3 IMS1 Bit 2 IMS0 Bit 1 CKR1 Bit 0 CKR0
CKR0 ~ CKR2 (Bit 0 ~ Bit 2): AD conversion Rate control bits. IMS2~IMS0 (Bit 2 ~ Bit 4): ADC configuration definition bit. Bits 5 ~ 7 are reserved.
7.3.13 ADC Configuration Register - ADCCR (0x97)
Bit 7 ADRUN Bit 6 ADIE Bit 5 Bit 4 Bit 3 AIPS3 Bit 2 AIPS2 Bit 1 AIPS1 Bit 0 AIPS0
Bit 0 ~ Bit3 (AIPS0~AIPS3): Analog Input Select. Bit 6 ~ Bit 7 (ADIE): ADC interrupt enable. 0 : ADC interrupt disable 1 : ADC interrupt enable
36 *
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Bit 7 (ADRUN): ADC starts to RUN 0 : reset on completion of the conversion; this bit cannot be reset by software. 1 : A/D conversion is started; this bit can be set by software. Bits 4 and 5 are reserved.
7.3.14 PWM Control Register - PWMCR (0x98)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 S_PWM1 Bit 2 S_PWM0 Bit 1 Bit 0 -
Bit 2 (S_PWM0): Selected PWM0 output enable. Bit 3 (S_PWM1): Selected PWM1 output enable. 0: disable PWM output 1: enable enable PWM output Bits 0, 1 and 4 ~ 7 are reserved.
7.3.15 BB Interrupt Control Register - RFINTE (0x99)
Bit 7 CSDE Bit 6 TX_AEE Bit 5 RX_AFE Bit 4 TX_ EMPTYE Bit 3 RX_OFE Bit 2 LINK_ DISE Bit 1 LOCK_OU TE Bit 0 LOCK_ INE
Bit 0 (LOCK_INE):
LOCK IN interrupt enable bit.
Bit 1 (LOCK_OUTE): LOCK OUT interrupt enable bit. Bit 2 (LINK_DISE): Bit 3 (RX_OFE): LINK_DIS interrupt enable bit. RX FIFO full interrupt enable bit.
Bit 4 (TX_EMPTYE): TX EMPTY interrupt enable bit. Bit 5 (RX_AFE): Bit 6 (TX_AEE): Bit 7 (CSDE): RX FIFO almost full interrupt enable bit. TX FIFO almost empty interrupt enable bit. carrier-sense interrupt enable bit. 0: disable interrupt function 1: enable interrupt function
Product Specification (V1.0) 10.09.2007
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7.4 Code Option (ROM-0x2FFF)
Register SCLK is located on the very last bit of EM77950's 12K program ROM. These values will be fetched first to be the system initial values as power-on. SCLKC: System Clock Control Register
SCLKC 0x2FFF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 SCLK1 Bit 0 SCLK0
RFCLK1 RFCLK0
SCLKC 0x2FFF
Bit 15 -
Bit 14 -
Bit 13 -
Bit 12 -
Bit 11 -
Bit 10 -
Bit 9 -
Bit 8 -
Bit 1 ~ Bit 2 (SCLKS1 ~ SCLKS0): System Clock Frequency Select Control Bits
SCLK1 0 0 1 1 SCLK0 0 1 0 1 System Clock (MHz) 6 12 24 48
Bit 3 ~ Bit 4 (RFCK1 ~ RFCK0): Wireless Modem Clock Frequency Select Control Bits
RFCLK1 0 0 1 1 RFCLK0 0 1 0 1 System Clock (MHz) 6 12 24 48
Bit5 ~ 15: Reserved
SCLK [1:0] 00 00/01/10/11 01/10/11 00/01/10/11 RFCLK [1:0] WDT_CON.GREEN 00 01/10/11 00/01/10/11 00/01/10/11 0 0 0 1 SYS CLK Bypass 6/12/24/48 12/24/48 IRC RF CLK Bypass 12/24/48 6/12/24/48 6/12/24/48 BB enable Note 1~20MHz (6MHz)
38 *
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
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BB Controller
8
Baseband (BB)
8.1 BB: Standard Interface for the RFW102 Series
8.1.1 Features
Parallel interface to RFW102 modem Serial to Parallel conversion of RFW102 interface Input FIFO (RX_FIFO) Output FIFO (TX_FIFO) Preamble Correlation Packet Address Filter (Network and unique) CRC calculation Working Frequencies: 6-24MHz Power Save modes: Idle, Power-down Inter-RFWAVES networks Carrier-sense Discharge of the RFW-102 reference capacitor Compensate for clock drifts between transmitting and the receiving the EM77950 up to 1000ppm. Hence, the EM77950 requires low performance crystal. Interrupt Driver - connected to the EM77950's internal interrupt and informs the EM77950 about BB events.
8.1.2 Description
RFWAVES has developed a very low cost wireless modem (RFW102) for short range, cost-sensitive applications. The modem is a physical layer element (PHY) - allowing the transmission and reception of bits from one end to the other. In an RFWAVES application, the MCU is in charge of the MAC layer protocol. In order to reduce the real-time demands of the MCU handling the MAC protocol, the BB was developed. The BB enables the MCU an easy interface to RFW102 through a parallel interface, similar to memory access. It converts the fast serial input to 8-bit words, which are much easier for an 8-bit MCU to work with, and requires a lower rate oscillator. It buffers the input through a TBD bytes FIFO, enabling the MCU to access the BB more efficiently. Instead of reading one byte per interrupt, the MCU can read up to 16 bytes in each interrupt. This reduces the MCU overhead in reading incoming words, insofar as stack stuffing and pipeline emptying are concerned, in cases where each incoming byte causes an interrupt. When using the FIFO, the MCU pays the same overhead for all the FIFO bytes as it paid for only one byte without a FIFO.
Product Specification (V1.0) 10.09.2007
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Having a low-cost BB with a built-in state machine that can support basic wireless communication elements presents the following advantages: Shorter development time, hence shorter time to market. Conserve CPU power and other resources for other applications. Offer an easy, standard integrated solution.
8.1.3 I/O and Package Description
MCU
RAM_ADDR [0~6] DATA [0~7] RD_n WR_n CS_n RST TX_AE RX_AF TX_EMPTY CS LOCK_IN LOCK_OUT SHDWN RF CLK 7 8
BB
RAM_ADDR [0~6] DATA [0~7] RD_n WR_n CS_n RST TX_AE RX_AF TX_EMPTY CS LOCK_IN LOCK_OUT SHDWN RF CLK Serial IO TX_RX RF_Active
RFW-102
Data IO TX_RX RF_Active
Fig. 8-1 Parallel Interface between the MCU and RFW-102 through BB
40 *
Product Specification (V1.0) 10.09.2007
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BB Controller
Name
Type
Description This bus comprises of eight TRI-STATE input/output lines. The bus provides bidirectional communication between the system and the MCU. Data, control words, and status information are transferred via the DATA [0-7] data bus. When RD_n is low while the system is enabled, BB outputs one of its internal register values to DATA[0-7] according to RAM_ADDR[0-6]. When WR_n is low while the system is enabled, BB enables writing to its internal registers. The register is determined by RAM_ADDR [0-6] and the value DATA[0-7]. These four input signals determine the register to which the MCU writes to or reads from. Chip select input pin. When CS_n is low, the chip is selected; when high, the chip is disabled. This pin overrides all pins excluding RST. This enables communication between BB and the MCU. This pin functions as wakeup pin for power-down and idle modes. Interrupt driver pins.
DATA [0-7]
I/O
RD_n
I
WR_n RAM_ADDR[0-6]
I
I
CS_n
I
TX_AE; TX_EMPTY; RX_AF; CS; LOCK_IN; LOCK_OUT
O
This pin goes high whenever any of the interrupt sources has an active high condition and is enabled via the IER. The purpose of this pin is to notify the MCU through its external interrupt pin that an event (such as empty TX_FIFO) has occurred. Goes low when IER register is read. Chip's reset pin. When this pin is set high, all registers and FIFOs are cleared to their initial values. All transceiver traffic is disabled and aborted. Reset is asynchronous to system clock. After power-up, a pulse in RST input should be applied (by POR).
RST
I
SHDWN RF_ACTIVE
I O
Shut Down BB This output pin controls the RFW102 working/shutdown mode. Its values are determined by SCR4(1). Serial input or output according to TX_RX mode. It functions as serial interface for the RFW-102 (RFWAVES modem). When SERIAL_IO is input, it is a Schmitt-trigger input. This pin controls RFW-102 operation mode. It should be connected to RFW-102 RX_TX input pin.
SERIAL_IO
I/O
RX_TX
O
When RX_TX is low, RFW-102 is in receiving mode. When RX_TX is high, RFW-102 is in transmitting mode. In most cases RX_TX output pin is determined by SCR2(0) register. SCR3(7) and the capacitor discharge mechanism affects this pin.
RF_CLK
I
Clock for RF operation
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8.1.4 BB Architecture
INT
Interrupt Handler
Address Filter
RX FIFO
Receiver
Preamble Correlation
Serial Input / Output
Parallel Interface
Address Bus
Control and Status Registers
CRC
Data Bus
TX FIFO
Transmitter
Fig. 8-2 BB Block Diagram
8.2 BB Description
8.2.1 Reset
A reset is achieved by holding the RST pin high for at least TBD oscillator cycles. To ensure good power-up, a reset should be given to BB after power-up.
8.2.2 Power Saving Modes
The BB was designed to work in similar working modes as a typical MCU. These modes enable the system to conserve power when the BB is not in use. 8.2.2.1 Power-Down Mode
The MCU is able to halt all activity in BB by stopping its clock. This enables the MCU to reduce the power consumption of the BB to a minimum. All registers and FIFOs retain their values when BB is in power-down mode. BB enters power-down mode by setting bit TBD in register TBD to "1". This bit is set by the MCU and cleared by BB. BB goes back to working mode by setting CS_n input pin to "0" for TBD msec. The wake-up time of BB from power-down mode to fully operating mode is TBD msec.
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Since BB retains all the register values in power-down mode, special care should be paid to the register values before it enters power-down. For example, the MCU should check that the BB is not in the middle of transmitting or receiving a packet. The RFACTIVE should be set low to shutdown the RFW-102, before entering power-down mode. 8.2.2.2 Idle Mode
In idle mode, the BB internally blocks the clock input. The external clock is not stopped, but it is not routed to the internal logic. By doing this, the MCU achieves substantial power savings and yet the wake-up time is still relatively short. The power consumption is not minimal since the external clock is still active. All registers and FIFOs retain their values when BB is in idle mode. BB enters idle mode by setting bit TBD in register TBD to "1". This bit is set by the MCU and cleared by BB. BB goes back to working mode by setting CS_n input pin to "0" for TBD sec. Since BB retains all the register values in idle mode, special care should be given to the register values before BB enters idle mode. For example, the MCU should check that the BB is not in the middle of transmission or receiving a packet. In addition, the RFACTIVE should be set low to shutdown the RFW-102.
8.2.3 Preamble Correlation
The transmitting BB sends the PREAMBLE in order to synchronize the receiver to its transmission. BB transmits a fixed size PREAMBLE of 16 bits. The received PREAMBLE has a variable length of 16 9 bits, determined by SCR2 [5:7]. The receiver correlates the 16 9 bits from its PRE-L and PRE-H registers to the 16 9 bits in its input shift-register. If a correlation was found, then BB receiver state machine is enabled. The purpose of the PREAMBLE is to filter the module packets from white noise or other transmissions on the channel. NODE_ID and NET_ID filter are used to filter packets from other module networks. The PREAMBLE is transmitted MSB to LSB (PRE-H first and then PRE-L). The value of the PREAMBLE is determined according to PRE-L and PRE-H registers. The BB has the same PREAMBLE when it is in transmitting mode (TX_RX=1) as when it is in receiving mode (TX_RX=0). The value of the PRE-L and PRE-H registers should be identical in the BB in all nodes in the network.
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8.2.4 Refresh Bit
When receiving a valid packet, The RFWaves modem (PHY layer) has to receive a "1" symbol each time a certain period has elapsed in order to maintain its sensitivity. The time between adjacent "1" symbols is determined by the value of the reference capacitor. This constraint is transparent to the application layer since the BB adds a "1" symbol (refresh bit) if too many "0" symbols are transmitted consecutively. On the receiver side, these additional "1" symbols (refresh bits) are removed by the BB. This feature is transparent to the application layer. The application layer has only to initialize the maximum allowed number of consecutive x"00" bytes. The BB has the flexibility to add a refresh bit every 1 to 7 bytes. This is configured by RB (0:2) bits in PPR register. The value of RB (0:2) bits in PPR register determines the overhead the refresh bit has on the throughput of the link. The refresh bit does not add substantial overhead on the bit stream, since it is only added when the number of consecutive x"00" bytes exceeds a certain value. The data that is sent is application dependent, so the application can be adjusted in order that there will be a negligible probability of this event happening. Typical RFWaves capacitor: C=1nF. Normal discharge current = 200nA. Each 10mV on the capacitor represent 1dB in receiving power.
I 200nA 1dB = = C V 1nF 10mV 50 sec
The capacitor is charged with each received "1" symbol. The receiver is allowed to lose 1dB before a new "1" is to be received. Thus, after each 50 consecutive "0" bits in 1Mbps (50sec) a "1" symbol should be sent. In this case, setting RB [0:2] in PPR register to be 5 ("101") would be sufficient (5 bytes = 40bits). When RB (0:2) bits are set to "000" a refresh bit is added to every transmitted byte, regardless of its content. This introduces a constant overhead of 12.5%.
8.2.5 Bit Structure
The BB uses an oscillator ranging from 6~24 MHz. In order to determine the output and input bit rate, the BB must be configured to the number of clocks consisting each bit. This gives the applicator the control over the bit rate with certain restrictions. Each bit must have at least 6 clock cycles.
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The maximum bit rate is: 1Mbps. The minimum bit rate is: 10Kbps (TBD) However it is recommended to work only at 1Mbps since reducing the bit rate does not change the energy of a transmitted bit. Meaning, reducing the bit-rate does not improve the bit error rate or the range between the transmitter and the receiver. Bit Length Register (BLR) determines the number of clock cycles per bit (bit period). BLR value is given a fixed offset of 6, since the minimum number of clock cycles in one bit is 6. Bit Rate = Oscillator/(BLR+6). The BB outputs (for the RFW-102) the bit structure shown below.
Bit "1" Structure - Even Clock Number
Bit "1" Structure - Odd Clock Number
Clock Period Bit Period
Clock Period Bit Period
Fig. 8-3 Bit Structure of the BB output to the RFW-102
In the odd number of clocks example BLR=1. In the even number of clocks example BLR=2. The number of clocks when the line is "1" is determined as follows:
BLR + 6 Number of "1" s = FLOOR - 1 2
In case of "0" bit, BB output "0" value for BLR+6 clock pulses. * FLOOR - Rounds towards zero.
8.2.6 CRC
The BB adds additional CRC information to each packet in the transmitter module, in order to enable the protocol to detect errors. The CRC is a redundant code, which is calculated and added to each packet on the transmitter side. The CRC is also calculated on the receiver side. The CRC calculation results of the receiver and the CRC field in the received packet are compared in the receiver using the CRC module in the chip. If CRC results are equal, then the receiver knows with reasonable probability that the packet was received correctly. If the CRC results are not equal then the receiver knows with probability 1 that the packet was received incorrectly. The CRC mode is configured in the PPR (3:4) register.
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Both the receiving node and the transmitting node in the network have to be in the same CRC mode. The BB can apply CRC in three different ways: 16-Bit CRC - using polynomial 1+X +X +X . 8-Bit CRC - using polynomial 1+X+X +X . No CRC. This gives each application the flexibility to choose the adequate amount of overhead it adds to each packet and the corresponding level of protection the CRC code has. If CRC is enabled, then BB calculates the CRC of each incoming packet. It does not put the received CRC value in the RX_FIFO. It just puts the result of its calculation in the RX_FIFO as the last byte of the packet: 0x55 - CRC received correctly. 0xAA - CRC was received incorrectly. The status bit SSR (0) stores the result of the last received packet.
2 8 2 15 16
8.2.7 RX FIFO
All received bytes are transferred to the RX_FIFO. The RX_FIFO stores the input data until the MCU reads the data from it. CRC and Preamble bytes are not transferred to the RX_FIFO. The RX_FIFO is accessed just like all the other read-only registers in the BB. The MCU cannot write to RX_FIFO - it can only read from it. RX_FIFO_SIZE is 16 bytes. The purpose of having an input FIFO in BB is to reduce the real-time burden from the MCU. The FIFO is used as a buffer, which theoretically enables the MCU to read the incoming data every RX_FIFO_SIZE x 8 bit/byte x 1sec = 128 sec, and not every 1sec in the case of serial input, or every 8sec in the case where there is a serial to parallel converter. The actual buffer size for practical use is a bit smaller, since the MCU response time is taken into account. The MCU has three ways to learn about the RX_FIFO status: The RX FIFO Status Register (RFSR) contains the number of bytes in the RX_FIFO. BB INT pin. I f configured appropriately, the INT pin will be "1" each time RX_FIFO is almost full. This invokes an MCU interrupt if the INT pin is connected to the MCU external interrupt pin.
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RX_FIFO Overflow Status Bit - bit RX_OF in SSR indicates when an overflow event has occurred. If a received byte is written to a full RX_FIFO, the last byte in the RX_FIFO is override and the RX_OF flag is raised. The RX_AF interrupt should invoke the MCU to read from the RX_FIFO. Using the almost full event gives the MCU 32sec (4 bytes x 8 sec) to respond before it loses data, assuming a bit rate of 1Mbps. It uses most of the RX_FIFO size even if the response latency of the MCU is very short. Should the MCU not respond properly to the almost full event, and an input byte is written to the RX_FIFO when it was full, then this byte would overrun the last byte in the RX_FIFO, meaning the byte that immediately preceded it. LOCK_OUT interrupt should also trigger the MCU to read from the RX_FIFO. In case a packet has ended and the RX_AF interrupt was not invoked, the MCU should be triggered by the LOCK_OUT interrupt.
8.2.8 TX FIFO
Transmitting data is done by writing it to the TX_FIFO. The interface to the TX_FIFO is similar to all the other write-only registers in BB. The purpose of the TX_FIFO is to reduce the real-time from the MCU in a transmitting process. The TX_FIFO enables the MCU, theoretically, to write to the TX_FIFO every 128sec and not every 8sec, as is the case with a regular 8-bit shift register. The TX_FIFO Status Register (TFSR) indicates the number of bytes in the TX_FIFO. The TX_FIFO can also invoke an MCU interrupt if TX_FIFO almost empty event occurs. Almost empty flag will rise when there are only 4 empty bytes in the TX_FIFO. It gives the MCU 32sec to respond time to reload the TX_FIFO in case the transmitted packet is bigger than the TX_FIFO. In case the MCU writes to a full TX_FIFO, then this byte overruns the last byte in the TX_FIFO, meaning the byte that was written just before it. Writing to a full TX_FIFO set the TX_OF flag in SSR.
8.2.9 Interrupt Driver
The INT output pin is the summation of all interrupt sources in the BB. Whenever an interrupt event has occurred and this interrupt is enabled (IER), INT will go from low to high. INT will remain high until IIR register is read. The IIR register contains all the interrupts event that have occurred since the last read. It shows the event only for enabled interrupts. If an interrupt is disabled, even if the event that invoked this interrupt has occurred, the interrupt flag will be low. The IER register is used to enable/disable each of the interrupt. SCR4 (0) enables/disables all the interrupts.
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There are 8 events in the BB that can cause the INT pin to go from low to high: 1. LOCK_IN - This interrupt indicates that the BB has started receiving a new packet. The Preamble has been identified. If the NET_ID or/and the NODE_ID are enabled, then they have been identified correctly. This event signals the beginning of an incoming packet. 2. LOCK OUT - BB has just finished receiving a packet. This means that if the BB is in fixed packet size mode, then it has finished receiving PSR bytes not including CRC bytes. If BB is not in fixed packet size mode, then it has just finished receiving a packet of size as indicated in the packet header. Although RX_STOP and setting TX_RX=1 (SCR2) terminate the receiving of the packet, they do not cause a LOCK_OUT event, since the MCU is already aware of it (the MCU initiated it). The LOCK_OUT interrupt tells the MCU when to get data out of the RX_FIFO. 3. LINK_DIS - This interrupt indicates that a "Zero counter" capacitor discharge event has occurred. If a consecutive number of zero bits (according to SCR3 (4:6)) have been received, this interrupt is set, even if zero count capacitor discharge is disabled (SCR3 (3) - EN_ZERO_DIS = '0'). The actual capacitor discharge and its interrupt are two separate registers (IER (2) for the interrupt and SCR3 (3) for the discharge). 4. RX_OF - This interrupt indicates that a byte from an incoming packet was discarded, since the RX_FIFO was already full. The receiver module tried to write a byte to a full RX_FIFO. The MCU should know that the corresponding packet is corrupted, since it is lacking at least one byte. 5. 6. 7. 8. TX_EMPTY - The BB has finished transmitting a packet. Meaning, the transmit shift register is empty and BB is now in RX mode (not TX mode). RX_FIFO_AF - RX_FIFO is almost full. If the MCU does not want the RX_FIFO to overflow, then it should empty it. TX_FIFO_AE - TX_FIFO is almost empty. If the MCU did not finish putting the transmitted packet in the TX_FIFO, then it should continue doing so now. CS - CS status line has gone from "1" to "0" invokes a CS interrupt. This signals the MCU that an unidentified (NET_ID or NODE_ID or Preamble were not identified) packet has ended. If the MCU has a packet to transmit, and CS="1" than the MCU waits for this event. All these events can be masked. If an event is masked, then even if that event occurs - it does not set the INT pin to "1". The masking is done by register IER. The reason for masking is that in different applications or in different situation in the same application these events have different priorities. The MCU determines which of these events will invoke an MCU interrupt.
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Moreover all these events can be masked together by IE in IER register. If INT pin is set to "1", the MCU learns which event has occurred by reading IIR register. INT goes "0" when MCU reads from IIR register.
8.2.10 Packet Size
There are two types of packet structure determined by PPR [5] (FIXED). Fixed Sized Packet - all packets have the same, fixed size. The packet size is determined in PSR register. The packet size can be 2 ~ 255 bytes. Variable Sized Packet - the header of the incoming packet determines the packet size. One of the header bytes contains the packet size. Bits SIZE_LOC[0:1] in LCR register determines the location (offset) of the packet size inside each incoming packet header. The BB reads the packet size byte in the packet header according to LCR register. In both cases the packet size does not include the CRC addition or the Preamble.
8.2.11 NET_ID and NODE_ID Filters
NET_ID and NODE_ID are two filters in the receiver. They filter incoming packets according to their network address and node address. The address field in each incoming packet is compared to NET_ID byte and NODE_ID byte. If one of the above comparisons fails, then the packet is discarded and the MCU will not be aware of it. NET_ID and NODE_ID are both one byte. Their values are stored in NIR and BIR registers accordingly. The byte to which they are compared is set by the LCR register. Each of them can be enabled or disabled independently (PPR register). NET_ID is targeted to be a filter on the network address. It is supposed to be common for all nodes in the network. NODE_ID is targeted to be a filter on the specific node address. It is supposed to be unique to each node in the network. The purpose of these filters is to conserve MCU power and to reduce its load. In a multi-node network, a node can filter all packets that are not sent to it, while in multi-network environment, a node can filter packets from other RFWaves networks. In certain network, a multicast ability inside the network is required. Even if NODE_ID filter is applied, Addresses `111111XX' in NODE_ID filter are preserved for multicast transmissions. NODE_ID filter will not discard those 4 addresses in any case.
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8.2.12 Carrier-Sense
Carrier-sense protocols are protocols in which a node (station) listens to the common channel before it starts transmitting. The node tries to identify other transmissions in order to avoid collision that might block its own transmission. In a wider perspective, a network that applies carrier-sense protocol utilizes the channel bandwidth more efficiently. A more efficient network enables lower power consumption to each node, shorter delay and higher probability of reaching destination to each packet. The BB uses one complimentary technique in order to achieve very wide-ranging carrier-sense abilities. It has an internal implementation of RFWaves Network Carrier-Sense algorithm. This enables it to avoid collision with other RFWaves stations on its network or from other networks in the area. While the Carrier-Sense status bit in SSR (CS) tells the MCU when not to transmit, the two interrupt CS and LINK_DIS gives the MCU a flag when to transmit. LINK_DIS will be invoked whenever any transmission has ended, while CS interrupt will be invoked only when an RFWaves transmission has ended. An application can use some of the above mechanisms though not all of them - according to its needs. 8.2.12.1 RFWaves Carrier-Sense Algorithm Assuming our bit rate is 1Mbps. According to the described bit structure (Section 8.2.5 Bit Structure), the time difference between two rising on DATA_IO must be an integer number of 1sec. If we take into account the frequency deviation between the two BB oscillators, the time difference between two rising edges is 1sec . The depends on the frequency deviation between the two BB oscillators. The BB uses this quality in its carrier-sense algorithm. If an N (N = (CSR (0:3) * 2) + 2) number of "1" bit, where each is preceded by at least one "0" bit, are received with time difference of an integer number of 1sec between two consecutive "1" bit, then the CS flag in SSR equals `1'. Basically, the BB counts "0" to "1" transits on DATA_IO input, where the time difference between two transits should be an integer number ( 2) of 1sec. The number of consecutive "1" bit that conforms to this rule is counted in the following example (Figure 8-2) in ONE_CNT counter. ONE_CNT is incremented only if a "1" bit that comes after a "0" bit is received, where the time gap between the "1" bit and the preceding "1" bit is as mentioned above. If the time difference between two consecutive "1" bit is out of the allowed deviation, the ONE_CNT is reset. ONE_CNT is also reset if the number of consecutive "0" exceeds (CSR (4:7) * 2) + 2, where CSR is the last "1" bit received is counted in ZERO_CNT. ZERO_CNT is reset each time "1" bit is received. Both M and N values are determined in CSR register (CSR (7:4) and CSR (3:0) accordingly).
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(0) ONE_CNT=0 ZERO_CNT=1 (1) ONE_CNT=1 ZERO_CNT=0 DATA_IO Signal
(2) ONE_CNT=1 ZERO_CNT=1 (3) ONE_CNT=2 ZERO_CNT=0
(4) ONE_CNT=2 ZERO_CNT=0
(6) ONE_CNT=1 ZERO_CNT=0 (5) ONE_CNT=2 ZERO_CNT=1
1usec Search Window
1usec
2 * 1usec Search Window
1usec
1usec Search Window
Fig. 8-4 Carrier-Sense Example
In the example shown in Figure 8-2, at time (1) a new "1" bit is received after a "0" bit was received. Thus, ONE_CNT equals 1 and ZERO_CNT is reset to 0. At time (2), a zero bit is received, so the ZERO_CNT is incremented. At time (3), a "1" is received after a "0" bit that was received before it. Thus ONE_CNT is incremented and ZERO_CNT is reset. At time (4) a "1" bit is received after a "1" bit, thus, there is no change in any counter. At time (6) a "1" bit is received out of the allowed window, so ONE_CNT is reset to 1. The CSR register is used to configure the carrier-sense algorithm sensitivity. The CSR register determines the number of "1" bit required in order to decide that a carrier exists. The CSR also determines the number of successive "0" bits that reset the carrier-sense state machine. In SSR register, bit CS notifies whether a carrier was identified. Carrier-sense can also be used as an interrupt. When CS in SSR goes from `1' to `0' i.e. the transmission has stopped, a CS interrupt is invoked (if enabled in IER). The purpose of this interrupt is to inform the MCU that the channel is free again. If the BB identifies a packet, the carrier-sense algorithm halts. When the BB is in RX mode and the LOCK flag in SSR is "0", the CS mechanism is working. When the LOCK flag in SSR is "1", the CS mechanism is not working, since the CS flag does not add any information because a Preamble was identified already. After a Preamble was identified the CS in SSR equals `1'.
8.2.13 Receiver Reference Capacitor Discharge
BB implements two independent mechanisms for receiver capacitor discharge: At the end of each received packet. Zero counter. Mechanism 1 is enabled/disabled by bit EN_CAP_DISCH in SCR3. Mechanism 2 is enabled/disabled by bit EN_ZERO_DISCH in SCR3.
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The number of "0" bits that will cause a discharge in Mechanism 2 are determined by bits ZERO_DISCH_CNT [0:2]. For both mechanisms, the discharge time is determined by CAP_DIS_PERIOD in SCR3. Discharge is done by setting RX_TX pin to `1' for a certain time and then setting it back to `0'. (*) More detailed explanations of the reference capacitor discharge algorithms and motivations are can be found in the "RFW - Capacitor Discharge.pdf" document.
8.2.14 Changing BB Configuration
It is not recommended to change the BB configuration while it is in the middle of receiving or transmitting a packet. Thus, before writing to any of the BB control registers (such as BLR, PRE-L, PRE-H, PPR etc), do thefollowing: 1. 2. 3. Change TX_RX mode to RX. Disable Preamble search (SEARCH_EN in SCR2) Stop all RX receiving - RX_STOP.
It is then safe to change the BB configuration.
8.2.15 Input Synchronizer
Handling asynchronous inputs to the BB.
Asynchronous Input
Synchronized Input
S R
SET
Q
S R
SET
Q
CLR
Q
CLR
Q
CLK
8.3 Register Description
The registers in the BB are divided into three groups:
* * *
Read-only registers. Mainly status registers. Write-only registers. Mainly control registers. Read and write registers.
In case of an RST pulse, all register are set to their default value.
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8.3.1 Bit Length Register (BLR)
This register is both a read and a write register. It determines the length of the bit in terms of clock cycles. The bit length will be (BLR+6) clocks, since the minimum length of a bit is 6 clocks. Default Value: 00 (0+6=6).
8.3.2 Preamble Low Register (PRE-L)
This register is a write-only register. This register contains the 8 least significant bits of the Preamble.
Name PRE-L Bit 7 PR-7 Bit 6 PR-6 Bit 5 PR-5 Bit 4 PR-4 Bit 3 PR-3 Bit 2 PR-2 Bit 1 PR-1 Bit 0 PR-0
Default Value: 0xEB.
8.3.3 Preamble High Register (PRE-H)
This register is a write-only register. This register contains the 8 most significant bits of the Preamble.
Name PRE-H Bit 7 PR-15 Bit 6 PR-14 Bit 5 PR-13 Bit 4 PR-12 Bit 3 PR-11 Bit 2 PR-10 Bit 1 PR-9 Bit 0 PR-8
Default Value: 0xFF.
8.3.4 Packet Parameter Register (PPR)
Name PPR Bit 7 NET ID_EN Bit 6 NODE ID_EN Bit 5 FIXED Bit 4 CRC1 Bit 3 CRC0 Bit 2 RB-2 Bit 1 RB-1 Bit 0 RB-0
This is a read and a write register. It contains control bits of the transmitted and received packet structure. Default Value: 0x3A.
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Bits 0-2 (RB-0~RB-2): Refresh Bits These bits determine the maximum number of successive "zero" bytes allowed before an added "one" bit is stuffed to the packet by the transmitter state machine. The reason for this feature is to keep the RFW-102 reference capacitor charged.
Refresh Bit Refresh bit is added to every byte. Refresh bit is added if 1 byte equals x"00". Refresh bit is added if 2 successive bytes equal x"00". Refresh bit is added if 3 successive bytes equal x"00". Refresh bit is added if 4 successive bytes equal x"00". Refresh bit is added if 5 successive bytes equal x"00". Refresh bit is added if 6 successive bytes equal x"00". Refresh bit is added if 7 successive bytes equal x"00". Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1
The value of the refresh bit is determined by the value of the reference capacitor. Bits 3, 4: CRC [0:1] These bits control the CRC operation for both transmit and receive mode:
CRC No CRC CRC8 CRC8 CRC16 Bit 4 0 0 1 1 Bit 3 0 1 0 1
Bit 5: FIXED This controls the packet mode when high system packets are fixed size and the length is specified in the Packet Size Register (PSR). When FIXED is low, the packet size is variable. The size is specified in the header of the incoming or outgoing packets. The location of the packet size field is specified in the LCR register. Bit 6: NODE_ID_EN This is NODE_ID control bit. 0: Disables Node ID search. 1: Enables Node ID search according to LCR, BIR.
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Bit 7: NET_ID_EN This is NET_ID control bit. 0: Disables Net ID search. 1: Enables Net ID search according to LCR, NIR.
8.3.5 System Control Register1 (SCR1)
Name N/A Bit 7 N/A Bit 6 N/A Bit 5 N/A Bit 4 N/A Bit 3 N/A Bit 2 N/A Bit 1 N/A Bit 0 N/A
This byte is reserved. Default Value: 0x00.
8.3.6 System Control Register 2 (SCR2)
Name SCR2 Bit 7
PRE MASK 2
Bit 6
PRE MASK 1
Bit 5
PRE MASK 0
Bit 4 STO P RX
Bit 3 TX FIFO RESET
Bit 2 RX FIFO RESET
Bit 1 SEARCH EN
Bit 0 TX_RX
This register is a read and a write register. This register controls the system operation modes. Bit 0: TX_RX Controls the transceiver mode: receive mode or transmit mode When TX_RX is low - BB is in receive mode (default mode). The output pin RX_TX is set to `0'. BB searches for a Preamble. If Preamble is found, it handles the process of receiving a packet. If SCR3 (7) is set, then the BB goes to RX mode and the output pin RX_TX is TX mode. The capacitor discharge can change the output pin RX_TX to TX mode even if we are in RX mode in the BB. In this case the output pin RX_TX will be in TX for a short duration and then return to RX mode. When TX_RX is high - BB is in transmit mode. The output pin RX_TX is set to `1'. BB handles the process of transmitting a packet according to the data in the TX_FIFO. When it finishes transmitting the packet, it automatically goes back to receive mode.
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Bit 1: SEARCH_EN Preamble search enable bit. When 1: Enables the search for Preamble in receive mode. When 0: Disables the search for Preamble in receive mode, (used when user configures the system while in default receive mode). This bit's default value is `0'. It must be set to `1' in order to start receiving a packet. Bit 2: RX_FIFO_RESET This bit resets the RX_FIFO address pointers when set to Logic 1. This bit is set by MCU and is cleared automatically by BB. Bit 3: TX_FIFO_RESET This bit resets the TX_FIFO address pointers when set to Logic 1. This bit is set by MCU and is cleared automatically by BB. Bit 4: STOP_RX This bit stops receiving the current command, resets the RX_FIFO counters and start new searches for preamble. This bit is set by MCU and is cleared automatically by BB. Bits 5-7: PRE_MASK [0:2] These bits determine the mask on PRE-H in preamble correlation. Meaning, it determines the size of the Preamble in the receiver. The PRE-L is always used in the Preamble correlation. BB cuts off bit from PRE-H register, starting from the MSB.
PRE MASK 0 0 0 0 0 1 1 1 1 PRE MASK 1 0 0 1 1 0 0 1 1 PRE MASK 2 0 1 0 1 0 1 0 1 Preamble Size 16 15 14 13 12 11 10 9
Default Value: 0x60
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BB Controller
8.3.7 System Control Register 3 (SCR3)
This register is a read and a write register.
Name SCR3 Bit 7 LOW MODE Bit 6 ZERO DISCH CNT 2 Bit 5 ZERO DISCH CNT 1 Bit 4 ZERO DISCH CNT 0 Bit 3 EN ZERO DISCH. Bit 2 CAP DIS PERIOD Bit 1 EN CAP DISCH. Bit 0 -
Bit 1: EN_CAP_DISCH Enables/disables capacitor discharge mechanism after each received packet: 0: Disables discharge. 1: Enables discharge. This bit overrides Bit 3. Bit 2: CAP_DIS_PERIOD Determines the capacitor discharge duration: 0: The pulse width is 36 clocks, (3 sec at 12 MHz clock). 1: The pulse width is 72 clocks, (3 sec at 24 MHz clock). Bit 3: EN_ZERO_DISCH Enables/disables zero counter mechanism for capacitor discharge: 0: Disables discharge 1: Enables discharge Bits 4-6: ZERO_DISCH_CNT [0:2] Determine the number of zero bits that will trigger a capacitor discharge by the zero counter mechanism.
ZERO DISCH CNT 0 0 0 0 0 1 1 1 1 ZERO DISCH CNT 1 0 0 1 1 0 0 1 1 ZERO DISCH CNT 2 0 1 0 1 0 1 0 1 Number of Zeros 5 10 15 20 25 30 35 40
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Bit 7: LOW_MODE Enables or disables low power mode for RFW-102 0: Disables low mode (normal mode). 1: Enables low mode. BB is in RX mode, while RFW-102 is in TX mode. User has to put the BB into RX mode to disable RX and Preamble search, before enabling LOW_MODE. This transfers the RFW-102 to TX mode using RX_TX pin, while the BB is still in RX mode. RFW-102 power consumption is lower in TX mode than in RX mode. BB cannot remain in TX mode, if it is not transmitting. The low mode is the combination of both of the above. Default Value: 0x01
8.3.8 System Control Register 4 (SCR4)
This register is a read and a write register.
Name SCR4 Bit 7 N/A Bit 6 N/A Bit 5 N/A Bit 4 N/A Bit 3 FIFO FLAGS Bit 2 WIN CONT Bit 1 RF_AC TIVE Bit 0 IE
Bit 0: IE This flag enables all interrupts when set to `1'. When `0' all interrupts are disabled. Bit 1: RF_ACTIVE This bit controls RF_ACTIVE pin. When this bit is high the RF Modem is active. Bit 2: WIN CONT This bit determines the size of the WINDOW in the Preamble search module. IF (BLR+6) > 14 and WIN_CONT=1, then the preamble window size is 5 Bit 3: FIFO FLAGS Determines the RX_FIFO AF flag and TX_FIFO AE flag: IF FIFO FLAGS = 0 then AF = 12 and AE = 4. IF FIFO FLAGS = 1 then AF = 8 and AE = 8. Default Value: 0x00.
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8.3.9 Transmit FIFO Status Register (TFSR)
This register is a read-only register. It contains the number of bytes in the TX_FIFO. Default Value: 0x00 (TX_FIFO empty).
8.3.10 Receive FIFO Status Register (RFSR)
This register is a read-only register. It contains the number of bytes in the RX_FIFO. Default Value: 0x00 (TR_FIFO empty).
8.3.11 Location Control Register (LCR)
This is a read and a write register.
Name LCR Bit 7 Bit 6 SIZE LOC 2 Bit 5 SIZE LOC 1 Bit 4 SIZE LOC 0 Bit 3 NET LOC1 Bit 2 NET LOC 0 Bit 1 NODE LOC 1 Bit 0 NODE LOC 0
Bits 0, 1: NODE_LOC [0:1] These bits determine the location of the NODE_ID parameter in the header (the location is specified in bytes excluding preamble). The location should be fixed for all of different kinds of packets transferred by the system. NODE_ID must never be set to be smaller than NET_ID, if both filters are enabled.
Location 2 3 4 5 NODE LOC 1 0 0 1 1 NODE LOC 0 0 1 0 1
Bits 2, 3: NET_LOC [0:1] These bits determine the location of the NET_ID parameter in the header (the location is specified in bytes excluding the Preamble). The location should be fixed for all the different kinds of packets transferred by the system.
Location 1 2 3 4 NET LOC 1 0 0 1 1 NET LOC 0 0 1 0 1
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Bits 4-5: SIZE_LOC [0:2] These bits determine the location of the Packet Size parameter in the header (the location is specified in bytes excluding the Preamble). The location should be fixed for all the different kinds of packets transferred by the system.
Location 2 3 4 5 6 7 8 9 SIZE LOC 2 0 0 0 0 1 1 1 1 SIZE LOC 1 0 0 1 1 0 0 1 1 SIZE LOC 0 0 1 0 1 0 1 0 1
Default Value: 0x00
8.3.12 Node Identity Register (BIR)
This is a read and a write register. When the Receiver State Machine builds the incoming packet, it compares the value in the BIR register to the received data at the location specified in LCR. If received NODE_ID and the expected NODE_ID are not equal, the packet is discarded. Four multicast NODE_ID addresses are implemented "111111XX". All packets whose 6 MSBs are "1" are not discarded. Default Value: 0x00
8.3.13 Net Identity Register (NIR)
This is a read and a write register. When the Receiver State Machine builds the incoming packet, it compares the value in the NIR to the received data at the location specified in LCR. If received NET_ID and the expected NET_ID are not equal, the packet is discarded. Default Value: 0x00
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8.3.14 System Status Register (SSR)
Name
SSR
Bit 7
-
Bit 6
TX_UF
Bit 5
BIT_ERROR
Bit 4
LOCK
Bit 3
CS
Bit 2
TX EMPTY
Bit 1
LOCKED
Bit 0
CRC ERROR
This register is a read-only register. This register provides status information to the MCU concerning the communication line and the data transfer. Bits 1, 2, 3 can trigger the interrupt if enabled in the IER. Bits 0, 5 and 6 are set by H/W and cleared automatically after the MCU reads the register. Bits 1~4 are set and cleared by H/W. Bit 0: CRC_ERROR This flag indicates a CRC Error in the packet. The CRC Block sets this flag at the end of each received packet according to the CRC calculation result. BB compares the calculated CRC and the received CRC. When these values differ, the flag goes high. The flag is cleared only after the MCU reads the SSR register. If the MCU does not read the SSR register, this flag remains "1". Bit 1: LOCKED This flag indicates that a packet is being received. Bit 1 is set to Logic 1 whenever the system identifies a new incoming packet (triggers LOCK IN interrupt). The bit will reset to Logic 0 when the packet ends (triggers LOCK OUT interrupt) or when one of the IDs fails (NET or BYTE). This indicator is important whenever we want to switch to transmit mode because it can tell us that the line is busy and that in most cases the transmission will not succeed. The Lock triggers interrupt for every change in the bit status. Bit 2: TX_EMPTY This bit is the Transmitter Empty flag. When this bit is high the system is available for loading the next packet for transmission and BB is in receive mode. When the flag is low, BB is in the middle of a packet transmission. When transmitting few successive packets, the MCU should wait to the end of a packet before it reloads the TX_FIFO with the next packet. Bit 3: CS Carrier Sense detection bit When this bit is high, the system has identified a structure of packet transmission in the air according to CSR. When low, no carrier has been detected. This bit is only valid in receive mode. The conditions for setting or clearing this flag are determined in the CS register. When LOCKED is high, then CS is meaningless.
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Bit 4: LOCK This signals whether a Preamble was identified or is still searching. When the flag is "0", the receiver is searching for Preamble. When the flag is "1" a Preamble was identified. If a packet was discarded for any reason, the LOCK flag goes to 1. Bit 5: BIT_ERROR This flag indicate that there was some error in the received package. The packet was not received according the expected timing specifications. The packet can still pass CRC verification. Bit 6: TX_UF This flag is set whenever the MCU reads a byte from an empty TX_FIFO. This flag indicates abnormal end of packet transmission. The MCU transmitter's state machine has expected to find a valid byte in the TX_FIFO according to the packet size, but it found an empty TX_FIFO. When this event occurs, the TX_EMPTY interrupt is invoked and TX_UF (underflow) flag is set to `1'. This flag is set by hardware and cleaned by MCU. It is cleaned whenever the MCU read the SSR register. Default Value: 0x04.
8.3.15 Packet Size Register (PSR)
This is a read and a write register. It contains the Packet Size in byte units. When working in fixed size packets (see Control Bit-1), the size will be fixed for all types of packets. The size in PSR excludes 2 bytes of Preamble and 2, 1 or 0 bytes of CRC. Default Value: 0x00.
8.3.16 Carrier Sense Register (CSR)
This is both a read and a write register.
Name CSR Bit 7 ZERO CNT.3 Bit 6 ZERO CNT.2 Bit 5 ZERO CNT.1 Bit 4 ZERO CNT.0 Bit 3 ONE CNT.3 Bit 2 ONE CNT.2 Bit 1 ONE CNT.1 Bit 0 ONE CNT.0
Bits 0-3: ONE_CNT [0:3] The number of successive "1" bits that set the carrier sense high. Bits 4-7: ZERO_CNT [0:3] The number of successive "0" bits that reset the carrier sense (CS='0'). Default Value: 0x44
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8.4 Interrupt Registers
8.4.1 Interrupt Enable Register (IER)
This register is a write and a read register.
Name IER Bit 7 CS Bit 6 TX_AE Bit 5 RX AF Bit 4 TX EMPTY Bit 3 RX_OF Bit 2 LINK_ DIS Bit 1 LOCK OUT Bit 0 LOCK IN
Default Value: 0x00. For all flags in this register, 0 : Disable 1 : Enable Bit 0: LOCK_IN This flag enables/disables the LOCK IN interrupt. PREAMBLE + NODE_ID + NET_ID identified correctly triggers LOCK IN interrupt. Bit 1: LOCK_OUT This flag enables/disables the LOCK OUT interrupt. End of received packet triggers LOCK_OUT interrupt. Bit 2: LINK_DIS This flag enables/disables the LINK_DIS interrupt. The zero counter capacitor discharge triggers the LINK_DIS interrupt. Bit 3: RX_OF This flag enables/disables the RX_OF interrupt. End of received packet triggers RX_OF interrupt. Bit 4: TX_EMPTY This flag enables/disables the TX_EMPTY (Transmitter Empty) interrupt. X_EMPTY interrupt tells the MCU that the transmitter has just finished transmitting a packet. BB goes to RX mode after finishing the transmission of a packet. Bit 5: RX_AF This flag enables/disables the RX_AF interrupt. The RX_AF interrupt is triggered when RX_FIFO AF flag goes from `0' to `1'. Bit 6: TX_AE This flag enables/disables the TX_AE interrupt. The TX_AE interrupt is triggered when TX_FIFO AE flag goes from `0' to `1'.
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Bit 7: CS This flag enables/disables the CS interrupt. CS flag in SSR negative edge triggers CS interrupt.
8.4.2 Interrupt Identification Register (IIR)
Name IIR Bit 7 CS Bit 6 TX AE Bit 5 RX AF Bit 4 TX EMPTY Bit 3 RX_OF Bit 2 LINK_ DIS Bit 1 LOCK OUT Bit 0 LOCK IN
This is a read only register. When the MCU accesses the IIR, all interrupts freeze. While the MCU access is occurring, the system records the changes in the interrupts but waits until the MCU access is complete before updating the register. A flag is active only when the matching interrupt enable bit is set, and does not depend on the IE bit value. The flags are set by H/W and cleared after the MCU reads the register. Bit 0: This bit reflects the LOCK IN flag interrupt when enabled by IER. This bit reflects the LOCK IN flag interrupt when enabled by IER. LOCK_IN interrupt is invoke whenever a PREAMBLE+NET_ID+NODE_ID where recognized. If NET_ID is disabled, then a received PREAMBLE+ NODE_ID invokes the interrupt. If NODE_ID is disabled, then a received PREAMBLE+ NET_ID invokes the interrupt. If NET_ID and NODE_ID are disabled, then a received PREAMBLE invokes the interrupt. Bit 1: This bit reflects the LOCK OUT flag interrupt when enabled by IER. This bit reflects the LOCK OUT flag interrupt when enabled by IER. LOCK_OUT interrupt is invoked whenever RFW-D100 has finished receiving a packet. The end of the packet is determined according to the packet size. Bit 2: This bit reflects the LINK_DIS flag interrupt when enabled by IER. This interrupt is invoked by the zero counter capacitor discharge mechanism. Bit 3: This bit reflects the RX_OF flag interrupt when enabled by IER. Bit 4: This bit reflects the TX EMPTY flag interrupt when enabled by IER. Bit 5: This bit reflects the RX FIFO AF flag interrupt when enabled by IER. Bit 6: This bit reflects the TX FIFO AE flag interrupt when enabled by IER. Bit 7: CS - when CS flag goes from "1" to "0", an interrupt is invoked.
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8.5 List of BB Register Mapping
Register Address 0 (00000) 1 (00001) 2 (00010) 3 (00011) 4 (00100) 5 (00101) 6 (00110) 7 (00111) 8 (01000) 9 (01001) 10 (01010) 11 (01011) 12 (01100) 13 (01101) 14 (01110) 15 (01111) 16 (10000) 17 (10001) 18 (10010) 19 (10011) 20 (10100) - - - - Write TX_FIFO PRE_L PRE_H FRC_L FRC_H SCR1 SCR2 SCR3 SCR4 LCR BIR NIR PSR PPR BLR CSR IER IIR SSR TFR RFR - - - - Read RX_FIFO - 0xFF 0xFF 0xFF 0xFF 0x00 0x60 0x01 0x00 0x00 0x00 0x00 0x00 0x3A 0x00 0x44 0x00 - 0x04 0x00 0x00 Default Values -
8.6 MCU BB Control Registers
8.6.1 Control Registers List
RFAAR (0x2D): Register R2D indicates WM indirect RAM address. RFDB (0x2E): Register R2E indicates WM indirect RAM data. RFACR (0x2F): Register R2F indicates WM RAM access control.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 RRST Bit 1 RFRD Bit 0 RFWR
RFINTF (0x30): BB interrupt flags.
Bit 7 CSDF Bit 6 TX_AEF Bit 5 RX_AFF Bit 4 TX_ EMPTYF Bit 3 RX_OFF Bit 2 LINK_ DISF Bit 1 Bit 0
LOCK_OU LOCK_ INF TF
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RFINTE (0x99): BB interrupt enable.
Bit 7 CSDE Bit 6 TX_AEE Bit 5 RX_AFE Bit 4 TX_ EMPTYE Bit 3 RX_OFE Bit 2 LINK_ DISE Bit 1 Bit 0
LOCK_OU LOCK_ INE TE
PRIE (0x80): Peripherals enable control.
Bit 7 SPIE Bit 6 Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE
8.6.2 BB Control Example
ORG BC RETI ORG START: BS NOP BC BS MOV MOV ENI 0X0060 RFINTF, TX_EMPTYF // TX_EMPTY INT address // RF data send out, clear INT flag.
0X0100 RFACR, RRST RFACR, RRST PRIE, WME A, #0x10 RFINTE, A // BB reset.
// BB power enable. // BB INT.TX_EMPTY enable. // enable all INT.
RF_TX_INITIAL: WRITE #SCR2, #8 WRITE #BLR, #10 WRITE #PPR, #33 WRITE WRITE WRITE #PSR, #6 #PRE_H, #0xDC #PRE_L, #0xA7
// // // // // // //
Reset TX_FIFO, RX mode. Set bit rate. Set package size to be fixed. Refresh bit mode 1. CRC disabled Set package size to 6. Set preamble High byte value. Set preamble Low byte value.
RF_SEND_DATA: WRITE #TX_FIFO, #0x01 WRITE WRITE WRITE WRITE WRITE READ WRITE WRITE WRITE
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// Write first byte of package to // TX_FIFO.
#TX_FIFO, #TX_FIFO, #TX_FIFO, #TX_FIFO,
#0x02 #0x03 #0x04 #0x05 // // // // // // Write last byte of package to TX_FIFO. Read TFR register data enable TX_EMPTY INT enable all INT. move from RX to TX mode.
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
#TX_FIFO, #0x06 #TFR, 0x60 #IER, #16 #SCR4, #0x03 #SCR2, #1
EM77950
BB Controller
LOOP: JMP
LOOP // BB register write SUB
WRITE_DATA_TO_RF: BC RFACR, RFWR NOP NOP BS RFACR, RFWR RET READ_DATA_FROM_RF: NOP NOP NOP NOP BC RFACR, RFRD NOP NOP NOP NOP NOP MOV NOP NOP NOP BS RET
// BB register read SUB
// Note the access time A, RFDB
RFACR, RFRD
; =============================================== WRITE MACRO#CON1, #CON2 // BB register write MACRO MOV A, #CON2 MOV RFDB, A MOV A, #CON1 MOV RFAAR, A CALL WRITE_DATA_TO_RF ENDM ; =============================================== READMACRO#CON, REG MOV A, #CON MOV RFAAR, A CALL READ_DATA_FROM_RF MOV REG, A ENDM
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// BB register read MACRO
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9
Direction Serial Peripheral Interface (SPI)
9.1 Introduction
The EM77950 communicates with other devices via SPI (Direction Serial Peripheral Interface) module, as shown in Fig. 9-1. To accomplish communication, SPI uses three wire synchronous protocols: Serial Clock, Serial Data Output, and Serial Data. If the EM77950 is a master controller, it sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If the EM77950, however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted on the basis of both the clock rate and the selected edge.
9.2 Features
3-wire, full duplex synchronous transceiver Operation in either Master mode or Slave mode Programmable baud rates of communication Programming clock polarity Programmable data transmission order Interrupt flag available for read buffer full Up to 8 MHz (maximum) bit frequency
9.3 Block Diagram
SDI SDO SCK
Clock Generator
SCK
Clock Generator
Shift Register (SPIS)
SDO
SDI
Shift Register (SPIS)
Read Buffer (SPIRB)
Write Buffer (SPIWB)
Write Buffer (SPIWB)
Read Buffer (SPIRB)
SPI Master
SPI Slave
Fig. 9-1 Typical SPI Transceiver Mode
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9.4 Transceiver Timing
SPIE
SCK CES = 1 SCK CES = 0 SDO SDOD = 0 SDO SDOD = 1 SDI SDID = 0 SDI SDID = 1 RBF
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 6
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 6
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 6
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 6
Fig. 9-2 SPI Transceiver Timing
9.5 Related Registers with SPI
As the SPI mode is defined, the related registers of this operation are shown below: SPIRB (0x1D): Serial peripheral interface read Register SPIWB (0x1E): Serial peripheral interface write Register INTF (0X11): Interrupt flag
Bit 7 ADIF Bit 6 RBFIF Bit 5 PWM1IF Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF
PRIE (0x80): Peripherals enable control
Bit 7 SPIE Bit 6 Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE
INTE (0X81): Interrupt enable control
Bit 7 GIE Bit 6 RBFIE Bit 5 PWM1IE Bit 4 PWM0IE Bit 3 EINT1E Bit 2 EINT0E Bit 1 TCCOE Bit 0 FRCOE
SPIC (0X85): SPI control.
Bit 7 SPI_RBF Bit 6 CES Bit 5 SBR2 Bit 4 SBR1 Bit 3 SBR0 Bit 2 SDID Bit 1 SDOD Bit 0 SPIS
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9.6 Function Description
9.6.1 Block Diagram Description
The following subsections describe the function of each blocks and signals. Fig. 9.2 depicts how the SPI communication is carried out. SDI: Serial Data In SCK: Serial clock SDO: Serial Data Out RBFIF: Set by Buffer Full Detector, and reset by software SPIS: Loads the data in SPIWB register, and begin to shift Shift reg.: Shifting byte out and in. The order is defined by bit SDOD. Both the Shift register and the SPIWB registers are loaded at the same time. Once data are written to, SPIS starts transmission / reception. The received data will be moved to the SPIRB register, as the shifting of the 8-bit data is completed. The RBFIF (Read Buffer Full) flag is equal to 1. SPIRB: Read buffer. The buffer will be updated, as the 8-bit shifting is completed. The data must be read before the next reception is finished. The RBF flag is cleared as the SPIRB register is read. SPIWB: Write buffer. The buffer will deny any write until the 8-bit shifting is completed. The SPIS bit will be kept in 1 if the communication is still undergoing. This flag must be cleared as the shifting is finished. Users can determine if the next write attempt is available. SBR2~SBR0: Programming the clock frequency/rates and sources. Edge Select: Selecting the appropriate clock edges by programming the CES bit.
9.6.2 Signal & Pin Description
The three pins, SDI, SDO, and SCK, which are shown in Fig. 9-1, will be explained in details as follows: SDI: SDI: Serial Data In Serial Data In Receive serially Defined as high-impedance, if not selected.
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Programmed the same clock rate and the same clock edge to latch on both the master device and slave device. The received byte will replace the corresponding transmitted byte. The RBFIF bit will be set, as the SPI operation is completed. Timing is shown in Fig. 9-2. SCK: Serial Clock. Generated by a master device. Synchronize the data communication on both the SDI pin and the SDO pin. The CES used to select the edge to communicate. The SBR0~SBR2 used to determine the baud rate of communication. The ES, SBR0, SBR1, and SBR2 bit have no effect in the slave mode. Timing is shown in Fig. 9-2 SDO: Serial Data Out Transmit serially Programmed the same clock rate and the same clock edge to latch on both the master device and slave device. The received byte will replace the transmitted byte. The SPIS bit will be reset, as the SPI operation is completed. Timing is shown in Fig. 9-2.
10 Analog to Digital Converter (ADC)
The analog-to-digital circuitry consists of one 16-to-1 multiplexer, two control registers (ADCAIS and ADCCR), one data register (ADDATA) and one ADC calculator with 8-bit resolution. The functional block diagram of the ADC is shown in Fig. 10. Port D [7:0] and Port E [7:0] can be selected as either normal digital I/O ports or analog input ports. A maximum of 16 analog input pins can be selected by ADCAIS register [5:3], IMS3 ~IMS0 bits. Control bits, AIPS3 ~ AIPS0, of ADCCR [3:0] are then used to select the ADC input channel that will supply analog signal to ADC calculator. CKR2 ~ CKR0 control bits are used to select the desired conversion rate. The ADC module, then, utilizes successive approximation to convert the unknown analog signal into an 8-bit digital output value. Finally, the 8-bit result is fed to the ADDATA register. If the ADC interrupt is enabled, the ADC interrupt flag will be set to "1" as the analog-to-digital conversion is completed.
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ADCF ADCE ADCD ADCC ADCB ADCA ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Fsco 8-1 MUX Power Down 4 3 IMS[0:2] ADE DATA BUS 3 2 1 0 AIPS[0:3] 2 1 0 7 7 ADIF 6 5 4 3 2 1 0 ADRUN 7 16 -1 Analog Switch
Vref
ADC ( successive approximation )
Start to Convert
5
4 ADE
CKR[0:2]
ADDATA
Fig.10 Analog-to-Digital Conversion Functional Block Diagram
10.1 ADC Control Registers
As the ADC mode is defined, the related registers of this operation are shown below: INTF (0X11): Interrupt flag,
Bit 7 ADIF Bit 6 RBFIF Bit 5 PWM1IF Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF
ADDATA (0x1F): ADC 8-bit data.
Bit 7 ADD7 Bit 6 ADD6 Bit 5 ADD5 Bit 4 ADD4 Bit 3 ADD3 Bit 2 ADD2 Bit 1 ADD1 Bit 0 ADD0
When the A/D conversion is completed, Bit 7 ~ Bit 0 are loaded to the ADDATA [7:0]. The ADCRUN bit is cleared, and the ADIF is set. PRIE (0x80): Peripherals enable control
Bit 7 SPIE Bit 6 Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE
ADCAIS (0x96): ADC analog input pin select and conversion rate select.
Bit 7 Bit 6 Bit 5 IMS2 Bit 4 IMS1 Bit 3 IMS0 Bit 2 CKR2 Bit 1 CKR1 Bit 0 CKR0
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IMS2~IMS0 (Bit 2 ~ Bit 4): ADC configuration definition bit.
IMS ADC 000 001 010 011 100 101 110 111 PTE PTE PTE PTE PTE PTE PTE PTE PTD PTD PTD PTD PTD PTD PTD PTD 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 F A A A A A A A A E A A A A A A A A D D A A A A A A A C D A A A A A A A B D D A A A A A A A D D A A A A A A 9 D D D A A A A A 8 D D D A A A A A 7 D D D D A A A A 6 D D D D A A A A 5 D D D D D A A A 4 D D D D D A A A 3 D D D D D D A A 2 D D D D D D A A 1 D D D D D D D A 0 D D D D D D D A
CKR2~CKR0 (Bit 2 ~ Bit 0): AD conversion Rate control bits.
A/D Conversion Rate CKR2: CKR1: CKR0 000 001 010 011 100 101 110 111 Divided Rate 6MHz Clock Source /2 /4 /8 / 16 / 32 / 64 / 128 / 256 250 125 62.5 31.3 15.6 7.8 3.9 2.0 12MHz Clock Source 500 250 125 62.5 31.3 15.6 7.8 3.9 Unit: kHz 48MHz Clock Source 2000 1000 500 250 125 62.5 31.3 15.6
24MHz Clock Source 1000 500 250 125 62.5 31.3 15.6 7.8
ADCCRR (0x97): ADC configuration register.
Bit 7 ADRUN Bit 6 ADIE Bit 5 Bit 4 Bit 3 AIPS3 Bit 2 SIPA2 Bit 1 AIPS1 Bit 0 AIPS0
AIPS0~AIPS3 (Bits 0~3): Analog Input Select. 0000 = AN0;0001 = AN1; 0010 = AN2;0011 = AN3 0100 = AN4;0101 = AN5; 0110 = AN6;0111 = AN7 1000 = AN8;1001 = AN9; 1010 = ANA;1011 = ANB 1100 = ANC;1101 = AND; 1110 = ANE;1111 = ANF They can only be changed when the ADIF bit and the ADRUN bit are both LOW.
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ADIE (Bit 6): ADC interrupt enable. ADRUN (Bit 7): ADC starts to RUN 0 = reset on completion of the conversion; this bit cannot be reset by software. 1 = an A/D conversion is started; this bit can be set by software.
10.2 Programming Steps/Considerations
Follow these steps to obtain data from the ADC: 1. 2. Set ADC function power on (PRIE.ADE). Write to the three bits (IMS2:IMS0) on the ADCCR register to define the characteristics of PD and PF: Digital I/O, analog channels, and voltage reference pin; 3. Write to the ADCAIS register to configure ADC module: i ii 4. 5. 6. 7. 8. 9. Select ADC input channel (AIPS3: AIPS0) Define ADC conversion clock rate (CKR2: CKR1: CKR0)
Set ADC interrupt enable (ADCCR.ADIE). Include the "ENI" instruction, if the interrupt function is employed. Set the ADRUN bit to 1 to begin sampling. Wait for either the interrupt flag to be set or the ADC interrupt to occur. Read the conversion data register ADDATA. Clear the interrupt flag bit (INTF.ADIF). For next conversion, go to Step 2 or Step 3 as required. At least 2Tct is required before the next acquisition starts.
NOTE To obtain an accurate value, it is necessary to avoid any data transition on the I/O pins during AD conversion.
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11 Dual Pulse Width Modulations (PWM0 and PWM1)
11.1 Overview
The EM77950 has two built-in PWM outputs with 16-bit resolution. Fig.11-1 shows the functional block diagram. A PWM output has a period and a duty cycle, and it keeps the output high. The baud rate of the PWM is the inverse of the period. Fig. 11-2 depicts the relationships between a period and a duty cycle.
PWM0IF
DT0H
DT0L
DT1H
DT1L
PWM1IF
DL0H
DL0L
DL1H
DL1L
Set as compare match
PWM0E S_PWM0
Duty Compare PWM0IE Circuit Q R Data Bus PWM1IE
Duty Compare Circuit
Set as compa re match
PWM1E S_WMP1
PWM0
R
Q
PWM1
S
TMR0HB
TMR0LB
TMR1HB
TMR1LB S
Set as compare match
Period Compare Circuit
Period Compare Circuit
Set as compare match
PRD0H MUX
PRD0L
PRD1H
PRD1L MUX
PWM0E
Fosc/2
PWM1E
Fosc/2
Fig. 11-1 The Functional Block Diagram of the Dual PWM
Period
Period
Period
Duty DUTY = TMR
Duty PRD= TMR
Duty
Fig. 11-2 PWM Output Timing Diagram Product Specification (V1.0) 10.09.2007
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11.2
PWM Control Registers
As the PWM mode is defined, the related registers of this operation are shown below: INTF (0x11): Interrupt flag
Bit 7 ADIF Bit 6 RBFIF Bit 5 PWM1IF Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF
DT0L (0x21): Duty of PWM0 low byte
Bit 7 DT07 Bit 6 DT06 Bit 5 DT05 Bit 4 DT04 Bit 3 DT03 Bit 2 DT02 Bit 1 DT01 Bit 0 DT00
DT0H (0x22): Duty of PWM0 high byte
Bit 7 DT0F Bit 6 DT0E Bit 5 DT0D Bit 4 DT0C Bit 3 DT0B Bit 2 DT0A Bit 1 DT09 Bit 0 DT08
DL0L (0x25): Duty latch of PWM0 low byte
Bit 7 DL07 Bit 6 DL06 Bit 5 DL05 Bit 4 DL04 Bit 3 DL03 Bit 2 DL02 Bit 1 DL01 Bit 0 DL00
DL0H (0x26): Duty latch of PWM0 high byte
Bit 7 DL0F Bit 6 DL0E Bit 5 DL0D Bit 4 DL0C Bit 3 DL0B Bit 2 DL0A Bit 1 DL09 Bit 0 DL08
DT1L (0x27): Duty of PWM1 low byte
Bit 7 DT17 Bit 6 DT16 Bit 5 DT15 Bit 4 DT14 Bit 3 DT13 Bit 2 DT12 Bit 1 DT11 Bit 0 DT10
DT1H (0x28): Duty of PWM1 high byte
Bit 7 DT1F Bit 6 DT1E Bit 5 DT1D Bit 4 DT1C Bit 3 DT1B Bit 2 DT1A Bit 1 DT19 Bit 0 DT18
DL1L (0x2B): Duty latch of PWM1low byte
Bit 7 DL17 Bit 6 DL16 Bit 5 DL15 Bit 4 DL14 Bit 3 DL13 Bit 2 DL12 Bit 1 DL11 Bit 0 DL10
DL2H (0x2C): Duty latch of PWM1 high byte
Bit 7 DL1F Bit 6 DL1E Bit 5 DL1D Bit 4 DL1C Bit 3 DL1B Bit 2 DL1A Bit 1 DL19 Bit 0 DL18
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX can be loaded at any time. However, it cannot be latched into DLX until the current value of DLX is equal to TMRX.
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The following formula describes how to calculate the PWM duty cycle: Duty Cycle = (DTX+1) * (2/Fosc) PRD0L (0x23): Period of PWM0 low byte
Bit 7 PRD07 Bit 6 PRD06 Bit 5 PRD05 Bit 4 PRD04 Bit 3 PRD03 Bit 2 PRD02 Bit 1 PRD01 Bit 0 PRD00
PRD0H (0x24): Period of PWM0 high byte
Bit 7 PRD0F Bit 6 PRD0E Bit 5 PRD0D Bit 4 PRD0C Bit 3 PRD0B Bit 2 PRD0A Bit 1 PRD09 Bit 0 PRD08
PRD1L (0x29): Period of PWM1 low byte
Bit 7 PRD17 Bit 6 PRD16 Bit 5 PRD15 Bit 4 PRD14 Bit 3 PRD13 Bit 2 PRD12 Bit 1 PRD11 Bit 0 PRD10
PRD1H (0x2A): Period of PWM1 high byte
Bit 7 PRD1F Bit 6 PRD1E Bit 5 PRD1D Bit 4 PRD1C Bit 3 PRD1B Bit 2 PRD1A Bit 1 PRD19 Bit 0 PRD18
The PWM period is defined by writing to PRDX. When TMRX is equal to PRDX, the following events occur on the next increment cycle: TMRX is cleared. The PWMX pin is set to 1. The PWMX duty cycle is latched from DTPS to DUTY.
NOTE The PWMX will not be set, if the duty cycle is 0;
The PWMXIF pin is set to 1. The following formula describes how to calculate the PWM period: Period = (PRD +2) * (2/Fosc) The function of PWM must be disabled before a new period being executed. In other word, bit PWMXE has to be reset by advance, if the contents of PRDX are reloaded. PRIE (0x80): Peripherals enable control
Bit 7 SPIE Bit 6 Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE
INTE (0x81): Interrupt enable control
Bit 7 GIE Bit 6 RBFIE Bit 5 PWM1IE Bit 4 PWM0IE Bit 3 EINT1E Bit 2 EINT0E Bit 1 TCCOE Bit 0 FRCOE
PWMCR (0x98): PWM control
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S_PWM1 S_PWM0
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11.3
PWM Programming Procedures/Steps
(1) Load PRDX with the PWMX period. (2) Load DTX with the PWMX Duty Cycle. (3) Enable the interrupt function by setting PWMXIE in the INTE register, if required. (4) Set the PWM pin as output by setting PWMCR.S_PWMX. (5) Enable the PWM function by setting PWMXE bit in the PRIE register. (6) Write the desired new duty to DTX before TMRX is equal to PRDX, then this new DTX will be latched into DLX if various duty cycle is required for the next PWMX operation. (7) Clear PWMXE bit and write the desired new period to PRDX, then enable it again if various periods are required for the next PWMX operation. (8) Clear the PWMXIF before the next operation if interrupt PWMXIE is employed.
12 Interrupts
12.1 Introduction
The EM77950 has 15 interrupt sources. By priority, these interrupts are classified into two levels, namely; peripherals and base band, as described in the following: The interrupt status registers record the interrupt requests in the corresponding control bits in the interrupt control registers. The global interrupt (GIE) is enabled by the ENI instruction and is disabled by the DISI instruction. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. The flags in the Interrupt Status Register are set regardless of the status of their corresponding mask bits or the execution of DISI. Note that the logic AND of an interrupt flag and its corresponding interrupt control bit is 1 which makes the program counter point to the right interrupt vector. Refer to Fig. 12-1. The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). Before the interrupt subroutine is executed, the contents of ACC, SR and ROMPS will be saved by the hardware. After the interrupt service routine is finished, ACC, SR and ROMPS will be pushed back.
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In EM77950, individual interrupt sources have their own interrupt vectors, depicted in the following table:
No 1 2 Mnemonic Mask KWUAE KWUBE EINT0E EINT1E Status KWUAIF KWUBIF EINT0F EINT1F FRCOF TCCOF RBFIF ADCIF PWM0IF PWM1IF CSDF TX_AEF RX_AFF 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0x10 Key Wake up 0x18 External Interrupt 0x20 FRC Overflow 0x28 TCC Overflow Read Buffer Full 0x30 of SPI 0x38 ADC complete PWM period 0x40 complete Carrier sense 0x48 interrupt TX FIFO almost 0x50 empty RX FIFO almost 0x58 full 0x60 TX FIFO empty 0x68 RX FIFO overflow LINK_DIS 0x70 interrupt 0x78 Lock out interrupt 0x80 Lock in interrupt Priority Vector Function Mask Status
Register Bit Register Bit 0x82 0x83 0x81 0x81 0x81 0x81 0x80 0x81 0x99 0x99 0x99 0x99 0x99 0x99 0x99 0x99 3~0 All 2 3 0 1 6 4 4 5 7 6 5 4 3 2 1 0 0x12 013 0x11 0x11 0x11 0x11 0x11 0x11 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 3~0 All 2 3 0 1 6 7 4 5 7 6 5 4 3 2 1 0
3 FRCOE 4 TCCOE 5 RBFIE 6 ADCIE 7 PWM0IE PWM1IE
8 CSDE 9 TX_AEE 10 RX_AFE
11 TX_EMPTY TX_EMPTYF 12 RX_OFE 13 LINK_DIS RX_OFF LINK_DIS
14 LOCK_OUTE LOCK_OUTF 15 LOCK_INE LOCK_INF
The interrupt priority is another useful feature provided by this IC. The latest interrupt, which has the highest priority than the others, will override and hold the currently executed interrupt until the interrupt is finished. Otherwise, the latest interrupt will be in queue right after all its peers.
Global INT Enable Function INT Enable Function INT Flag Function INT Vector Address
Function INT Condition Happened Function Enable
Fig. 12 Block Diagram of Interrupts
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13 Circuitry of Input and Output Pins
13.1 Introduction
The EM77950 has six parallel ports, namely Port A, Port B, Port C, Port D, Port E and Port F. There are 40 available I/O pins. A control bit defines the configuration of its corresponding pin. Refer to Fig. 3.1 for the Pin Assignment. The I/O registers, from Port A to Port F, are bidirectional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOCA, IOCB, IOCD, IOCE and IOCF) under program control. The I/O registers and I/O control registers are both readable and writable.
14 Timer/Counter System
14.1 Introduction
The EM77950 provides two timer modules: 8-bit TCC (Timer Clock/Counter), and 16-bit FRC (Free Run Counter). The clock sources of TCC come from one of the instruction cycles and low frequency oscillator (IRC). The clock source of FRC is from either the instruction cycle or low frequency oscillator (IRC).
14.2
Time Clock Counter (TCC)
An 8-bit counter is available as prescaler for the TCC. The prescaler ratio is determined by the PS0~PS2 bits. When in TCC mode, the prescaler is cleared each time an instruction writes to the TCC. TCC is an 8-bit timer/counter. If the TCC signal source is from the system clock, TCC will be incremented by 1 for every instruction cycle (without prescaler). If the TCC signal source is from the IRC clock input, TCC will be incremented by 1 on every falling edge or rising edge of the TCC pin. The prescaler counter (PRC) can be read from Address 0x0F. In other words, the combination of TCC and PRC can be used as a 16-bit counter without prescaler
14.2.1 Block Diagram of TCC
TCCS0 TCCE Data Bus
Fosc
0 M U X PRC (8- bit Counter) Sync with Internal Clock 2 clocks delay TCCOF TCC
IRC
1
PS0
PS1
PS2
8-1 MUX
Fig. 14-1 Function Block Diagram of TCC 80 * Product Specification (V1.0) 10.09.2007
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14.2.2 TCC Control Registers
As the TCC mode is defined, the related registers involved in this operation are shown below: PRC (0x0F): Prescale counter. TCC (0x10): Timer clock/counter. INTF (0x11): Interrupt flag.
Bit 7 ADIF Bit 6 RBFIF Bit 5 PWM1IF Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF
PRIE (0x80): Peripherals enable control
Bit 7 SPIE Bit 6 Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE
INTE (0x81): Interrupt enable control
Bit 7 GIE Bit 6 RBFIE Bit 5 PWM1IE Bit 4 PWM0IE Bit 3 EINT1E Bit 2 EINT0E Bit 1 TCCOE Bit 0 FRCOE
TCCC (0x93): Timer clock/counter control.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TCCS0 Bit 2 PS2 Bit 1 PS1 Bit 0 PS0
14.2.3 TCC Programming Procedures/Steps
(1) Load TCCC with the prescaler and TCC clock source. (2) Load TCC with the TCC overflow period. (3) Enable the interrupt function by setting TCCOE in the INTE register, if required. (4) Enable the TCC function by setting the TCCE bit in the PRIE register. (5) Wait for either the interrupt flag to be set (TCCOF) or the TCC interrupt to occur. (6) The following formula describes how to calculate the TCC overflow period:
1 TCC Timer = (0 x100 - TCC ) x Pr escaler ClockSource
where Clock Source = Fosc or IRC
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14.3
Free Run Counter
Dual 8-bit counters, high byte register and low byte register, make up the 16-bit software programmable counter. The driving clock source is either the system clock divided by 2 or the low frequency oscillator. A read of the low byte register allows full control of the corresponding timer function. On the contrary, accessing a high byte register will inhibit the specific timer function until the corresponding low byte is read as well.
14.3.1 Block Diagram of FRC
FRCE FRCCS
Fosc
0 M U X Sync with Internal Clock
L FRF
HFRC
FRCOF
IRC
1
L FRFB
Data Bus
Fig. 14-2 Function Block Diagram of Timer 1
14.3.2 FRC Control Registers
As the FRC mode is defined, the related registers of this operation are shown below: INTF (0x11): Interrupt flag.
Bit 7 ADIF Bit 6 RBFIF Bit 5 PWM1IF Bit 4 PWM0IF Bit 3 EINT1F Bit 2 EINT0F Bit 1 TCCOF Bit 0 FRCOF
LFRC (0x1A): Least significant byte of 16-bit free run counter. HFRC (0x1B): Most significant byte of 16-bit free run counter. LFRCB (0x1C): Least significant byte buffer of 16-bit free run counter. PRIE (0x80): Peripherals enable control
Bit 7 SPIE Bit 6 Bit 5 BBE Bit 4 ADE Bit 3 PWM1E Bit 2 PWM0E Bit 1 TCCE Bit 0 FRCE
INTE (0x81): Interrupt enable control
Bit 7 GIE Bit 6 RBFIE Bit 5 PWM1IE Bit 4 PWM0IE Bit 3 EINT1E Bit 2 EINT0E Bit 1 TCCOE Bit 0 FRCOE
FRCC (0x94): Free run counter control.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PPSCL2 Bit 2 PPSCL1 Bit 1 PPSCL0 Bit 0 FRCCS
OSCO2E OSCO2SL1 OSCO2SL0
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14.3.3 FRC Programming Procedures/Steps
(1) Load LFRCB with the FRC overflow period low byte. (2) Load HFRC with the TCC overflow period high byte. Then LFRC will load with the LFRCB automatically. (3) Enable interrupt function by setting FRCOE in the INTE register, if required. (4) Enable FRC function by setting FRCE bit in the PRIE register. (5) Wait for either the interrupt flag to be set (FRCOF) or the FRC interrupt to occur. (6) An access of low byte of a 16-bit counter receives the count value at the moment of the read. However, the contents of low byte will transfer to the buffer, the LFRCB register, if a high byte is read first. The value in the LFRCB register remains unchanged until the corresponding low byte is read. (7) The following formula describes how to calculate the FRC overflow period:
FRC Timer = 0 x10000 - HFRC : LFRC
(
)x
1 ClockSource
where Clock Source = Fosc or IRC
15 Reset and Wake up
15.1 Reset
A reset can be caused by one of the following: (1) Power-on reset (2) /RESET pin input "low", or (3) Watchdog timer time-out (if enabled) The device will remain in a reset condition for a period of 8-bit external RC ripple counter (one oscillator start-up timer period) after the reset is detected. The initial Address is 000h.
15.2
The Status of RST, T, and P of the STATUS Register
A reset condition can be caused by the following events: (1) A power-on condition (external); (2) A high-low-high pulse on the /RESET pin (external); and (3) Watchdog timer time-out (internal). The values of bits RST, T and P, listed in Table 17.1 can be used to check how the processor wakes up.
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Table 17.1 Values of RST, T and P after a reset
Condition Power on WDTC instruction WDT timeout SLEP instruction Wake-Up on pin change during SLEEP mode RST 0 *P *P *P 1 T 1 1 0 *P 1 P 1 *P *P 0 0
*P: Previous status before reset
15.3
System Set-up Time (SST)
In order to have a successful start up, System Set-up Time (SSU) is employed to guarantee a stable clock for IC operation. It is made up of two delay sources: (1) Internal RC Oscillation Set-up Delay (IRCOSUD): Internal RC oscillation shared with a watchdog timer divided by an 8-bit ripple counter. (2) Main Oscillation Set-up Delay (MOSUD): A 10-bit ripple counter is used to filter unstable main clocks at the beginning of power-on before the chip starts to run. This delay is performed right after IRCOSUD, if enabled
1 1 8 10 SST = x2 + Main Clock x 2 32.768 K
OSC1
10 -
bit Ripple Counter
SST
8-
bit Ripple Counter
Internal RC Osc .
RCSUTE
Fig. 15 System Set-up Time
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15.4
Wake-up Procedure on Power-on Reset
Power-on Voltage Detector (POVD) will allow the VDD whose value is over the default threshold voltage (2.0 V for the EM77950) to enter the IC, and the SST delay starts. The following three cases may be taken into consideration: (1) /RESET pin goes high with VDD at the same time. In hardware, this pin and VDD are tied together. The internal reset will remain low until the SST delay is over. (2) /RESET pin goes high during the SST delay. It is similar to Case 1. The IC will start to operate when the SST delay is over. /RESET pin goes high after an SST delay. The EM77950 will start program execution immediately
16 Oscillators
16.1 Introduction
The EM77950 provides three main oscillators: One high frequency crystal oscillator (connected to OSCI and OSCO), internal RC, and four PLL (Phase Lock Loop) outputs. Versatile combinations of oscillation are provided for a wide range of applications. On-chip clock sources can be either dual clocks or single clock.
16.2
Clock Signal Distribution
RF-BB 8 bit ADC SPI 16 bit PWM
SYS_CLK 0/1=0 & RF_CLK 0/1=0 BYP 6 MHz PLL 6 12 24 48 SYS_CLK 0/1 RF_CLK 0/1 SR.GREEN SYS_NCLK
PD (Power Down)
MCU Kernel
SYS_ICLK
IRC CLK
TCCC.TCCS0
FRCC.FRCCS
WDT
8 bit TCC
16 bit FRC
Fig. 16 Clock Tours
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16.3
PLL Oscillator
The Phase-locked loop (PLL) technology is employed to produce four different frequencies: 6 MHz, 12MHz, 24MHz and 48 MHz (external 6MHz crystal). Setting the SYS_CLK bits can select the system clock source. PLL is enabled except when entering Green and Sleep mode.
16.4
Selected PLL Oscillation out
As shown in register FRCC (0x94), EM77950 can output the selected PLL frequency divided by the prescaler. Once the pin is enabled as a PLL clock out, the output frequency can be implemented by the peripherals of the chip. If disabled, this pin is used as pin PF0, a general purpose I/O pin.
17 Low-Power Mode
17.1 Introduction
The EM77950 has two power-saving modes, green mode and sleep mode. Figure 17 shows the mode change diagram.
Power On
Normal
1. Key Wake-up 2. WDT Time out 3. /Reset
WDTC[7].Green=0 SLEP INST. Key Wake up 1. WDTC[7].Green=1 2. WDT Time out 3. /Reset
Green
SLEP INST.
Sleep
Fig. 17 Three-Mode State
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17.2
Green Mode
The "GREEN" bit of WDTC [7] register is the only control bit used for mode switching between normal mode and green mode. Its initial value is "0", normal mode. When "GREEN" bit is written with a 1, the MCU will switch to green mode from normal mode. In contrast, the MCU will go back to normal mode when the "GREEN" bit is written from 1 to 0. During green mode, the main oscillator and PLL will be turned off. The MCU and all the peripherals are driven by the internal RC oscillator - IRC. Once BB peripheral is functional and then switched into green mode, the clock source of all other peripherals, except PLL, will be provided by IRC. PLL will keep running as BB circuit's clock source.
17.3
Sleep Mode
The execution of "SLEP" instruction will turn the whole chip into Sleep mode. The main clock will be shut down. The IRC oscillator is halted also if the watchdog function is disabled. All registers, memory and I/O port remain in their previous states during sleep mode. The overflow of the watchdog timer driven by IRC will generate a reset to resume normal operation. Key Wake up (KWU) interrupt and /RESET pin are other methods to exit sleep mode. It is essential to wait for stable Oscillation start-up time before normal operation. The stabilizing time is SST.
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18 Instruction Description
18.1 Instruction Set Summary
Type 0000 0000 0000 System Control 0000 0000 0000 0000 0000 1010 1010 1010 Table Look up 0000 0000 0000 0011 1010 0000 0000 0000 0000 0000 0000 0000 0000 0000 Logic 0000 0000 1011 1011 1011 1011 0101 0101 Binary Instruction 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0000 0000 0000 1101 1011 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 00kk 01kk 10kk 11kk 10kk 11kk 0000 0000 0000 0000 0000 0000 0000 0000 rrrr rrrr rrrr 0000 0000 0000 0000 kkkk rrrr rrrr kkkk Rrrr Rrrr kkkk Rrrr rrrr kkkk rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 0000 0001 0010 0011 0100 0101 0110 0111 rrrr rrrr rrrr 1010 1011 1100 0010 kkkk rrrr rrrr kkkk rrrr rrrr kkkk rrrr rrrr kkkk rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr Mnemonic NOP WDTC RET RETI SLEP ENI DISI DAA TBRDP r TBRD r TBRDM r TBRDP A TBRD A TBRDM A TBL RETL #k OR A, r OR r, A OR A, #k AND A, r AND r, A AND A, #k XOR A, r XOR r, A XOR A, #k COMA r COM r RRCA r, #k RRC r, #k RLCA r, #k RLC r, #k SHRA r, #k SHLA r, #k Operation No operation WDT 0 PC (Top of Stack) PC (Top of Stack); Enable Interrupt WDT 0 Stop oscillator Enable Interrupt Disable Interrupt Decimal Adjust A r ROM[(TABPT[15:1])] TABPT TABPT+1 r ROM[(TABPT[15:1])] r ROM[(TABPT[15:1])] TABPT TABPT-1 A ROM[(TABPT[15:1])] TABPT TABPT+1 A ROM[(TABPT[15:1])] A ROM[(TABPT[15:1])] TABPT TABPT-1 R2 R2+A Ak PC [Top of Stack] A A .or. r r r .or. A A A .or. k A A .and. r r r .and. A A A .and. k A A .xor. r r r .xor. A A A .xor. k A /r r /r [C,r] rotate right k bits to [C,A] [C,r] rotate right k bits to [C,r] [C,r] rotate left k bits to [C,A] [C,r] rotate left k bits to [C,r] [C,r] shift right k bits to A Insert C into high order bits [C,r] shift left k bits to A Insert C into low order bits Status Cycles Affected None None None None None None None C None None None None None None C, DC, Z None Z Z Z Z Z Z Z Z Z Z Z C C C C None None 1 1 1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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EM77950
BB Controller
Type 0001 xxaa 0001 xxaa Compare Branch 0101 xxaa 0101 xxaa 0101 xxaa 0101 xxaa 0010 0010 0011 0011 Process 0011 1010 0000 1010 0011 0011 0011 0100 Arithmetic 0100 0100 0100 0100 0101 0101 1010 1010 Move 0110 1010 110a Branch 111a Bank Page 1010 1010
Binary Instruction 0bbb aaaa 1bbb aaaa 0010 aaaa 0011 aaaa 0100 aaaa 0101 aaaa 0bbb 1bbb 0bbb 1000 1001 1100 0000 1111 1100 1101 1110 0010 0011 0100 1110 1111 0000 0001 1000 1001 rrrr aaaa rrrr aaaa rrrr aaaa rrrr aaaa rrrr aaaa rrrr aaaa rrrr rrrr rrrr rrrr rrrr rrrr 0000 rrrr rrrr rrrr kkkk rrrr rrrr kkkk rrrr rrrr rrrr rrrr rrrr rrrr rrrr aaaa rrrr aaaa rrrr aaaa rrrr aaaa rrrr aaaa rrrr aaaa rrrr rrrr rrrr rrrr rrrr rrrr 1101 rrrr rrrr rrrr kkkk rrrr rrrr kkkk rrrr rrrr rrrr rrrr rrrr rrrr
Mnemonic JBC r,b,addr JBS r,b,addr
Operation If r(b)=0, jump to addr If r(b)=1, jump to addr
Status Cycles Affected None None None None None None None None None None None Z None Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z Z None None None None None None None 2/3 2/3 2/3 2/3 2/3 2/3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DJZA r,addr A r-1, jump to addr if zero DJZ r,addr JZA r,addr JZ r,addr BC r,b BS r,b BTG r,b SWAP r SWAPA r ZCHK r RPT CLR r ADD A,r ADD r,A ADD A,#k SUB A,r SUB r,A SUB A,#k INCA r INC r DECA r DEC r MOV A,r MOV r,A MOVRR r1, r2 MOV A,#k JMP addr CALL addr BANK #k PAGE #k r r-1, jump to addr if zero Ar+1, jump to addr if zero r r+1, jump to addr if zero r(b) 0 r(b) 1 r(b) /r(b) r(0:3) r(4:7) A(4:7) r(0:3) A(0:3) r(4:7) Z 0 if r < > 0 Z 1 if r = 0 Single repeat CS times on next TBRD instruction r0 A A+r r r+A A A+k A r-A f r-A A k-A A r+1 r r+1 A r-1 r r-1 Ar r A Register r1 Register r2 Ak PC addr PC[13..16] unchange [Top of Stack] PC + 1 PC addr PC [13..16] unchange R4(RAMBS0) k (0~6) R5(PAGES) k (0~1)
r2 r2 r2 r2 r2 r1 r1 r1 r1 r2 r1 r1 0111 aaaa aaaa 1110 1101 kkkk aaaa aaaa 0000 0000 kkkk aaaa aaaa 0kkk 000k
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
* 89
EM77950
BB Controller
19 Electrical Specification
19.1 Absolute Maximum Ratings
Temperature under Bias Storage temperature Input voltage Output voltage 0C -65C -0.3V -0.3V to to to to 70C 150C +3.6V +3.6V
19.2
DC Electrical Characteristic
Ta=0C ~ 70 C, VDD=3.3V5%, VSS=0V
Symbol Fxt IIL VIH VIL VIHT VILT VIHX VILX Parameter Condition Min DC -
0.8xVDD
Typ - - - - - - - - -
Max 48.0 2 -
0.2xVDD
Unit MHz A V V V V V V V
Crystal: VDD ~ 2.75V One cycle with one clock Input Leakage VIN = VDD, VSS Current for input pins Input High Voltage Input Low Voltage Port A ~ Port F Port A ~ Port F
VSS 2.0 - 2.5 - 2.4
Input High Threshold /RST Voltage Input Low Threshold /RST Voltage Clock Input High Voltage Clock Input Low Voltage OSCI, OSCO OSCI, OSCO
- 0.8 - 1.0 -
Output High Voltage: VOH1 PTA, PTC, PTD, IOH = -8.0 mA PTE, PTF Output High Voltage: VOH2 PTB; IOH = -8.0 mA RFIO VOL1 VOL2 IPH ISB ISB Output Low Voltage: IOL = 8.0 mA PTA, PTC, PTD, PTE, PTF Output Low Voltage: IOL = 8.0 mA PTB; RFIO Pull-high current Pull-high active, input pin at VSS
2.4
-
-
V
- - - - -
- - -6.5 - -
0.4 0.4 - 2 1
V V A A A
All input and I/O pins at VDD, Power down current Output pin floating, WDT enabled. All input and I/O pins at VDD, Power down current Output pin floating, WDT and all peripherals disabled. Operating supply current (VDD = 3.3V) Operating supply current (VDD = 3.3V) /RESET = 'High', Fosc = 32kHz (RC type), Output pin floating, WDT and all peripherals disabled. /RESET= 'High', Fosc = 6MHz (Crystal type), Output pin floating, and all peripherals disabled.
ICC1
-
60
-
A
ICC3
-
5
-
mA
90 *
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
EM77950
BB Controller
19.3
Voltage Detector Electrical Characteristic
Ta=25C
Symbol Vdet Vrel Iss Vop Vdet/Ta Parameter Detect voltage Release voltage Current consumption Operating voltage Vdet Temperature characteristic Condition - - VDD = 3V - 0C Ta 70C Min 1.8 - - 0.7* - Typ 2.0
Vdet x 1.05
Max 2.2 - 0.8 3.5 -2
Unit V V A V
MV/C
- - -
* When the VDD voltage rises between Vop=0.7V and Vdet, the voltage detector output must be "Low".
19.4
AC Electrical Characteristic
19.4.1 MCU
Ta=0C ~ 70 C, VDD=3.3 V5%, VSS=0V Ta=0C ~ 70 C, VDD=3.3 V5%, VSS=0V
Symbol Dclk Tins Ttcc Tdrh Trst Twdt Tset Thold Tdelay Parameter Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input period Device reset hold time /RESET pulse width Watchdog timer period Input pin setup time Input pin hold time Output pin delay time Conditions - Crystal type RC type - Ta = 25C Ta = 25C Ta = 25C - - Cload=20pF Min 45 125 500
(Tins+20)/N*
Typ 50 - - 18 - 18 0 20 50
Max 55 DC DC - 30 - 30 - - -
Unit % ns ns ns ms ns ms ms ms ms
9 2000 9 - - -
* N= selected prescaler ratio.
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
* 91
EM77950
BB Controller
19.4.2 BB
Ta=0C ~ 70 C, VDD=3.3 V5%, VSS=0V
Symbol 1/tOSC tRDPW tCSRD tADRD tRDDV tRHDT tDHAR tRHDT tRDAN Parameter Oscillator frequency RD pulse width CS low to RD low Address valid for RD low RD low to Data valid Data float after RD. Data hold after RD Time between consecutive RD pulses Address valid after RD low Min 0.1 3*tOSC+ tOSC 0 - - 0 2*tOSC 3*tOSC+ Max 24 - - - 3*tOSC+ tOSC - - - Unit MHz ns ns ns ns ns ns ns ns
>0 will be determined according to cell library simulation. The values above were determined according to behavioral simulations. They take into account only the BB digital state-machine. Thus, such values are for reference only.
92 *
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
1
2
3
4
5
6
VCC RV1 3 2 1 3 2 1 JSR_BL JoyStick Right R21 24K VCC VCC R23 1K5 Joy Stick Right1 Joy Stick Left1 R34 1K5 VCC RV2B VCC RV1B Joy Stick Right2 Joy Stick Left2 TR1 MTR_VCCPWR_VCC 2 V_IN V_OUT 1 APL5883 VCC R32 1K5 R30 1K5 R28 1K5 R22 1.5K R20 1.5K R18 1.5K R16 1.5K RV2C VCC RV1C 1K5 1K5 1K5 R26 R25 R24 VCC D R19 24K R17 24K R15 24K JoyStick_Left R33 24K R31 24K R29 24K R27 24K JSR_BR
CN1
CN2
VCC
RV2
D
+ 1uF 3 100nf SW1 PD PD PD PD PD 5 6 C 8 VCC SW DIP VCC 2 3 4 R1 R R9 7 8 9 10 TR2 11 C? 0.1 C11 100nF TR1 8051 Low Power CN7 TX/RX RSSI CN2 B D4148 C4 100nF SW1 S_MTR SELECT SW2 R11 START 1K R10 TR5 100K 8051 R7 1R ANALOG SW3 VCC 2 1 D1 JSR_BR JSR_BL RFIO RF_ACT GND VCC 1 2 3 4 5 6 RF Module Connector 7 6 5 4 3 2 1 0 0 R4 R MTR_VCC P C 1 /S D O 26 P C 0 /S D I 25 DV SS 24 R F IO 23 TX R X 22 RF_ ACT 21 P B 7 /K W U 20 P B 6 /K W U 19 P B 5 /P W M 18 P B 4 /K W U 17 P B 3 /K W U 16 P B 2 /K W U 15 P B 1 /K W U 14 P B 0 /K W U 13 P A 7/P W M 12 PA6 PC2/SDO 27 R12 100K 8051 PA5 PC3/INT0 PA4 28 R13 0.1 PC4/INT1 1K /RST 29 PC5/PWM1 PA3/KWUB 30 TR4 8051 PLCC 31 R3 Low Power 1M 22M PA2/KWUA C9 OSCO1 2.2M VCC 6 ET44R510 EM77950 32 PA1/KWU9 OSCI R2 5 PA0/KWU8 33 AVSS C5 D4148 100nF DVDD 34 22pF D2 1 2 S_MTR PD0/ADC0 AVDD 35 C7 PD1/ADC1 36 PF1 6Mhz CN2 PD2/ADC2 1 1M 37 R14 1 Y1 7 2 3 MTR_VCC 4 JP1 C8 22pF 10uF C3
GN D VCC
Product Specification (V1.0) 10.09.2007
20 Application Circuit
C1
+
C2
3/A D C 3 38 4/A D C 4 39 5/A D C 5 40 6/A D C 6 41 7/A D C 7 42 V re f 43 P E 0/A D C 8 44 P E 1/A D C 9 45 P E 2/A D C A 46 P E 3/A D C B 47 P E 4/A D C C 48 P E 5/A D C D 49 P E 6/A D C E 50 P E 7/A D C F 51 P F 0 /O S C O 2 52
(This specification is subject to change without further notice)
C B 220nH L1 10uF C24 10uF C25 C26 1uF A Title ET44R510 Wireless Joystick demo Size B Date: File: 1 2 3 4 5 20-Aug-2003 Sheet of D:\Documents and Settings\Administrator\My Documents\MCU_Line\keep data\demo boa Drawn By: 6 Number Revision A
EM77950
BB Controller
* 93
Formatted: Font: 3 pt, Font color: Dark Blue
EM77950
BB Controller
APPENDIX A Package Type
ET NO EM77950A EM77950B Package Type QFP52 QFP44 Pin count 52 44 Package Size 14x20MM 10x10MM
B Package Information
94 *
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)

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