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merging Memory & Logic Solutions Inc.
Document Title
64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
EM610FV16 Series
Low Power, 64Kx16 SRAM
Revision History
Revision No.
0.0 0.1
History
Initial Draft 2'nd Draft Add Pb-free part number
Draft Date
May 9 , 2003 February 13 , 2004
Remark
Emerging Memory & Logic Solutions Inc.
IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160 Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1
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FEATURES
* * * * * * Process Technology : 0.18m Full CMOS Organization : 64K x 16 bit Power Supply Voltage : 2.7V ~ 3.6V Low Data Retention Voltage : 1.5V(Min.) Three state output and TTL Compatible Package Type : 48-FPBGA 6.0x7.0
EM610FV16 Series
Low Power, 64Kx16 SRAM
GENERAL DESCRIPTION
The EM610FV16 families are fabricated by EMLSI's advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family EM610FV16 Operating Temperature Industrial (-40 ~ 85oC) Vcc Range Speed Standby (I SB1 , Typ.) 0.5A2) Operating (I CC1.Max.) 3 mA PKG Type
2.7V~3.6V
551) /70ns
48-FPBGA
1. The parameter is measured with 30pF test load. 2. Typical values are measured at Vcc=3.3V, T A =25 oC and not 100% tested.
PIN DESCRIPTION
1 A B C D E F G H 2 3 4 5 6
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
LB I/O 9
OE UB
A0 A3 A5 DNU
A1 A4 A6 A7
A2 CS1 I/O2 I/O4 I/O5 I/O6 WE A11
CS2 I/O1 I/O3 VCC V SS I/O7 I/O8 DNU
A A11 10 A 12 A13 A14 A15
Row S elect
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
VC C VSS
Memory Array 1024 x 1024
I/O10 I/O11 V SS VC C I/O12 I/O13
DNU DNU A14 A12 A9 A15 A13 A10
I/O1 ~ I/O8 I/O9 ~ I/O16
Data Cont Data Cont
I/O Circuit Column Select
I/O15 I/O14 I/O16 DNU DNU A8
48-FPBGA : Top view (ball down)
W E O E UB LB
Control Logic
Name CS 1 ,CS 2 OE WE A 0 ~A15
Function Chip select inputs Output Enable input Write Enable input Address Inputs
Name Vcc Vss UB LB DNU
Function Power Supply Ground Upper Byte (I/O 9~16) Lower Byte (I/O 1~8 ) Do Not Use
CS 1 CS 2
I/O1 ~I/O16 Data Inputs/outputs
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ABSOLUTE MAXIMUM RATINGS * Parameter
Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature
EM610FV16 Series
Low Power, 64Kx16 SRAM
Symbol
VIN , VOUT VCC PD TA
Ratings
-0.2 to Vcc+0.3(Max. 4.0V) -0.2 to 4.0V 1.0 -40 to 85
Unit
V V W
oC
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS1 H X X L L L L L L L L CS 2 X L X H H H H H H H H OE X X X H H L L L X X X WE X X X H H H H H L L L LB X X H L X L H L L H L UB X X H X L H L L H L L I/O 1-8 High-Z High-Z High-Z High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In I/O9-16 High-Z High-Z High-Z High-Z High-Z High-Z Data Out Data Out High-Z Data In Data In Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Stand by Stand by Stand by Active Active Active Active Active Active Active Active
Note: X means don't care. (Must be low or high state)
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RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter Supply voltage Ground Input high voltage Input low voltage
1. 2. 3. 4.
EM610FV16 Series
Low Power, 64Kx16 SRAM
Symbol VCC VSS VIH VIL
Min 2.7 0 2.2 -0.23)
Typ 3.3 0 -
Max 3.6 0 VCC + 0.22) 0.6
Unit V V V V
TA= -40 to 85o C, otherwise specified Overshoot: VCC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE 1) (f =1MHz, TA=25oC)
Item Input capacitance Input/Ouput capacitance
1. Capacitance is sampled, not 100% tested
Symbol C IN CIO
Test Condition VIN=0V VIO =0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Parameter Input leakage current Output leakage current Operating power supply Symbol I LI ILO I CC ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current (TTL) VOL VOH ISB
V IN =VSS to VCC CS 1=V I H or CS 2 =V IL or OE=V IH or WE=V IL or LB=UB = VIH V IO =VSS to V CC IIO =0mA, CS 1=V IL , CS 2= WE= VIH , VI N=V I H or V IL Cycle time=1s, 100% duty, IIO=0mA, CS 1< 0.2V, LB <0.2V or/and UB <0.2V, CS 2>V CC-0.2V, V IN< 0.2V or VIN >V CC-0.2V Cycle time = Min, I IO =0mA, 100% duty, CS 1=V IL, CS 2=V IH, LB=VIL or/and UB=V IL , V IN=V IL or VI H IOL = 2.1mA IO H = -1.0mA CS 1=V I H, CS 2 = VIL , Other inputs=V I H or V IL CS 1> V C C-0.2V, CS 2 >V CC -0.2V (CS1 controlled)
Test Conditions
Min -1 -1 55ns 70ns 2.4 -
Typ -
Max 1 1 3 3 26 20 0.4 0.3
Unit A A mA mA
mA V V mA
Standby Current (CMOS)
I SB1
or 0V< CS2 <0.2V (CS 2 controlled), Other inputs = 0~VCC (Typ. condition : V CC=3.3V @ 25 o C) o
LL LF
-
0.5 1)
5
A
(Max. condition : VCC=3.6V @ 85 C)
NOTES
1. Typical values are measured at Vcc=3.3V, T A=25o C and not 100% tested. 4
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AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.4 to 2.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL = 100pF+ 1 TTL CL 1) = 30pF + 1 TTL 1. Including scope and Jig capacitance 2. R1 =3070, R 2 =3150 3. VTM=2.8V
EM610FV16 Series
Low Power, 64Kx16 SRAM
VTM 3) R12)
CL1)
R22)
READ CYCLE (V cc =2.7 to 3.6V, Gnd = 0V, T A = -40oC to +85oC)
Parameter
Read cycle time Address access time Chip select to output Output enable to valid output UB, LB acess time Chip select to low-Z output UB, LB enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB, LB disable to high-Z output Output disable to high-Z output Output hold from address change
Symbol
tRC tAA tco1, tco2 tO E tBA tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tOH
55ns Min 55 Max 55 55 25 55 10 10 5 0 0 0 10 20 20 20 10 10 5 0 0 0 10 Min 70 -
70ns Max 70 70 35 70 25 25 25 -
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Write cycle time Chip select to end of write Address setup time Address valid to end of write UB, LB valid to end of write Write pulse width Write recovery time Write to ouput high-Z Data to write time overlap Data hold from write time End write to output low-Z
Symbol
tWC tCW1, tCW2 tAs tAW tBW tWP tWR tWHZ tDW tDH tOW
55ns Min 55 45 0 45 45 40 0 0 25 0 5 Max 20 Min 70 60 0 60 60 50 0 0 30 0 5
70ns Max 20
Unit
ns ns ns ns ns ns ns ns ns ns ns
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TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1).
EM610FV16 Series
Low Power, 64Kx16 SRAM
(Address Controlled, CS1=OE=VIL, CS2= WE=V IH, UB or/and LB= VI L)
tRC Address tAA tOH Data Out
Previous Data Valid Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC Address tAA CS1 tCO tOH
CS2 tBA UB,LB tO E OE tOLZ Data Out High-Z
Data Valid
tHZ
tBHZ
tOHZ
tBLZ tLZ
NOTES (READ CYCLE) 1. t HZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels. 2. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ(Min.) both for a given device and from device to device interconnection.
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TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC Address tCW (2) CS1
EM610FV16 Series
Low Power, 64Kx16 SRAM
tWR (4)
CS2 tAW tBW UB ,LB tWP (1) WE tAS(3) Data in High-Z
Data Valid
tDW
tDH High-Z tOW
tWHZ Data out Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
tWC Address tAS(3) CS1 tCW (2) tWR(4)
CS2 tAW tBW UB,LB tWP (1) WE tDW Data in
Data Valid
tDH
Data out
High-Z
High-Z
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TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
EM610FV16 Series
Low Power, 64Kx16 SRAM
tWC Address tCW(2) CS1 tW R(4)
CS2 tA W tB W UB ,LB tA S(3) WE tDW Data in Data out High-Z
Data Valid
tW P(1)
tDH
High-Z
NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP ) of low CS1 and low WE. A write begins when CS 1 goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. t CW is measured from the CS1 going low to end of write. 3. t A S is measured from the address valid to the beginning of write. 4. t WR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high.
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DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time NOTES
EM610FV16 Series
Low Power, 64Kx16 SRAM
Symbol
VDR I DR tSDR tRDR
Test Condition
ISB1 Test Condition (Chip Disabled)
1)
Min
1.5 0
Typ2)
0.25 -
Max
3.6 -
Unit
V A
VCC =1.5V, I SB1 Test Condition (Chip Disabled) 1) See data retention wave form
ns tRC -
1. See the IS B 1 measurement condition of datasheet page 4. 2.Typical values are measured at T A=25o C and not 100% tested.
DATA RETENTION WAVE FORM
tSDR Vcc 2.7V
Data Retention Mode
tRDR
2.2V VDR
CS 1 > Vcc-0.2V
CS 1 GND Vcc 2.7V CS 2 tSDR
Data Retention Mode
tRDR
VDR 0.4V
CS2 < 0.2V
GND
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EM610FV16 Series
Low Power, 64Kx16 SRAM
Unit: millimeters
PACKAGE DIMENSION
48 Ball Fine Pitch BGA (0.75mm ball pitch) Top View
B
Bottom View
A1 index Mark
B B1 6 A B C 5 4 3 21
0.5 0.5 Y C1 C B/2
#A1
C
D E C1/2 F G H
Side View
0.26 E2 D
0.25 Typ.
Detail A
A
E E1
Min A B B1 C C1 D E E1 E2 Y 5.93 6.93 0.30 1.00 -
Typ 0.75 6.00 3.75 7.00 5.25 0.35 1.04 0.79 0.25 -
Max 6.03 7.03 0.40 1.10 0.08
NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75x0.75) (typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max)
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0.79 Typ.
C
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MEMORY FUNCTION GUIDE
EM610FV16 Series
Low Power, 64Kx16 SRAM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory 2. Device Type 3. Density 4. Option 5. Technology 6. Operating Voltage
1. Memory Component 2. Device Type 6 ------------------------ Low Power SRAM 7 ------------------------ STRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 16 ----------------------- 16M 32 ----------------------- 32M 64 ----------------------- 64M 4. Option 0 ----------------------- Dual CS 1 ----------------------- Single CS 5. Technology Blank ------------------ CMOS F ------------------------ Full CMOS 6. Operating Voltage Blank ------------------ 5.0V V ------------------------- 2.7V~3.6V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 7. Orginzation 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 11
11. Power 10. Speed
9. Packages 8. Version 7. Orgainzation
8. Version Blank ----------------- Mother Die A ----------------------- First revision B ----------------------- Second revision C ----------------------- Third revision D ----------------------- Fourth revision 9. Package Blank ---------------------- FPBGA S ---------------------------- 32 sTSOP1 T ---------------------------- 32 TSOP1 U ---------------------------- 44 TSOP2 W ---------------------------- Wafer 10. Speed 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 10 --------------------- 100ns 12 --------------------- 120ns 11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power (Pb-free) L ---------------------- Low Power S ---------------------- Standard Power

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