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| Preliminary EM7323SU16H 2Mx16 Async. / Page StRAM Document Title 2M x 16Bit Asynchronous / Page Mode StRAM Revision History Revision No. 0.0 History Initial Draft Draft Date Oct. 23 , 2007 Remark Preliminary Emerging Memory & Logic Solutions Inc. 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Zip Code : 690-717 The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 Rev. 0.0 Preliminary EM7323SU16H 2Mx16 Async. / Page StRAM 2M x16 Bit Async./Page StRAM FEATURES - Single power supply voltage of 2.6 to 3.3V - Direct TTL compativility for all inputs and outputs. - Deep power-down mode : Memory cell data invalid. - Supplied in KGD(Known Good Die) form. - Page operation mode Page read operation by 8 words. - Logic compatible with SRAM R/W pin. - Standby Current Standby 120 uA Deep power-down standby (10) uA - Access Time Access Time CE1 Access Time OE Access Time Page Access Time 65ns 65ns 25ns 20NS GENERAL DISCRIPTION The EM7323SU16H is a 32M-bit StRAM organized as 2M words by 16 bits. It provides high density, high speed and low power. The device operates single power supply. The device also features SRAM-like W/R timing whereby the device is controlled by CE1, OE and WE on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports deep powerdown mode, realizing low-power standby. PAD DESCRIPTION SYMBOL A0~A20 A0~A2 CE1 CE2 WE OE LB UB DQ0~DQ15 VDD VSS VDDQ VSSQ NC Address input Page Address input DESCRIPTION Chip Enable Input1, Low : Enable Chip Enable Input2, High:Enable, Low:Enter Power Down mode Write Enable input, Low :Enable Output Enable input, Low :Enable Lower byte write control Upper byte write control Data inputs/outputs Device Power supply VSS must be connected ground I/O Power supply VSS must be connected ground Not Connection 2 Rev. 0.0 Preliminary EM7323SU16H 2Mx16 Async. / Page StRAM FUNCTION BLOCK DIAGRAM CE A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 ROW ADDRESS DECODER ROW ADDRESS BUFFER VDD GND MEMORY CELL ARRAY DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Sense AMP DATA OUTPUT BUFFER DATA INPUT BUFFER COLUMN ADDRESS DECODER COLUMN ADDRESS BUFFER REFRESH CONTROL REFRESH ADDRESS COUNTER A0 A1 A2 A3 A4 A5 A6 A7 CONTROL SIGNAL GENERATOR CE WE OE UB LB CE1 CE2 CE 3 DATA OUTPUT BUFFER DATA INPUT BUFFER Rev. 0.0 Preliminary EM7323SU16H 2Mx16 Async. / Page StRAM OPERATION MODE CE1 CE2 L L L L L L L H H H H H H H H H H L OE L L L X X X H X X WE H H H L L L H X X LB L L H L L H X X X UB L H L L H L X X X Add DQ0 to DQ7 DQ8 to DQ15 X X X X X X X X X Data Out Data Out High-Z Data In Data In Invalid High-Z High-Z High-Z Data Out High-Z Data Out Data In Invalid Data In High-Z High-Z High-Z Mode Read(Word) Read(Lower Byte) Read(Upper Byte) Write(Word) Write(Lower Byte) Write(Upper Byte) Outputs Disabled Standby Deep Power-down Standby Power IDD0 IDD0 IDD0 IDD0 IDD0 IDD0 IDD0 IDDS IDDSD Note: X means don't care. (Must be low or high state) ABSOLUTE MAXIMUM RATINGS (SEE NOTE1) SYMBOL VDD VIN VOUT Topr. Tstrg. PD IOUT RATING Device Power Supply Voltage Input Voltage Output Voltage Operating Temperature Stroage Temperature Power Dissipation Short Circuit Output Current VALUE -1.0 to 3.6 -1.0 to 3.6 -1.0 to 3.6 -25 to 85 -55 to 150 0.6 50 UNIT V V V W mA DC RECOMMENDED OPERATING CONDITIONS(Ta = -25 SYMBOL VDD VIH VIL PARAMETER Device Power Supply Voltage Input High Voltage Input Low Voltage MIN 2.6 0.8*VDD -0.3 to 85 TYP 2.75 - ) Max 3.3 VDD + 0.3 0.15*VDD V Unit VIH(Max) VDD+1.0V with 10ns pulse width VIL(Min)-1.0V with 10ns pulse width 4 Rev. 0.0 Preliminary EM7323SU16H 2Mx16 Async. / Page StRAM DC CHARACTERISTICS(Ta = -25 Parameter Input leakage current Output leakage current Operating current Page Access Operating current Output high voltage Output low voltage Standby Current (CMOS) Deep Power-down Standby Curret Symbol ILI ILO IDDO1 IDDO2 VOH VOL IDDS VDDSD (*1, *2) VIN=0 to VDD to 85 , VDD=2.6 to 3.3V) (SEE NOTE 3 to 4) Min -1 -1 0.8*VDD Test Conditions Typ - Max 1 1 25 15 0.15*VCCQ Unit uA uA mA mA V V uA uA Output disable, VOUT= 0V to VDD tRC= Min, CE1=VIL , CE2=VIH , IOUT=0mA tPC = Min, CE1=VIL, CE2=VIH , IOUT=0mA, Page add. cycling. IOH = -0.5mA IOL = 1.0mA, VCC=VCCmin CE1>VDD-0.2V, CE2=VDD -0.2V CE2 = 0.2V - 120 10 Note *1. Max VIL of signals(i.e. A0~A20, DQ1~DQ16, CE1#, CE2, WE#, OE#, LB#, UB#) can be 0.2V to 0.616V. *2. For deep power-down, CE2<=0.2V is essential. If max VIL of CE2 is from 0.2V to 0.616V, the (10)uA deep-power current will not be guaranteed, and the deep-power current might go high as (15)uA. CAPACITANCE (f =1MHz, TA=25oC) Item Input capacitance Ouput capacitance Symbol CIN COUT Test Condition VIN=VSS VOUT=VSS Min Max 10 10 Unit pF pF Note : This parameter is sampled periodically and is not 100% tested 5 Rev. 0.0 Preliminary EM7323SU16H 2Mx16 Async. / Page StRAM AC TEST CONDITIONS PARAMETER Output load Input pulse level Timing measurements Reference level tR, tF 50 ohm+0.5 * VDD VDD-0.2V, 0.2V VDD * 0.5 VDD * 0.5 5 ns CONDITION AC CHARACTERISTICS (Vcc = 2.6 to 3.3V, Gnd = 0V, TA = -25oC to +85oC) (SEE NOTE 5-11) Symbol tRC tACC tCO tOE tBA tCOE tOEE tBE tOD tODO tBD tOH tPM tPC tAA tAOH tWC tWP tCW tBW tAW tAS tWR tCEH tWEH tODW tOEW tDS tDH tCS tCH tDPD tCHC tCHP Read Cycle Time Address Access Time Chip Enable(CE1) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Ouput High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time Page Mode Time Page Mode Cycle Time Page Mode Address Access Time Page Mode Output Data Hold Time Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Valid to End of Write Address Set-up Time Write Recovery Time Chip Enable High Pulse Width Write Enable High Pulse Width WE Low to Output High-Z WE High to Output Active Data Set-up Time Data Hold Time CE2 Set-up Time CE2 Hold Time CE2 Pulse Width CE2 Hold from CE1 CE2 Hold from Power On Parameter List Speed Min 65 10 0 0 5 65 20 5 65 50 65 60 60 0 0 10 6 0 30 0 0 300 10 0 30 Max 10000 65 65 25 25 20 20 20 10000 20 10000 20 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us ms ns us 6 Rev. 0.0 Preliminary EM7323SU16H 2Mx16 Async. / Page StRAM TIMING WAVEFORM OF READ CYCLE tRC Address A0 to A20 tACC tCO tOH CE1 CE2 tOD OE tODO WE UB, LB tOEE High-Z tBE Dout DQ0 ~ DQ15 tBD Valid Data tCOE High-Z TIMING WAVEFORM OF PAGE READ CYCLE (8 words access) tPM Address A0 to A2 tRC Address A3 to A20 tPC tPC CE1 CE2 tOE OE WE tBA UB, LB Dout DQ0 ~ DQ15 tOEE tBE High-Z tAOH tAOH tAOH tBD tOD High-Z tOH tODO tCOE tACC tACC Dout tAA Dout Dout tAA Dout 7 Rev. 0.0 Preliminary EM7323SU16H 2Mx16 Async. / Page StRAM TIMING WAVEFORM OF WRITE CYCLE1 (WE CONTROLLED) (SEE NOTE 8) tWC Address A0 to A20 tAW tWEH tWP tAS tCW tWR WE CE1 tCH CE2 tBW tWR UB, LB tODW tOEW High - Z tDS tDH (See Note 9) (See Note11) Dout DQ0 ~ DQ15 Din DQ0 ~ DQ15 (See Note 10) (See Note 9) Valid Data TIMING WAVEFORM OF WRITE CYCLE 2 (CE CONTROLLED) (SEE NOTE 8) tWC Address A0 to A20 tAW tWR tWP WE tCW tWR tCEH CE1 tCH tAS CE2 tBW tWR UB, LB tODW Dout DQ0 ~ DQ15 Din DQ0 ~ DQ15 High - Z tCOE (See Note9) tBE High - Z tDS tDH Valid Data 8 Rev. 0.0 Preliminary EM7323SU16H 2Mx16 Async. / Page StRAM DEEP POWER-DOWN TIMING CE1 tDPD CE2 tCS tCH POWER_ON TIMING VDD VDD min CE1 tCHC CE2 tCHP tCH PROVISIONS OF ADDRESS SKEW Read In case, multiple invalid address cycles shorter than tRC_min sustain over 10us in a active status, as least one valid address cycle over tRC_min must be needed during 10us. over 10 us CE1 WE Address tRCmin Write In case, multiple invalid address cycles shorter than tWC_min sustain over 10us in a active status, as least one valid address cycle over tRC_min with tWP_min must be needed during 10us. over 10 us CE1 tWPmin WE Address tWCmin 9 Rev. 0.0 Preliminary EM7323SU16H 2Mx16 Async. / Page StRAM Notes : 1. Stresses greater than listed under "Absolute Maximum Ratings" may cause permanet damage to the device. 2. All voltages are reference to VSS. 3. IDD0 depends on the cycle time. 4. IDD0 depends on output loading. Specified values are defined with the output open condition. 5. AC measurement are assumed tR, tF = 5ns. 6. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage reference levels 7. Data cannot be retained at deep power-down stand-by mode. 8. If OE is high during the write cycle, the outputs will remain at high impedence. 9. During the output state of DQ signals, input signals of reverse polarity must not be applied. 10. If CE1 or LB / UB goes LOW coincident with or after WE goes LOW, the outputs will remain at high impedence. 11. If CE1 or LB./UB goes HIGH coincident with or before WE goes HIGH, the outputs will remain at high impedence. 10 Rev. 0.0 Preliminary EM7323SU16H 2Mx16 Async. / Page StRAM MEMORY FUNCTION GUIDE EM X XX X X X XX X X X - XX XX 1. EMLSI Memory 2. Device Type 3. Density 4. Function 5. Technology 6. Operating Voltage 1. Memory Component 2. Device Type 6 ---------------------- Low Power SRAM 7 ---------------------- STRAM C ---------------------- CellularRAM 3. Density 4 ----------------------- 4M 8 ----------------------- 8M 16 --------------------- 16M 32 --------------------- 32M 64 --------------------- 64M 28 --------------------- 128M 4. Function 2 ----Multiplexed async. 3-----Demultiplexed async. with page mode 4-----Demultiplexed async. with direct DPD 5-----Multiplexed sync. 6-----Optional mux/demuxed sync. 5. Technology S ----------------------- Single Transistor & Trench Cell 6. Operating Voltage V ----------------------- 3.3V U ----------------------- 3.0V S ----------------------- 2.5V R ----------------------- 2.0V P ----------------------- 1.8V L ----------------------- 1.5V 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 12. Power 11. Speed 10. PKG 9. Option 8. Version 7. Organization 8. Version Blank ----------------- Mother die A ----------------------- 2'nd generation B ----------------------- 3'rd generation C ----------------------- 4'th generation D ----------------------- 5'th generation 9. Option Blank ---- No optional mode H ----------- Demultiplexed with DPD J ------------ Demultiplexed with DPD & RBC K ------------ Multiplexed with RBC L ------------ Multiplexed with DPD & RBC 10. Package Blank ---------------------- Wafer S ---------------------- 32 sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 P ---------------------- 48 FPBGA Z ---------------------- 52 FPBGA Y ---------------------- 54 FPBGA V ---------------------- 90 FPBGA 11. Speed (@async.) 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 90 ---------------------- 90ns 10 --------------------- 100ns 12 --------------------- 120ns 12. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power (Pb-Free&Green) L ---------------------- Low Power 11 Rev. 0.0 |
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