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19-4159; Rev 1; 10/08
KIT ATION EVALU BLE AVAILA
Low-Power Audio/Video Interface for Single SCART Connectors
General Description Features
53mW Quiescent Power Consumption 5W Shutdown Consumption Audio Operational Amplifiers to Create Input Filters Clickless/Popless, DirectDrive Audio Video Reconstruction Filter with 10MHz Passband and 43dB Attenuation at 27MHz 3.3V and 12V Supply Voltages
MAX9597
The MAX9597 single SCART interface routes audio and video signals between a set-top box decoder chip and an external SCART connector under I 2 C control. Operating from a 3.3V supply and a 12V supply, the MAX9597 consumes 53mW during quiescent operation and 254mW during average operation when driving typical signals into typical loads. The MAX9597 audio section contains left and right audio paths with an independent operational amplifier at the inputs. The DirectDrive (R) output amplifiers create a 2VRMS full-scale audio signal biased around ground, eliminating the need for bulky output capacitors and reducing click-and-pop noise. The zero-cross detection circuitry also further reduces clicks and pops by enabling audio sources to switch only during a zerocrossing. The MAX9597 video section contains 4 channels of video filter amplifiers. The standard-definition video signals from the set-top box decoder chip are lowpass filtered to remove out-of-bandwidth artifacts. The MAX9597 also supports slow-switching and fast-switching signals. The MAX9597 is available in a compact 28-pin thin QFN package and is specified over the 0C to +70C commercial temperature range.
Ordering Information
PART MAX9597CTI+ TEMP RANGE 0C to +70C PIN-PACKAGE 28 TQFN-EP*
+Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad.
Applications
Set-Top Boxes AV Receivers TVs DVD Players
DirectDrive is a registered trademark of Maxim Integrated Products, Inc.
System Block Diagram
V12 12V VID 3.3V VAUD 3.3V
STB CHIP
MAX9597
I2C INTERFACE AND REGISTERS RGB, Y/C, CVBS VIDEO FILTERS L/R AUDIO FAST AND SLOW SWITCHING AUDIO WITH DirectDrive OUTPUTS TV SCART
C
I2C
VIDEO ENCODER
RGB, Y/C, CVBS
STEREO AUDIO DAC
SINGLE OR DIFFERENTIAL STEREO AUDIO
SLOW SWITCHING FAST SWITCHING
CHARGE PUMP EP GND
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.) VVID ..........................................................................-0.3V to +4V V12 to EP ................................................................-0.3V to +14V VAUD to EP ...............................................................-0.3V to +4V EP to GND .............................................................-0.1V to +0.1V All Video Inputs .......................................................-0.3V to +4V All Audio Inputs to EP .............................(VEP - 1)V to (VEP + 1)V SDA, SCL, DEV_ADDR ............................................-0.3V to +4V TV_SS_OUT .................................................-0.3V to (V12 + 0.3V) Current All Video/Audio Inputs ..................................................20mA C1P, C1N, CPVSS ........................................................50mA Output Short-Circuit Current Duration All Video Outputs, TV_FS_OUT to VVID, GND........Continuous Audio Outputs to VAUD, EP ....................................Continuous TV_SS_OUT to V12, EP...........................................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin Thin QFN (derate 21.3mW/C above +70C) ...........................1702mW Operating Temperature Range ..............................0C to +70C Junction Temperature .....................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Video Supply Voltage Range Audio Supply Voltage Range Slow-Switching Supply Voltage Range VVID Quiescent Supply Current SYMBOL VVID VAUD V12 CONDITIONS Inferred from video PSRR test at 3.0V and 3.6V Inferred from audio PSRR tests at 3.0V and 3.6V Inferred from slow-switching levels Normal operation, all video output amplifiers are enabled Shutdown VAUD Quiescent Supply Current V12 Quiescent Supply Current VIDEO CHARACTERISTICS DC-COUPLED INPUT Input Voltage Range Input Current Input Resistance AC-COUPLED INPUT Sync-Tip Clamp Level Sync Crush Input Clamping Current VCLP Sync-tip clamp Sync-tip clamp; percentage reduction in sync pulse (0.3VP-P); guaranteed by input clamping current measurement Sync-tip clamp 2 -5 0 6.1 2 3 mV % A VIN IIN RIN RL = 75 to GND or 150 to VVID/2, inferred from gain test VIN = GND VVID = 3V VVID = 3.135V VVID = 3.3V 1.3 2 300 3 A k 1.15 1.2 VP-P IAUD_Q I12_Q Normal operation Shutdown Normal operation Shutdown MIN 3.0 3.0 11.4 TYP 3.3 3.3 12 13 1 3 0.01 1.5 0.1 MAX 3.6 3.6 12.6 20 10 4.1 10 100 10 UNITS V V V mA A mA A A
IVID_Q
2
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Low-Power Audio/Video Interface for Single SCART Connectors
ELECTRICAL CHARACTERISTICS (continued)
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Max Input Source Resistance Bias Voltage Input Resistance DC CHARACTERISTICS VVID = 3V, VIN = VCLP to (VCLP + 1.15V) RL = 75 to GND or RL = 150 to VVID/2 VVID = 3.135V, VIN = VCLP to (VCLP + 1.2V) VVID = 3V, VIN = (VBIAS - 0.575V) to (VBIAS + 0.575V) VVID = 3.135V VIN = (VBIAS - 0.6V) to (VBIAS + 0.6V) DC Gain Mismatch Output Level Guaranteed by DC voltage gain Sync-tip clamp Bias circuit Sync-tip clamp, measured at output, VVID = 3V, VIN = VCLP to (VCLP + 1.15V), RL = 75 to GND or RL = 150 to VVID/2 Measured at output, VVID = 3.135V, VIN = VCLP to (VCLP + 1.2V), RL = 75 to GND or Guaranteed RL = 150 to VVID/2 by DC Bias circuit, measured at voltage gain output, VVID = 3V, VIN = (VBIAS - 0.575V) to (VBIAS + 0.575V), RL = 75 to GND or RL = 150 to VVID/2 Measured at output, VVID = 3.135V, VIN = (VBIAS - 0.6V) to (VBIAS + 0.6V), RL = 75 to GND or RL = 150 to VVID/2 Output disabled 3.0V VVID 3.6V 50 2 VBIAS Bias circuit Bias circuit 0.57 SYMBOL CONDITIONS MIN TYP 300 0.6 10 0.63 MAX UNITS V k
MAX9597
1.93
2
2.05 V/V
DC Voltage Gain
AV
2
1.93 -2 0.2 1.38
2
2.05 +2 % V
0.30 1.5
0.4 1.62
2.3
2.316
2.4
2.46 VP-P
Output Voltage Swing
2.3
2.316
2.4
2.46
Output Short-Circuit Current Output Leakage Current Power-Supply Rejection Ratio
100 0.02 75 10
mA A dB
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3
Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
ELECTRICAL CHARACTERISTICS (continued)
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER AC CHARACTERISTICS Filter Passband Flatness Filter Attenuation Differential Gain Differential Phase 2T Pulse-to-Bar K Rating 2T Pulse Response 2T Bar Response Nonlinearity Group Delay Distortion Peak Signal to RMS Noise Power-Supply Rejection Ratio Output Impedance Video Crosstalk Voltage Gain Gain Mismatch Flatness Frequency Bandwidth Capacitive Drive Input Signal Amplitude Output DC Level Power-Supply Rejection Ratio Signal-to-Noise Ratio Total Harmonic Distortion Plus Noise Output Impedance Mute Suppression Audio Crosstalk f = 20Hz to 20kHz, 0.25VRMS input 0.25VRMS input, frequency where output is -3dB referenced to 1kHz No sustained oscillations, 75 series resistor on output f = 1kHz, THD < 1% No input signal, VIN = 0V DC f = 1kHz f = 1kHz, 0.25VRMS input, 20Hz to 20kHz RL = 3.33k, f = 1kHz f = 1kHz f = 1kHz, 0.25VRMS input f = 1kHz, 0.25VRMS input 0.25VRMS input 0.5VRMS input -3 75 110 91 97 0.0011 0.0021 0.28 101 100 DG DP VOUT = 2VP-P, f = 100kHz to 10MHz VOUT = 2VP-P, attenuation is referred to 100kHz f = 11MHz f = 27MHz f = 54MHz 1 3 43 63 0.2 0.3 0.5 0.5 0.5 0.5 3.5 60 47 5.5 -68.5 3.95 -1.5 0.01 205 300 0.5 +3 4 4.05 +1.5 % Degrees K% K% K% % ns dB dB dB V/V % dB kHz pF VRMS mV dB dB % dB dB dB dB SYMBOL CONDITIONS MIN TYP MAX UNITS
5-step modulated staircase, f = 4.43MHz 5-step modulated staircase, f = 4.43MHz 2T = 200ns; bar time is 18s; the beginning 2.5% and the ending 2.5% of the bar time is ignored 2T = 200ns 2T = 200ns; bar time is 18s; the beginning 2.5% and the ending 2.5% of the bar time is ignored 5-step staircase 100kHz f 5MHz, outputs are 2VP-P 100kHz f 5MHz f = 100kHz, 100mVP-P f = 5MHz f = 4.43MHz
AUDIO CHARACTERISTICS OUTPUT AMPLIFIER (Note 2)
4
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Low-Power Audio/Video Interface for Single SCART Connectors
ELECTRICAL CHARACTERISTICS (continued)
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER VIDEO TO AUDIO INTERACTION Crosstalk Video input: f = 15kHz, 1VP-P signal Audio input: f = 15kHz, 0.1VRMS signal TA = +25C TA = 0C to +70C 100 1.5 -0.707 80 VCM = 0V VCM = 0V, -0.8V VOUT +0.8V RL = 124, inferred from AVOL test 90 60 1.6 8.25 1.24 f = 1kHz f = 1kHz AVCL = 1V/V, no sustained oscillation 13.5 0.2 20 580 IOL = 0.5mA IOH = 0.5mA VVID 0.1 0.003 VVID 0.003 5.5 RL = 143 to GND RL = 143 to GND 10k to EP, 11.4V V12 12.6V 10k to EP, 11.4V V12 12.6V 10k to EP, 11.4V V12 12.6V 5 10 -1 0.7 x VVID +1 2 2 1.5 6.5 0.1 100 125 80 100 102 25 100 225 550 30 +0.707 dB SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9597
INPUT AMPLIFIER OPEN-LOOP CHARACTERISTICS Input Offset Voltage Input Bias Current Input Offset Current Common-Mode Input Voltage Range Common-Mode Rejection Ratio Power-Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Gain-Bandwidth Product Slew Rate Input Voltage-Noise Density Input Current-Noise Density Capacitive Load Stability CHARGE PUMP Switching Frequency FAST SWITCHING Output Low Voltage Output High Voltage Output Resistance Rise Time Fall Time SLOW SWITCHING Output Low Voltage Output Medium Voltage Output High Voltage Input Current DIGITAL INTERFACE (SDA, SCL) Input High Voltage VIH V V V V A V V ns ns kHz VOS IB IOS VCM CMRR PSRR AVOL VOUT GBWP SR VN IN VCM = 0V VCM = 0V VCM = 0V Inferred from CMRR test V nA nA V dB dB dB VP-P MHz V/s nV/Hz pA/Hz pF
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5
Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
ELECTRICAL CHARACTERISTICS (continued)
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance VVIDMAX = 3.6V 0.1VVID < SDA < 0.9VVIDMAX 0.1VVID < SCL < 0.9VVIDMAX I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VVID is switched off ISINK = 6mA SYMBOL VIL VHYS IIH, IIL SCL and SDA have 40k pullup resistors to VVID 0.05 x VVID -1 10 +1 CONDITIONS MIN TYP MAX 0.3 x VVID UNITS V V A pF
Input Current
-10
+10
A
Output Low Voltage SDA Serial-Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time, (REPEATED) START Condition Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a REPEATED START Condition
VOL fSCL tBUF tHD, STA tLOW tHIGH tSU, STA
0.4 0 1.3 0.6 1.3 0.6 0.6 400
V kHz s s s s s
Data Hold Time
tHD, DAT tHD, DAT tF tSU, STO tSP
A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL's falling edge CB = total capacitance of one bus line in pF < 400pF; tR and tF measured between 0.3VVID and 0.7VVID (CB is in pF)
0
0.9
s
Data Setup Time Fall Time of SDA Transmitting Setup Time for STOP Condition Pulse Width of Spike Suppressed OTHER DIGITAL I/O DEV_ADDR Low Level DEV_ADDR High Level DEV_ADDR Input Current
100 250 0.6 Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns 0 50
ns ns s ns
0.3 x VVID 0.7 x VVID -1 +1
V V A
Note 1: All devices are 100% production tested at TA = +25C and are guaranteed by design for TA = 0C to +70C as specified. Note 2: Input operational amplifier configured in voltage follower configuration, unless otherwise noted.
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Low-Power Audio/Video Interface for Single SCART Connectors
Typical Operating Characteristics
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, video load is 150 to GND, audio load is 10k to GND, TA = +25C, unless otherwise noted.)
VIDEO SMALL-SIGNAL GAIN vs. FREQUENCY
10 5 0 -5 -10 GAIN (dB) GAIN (dB) -15 -20 -25 -30 -35 -40 -45 -50 100k 1M 10M 100M FREQUENCY (Hz)
MAX9597 toc01
MAX9597
VIDEO SMALL-SIGNAL GAIN FLATNESS vs. FREQUENCY
MAX9597 toc02
VIDEO LARGE-SIGNAL GAIN vs. FREQUENCY
10 5 0 -5 -10 GAIN (dB) -15 -20 -25 -30 -35 -40 -45 -50 VOUT = 2VP-P
MAX9597 toc03 MAX9597 toc09 MAX9597 toc06
2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 100k 1M 10M FREQUENCY (Hz) VOUT = 100mVP-P
VOUT = 100mVP-P
100M
100k
1M 10M FREQUENCY (Hz)
100M
VIDEO LARGE-SIGNAL GAIN FLATNESS vs. FREQUENCY
MAX9597 toc04
VIDEO CROSSTALK vs. FREQUENCY
MAX9597 toc05
VIDEO GROUP DELAY DISTORTION vs. FREQUENCY
100 90 80 GROUP DELAY (ns) 70 60 50 40 30 20 10 0 VOUT = 2VP-P
2 1 0 -1 GAIN (dB) -2 -3 -4 -5 -6 -7 -8 100k 1M 10M FREQUENCY (Hz) VOUT = 2VP-P
0 VOUT = 2VP-P -10 -20 CROSSTALK (dB) -30 -40 -50 -60 -70 -80
100M
100k
1M 10M FREQUENCY (Hz)
100M
100k
1M 10M FREQUENCY (Hz)
100M
VIDEO POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
MAX9597 toc07
VOLTAGE GAIN vs. TEMPERATURE
MAX9597 toc08
VIDEO OUTPUT VOLTAGE vs. INPUT VOLTAGE
3.5 3.0 OUTPUT VOLTAGE (V) 2.5 2.0 1.5 1.0 0.5
0 -5 -10 -15 PSRR (dB) -20 -25 -30 -35 -40 -45 -50 100k 1M 10M FREQUENCY (Hz)
2.03 2.02 VOLTAGE GAIN (V/V) 2.01 2.00 1.99 1.98 1.97
0 -0.5 0 25 50 75 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 INPUT VOLTAGE (V) TEMPERATURE (C)
100M
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7
Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
Typical Operating Characteristics (continued)
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, video load is 150 to GND, audio load is 10k to GND, TA = +25C, unless otherwise noted.)
DIFFERENTIAL GAIN AND PHASE
DIFFERENTIAL GAIN (%) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0 1 2 3 4 5 100ns/div 1 2 3 4 5 OUTPUT 400mV/div
MAX9597 toc10
2T RESPONSE
MAX9597 toc11
12.5T RESPONSE
MAX9597 toc12
INPUT 200mV/div
INPUT 200mV/div
DIFFERENTIAL PHASE (deg)
OUTPUT 400mV/div
400ns/div
PAL VIDEO TEST SIGNAL
MAX9597 toc13
VIDEO OUTPUT BIAS VOLTAGE vs. TEMPERATURE
MAX9597 toc14
AUDIO LARGE-SIGNAL BANDWIDTH vs. FREQUENCY
VIN = 0.25VRMS RL = 10k
MAX9597 toc15
1.480 VIDEO OUTPUT BIAS VOLTAGE (V)
10 5 0
INPUT 0.5V/div
1.476
1.472
GAIN (dB)
-5 -10 -15 -20
1.468
OUTPUT 1V/div
1.464
1.460 10s/div 0 25 50 75 TEMPERATURE (C)
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
AUDIO CROSSTALK vs. FREQUENCY
VIN = 0.25VRMS RL = 10k
MAX9597 toc16
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX9597 toc17
VAUD POWER-SUPPLY REJECTION RATIO (INPUT REFERRED) vs. FREQUENCY
VAUD = 3.3V + 100mVP-P
MAX9597 toc18
0 -20 CROSSTALK (dB) -40
0.1 RL = 3.3k
0 -20 -40
0.01 THD+N (%) VIN = 0.25VRMS 0.001 PSRR (dB)
-60 -80 -100 -120 100 1k 10k 100k FREQUENCY (Hz)
-60 -80 -100
VIN = 0.5VRMS
0.0001 10 100 1k FREQUENCY (Hz) 10k 100k
-120 10 100 1k FREQUENCY (Hz) 10k 100k
8
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Low-Power Audio/Video Interface for Single SCART Connectors
Typical Operating Characteristics (continued)
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, video load is 150 to GND, audio load is 10k to GND, TA = +25C, unless otherwise noted.)
VVID QUIESCENT SUPPLY CURRENT vs. TEMPERATURE
MAX9597 toc19
MAX9597
VAUD QUIESCENT SUPPLY CURRENT vs. TEMPERATURE
MAX9597 toc20
V12 QUIESCENT SUPPLY CURRENT vs. TEMPERATURE
MAX9597 toc21
14.3 QUIESCENT SUPPLY CURRENT (mA)
3.6 QUIESCENT SUPPLY CURRENT (mA) 3.5 3.4 3.3 3.2 3.1 3.0 2.9
0.20 QUIESCENT SUPPLY CURRENT (A)
14.2
0.15
14.1
0.10
14.0
0.05
13.9
13.8 0 25 50 75 TEMPERATURE (C)
0 0 25 50 75 0 25 50 75 TEMPERATURE (C) TEMPERATURE (C)
INPUT-AMPLIFIER INPUT OFFSET VOLTAGE vs. TEMPERATURE
MAX9597 toc22
INPUT-AMPLIFIER INPUT BIAS CURRENT vs. TEMPERATURE
MAX9597 toc23
20 15 INPUT OFFSET VOLTAGE (mV) 10 5 0 -5 -10 -15 0 25 50
0.3
INPUT BIAS CURRENT (A)
0.2
0.1
0 75 -50 25 50 75 TEMPERATURE (C) TEMPERATURE (C)
INPUT-AMPLIFIER GAIN AND PHASE vs. FREQUENCY
PHASE MARGIN (CL = 0pF) = 60 PHASE MARGIN (CL = 22pF) = 44 GAIN PHASE (deg) 20 GAIN (dB) 0 PHASE -20 -40 -60 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) AV = +100V/V VIN = 10mVP-P RLOAD = OPEN CL = 0pF/22pF CL = OpF 60 0 -60 -120 CL = 22pF -180 0.0001 THD+N (%) 0.01
MAX9597 toc24
INPUT-AMPLIFIER TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
UNITY GAIN RL = OPEN
MAX9597 toc25
60 40
180 120
0.1
0.001
VIN = 0.25VRMS VIN = 0.5VRMS
10
100
1k FREQUENCY (Hz)
10k
100k
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9
Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
Typical Operating Characteristics (continued)
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, video load is 150 to GND, audio load is 10k to GND, TA = +25C, unless otherwise noted.)
INPUT-AMPLIFIER SMALL-SIGNAL TRANSIENT RESPONSE
MAX9597 toc26
INPUT-AMPLIFIER SMALL-SIGNAL TRANSIENT RESPONSE
UNITY GAIN RL = 124 0V
MAX9597 toc27
UNITY GAIN RL = OPEN 0V
INPUT 50mV/div
INPUT 50mV/div
0V
OUTPUT 50mV/div
0V
OUTPUT 50mV/div
200ns/div
200ns/div
INPUT-AMPLIFIER LARGE-SIGNAL TRANSIENT RESPONSE
UNITY GAIN RL = OPEN 0V
MAX9597 toc28
INPUT-AMPLIFIER LARGE-SIGNAL TRANSIENT RESPONSE
UNITY GAIN RL = 124 0V
MAX9597 toc29
INPUT 500mV/div
INPUT 500mV/div
0V
OUTPUT 500mV/div
0V
OUTPUT 500mV/div
1s/div
1s/div
10
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Low-Power Audio/Video Interface for Single SCART Connectors
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 -- NAME VAUD C1P C1N CPVSS DEV_ADDR SDA SCL ENC_B_IN ENC_G_IN ENC_R/C_IN ENC_CVBS_IN TV_CVBS_OUT VVID TV_FS_OUT GND TV_R/C_OUT TV_G_OUT TV_B_OUT V12 TV_SS_OUT TV_OUTL ENC_INL+ ENC_INLENC_INLOUT ENC_INROUT ENC_INRENC_INR+ TV_OUTR EP FUNCTION Audio Supply. Connect to a 3.3V supply. Bypass with a 10F aluminum electrolytic capacitor in parallel with a 0.1F ceramic capacitor to EP. Charge-Pump Flying Capacitor Positive Terminal. Connect a 1F capacitor from C1P to C1N. Charge-Pump Flying Capacitor Negative Terminal. Connect a 1F capacitor from C1P to C1N. Charge-Pump Negative Power Supply. Bypass with a 10F aluminum electrolytic capacitor in parallel with a 1F ceramic capacitor to EP. Device Address Set Input. Connect DEV_ADDR to GND, VVID, SDA, or SCL. See Table 3. Bidirectional, I2C Data I/O. Output is open drain and tolerates up to 3.6V. I2C Clock Input Encoder Blue Video Input Encoder Green Video Input Encoder Red/Chroma Video Input Encoder Composite Video Input TV SCART Composite Video Output. The sync tip is biased at 0.3V. Video and Digital Supply. Connect to a +3.3V supply. Bypass with a parallel 1F and 0.1F ceramic capacitor to GND. VVID also serves as a digital supply for the I2C interface. TV SCART Fast-Switching Logic Output. This signal drives a back-terminated, 75 transmission line. Video Ground TV SCART Red/Chroma Video Output. The black level of the red signal is set to 0.3V and the blank level of the chroma signal is 1.5V. TV SCART Green Video Output. The black level of the green signal is set to 0.3V. TV SCART Blue Video Output. The black level of the blue signal is set to 0.3V. +12V Supply. Bypass V12 with a 0.1F capacitor to EP. TV SCART Slow-Switch Signal Output TV SCART Left-Channel Audio Output Left Input-Amplifier Noninverting Terminal Left Input-Amplifier Inverting Terminal Left Input-Amplifier Output Right Input-Amplifier Output Right Input-Amplifier Noninverting Terminal Right Input-Amplifier Inverting Terminal TV SCART Right-Channel Audio Output Exposed Pad. The exposed pad is the internal ground for the audio amplifiers and charge pump. A low-impedance connection to EP is required for proper isolation.
MAX9597
______________________________________________________________________________________
11
Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
Detailed Description
The MAX9597 represents Maxim's third generation of SCART audio/video (A/V) switches. Under I2C control, these devices route audio, video, and control information between the set-top box decoder chip and a SCART connector. The audio signals are left audio and right audio. The video signals are composite video with blanking and sync (CVBS) and component video (red, green, blue). S-video (Y/C) can be transported across the SCART interface if CVBS is reassigned to luma (Y) and red is reassigned to chroma (C). Support for S-video is optional. The slow-switch signal and the fastswitch signal carry control information. The slow-switch signal is a 12V, trilevel signal that indicates whether the picture aspect ratio is 4:3, 16:9, or causes the television to use an internal A/V source, such as an antenna. The fast-switch signal indicates whether the television should display CVBS or RGB signals. CVBS, left audio, and right audio are full duplex. All the other signals are half duplex. Therefore, one device on the link must be designated as the transmitter, and the other device must be designated as the receiver. The low power consumption of the MAX9597 enables the creation of lower power set-top boxes, televisions, and DVD players. Unlike competing SCART ICs, the audio and video circuits of the MAX9597 operate entirely from 3.3V rather than from 5V and 12V. Only the slowswitch circuit of the MAX9597 requires a 12V supply. The MAX9597 features DirectDrive audio circuitry to eliminate click-and-pop noise. With DirectDrive, the DC bias of the audio line outputs is always at ground when the MAX9597 is being powered up or powered down. Conventional audio line output drivers that operate from a single supply require series AC-coupling capacitors. During power-up, the DC bias on the AC-coupling capacitor moves from ground to a positive voltage, and during power-down, the opposite occurs. The changing DC bias usually causes an audible transient.
Audio Section
The audio circuit consists of a left and right audio path, each with an independent operational amplifier followed by a gain-of-4 amplifier. The encoder (stereo audio DAC) is the input source, and the output goes to the TV SCART connector. See Figure 1.
ENC_INR+ INPUT OP AMP ZERO-CROSS DETECTOR VAUD EP AV = 4V/V ENC_INROUT TV_OUTR
ENC_INR-
ENC_INL+ INPUT OP AMP ZERO-CROSS DETECTOR VAUD EP TV_OUTL AV = 4V/V ENC_INLOUT VAUD C1P C1N CPVSS EP CHARGE PUMP
ENC_INL-
MAX9597
Figure 1. MAX9597 Audio Section Functional Diagram
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Low-Power Audio/Video Interface for Single SCART Connectors
The full-scale output of the independent operational amplifiers is 0.5VRMS. The closed-loop gain of the operational amplifier circuit should be designed such that the resulting full-scale output is 0.5VRMS. The fixed, gain-of-4 amplifiers that follow the independent operational amplifiers amplify the 0.5VRMS to 2VRMS, which complies with the SCART standard. An integrated charge pump inverts the +3.3V supply (VAUD) to create a -3.3V supply (CPVSS), enabling the audio circuit to operate from bipolar supplies. The audio signal from the beginning to the end of the signal path is always biased at ground.
CONVENTIONAL DRIVER-BIASING SCHEME
MAX9597
VDD VOUT VDD/2 GND
Clickless Muting and Unmuting The TV audio channel incorporates a zero-crossing detect (ZCD) circuit that minimizes click noise due to abrupt signal level changes that occur when entering or coming out of a mute condition at an arbitrary moment. To implement the zero-crossing function when switching audio signals, set ZCD (register 00h, bit 6) high. The MAX9597 switches the signal in or out of mute at the next zero crossing after the mute or unmute request occurs. See Table 8. Audio Outputs The MAX9597 audio output amplifiers feature Maxim's patented DirectDrive architecture, eliminating the need for output-coupling capacitors required by conventional single-supply audio line drivers. Conventional singlesupply audio line drivers have their outputs biased about a nominal DC voltage (typically half the supply) for maximum dynamic range. Large coupling capacitors are needed to block this DC bias. Clicks and pops are created when the coupling capacitors are charged during power-up and discharged during power-down. An internal charge pump inverts the positive supply (VAUD), creating a negative supply (CPVSS). The audio output amplifiers operate from the bipolar supplies with the outputs biased about audio ground (Figure 2). The benefit of this audio ground bias is that the amplifier outputs do not have a DC component. The DC-blocking capacitors required with conventional audio line drivers are unnecessary, conserving board space, reducing system cost, and improving frequency response.
The MAX9597 features a low-noise charge pump that requires only two small ceramic capacitors. The 580kHz switching frequency is well beyond the audio range and does not interfere with audio signals. The switch drivers feature a controlled switching speed that minimizes noise generated by turn-on and turn-off transients. The di/dt noise caused by the parasitic bond
U.S.
+VDD
VOUT
GND
-VDD
DirectDrive BIASING SCHEME
Figure 2. Conventional Driver Output Waveform vs. MAX9597 Output Waveform
wire and trace inductance is minimized by limiting the switching speed of the charge pump. The SCART standard specifies 2VRMS as the full-scale for audio signals. As the audio circuits process 0.5V RMS full-scale audio signals internal to the MAX9597, the gain-of-4 output amplifiers restore the audio signals to a full scale of 2VRMS.
Video Section
The video circuit routes different video formats between the set-top box decoder and the TV SCART connector. It also routes slow-switch and fast-switch control information as shown in Figure 3.
Video Inputs Whether the incoming video input signal is AC-coupled or DC-coupled into the MAX9597 depends upon the origin, format, and voltage range of the video signal. Table 1 below shows the recommended connections. Always AC-couple an external video signal through a 0.1F capacitor because its voltage range is not well defined (see the Typical Application Circuit). For example, the
Patent #7,061,327
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
ENC_CVBS_IN
CLAMP
LPF
AV = 2V/V
TV_CVBS_OUT
ENC_R/C_IN
CLAMP/BIAS
LPF
AV = 2V/V
TV_R/C_OUT
ENC_G_IN
CLAMP
LPF
AV = 2V/V
TV_G_OUT
ENC_B_IN
CLAMP
LPF
AV = 2V/V
TV_B_OUT
VVID AV = 1V/V GND TV_FS_OUT
V12 AV = 1V/V +6V EP TV_SS_OUT
MAX9597
Figure 3. MAX9597 Video Section Function Diagram
video transmitter circuit might have a different ground than the video receiver, thereby level shifting the DC bias. The 50Hz power line hum might cause the video signal to change DC bias slowly. Internal video signals that are between 0V and 1V can be DC-coupled. Most video DACs generate video signals between 0V and 1V because the video DAC sources current into a ground-referenced resistor. For the minority of video DACs that generate video signals between 2.3V and 3.3V because the video DAC sinks current from a VDD-referenced resistor, AC-couple the video signal to the MAX9597. The MAX9597 restores the DC level of incoming, AC-coupled video signals with either transparent synctip clamps or bias circuits. When using an AC-coupled input, the transparent sync-tip clamp automatically clamps the input signal minimum to ground, preventing it
14
from going lower. A small current of 2A pulls down on the input to prevent an AC-coupled signal from drifting outside the input range of the part. The transparent synctip clamp is used with CVBS, RGB, and luma signals. The transparent sync-tip clamp is transparent when the incoming video signal is DC-coupled and at ground or above. Under such conditions, the clamp never activates. Therefore, the outputs of video DACs that generate signals between 0V and 1V can be directly connected to the MAX9597 inputs. The bias circuit accepts AC-coupled chroma, which is a subcarrier with the color information modulated onto it. The bias voltage of the bias circuits is around 600mV. ENC_R/C_IN can receive either a red video signal or a chroma video signal. Set the input configuration by writing to bit 3 of register 08h. See Table 10.
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
Table 1. Recommended Coupling for Incoming Video Signals and Input Circuit Configuration**
VIDEO ORIGIN External External External External Internal Internal Internal Internal Internal Internal Internal Internal FORMAT CVBS RGB Y C CVBS R, G, B Y, C Y, Pb, Pr CVBS R, G, B Y C VOLTAGE RANGE (V) Unknown Unknown Unknown Unknown 0 to 1 0 to 1 0 to 1 0 to 1 2.3 to 3.3 2.3 to 3.3 2.3 to 3.3 2.3 to 3.3 COUPLING AC AC AC AC DC DC DC DC AC AC AC AC INPUT CIRCUIT CONFIGURATION Transparent sync-tip clamp Transparent sync-tip clamp Transparent sync-tip clamp Bias circuit Transparent sync-tip clamp Transparent sync-tip clamp Transparent sync-tip clamp Transparent sync-tip clamp Transparent sync-tip clamp Transparent sync-tip clamp Transparent sync-tip clamp Bias circuit
**Use a 0.1F capacitor to AC-couple a video signal into the MAX9597.
Video Reconstruction Filter The video DAC outputs of the set-top box decoder chip need to be lowpass-filtered to reject the out-of-band noise. The MAX9597 integrates sixth-order, Butterworth filters. The filter passband (1dB) is typically 10MHz, and the attenuation at 27MHz is 43dB. The filters are suited for standard-definition video. Video Outputs The video output amplifiers can both source and sink load current, allowing output loads to be DC- or AC-coupled. The amplifier output stage needs approximately 300mV of headroom from either supply rail. If the supply voltage is greater than 3.135V (5% below a 3.3V supply), each amplifier can drive two DC-coupled video loads to ground. If the supply is less than 3.135V, each amplifier can drive only one DC-coupled or AC-coupled video load. The SCART standard allows for video signals to have a superimposed DC component within 0V and 2V. Therefore, most video signals are DC-coupled at the output. In the unlikely event that the video signal needs to be AC-coupled, the coupling capacitors should be 220F or greater to keep the highpass filter formed by the 37.5 equivalent resistance of the video transmission line to a corner frequency of 4.8Hz or below to keep it well below the 25Hz frame rate of the PAL standard.
The video outputs can be enabled or disabled by bits 1 to 5 of register 0Dh. See Table 11.
Slow Switching The MAX9597 supports the IEC 933-1, Amendment 1, trilevel slow-switching standard that selects the aspect ratio for the display (TV). Under I 2 C control, the MAX9597 sets the slow-switching output voltage level. Table 2 shows the valid input levels of the slow-switching signal and the corresponding operating modes of the display device. One port is available for slow-switching signals for the TV. The slow-switching outputs can be set to a logic level or high impedance by writing to bit 0 and 1 of register 07h. See Table 9.
Table 2. Slow-Switching Modes
SLOW-SWITCHING SIGNAL VOLTAGE (V) MODE
0 to 2
Display device uses an internal source such as a built-in tuner to provide a video signal. Display device uses a video signal from the SCART connector and sets the display to a 16:9 aspect ratio. Display device uses a signal from the SCART connector and sets the display to a 4:3 aspect ratio.
4.5 to 7.0
9.5 to 12.6
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
Table 3. Slave Address
DEV_ADDR GND VVID SCL SDA B7 1 1 1 1 B6 0 0 0 0 B5 0 0 0 0 B4 1 1 1 1 B3 0 0 1 1 B2 1 1 0 0 B1 0 1 0 1 B0 R/W R/W R/W R/W WRITE ADDRESS (HEX) 94h 96h 98h 9Ah READ ADDRESS (HEX) 95h 97h 99h 9Bh
SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tBUF tHD, STA tSP tSU, STO
Figure 4. I2C Serial-Interface Timing Diagram
Fast Switching The fast-switching signal was originally used to switch between CVBS and RGB signals on a pixel-by-pixel basis so that on-screen display (OSD) information could be inserted. Since modern set-top box decoder chips have integrated OSD circuitry, there is no need to create OSD information using the older technique. Now, the fast-switching signal is just used to switch between CVBS and RGB signal sources. Set the source of the fast-switching signal by writing to bits 4 and 3 of register 07h. The fast-switching signal to the TV SCART connector can be enabled or disabled by bit 1 of register 0Dh. See Tables 9 and 11.
I2C Serial Interface
The MAX9597 features an I2C/SMBusTM-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9597 and the master at clock rates up to 400kHz. Figure 4 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. A master device writes data to the MAX9597 by transmitting a START (S) condition, the proper slave address with the R/W bit set to 0, followed by the register address and then the data word. Each transmit sequence is framed by a START and a STOP (P) condition. Each word transmitted to the MAX9597 is 8 bits long and is followed by
16
an acknowledge clock pulse. A master reads from the MAX9597 by transmitting the slave address with the R/W bit set to 0, the register address of the register to be read, a REPEATED START (Sr) condition, the slave address with the R/W bit set to 1, followed by a series of SCL pulses. The MAX9597 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, an acknowledge or a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500, is required on the SDA bus. SCL operates as only an input. A pullup resistor, typically greater than 500, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9597 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals.
Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP
SMBus is a trademark of Intel Corp.
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Low-Power Audio/Video Interface for Single SCART Connectors
Conditions section). SDA and SCL idle high when the I2C bus is not busy. START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 5). A START condition from the master signals the beginning of a transmission to the MAX9597. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The MAX9597 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The slave address is defined as the 7 most significant bits (MSBs) followed by the read/write (R/W) bit. Set the R/W bit to 1 to configure the MAX9597 to read mode. Set the R/W bit to 0 to configure the MAX9597 to write mode. The slave address is always the first byte of information sent to the MAX9597 after a START or a REPEATED START condition. The MAX9597 slave address is configurable with DEV_ADDR. Table 3 shows the possible slave addresses for the MAX9597. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9597 uses to handshake receipt of each byte of data when in write mode (see Figure 6). The MAX9597 pulls down SDA during the entire master-generated ninth clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when the MAX9597 is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9597, followed by a STOP condition.
SCL
MAX9597
S
Sr
P
SDA
Figure 5. START, STOP, and REPEATED START Conditions
START CONDITION SCL 1 2
CLOCK PULSE FOR ACKNOWLEDGMENT
8 NOT ACKNOWLEDGE
9
SDA ACKNOWLEDGE
Figure 6. Acknowledge
Write Data Format A write to the MAX9597 consists of transmitting a START condition, the slave address with the R/W bit set to 0, one data byte to configure the internal register address pointer, one or more data bytes, and a STOP condition. Figure 7 illustrates the proper frame format for writing one byte of data to the MAX9597. Figure 8 illustrates the frame format for writing n-bytes of data to the MAX9597.
The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9597. The MAX9597 acknowledges receipt of the address byte during the master-generated ninth SCL pulse. The second byte transmitted from the master configures the MAX9597's internal register address pointer. The pointer tells the MAX9597 where to write the next byte of data. An acknowledge pulse is sent by the MAX9597 upon receipt of the address pointer data. The third byte sent to the MAX9597 contains the data that is written to the chosen register. An acknowledge pulse from the MAX9597 signals receipt of the data byte. The address pointer autoincrements to the next
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
ACKNOWLEDGE FROM MAX9597 B7 ACKNOWLEDGE FROM MAX9597 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9597 REGISTER ADDRESS A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P B6 B5 B4 B3 B2 B1 B0
Figure 7. Writing a Byte of Data to the MAX9597
ACKNOWLEDGE FROM MAX9597 B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9597 S SLAVE ADDRESS R/W 0 ACKNOWLEDGE FROM MAX9597 A REGISTER ADDRESS A DATA BYTE 1 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A
ACKNOWLEDGE FROM MAX9597 B7 B6 B5 B4 B3 B2 B1 B0
DATA BYTE n 1 BYTE
A
P
Figure 8. Writing n-Bytes of Data to the MAX9597
register address after each received data byte. This autoincrement feature allows a master to write to sequential register address locations within one continuous frame. The master signals the end of transmission by issuing a STOP condition.
Read Data Format The master presets the address pointer by first sending the MAX9597's slave address with the R/W bit set to 0 followed by the register address after a START condition. The MAX9597 acknowledges receipt of its slave address and the register address by pulling SDA low during the ninth SCL clock pulse. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9597 transmits the contents of the specified register. Transmitted data is valid on the rising edge of the master-generated serial clock (SCL). The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from the register address location set by the previous transaction and not 00h and subsequent reads autoincrement the address pointer
18
until the next STOP condition. Attempting to read from register addresses higher than 01h results in repeated reads from a dummy register containing FFh data. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figures 9 and 10 illustrate the frame format for reading data from the MAX9597.
Applications Information
Operating Modes
The MAX9597 has two operating modes: full power and shutdown. The operations can be set by writing to bit 7 of register 10h. See Table 12. In shudown mode, all circuitry is shut down except for the I2C interface, which is designed with static CMOS logic. If the I2C bus is quiet, the I2C interface draws only leakage current.
Power Consumption
With a low 3.3V supply, the quiescent power consumption and average power consumption of the MAX9597 is very low. Quiescent power consumption is defined
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX9597 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9597 REGISTER ADDRESS A ACKNOWLEDGE FROM MAX9597 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P
REPEATED START
Figure 9. Reading One Indexed Byte of Data from the MAX9597
ACKNOWLEDGE FROM MAX9597 S SLAVE ADDRESS R/W 0 A
ACKNOWLEDGE FROM MAX9597 REGISTER ADDRESS A
ACKNOWLEDGE FROM MAX9597 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P
REPEATED START
Figure 10. Reading n-Bytes of Indexed Data from the MAX9597
when the MAX9597 is operating without loads and without any audio or video signals. Table 4 shows the quiescent power consumption in both operating modes. Average power consumption is defined when the MAX9597 drives typical signals into typical loads. Table 5 shows the average power consumption in full-power mode, and Table 6 shows the input and output conditions.
Table 4. Quiescent Power Consumption
OPERATING MODE Shutdown Full power POWER CONSUMPTION (mW) 0.05 53
Table 5. Average Power Consumption
OPERATING MODE Full power POWER CONSUMPTION (mW) 254
Interfacing to an RF Modulator
If the set-top box modulates CVBS and mono audio onto an RF carrier (for example, channel 3), a simple application circuit can provide the needed signals (see Figure 11). A 10k resistor summer circuit between TV_OUTR and TV_OUTL creates the mono audio signal. The resistor-divider to ground on TV_CVBS_OUT creates a video signal with normal amplitude. The unique feature of the MAX9597 that facilitates this application circuit is that the audio and video output amplifiers of the MAX9597 can drive multiple loads if VAUD and VVID are both greater than 3.135V.
Floating-Chassis Discharge Protection and ESD
Some set-top boxes have a floating chassis problem in which the chassis is not connected to earth ground. As a result, the chassis can charge up to 500V. When a SCART cable is connected to the SCART connector, the charged chassis can discharge through a signal pin. The equivalent circuit is a 2200pF capacitor charged to 311V connected through less than 0.1 to a signal pin. The MAX9597 is soldered on the PCB when it experiences such a discharge. Therefore, the current spike flows through both external and internal ESD protection devices and is absorbed by the supply bypass capacitors, which have high capacitance and low ESR.
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
TV_OUTR 10k
MAX9597
MONO AUDIO 10k
TV_OUTL 75 TV_CVBS_OUT 75 OR GREATER
TV SCART
75 OR GREATER
RF MODULATOR
Figure 11. Application Circuit to Connect CVBS and Mono Audio from TV SCART to RF Modulator
Table 6. Conditions for Average Power Consumption Measurement
PIN 1 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME VAUD ENC_B_IN ENC_G_IN ENC_R/C_IN ENC_CVBS_IN TV_CVBS_OUT VVID TV_FS_OUT GND TV_R/C_OUT TV_G_OUT TV_B_OUT V12 TV_SS_OUT TV_OUTL ENC_INL+ ENC_INLENC_INLOUT ENC_INROUT ENC_INRENC_INR+ TV_OUTR TYPE Supply Input Input Input Input Output Supply Output Supply Output Output Output Supply Output Output Input Input Output Output Input Input Output SIGNAL 3.3V 50% flat field 50% flat field 50% flat field 50% flat field 50% flat field 3.3V 3.3V 0 50% flat field 50% flat field 50% flat field 12V 12V 1VRMS, 1kHz 0.25VRMS, 1kHz N/A N/A N/A N/A 0.25VRMS, 1kHz 1VRMS, 1kHz LOAD N/A N/A N/A N/A N/A 150 to ground N/A 150 to ground N/A 150 to ground 150 to ground 150 to ground N/A 10k to ground 10k to ground N/A N/A 1k to ground 1k to ground N/A N/A 10k to ground
Note: Input operational amplifiers set to unity-gain configuration.
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
12V +3.3V 0.1F 3.3V 0.1F 3.3V 0.1F VAUD STB CHIP SDA C SCL 300 V12 VVID VAUD TV_OUTR 300 VAUD CPVSS V12 100 TV_SS_OUT 75 DEV_ADDR VIDEO ENCODER ENC_CVBS_IN 75 TV_R/C_OUT ENC_R/C_IN TV_FS_OUT 75 75 TV_CVBS_OUT ENC_G_IN 75 C1P GND GND 75 TV_G_OUT 75 TV_B_OUT 75 CPVSS VVID EP VVID GND VVID GND VVID GND VVID TV SCART
MAX9597
TV_OUTL
ENC_B_IN 75
C1N CPVSS
GND ENC_INL+ EP 124 15nF
ENC_INLSTEREO AUDIO DACS WITH DIFFERENTIAL OUTPUTS 124 15nF ENC_INLOUT ENC_INR+ 124 15nF
ENC_INR124 15nF ENC_INROUT NOTE: OPTIONAL RESISTOR CAN BE PLACED FROM AUDIO DAC OUTPUTS TO GROUND TO DECREASE SWING AT AUDIO DAC OUTPUTS.
:BAV99, SMALL-SIGNAL DIODE
Figure 12. Application Circuit to Connect Series Resistors and External ESD Protection Diodes at MAX9597 Outputs
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
PCM1742 DAC 10F 604 LEFT 1.2nF 3.01k 390pF ENC_INLOUT 3.01k ENC_INR+ 10F RIGHT 1.2nF 3.01k NOTE: ALL RESISTORS ARE 1%. 390pF ENC_INROUT 604 6.04k ENC_INR6.04k ENC_INL-
3.01k
MAX9597
ENC_INL+
Figure 13. Lowpass Filter Configuration for the Burr-Brown PCM1742
To better protect the MAX9597 against excess voltages during the cable discharge condition or ESD events, add series resistors to all inputs and outputs to the SCART connector if series resistors are not already present in the application circuit. Also add external ESD protection diodes (for example, BAV99) on all inputs and output to the SCART connector.
FILTER RESPONSE vs. FREQUENCY PCM1742 APPLICATION CIRCUIT WITHOUT THE DAC
10 5 0 GAIN (dB) -5 -10 -15 -20 -25 -30 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) VIN = 0.25VRMS
Lowpass Filter Configuration for PCM1742 and CS4334
The lowpass filter configurations shown in Figures 13 and 15 are recommended when connecting a stereo audio DAC to the audio preamplifier (input amplifier) of the MAX9597. The filter configuration helps eliminate the switching noise caused by the audio DAC. The corner frequency of the filter configuration should be set above the maximum audio frequency (20kHz) and below the sampling frequency of the DAC. The frequency response of the filter configurations is shown in Figures 14 and 16.
Differential to Single-Ended Conversion of Audio Signals
If the stereo audio DAC generates an analog, voltage mode, differential audio signal, the circuit shown in Figure 17 can be used to convert the signal to single ended. The gain of the circuit is represented by this equation: R2 GAIN = x 4 R1
22
Figure 14. Filter Response of PCM1742 Filter Configuration
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
CS4334 DAC 10F 1.21k LEFT 2.7nF 270k 3.3nF 2.40k 560pF ENC_INLOUT 3.57k ENC_INR+ 10F RIGHT 2.7nF 270k 3.3nF 2.40k 560pF ENC_INROUT NOTE: ALL RESISTORS ARE 1%. 1.21k 4.64k 1.21k ENC_INR4.64k 1.21k ENC_INL-
3.57k
MAX9597
ENC_INL+
Figure 15. Lowpass Filter Configuration for the Cirrus CS4334
Keep the full-scale audio output of the preamplifiers to 0.5VRMS. Capacitors C1 and C2 create a one-pole, lowpass filter to attenuate any high-frequency noise coming from the stereo audio DAC. The frequency of the lowpass pole is represented by this equation: f-3dB = 1 1 or f-3dB = R1 x R2 R1 x R2 2 2 C2 C1 R1 + R2 R1 + R2
FILTER RESPONSE vs. FREQUENCY CS4334 APPLICATION CIRCUIT WITHOUT THE DAC
10 0 -10 GAIN (dB) -20 -30 -40 -50 -60 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) VIN = 0.25VRMS
If the stereo audio DAC generates an analog, current mode, and differential audio signal, the Typical Application Circuit can be used to convert the signal to single ended. The transresistance of the circuit is represented by this equation: VOUT = IDIFF x RF Keep the full-scale audio output of the preamplifiers to 0.5VRMS. Capacitors C1 and C2 create a one-pole, lowpass filter to attenuate any high-frequency noise coming from the stereo audio DAC. The frequency of the lowpass pole is represented by this equation: f-3dB = 1 1 or f-3dB = 2(RF )C1 2(RF )C2
Figure 16. Filter Response of CS4334 Filter Configuration
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
STB CHIP R2 LEFT_P R1 LEFT_N R2 R2 C1 R2 RIGHT_P R1 RIGHT_N R1 R2 C2 ENC_INROUT ENC_INRENC_INLOUT ENC_INR+ C2 ENC_INLC1
MAX9597
ENC_INL+
Figure 17. Differential to Single-Ended Conversion Circuit for Voltage Mode, Differential Audio Signals
Stand-Alone Operational Amplifier Applications
The input amplifier of the audio section can be utilized for stand-alone operational amplifier applications by configuring ENC_INR+ and ENC_INL+ input as the noninverting input, ENC_INR- and ENC_INL- input as the inverting input and ENC_INROUT and ENC_INLOUT output as the output of the stand-alone operational amplifier. The gain-bandwidth product of the amplifier is 7MHz (typ).
10F electrolytic capacitor in parallel with a 0.1F ceramic capacitor to audio ground. Bypass VVID to GND with a 0.1F ceramic capacitor.
Applications That Do Not Need the Slow-Switch Signal
V12 should be left unconnected if the MAX9597 is used in an application that does not require the slowswitch output signal. See Figure 18.
Using a Digital Supply The MAX9597 was designed to operate from noisy digital supplies. The high video PSRR (47dB at 100kHz) allows the MAX9597 to reject the noise from the digital power supplies (see the Typical Operating Characteristics). If the digital power supply is very noisy and stripes appear on the television screen, increase the supply bypass capacitance. An additional, smaller capacitor in parallel with the main bypass capacitor can reduce digital supply noise because the smaller capacitor has lower equivalent series resistance (ESR) and equivalent series inductance (ESL).
Power-Supply Bypassing
The MAX9597 features single 3.3V and 12V supply operation and requires no negative supply. The 12V supply V12 is for the SCART slow-switching function. For pin V12, place a 0.1F bypass capacitor as close to it as possible. Connect VAUD to 3.3V and bypass with a
Layout and Grounding
For optimal performance, use controlled-impedance traces for video signal paths and place input termination resistors and output back-termination resistors close to the MAX9597. Avoid routing video traces parallel to high-speed data lines.
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
V12 N.C. VID 3.3V VAUD 3.3V
MAX9597
STB CHIP I2C INTERFACE AND REGISTERS
C
I2C
CVBS VIDEO FILTERS Y VIDEO ENCODER CVBS, Y/C C AUDIO WITH DirectDrive OUTPUTS 2 43 1
LEFT AUDIO RIGHT AUDIO
STEREO AUDIO DAC
SINGLE OR DIFFERENTIAL STEREO AUDIO
SLOW SWITCHING FAST SWITCHING
CHARGE PUMP
EP
GND
Figure 18. Set-Top Box with CVBS Output, S-Video Output, and Stereo Audio Outputs
The MAX9597 provides separate ground connections for video and audio supplies. For best performance, use separate ground planes for each of the ground returns and connect all ground planes together at a single point. Refer to the MAX9597 Evaluation Kit for a proven circuit board layout example.
If the MAX9597 is mounted using flow soldering or wave soldering, the ground via(s) for the exposed pad should have a finished hole size of at least 14mil to ensure adequate wicking of soldering onto the exposed pad. If the MAX9597 is mounted using the solder mask technique, the via requirement does not apply. In either case, a good connection between the exposed pad and ground is required to minimize noise from coupling onto the outputs.
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25
Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
Register Tables
Table 7. Data Format for Write Mode
REGISTER ADDRESS (HEXADECIMAL) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x10 Not used Operating mode Not used Not used TV_B_OUT Not used TV_G_OUT Not used Not used Not used Not used Not used Not used Not used BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TV audio mute
Not used
ZCD
Not used Not used Not used Not used Not used Not used Not used Set TV fast switching Not used ENC_R/C_IN clamp Not used Not used Not used Not used TV_R/C_OUT Not used TV_CVBS_OUT Not used TV_FS_OUT Not used Not used Not used
Set TV slow switching Not used Not used
Not used Not used
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
Table 8. Register 00h: Audio Control
DESCRIPTION TV audio mute Zero-crossing detector BIT 7 -- -- -- -- 6 -- -- 0 1 5 -- -- -- -- 4 -- -- -- -- 3 -- -- -- -- 2 -- -- -- -- 1 -- -- -- -- 0 0 1 -- -- Off On (power-on default) Off On (power-on default) COMMENTS
Table 9. Register 07h: TV Video Output Control
DESCRIPTION BIT 7 -- -- -- -- -- Set TV fast switching -- -- -- 6 -- -- -- -- -- -- -- -- 5 -- -- -- -- -- -- -- -- 4 -- -- -- -- 0 0 1 1 3 -- -- -- -- 0 1 0 1 2 -- -- -- -- -- -- -- -- 1 0 0 1 1 -- -- -- -- 0 0 1 0 1 -- -- -- -- COMMENTS Low (< 2V) internal source (power-on default) Medium (4.5V to 7V) external SCART source with 16:9 aspect ratio High impedance High ( > 9.5V) external SCART source with 4:3 aspect ratio GND (power-on default) Not used Same level as VCR_FB_IN VVID
Set TV slow switching
Table 10. Register 08h: VCR Video Input Control
DESCRIPTION BIT 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 0 1 2 -- -- 1 -- -- 0 -- -- COMMENTS DC restore clamp active at input (power-on default) Chrominance bias applied at input
ENC_R/C_IN clamp/bias
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27
Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
Table 11. Register 0Dh: Output Enable
DESCRIPTION TV_FS_OUT enable TV_CVBS_OUT enable TV_B_OUT enable TV_G_OUT enable TV_R/C_OUT enable BIT 7 -- -- -- -- -- -- -- -- -- -- 6 -- -- -- -- -- -- -- -- -- -- 5 -- -- -- -- -- -- -- -- 0 1 4 -- -- -- -- -- -- 0 1 -- -- 3 -- -- -- -- 0 1 -- -- -- -- 2 -- -- 0 1 -- -- -- -- -- -- 1 0 1 -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- On Off (power-on default) On Off (power-on default) On Off (power-on default) On Off (power-on default) On COMMENTS Off (power-on default)
Table 12. Register 10h: Operating Modes
DESCRIPTION Operating mode BIT 7 0 1 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 -- -- 0 -- -- Shutdown Full-power mode (power-on default) COMMENTS
Pin Configuration
TOP VIEW
TV_R/C_OUT
Chip Information
PROCESS: BiCMOS
TV_SS_OUT
TV_G_OUT
TV_B_OUT
TV_OUTL
21 ENC_INL+ 22 ENC_INL- 23 ENC_INLOUT 24 ENC_INROUT 25 ENC_INR- 26 ENC_INR+ 27 TV_OUTR 28 + 1 VAUD
20
19
18
17
16
15 14 13 12 TV_FS_OUT VVID TV_CVBS_OUT ENC_CVBS_IN ENC_R/C_IN ENC_G_IN ENC_B_IN
GND 11 10 9 8 7 SCL
V12
MAX9597
EP*
2 C1P
3 C1N
4 CPVSS
5 DEV_ADDR
6 SDA
*EXPOSED PAD. CONNECT EP TO AUDIO GROUND FOR PROPER THERMAL AND ELECTRICAL PERFORMANCE
28
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Low-Power Audio/Video Interface for Single SCART Connectors
Typical Application Circuit
12V +3.3V 0.1F 3.3V 0.1F 3.3V 0.1F
MAX9597
STB CHIP SDA C SCL
V12
VVID
VAUD TV_OUTR
300
300
MAX9597
TV_OUTL 100 TV_SS_OUT 75
DEV_ADDR VIDEO ENCODER ENC_CVBS_IN 75
TV_B_OUT 75 TV_G_OUT 75 TV_R/C_OUT
TV SCART
ENC_R/C_IN TV_FS_OUT 75
75
75 TV_CVBS_OUT ENC_G_IN 75 C1P
ENC_B_IN 75
C1N CPVSS
GND ENC_INL+ EP 124 (RF) 15nF (C1)
ENC_INLSTEREO AUDIO CURRENT DACS WITH DIFFERENTIAL OUTPUTS 124 (RF) 15nF (C2) ENC_INLOUT ENC_INR+ 124 (RF) 15nF (C1)
ENC_INR124 (RF) 15nF (C2) ENC_INROUT NOTE: OPTIONAL RESISTOR CAN BE PLACED FROM AUDIO DAC OUTPUTS TO GROUND TO DECREASE SWING AT AUDIO DAC OUTPUTS.
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Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 28 TQFN-EP PACKAGE CODE T2855-8 DOCUMENT NO. 21-0140
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QFN THIN.EPS
Low-Power Audio/Video Interface for Single SCART Connectors
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
MAX9597
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31
Low-Power Audio/Video Interface for Single SCART Connectors MAX9597
Revision History
REVISION NUMBER 0 1 REVISION DATE 6/08 10/08 DESCRIPTION Initial release Corrected resistor value in Figure 13 PAGES CHANGED -- 22
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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